From 661e995acd0b39eeee3b3ac142728f1c8ae51fef Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Mon, 9 Sep 2024 20:44:35 +0300 Subject: [PATCH] chore(CMSIS,PeriphDrivers): Sync latest MAX32657 changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit content comes from feat/ME30 branch. CMSIS register, includes, peripheral source files copied from feat/ME30 branch to here to these files being merged into main. These files requires to push MAX32657 to the upstream. Co-authored-by: Jake-Carter Co-authored-by: sihyung-maxim Co-authored-by: EricB-ADI Co-authored-by: Bobby Co-authored-by: Anıl Kara Co-authored-by: Tahsin Mutlugun Co-authored-by: Sadik Ozer --- .../Maxim/MAX32657/Include/boost_regs.h | 220 ++ .../Device/Maxim/MAX32657/Include/crc_regs.h | 1 - .../Device/Maxim/MAX32657/Include/dma_regs.h | 20 +- .../Device/Maxim/MAX32657/Include/fcr_regs.h | 190 +- .../Device/Maxim/MAX32657/Include/flc_regs.h | 56 - .../Device/Maxim/MAX32657/Include/gcr_regs.h | 97 +- .../Device/Maxim/MAX32657/Include/icc_regs.h | 12 +- .../Device/Maxim/MAX32657/Include/max32657.h | 312 +- .../Maxim/MAX32657/Include/max32657.svd | 2723 ++++++++++------- .../Device/Maxim/MAX32657/Include/mcr_regs.h | 100 +- .../Device/Maxim/MAX32657/Include/mpc_regs.h | 280 ++ .../Device/Maxim/MAX32657/Include/nspc_regs.h | 72 + .../MAX32657/Include/partition_max32657.h | 1286 -------- .../Maxim/MAX32657/Include/pwrseq_regs.h | 39 +- .../Device/Maxim/MAX32657/Include/rstz_regs.h | 169 + .../Device/Maxim/MAX32657/Include/sema_regs.h | 201 -- .../Device/Maxim/MAX32657/Include/simo_regs.h | 378 --- .../Device/Maxim/MAX32657/Include/sir_regs.h | 34 +- .../Device/Maxim/MAX32657/Include/spc_regs.h | 149 +- .../Device/Maxim/MAX32657/Include/spi_regs.h | 12 +- .../Maxim/MAX32657/Include/system_max32657.h | 18 + .../Device/Maxim/MAX32657/Include/uart_regs.h | 8 +- .../MAX32657/Source/sla_header_max32657.c | 55 + .../Maxim/MAX32657/Source/system_max32657.c | 103 +- .../PeriphDrivers/Include/MAX32657/dma.h | 6 +- .../PeriphDrivers/Include/MAX32657/gpio.h | 4 +- .../PeriphDrivers/Include/MAX32657/i3c.h | 4 +- .../PeriphDrivers/Include/MAX32657/icc.h | 8 +- Libraries/PeriphDrivers/Include/MAX32657/lp.h | 9 - .../PeriphDrivers/Include/MAX32657/mpc.h | 97 + .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 14 +- .../PeriphDrivers/Include/MAX32657/nspc.h | 99 + .../Include/MAX32657/nvic_table.h | 42 - .../PeriphDrivers/Include/MAX32657/spc.h | 212 ++ .../PeriphDrivers/Include/MAX32657/spi.h | 4 +- .../PeriphDrivers/Source/BOOST/boost_reva.svd | 159 + Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 17 +- .../Source/DMA/dma_reva_me30.svd | 48 +- Libraries/PeriphDrivers/Source/FLC/flc_me30.c | 31 +- Libraries/PeriphDrivers/Source/FLC/flc_reva.c | 6 + .../Source/FLC/flc_revb_me30.svd | 57 +- .../PeriphDrivers/Source/GPIO/gpio_me30.c | 32 +- Libraries/PeriphDrivers/Source/ICC/icc_me30.c | 17 +- .../Source/ICC/icc_reva_me30.svd | 25 +- Libraries/PeriphDrivers/Source/LP/lp_me30.c | 88 +- .../PeriphDrivers/Source/LP/pwrseq_me30.svd | 68 +- .../PeriphDrivers/Source/RSTZ/rstz_reva.svd | 139 + Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 37 +- .../Source/SPI/spi_reva_me30.svd | 6 +- .../PeriphDrivers/Source/SYS/SVD/fcr_me30.svd | 157 +- .../PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 114 +- .../PeriphDrivers/Source/SYS/SVD/mcr_me30.svd | 135 +- .../PeriphDrivers/Source/SYS/SVD/sir_me30.svd | 30 +- Libraries/PeriphDrivers/Source/SYS/sys_me30.c | 9 +- Libraries/PeriphDrivers/Source/TMR/tmr_me30.c | 2 - Libraries/PeriphDrivers/Source/TMR/tmr_revb.c | 2 +- Libraries/PeriphDrivers/Source/TZ/mpc_me30.c | 249 ++ .../PeriphDrivers/Source/TZ/mpc_me30.svd | 283 ++ Libraries/PeriphDrivers/Source/TZ/nspc_me30.c | 63 + .../PeriphDrivers/Source/TZ/nspc_me30.svd | 189 ++ Libraries/PeriphDrivers/Source/TZ/spc_me30.c | 182 ++ .../PeriphDrivers/Source/TZ/spc_me30.svd | 575 ++++ .../PeriphDrivers/Source/UART/uart_revb.c | 29 +- .../Source/UART/uart_revb_me30.svd | 18 +- 64 files changed, 5917 insertions(+), 3884 deletions(-) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mpc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/nspc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/spc.h create mode 100644 Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd create mode 100644 Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd create mode 100644 Libraries/PeriphDrivers/Source/TZ/mpc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/TZ/nspc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/TZ/spc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/TZ/spc_me30.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h new file mode 100644 index 00000000000..f501eddd823 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h @@ -0,0 +1,220 @@ +/** + * @file boost_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BOOST Peripheral Module. + * @note This file is @generated. + * @ingroup boost_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup boost + * @defgroup boost_registers BOOST_Registers + * @brief Registers, Bit Masks and Bit Positions for the BOOST Peripheral Module. + * @details Boost Controller + */ + +/** + * @ingroup boost_registers + * Structure type to access the BOOST Registers. + */ +typedef struct { + __IO uint32_t disable; /**< \b 0x000: BOOST DISABLE Register */ + __IO uint32_t vregctrl; /**< \b 0x004: BOOST VREGCTRL Register */ + __I uint32_t ipeak; /**< \b 0x008: BOOST IPEAK Register */ + __I uint32_t maxton; /**< \b 0x00C: BOOST MAXTON Register */ + __I uint32_t iload; /**< \b 0x010: BOOST ILOAD Register */ + __IO uint32_t alert; /**< \b 0x014: BOOST ALERT Register */ + __I uint32_t rdy; /**< \b 0x018: BOOST RDY Register */ + __I uint32_t zxcal; /**< \b 0x01C: BOOST ZXCAL Register */ + __IO uint32_t inten; /**< \b 0x020: BOOST INTEN Register */ + __IO uint32_t intfl; /**< \b 0x024: BOOST INTFL Register */ +} mxc_boost_regs_t; + +/* Register offsets for module BOOST */ +/** + * @ingroup boost_registers + * @defgroup BOOST_Register_Offsets Register Offsets + * @brief BOOST Peripheral Register Offsets from the BOOST Base Peripheral Address. + * @{ + */ +#define MXC_R_BOOST_DISABLE ((uint32_t)0x00000000UL) /**< Offset from BOOST Base Address: 0x0000 */ +#define MXC_R_BOOST_VREGCTRL ((uint32_t)0x00000004UL) /**< Offset from BOOST Base Address: 0x0004 */ +#define MXC_R_BOOST_IPEAK ((uint32_t)0x00000008UL) /**< Offset from BOOST Base Address: 0x0008 */ +#define MXC_R_BOOST_MAXTON ((uint32_t)0x0000000CUL) /**< Offset from BOOST Base Address: 0x000C */ +#define MXC_R_BOOST_ILOAD ((uint32_t)0x00000010UL) /**< Offset from BOOST Base Address: 0x0010 */ +#define MXC_R_BOOST_ALERT ((uint32_t)0x00000014UL) /**< Offset from BOOST Base Address: 0x0014 */ +#define MXC_R_BOOST_RDY ((uint32_t)0x00000018UL) /**< Offset from BOOST Base Address: 0x0018 */ +#define MXC_R_BOOST_ZXCAL ((uint32_t)0x0000001CUL) /**< Offset from BOOST Base Address: 0x001C */ +#define MXC_R_BOOST_INTEN ((uint32_t)0x00000020UL) /**< Offset from BOOST Base Address: 0x0020 */ +#define MXC_R_BOOST_INTFL ((uint32_t)0x00000024UL) /**< Offset from BOOST Base Address: 0x0024 */ +/**@} end of group boost_registers */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_DISABLE BOOST_DISABLE + * @brief Boost Disable Register. + * @{ + */ +#define MXC_F_BOOST_DISABLE_DIS_POS 0 /**< DISABLE_DIS Position */ +#define MXC_F_BOOST_DISABLE_DIS ((uint32_t)(0x1UL << MXC_F_BOOST_DISABLE_DIS_POS)) /**< DISABLE_DIS Mask */ + +/**@} end of group BOOST_DISABLE_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_VREGCTRL BOOST_VREGCTRL + * @brief Boost Voltage Regulator Control Register. + * @{ + */ +#define MXC_F_BOOST_VREGCTRL_SET_POS 0 /**< VREGCTRL_SET Position */ +#define MXC_F_BOOST_VREGCTRL_SET ((uint32_t)(0x1FUL << MXC_F_BOOST_VREGCTRL_SET_POS)) /**< VREGCTRL_SET Mask */ + +/**@} end of group BOOST_VREGCTRL_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_IPEAK BOOST_IPEAK + * @brief Low Side FET Peak Current Register. + * @{ + */ +#define MXC_F_BOOST_IPEAK_SET_POS 0 /**< IPEAK_SET Position */ +#define MXC_F_BOOST_IPEAK_SET ((uint32_t)(0x7UL << MXC_F_BOOST_IPEAK_SET_POS)) /**< IPEAK_SET Mask */ + +/**@} end of group BOOST_IPEAK_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_MAXTON BOOST_MAXTON + * @brief Maximum Low Side FET Time-On Register. + * @{ + */ +#define MXC_F_BOOST_MAXTON_THD_POS 0 /**< MAXTON_THD Position */ +#define MXC_F_BOOST_MAXTON_THD ((uint32_t)(0xFUL << MXC_F_BOOST_MAXTON_THD_POS)) /**< MAXTON_THD Mask */ + +/**@} end of group BOOST_MAXTON_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ILOAD BOOST_ILOAD + * @brief Boost Cycle Count Register. + * @{ + */ +#define MXC_F_BOOST_ILOAD_CNT_POS 0 /**< ILOAD_CNT Position */ +#define MXC_F_BOOST_ILOAD_CNT ((uint32_t)(0xFFUL << MXC_F_BOOST_ILOAD_CNT_POS)) /**< ILOAD_CNT Mask */ + +/**@} end of group BOOST_ILOAD_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ALERT BOOST_ALERT + * @brief Boost Cycle Count Alert Register. + * @{ + */ +#define MXC_F_BOOST_ALERT_THD_POS 0 /**< ALERT_THD Position */ +#define MXC_F_BOOST_ALERT_THD ((uint32_t)(0xFFUL << MXC_F_BOOST_ALERT_THD_POS)) /**< ALERT_THD Mask */ + +/**@} end of group BOOST_ALERT_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_RDY BOOST_RDY + * @brief Boost Output Ready Register. + * @{ + */ +#define MXC_F_BOOST_RDY_OUT_POS 0 /**< RDY_OUT Position */ +#define MXC_F_BOOST_RDY_OUT ((uint32_t)(0x1UL << MXC_F_BOOST_RDY_OUT_POS)) /**< RDY_OUT Mask */ + +/**@} end of group BOOST_RDY_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ZXCAL BOOST_ZXCAL + * @brief Zero Cross Calibration Register. + * @{ + */ +#define MXC_F_BOOST_ZXCAL_VAL_POS 0 /**< ZXCAL_VAL Position */ +#define MXC_F_BOOST_ZXCAL_VAL ((uint32_t)(0x1FUL << MXC_F_BOOST_ZXCAL_VAL_POS)) /**< ZXCAL_VAL Mask */ + +/**@} end of group BOOST_ZXCAL_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_INTEN BOOST_INTEN + * @brief Boost Alert Interrupt Enable Register. + * @{ + */ +#define MXC_F_BOOST_INTEN_ALERT_POS 0 /**< INTEN_ALERT Position */ +#define MXC_F_BOOST_INTEN_ALERT ((uint32_t)(0x1UL << MXC_F_BOOST_INTEN_ALERT_POS)) /**< INTEN_ALERT Mask */ + +/**@} end of group BOOST_INTEN_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_INTFL BOOST_INTFL + * @brief Boost Alert Interrupt Status Register. + * @{ + */ +#define MXC_F_BOOST_INTFL_ALERT_POS 0 /**< INTFL_ALERT Position */ +#define MXC_F_BOOST_INTFL_ALERT ((uint32_t)(0x1UL << MXC_F_BOOST_INTFL_ALERT_POS)) /**< INTFL_ALERT Mask */ + +/**@} end of group BOOST_INTFL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index 1cbe04b2618..8f2430af694 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -78,7 +78,6 @@ typedef struct { __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; - __R uint8_t rsv_0x5_0x7[3]; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ } mxc_crc_regs_t; diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index 0d77fc7711d..7c196348590 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -176,22 +176,26 @@ typedef struct { #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPIRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UARTRX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UARTRX Value */ #define MXC_S_DMA_CTRL_REQUEST_UARTRX (MXC_V_DMA_CTRL_REQUEST_UARTRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTRX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I3CRX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I3CRX (MXC_V_DMA_CTRL_REQUEST_I3CRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPIRX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX_CONT Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_CONT Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG ((uint32_t)0x8UL) /**< CTRL_REQUEST_I3CRX_TARG Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_TARG Setting */ #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPITX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */ #define MXC_V_DMA_CTRL_REQUEST_UARTTX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UARTTX Value */ #define MXC_S_DMA_CTRL_REQUEST_UARTTX (MXC_V_DMA_CTRL_REQUEST_UARTTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTTX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I3CTX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I3CTX (MXC_V_DMA_CTRL_REQUEST_I3CTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX_CONT Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_CONT Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG ((uint32_t)0x28UL) /**< CTRL_REQUEST_I3CTX_TARG Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_TARG Setting */ #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPITX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */ #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 01f4cd18d34..da7cb86b8e8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -72,12 +72,19 @@ extern "C" { * Structure type to access the FCR Registers. */ typedef struct { - __IO uint32_t fctrl0; /**< \b 0x00: FCR FCTRL0 Register */ - __IO uint32_t fctrl1; /**< \b 0x04: FCR FCTRL1 Register */ - __IO uint32_t fctrl2; /**< \b 0x08: FCR FCTRL2 Register */ - __IO uint32_t fctrl3; /**< \b 0x0C: FCR FCTRL3 Register */ + __IO uint32_t ctrl; /**< \b 0x00: FCR CTRL Register */ + __IO uint32_t autocal0; /**< \b 0x04: FCR AUTOCAL0 Register */ + __IO uint32_t autocal1; /**< \b 0x08: FCR AUTOCAL1 Register */ + __IO uint32_t autocal2; /**< \b 0x0C: FCR AUTOCAL2 Register */ __R uint32_t rsv_0x10_0x17[2]; __IO uint32_t erfoks; /**< \b 0x18: FCR ERFOKS Register */ + __IO uint32_t intfl; /**< \b 0x1C: FCR INTFL Register */ + __IO uint32_t inten; /**< \b 0x20: FCR INTEN Register */ + __R uint32_t rsv_0x24; + __IO uint32_t frqcntctrl; /**< \b 0x28: FCR FRQCNTCTRL Register */ + __IO uint32_t frqcntcmp; /**< \b 0x2C: FCR FRQCNTCMP Register */ + __I uint32_t refclk; /**< \b 0x30: FCR REFCLK Register */ + __I uint32_t cmpclk; /**< \b 0x34: FCR CMPCLK Register */ } mxc_fcr_regs_t; /* Register offsets for module FCR */ @@ -87,86 +94,92 @@ typedef struct { * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. * @{ */ -#define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ -#define MXC_R_FCR_FCTRL1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ -#define MXC_R_FCR_FCTRL2 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ -#define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ +#define MXC_R_FCR_CTRL ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +#define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ +#define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ +#define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ +#define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ +#define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: 0x0028 */ +#define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: 0x002C */ +#define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: 0x0030 */ +#define MXC_R_FCR_CMPCLK ((uint32_t)0x00000034UL) /**< Offset from FCR Base Address: 0x0034 */ /**@} end of group fcr_registers */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL0 FCR_FCTRL0 - * @brief Register 0. + * @defgroup FCR_CTRL FCR_CTRL + * @brief Function Control 0 Register. * @{ */ -#define MXC_F_FCR_FCTRL0_BTLELDO_TX_POS 0 /**< FCTRL0_BTLELDO_TX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDO_TX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_TX_POS)) /**< FCTRL0_BTLELDO_TX Mask */ +#define MXC_F_FCR_CTRL_BTLELDO_RF_POS 0 /**< CTRL_BTLELDO_RF Position */ +#define MXC_F_FCR_CTRL_BTLELDO_RF ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_RF_POS)) /**< CTRL_BTLELDO_RF Mask */ -#define MXC_F_FCR_FCTRL0_BTLELDO_RX_POS 8 /**< FCTRL0_BTLELDO_RX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDO_RX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_RX_POS)) /**< FCTRL0_BTLELDO_RX Mask */ +#define MXC_F_FCR_CTRL_BTLELDO_BB_POS 8 /**< CTRL_BTLELDO_BB Position */ +#define MXC_F_FCR_CTRL_BTLELDO_BB ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_BB_POS)) /**< CTRL_BTLELDO_BB Mask */ -#define MXC_F_FCR_FCTRL0_I3CDGEN0_POS 20 /**< FCTRL0_I3CDGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I3CDGEN0_POS)) /**< FCTRL0_I3CDGEN0 Mask */ +#define MXC_F_FCR_CTRL_I3CDGEN0_POS 20 /**< CTRL_I3CDGEN0 Position */ +#define MXC_F_FCR_CTRL_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_CTRL_I3CDGEN0_POS)) /**< CTRL_I3CDGEN0 Mask */ -#define MXC_F_FCR_FCTRL0_I3CDGEN1_POS 21 /**< FCTRL0_I3CDGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I3CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I3CDGEN1_POS)) /**< FCTRL0_I3CDGEN1 Mask */ +#define MXC_F_FCR_CTRL_I3CDGEN1_POS 21 /**< CTRL_I3CDGEN1 Position */ +#define MXC_F_FCR_CTRL_I3CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_CTRL_I3CDGEN1_POS)) /**< CTRL_I3CDGEN1 Mask */ -/**@} end of group FCR_FCTRL0_Register */ +/**@} end of group FCR_CTRL_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL1 FCR_FCTRL1 - * @brief Register 1. + * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 + * @brief Automatic Calibration 0 Register. * @{ */ -#define MXC_F_FCR_FCTRL1_AC_EN_POS 0 /**< FCTRL1_AC_EN Position */ -#define MXC_F_FCR_FCTRL1_AC_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_EN_POS)) /**< FCTRL1_AC_EN Mask */ +#define MXC_F_FCR_AUTOCAL0_EN_POS 0 /**< AUTOCAL0_EN Position */ +#define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ -#define MXC_F_FCR_FCTRL1_AC_RUN_POS 1 /**< FCTRL1_AC_RUN Position */ -#define MXC_F_FCR_FCTRL1_AC_RUN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_RUN_POS)) /**< FCTRL1_AC_RUN Mask */ +#define MXC_F_FCR_AUTOCAL0_RUN_POS 1 /**< AUTOCAL0_RUN Position */ +#define MXC_F_FCR_AUTOCAL0_RUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_RUN_POS)) /**< AUTOCAL0_RUN Mask */ -#define MXC_F_FCR_FCTRL1_LOAD_TRIM_POS 2 /**< FCTRL1_LOAD_TRIM Position */ -#define MXC_F_FCR_FCTRL1_LOAD_TRIM ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_LOAD_TRIM_POS)) /**< FCTRL1_LOAD_TRIM Mask */ +#define MXC_F_FCR_AUTOCAL0_LOAD_TRIM_POS 2 /**< AUTOCAL0_LOAD_TRIM Position */ +#define MXC_F_FCR_AUTOCAL0_LOAD_TRIM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_TRIM_POS)) /**< AUTOCAL0_LOAD_TRIM Mask */ -#define MXC_F_FCR_FCTRL1_GAIN_INV_POS 3 /**< FCTRL1_GAIN_INV Position */ -#define MXC_F_FCR_FCTRL1_GAIN_INV ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_GAIN_INV_POS)) /**< FCTRL1_GAIN_INV Mask */ +#define MXC_F_FCR_AUTOCAL0_GAIN_INV_POS 3 /**< AUTOCAL0_GAIN_INV Position */ +#define MXC_F_FCR_AUTOCAL0_GAIN_INV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAIN_INV_POS)) /**< AUTOCAL0_GAIN_INV Mask */ -#define MXC_F_FCR_FCTRL1_ATOMIC_POS 4 /**< FCTRL1_ATOMIC Position */ -#define MXC_F_FCR_FCTRL1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_ATOMIC_POS)) /**< FCTRL1_ATOMIC Mask */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ -#define MXC_F_FCR_FCTRL1_MU_POS 8 /**< FCTRL1_MU Position */ -#define MXC_F_FCR_FCTRL1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_FCTRL1_MU_POS)) /**< FCTRL1_MU Mask */ +#define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ +#define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ -#define MXC_F_FCR_FCTRL1_AC_TRIM_OUT_POS 23 /**< FCTRL1_AC_TRIM_OUT Position */ -#define MXC_F_FCR_FCTRL1_AC_TRIM_OUT ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_OUT_POS)) /**< FCTRL1_AC_TRIM_OUT Mask */ +#define MXC_F_FCR_AUTOCAL0_TRIM_OUT_POS 23 /**< AUTOCAL0_TRIM_OUT Position */ +#define MXC_F_FCR_AUTOCAL0_TRIM_OUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_OUT_POS)) /**< AUTOCAL0_TRIM_OUT Mask */ -/**@} end of group FCR_FCTRL1_Register */ +/**@} end of group FCR_AUTOCAL0_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL2 FCR_FCTRL2 - * @brief Register 2. + * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 + * @brief Automatic Calibration 1 Register. * @{ */ -#define MXC_F_FCR_FCTRL2_AC_INIT_TRIM_POS 0 /**< FCTRL2_AC_INIT_TRIM Position */ -#define MXC_F_FCR_FCTRL2_AC_INIT_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL2_AC_INIT_TRIM_POS)) /**< FCTRL2_AC_INIT_TRIM Mask */ +#define MXC_F_FCR_AUTOCAL1_INIT_TRIM_POS 0 /**< AUTOCAL1_INIT_TRIM Position */ +#define MXC_F_FCR_AUTOCAL1_INIT_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INIT_TRIM_POS)) /**< AUTOCAL1_INIT_TRIM Mask */ -/**@} end of group FCR_FCTRL2_Register */ +/**@} end of group FCR_AUTOCAL1_Register */ /** * @ingroup fcr_registers - * @defgroup FCR_FCTRL3 FCR_FCTRL3 - * @brief Register 3. + * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 + * @brief Automatic Calibration 2 Register. * @{ */ -#define MXC_F_FCR_FCTRL3_AC_RUNTIME_POS 0 /**< FCTRL3_AC_RUNTIME Position */ -#define MXC_F_FCR_FCTRL3_AC_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_AC_RUNTIME_POS)) /**< FCTRL3_AC_RUNTIME Mask */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ -#define MXC_F_FCR_FCTRL3_AC_DIV_POS 8 /**< FCTRL3_AC_DIV Position */ -#define MXC_F_FCR_FCTRL3_AC_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_FCTRL3_AC_DIV_POS)) /**< FCTRL3_AC_DIV Mask */ +#define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ +#define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ -/**@} end of group FCR_FCTRL3_Register */ +/**@} end of group FCR_AUTOCAL2_Register */ /** * @ingroup fcr_registers @@ -195,6 +208,87 @@ typedef struct { /**@} end of group FCR_ERFOKS_Register */ +/** + * @ingroup fcr_registers + * @defgroup FCR_INTFL FCR_INTFL + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_FCR_INTFL_ERTOC_RDY_POS 0 /**< INTFL_ERTOC_RDY Position */ +#define MXC_F_FCR_INTFL_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_ERTOC_RDY_POS)) /**< INTFL_ERTOC_RDY Mask */ + +#define MXC_F_FCR_INTFL_FRQCNT_POS 1 /**< INTFL_FRQCNT Position */ +#define MXC_F_FCR_INTFL_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_FRQCNT_POS)) /**< INTFL_FRQCNT Mask */ + +/**@} end of group FCR_INTFL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_INTEN FCR_INTEN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_FCR_INTEN_ERTOC_RDY_POS 0 /**< INTEN_ERTOC_RDY Position */ +#define MXC_F_FCR_INTEN_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_ERTOC_RDY_POS)) /**< INTEN_ERTOC_RDY Mask */ + +#define MXC_F_FCR_INTEN_FRQCNT_POS 1 /**< INTEN_FRQCNT Position */ +#define MXC_F_FCR_INTEN_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_FRQCNT_POS)) /**< INTEN_FRQCNT Mask */ + +/**@} end of group FCR_INTEN_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL + * @brief Frequency Counter Control Register. + * @{ + */ +#define MXC_F_FCR_FRQCNTCTRL_START_POS 0 /**< FRQCNTCTRL_START Position */ +#define MXC_F_FCR_FRQCNTCTRL_START ((uint32_t)(0x1UL << MXC_F_FCR_FRQCNTCTRL_START_POS)) /**< FRQCNTCTRL_START Mask */ + +#define MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS 1 /**< FRQCNTCTRL_CMP_CLKSEL Position */ +#define MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS)) /**< FRQCNTCTRL_CMP_CLKSEL Mask */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC ((uint32_t)0x0UL) /**< FRQCNTCTRL_CMP_CLKSEL_RTC Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_RTC Setting */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO ((uint32_t)0x2UL) /**< FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO Setting */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO ((uint32_t)0x3UL) /**< FRQCNTCTRL_CMP_CLKSEL_INRO Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_INRO Setting */ + +/**@} end of group FCR_FRQCNTCTRL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FRQCNTCMP FCR_FRQCNTCMP + * @brief Frequency Counter Compared Target Register. + * @{ + */ +#define MXC_F_FCR_FRQCNTCMP_TARGET_POS 0 /**< FRQCNTCMP_TARGET Position */ +#define MXC_F_FCR_FRQCNTCMP_TARGET ((uint32_t)(0x3FFFUL << MXC_F_FCR_FRQCNTCMP_TARGET_POS)) /**< FRQCNTCMP_TARGET Mask */ + +/**@} end of group FCR_FRQCNTCMP_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_REFCLK FCR_REFCLK + * @brief Reference Clock Result Register. + * @{ + */ +#define MXC_F_FCR_REFCLK_RESULT_POS 0 /**< REFCLK_RESULT Position */ +#define MXC_F_FCR_REFCLK_RESULT ((uint32_t)(0xFFFFFUL << MXC_F_FCR_REFCLK_RESULT_POS)) /**< REFCLK_RESULT Mask */ + +/**@} end of group FCR_REFCLK_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_CMPCLK FCR_CMPCLK + * @brief Compared Clock Result Register. + * @{ + */ +#define MXC_F_FCR_CMPCLK_RESULT_POS 0 /**< CMPCLK_RESULT Position */ +#define MXC_F_FCR_CMPCLK_RESULT ((uint32_t)(0x3FFFUL << MXC_F_FCR_CMPCLK_RESULT_POS)) /**< CMPCLK_RESULT Mask */ + +/**@} end of group FCR_CMPCLK_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h index 0027d3c335b..491a95737d0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -81,14 +81,6 @@ typedef struct { __IO uint32_t eccdata; /**< \b 0x2C: FLC ECCDATA Register */ __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ - __R uint32_t rsv_0x44_0x7f[15]; - __IO uint32_t welr0; /**< \b 0x80: FLC WELR0 Register */ - __R uint32_t rsv_0x84; - __IO uint32_t welr1; /**< \b 0x88: FLC WELR1 Register */ - __R uint32_t rsv_0x8c; - __IO uint32_t rlr0; /**< \b 0x90: FLC RLR0 Register */ - __R uint32_t rsv_0x94; - __IO uint32_t rlr1; /**< \b 0x98: FLC RLR1 Register */ } mxc_flc_regs_t; /* Register offsets for module FLC */ @@ -105,10 +97,6 @@ typedef struct { #define MXC_R_FLC_ECCDATA ((uint32_t)0x0000002CUL) /**< Offset from FLC Base Address: 0x002C */ #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ -#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: 0x0080 */ -#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: 0x0088 */ -#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: 0x0090 */ -#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: 0x0098 */ /**@} end of group flc_registers */ /** @@ -233,50 +221,6 @@ typedef struct { /**@} end of group FLC_ACTRL_Register */ -/** - * @ingroup flc_registers - * @defgroup FLC_WELR0 FLC_WELR0 - * @brief WELR0 - * @{ - */ -#define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ -#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ - -/**@} end of group FLC_WELR0_Register */ - -/** - * @ingroup flc_registers - * @defgroup FLC_WELR1 FLC_WELR1 - * @brief WELR1 - * @{ - */ -#define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ -#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ - -/**@} end of group FLC_WELR1_Register */ - -/** - * @ingroup flc_registers - * @defgroup FLC_RLR0 FLC_RLR0 - * @brief RLR0 - * @{ - */ -#define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ -#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ - -/**@} end of group FLC_RLR0_Register */ - -/** - * @ingroup flc_registers - * @defgroup FLC_RLR1 FLC_RLR1 - * @brief RLR1 - * @{ - */ -#define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ -#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ - -/**@} end of group FLC_RLR1_Register */ - #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 817963f7fc1..3b2350d72fc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -91,11 +91,13 @@ typedef struct { __IO uint32_t sysinten; /**< \b 0x54: GCR SYSINTEN Register */ __R uint32_t rsv_0x58_0x63[3]; __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ - __R uint32_t rsv_0x68; + __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ __IO uint32_t eccinten; /**< \b 0x6C: GCR ECCINTEN Register */ __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ __IO uint32_t btleldodly; /**< \b 0x78: GCR BTLELDODLY Register */ + __R uint32_t rsv_0x7c; + __IO uint32_t gpr; /**< \b 0x80: GCR GPR Register */ } mxc_gcr_regs_t; /* Register offsets for module GCR */ @@ -120,10 +122,12 @@ typedef struct { #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ #define MXC_R_GCR_SYSINTEN ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ #define MXC_R_GCR_ECCINTEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ #define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: 0x0078 */ +#define MXC_R_GCR_GPR ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: 0x0080 */ /**@} end of group gcr_registers */ /** @@ -191,9 +195,6 @@ typedef struct { #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ -#define MXC_F_GCR_RST0_BTLE_POS 18 /**< RST0_BTLE Position */ -#define MXC_F_GCR_RST0_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST0_BTLE_POS)) /**< RST0_BTLE Mask */ - #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ @@ -296,7 +297,7 @@ typedef struct { #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ -#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x9UL) /**< PM_MODE_BACKUP Value */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ #define MXC_V_GCR_PM_MODE_PDM ((uint32_t)0xAUL) /**< PM_MODE_PDM Value */ #define MXC_S_GCR_PM_MODE_PDM (MXC_V_GCR_PM_MODE_PDM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_PDM Setting */ @@ -427,6 +428,12 @@ typedef struct { #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ +#define MXC_F_GCR_RST1_AUTOCAL_POS 12 /**< RST1_AUTOCAL Position */ +#define MXC_F_GCR_RST1_AUTOCAL ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AUTOCAL_POS)) /**< RST1_AUTOCAL Mask */ + +#define MXC_F_GCR_RST1_BTLE_POS 18 /**< RST1_BTLE Position */ +#define MXC_F_GCR_RST1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS)) /**< RST1_BTLE Mask */ + /**@} end of group GCR_RST1_Register */ /** @@ -444,9 +451,6 @@ typedef struct { #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ -#define MXC_F_GCR_PCLKDIS1_SPI_POS 16 /**< PCLKDIS1_SPI Position */ -#define MXC_F_GCR_PCLKDIS1_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI_POS)) /**< PCLKDIS1_SPI Mask */ - #define MXC_F_GCR_PCLKDIS1_DMA1_POS 21 /**< PCLKDIS1_DMA1 Position */ #define MXC_F_GCR_PCLKDIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_DMA1_POS)) /**< PCLKDIS1_DMA1 Mask */ @@ -505,13 +509,24 @@ typedef struct { /**@} end of group GCR_ECCERR_Register */ +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCCED GCR_ECCCED + * @brief ECC Correctable Error Detect Register. + * @{ + */ +#define MXC_F_GCR_ECCCED_FLASH_POS 0 /**< ECCCED_FLASH Position */ +#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ + +/**@} end of group GCR_ECCCED_Register */ + /** * @ingroup gcr_registers * @defgroup GCR_ECCINTEN GCR_ECCINTEN * @brief ECC Interrupt Enable Register * @{ */ -#define MXC_F_GCR_ECCINTEN_FLASH_POS 11 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH_POS 0 /**< ECCINTEN_FLASH Position */ #define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ /**@} end of group GCR_ECCINTEN_Register */ @@ -548,47 +563,47 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_POS 0 /**< BTLELDOCTRL_TX_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_POS)) /**< BTLELDOCTRL_TX_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 0 /**< BTLELDOCTRL_RF_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS 1 /**< BTLELDOCTRL_TX_PD_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS)) /**< BTLELDOCTRL_TX_PD_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 1 /**< BTLELDOCTRL_RF_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS 2 /**< BTLELDOCTRL_TX_VSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS)) /**< BTLELDOCTRL_TX_VSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 2 /**< BTLELDOCTRL_RF_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_POS 4 /**< BTLELDOCTRL_RX_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_POS)) /**< BTLELDOCTRL_RX_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 4 /**< BTLELDOCTRL_BB_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS 5 /**< BTLELDOCTRL_RX_PD_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS)) /**< BTLELDOCTRL_RX_PD_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 5 /**< BTLELDOCTRL_BB_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS 6 /**< BTLELDOCTRL_RX_VSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS)) /**< BTLELDOCTRL_RX_VSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 6 /**< BTLELDOCTRL_BB_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS 8 /**< BTLELDOCTRL_RX_BP_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS)) /**< BTLELDOCTRL_RX_BP_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 8 /**< BTLELDOCTRL_BB_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS 9 /**< BTLELDOCTRL_RX_DISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS)) /**< BTLELDOCTRL_RX_DISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 9 /**< BTLELDOCTRL_BB_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS 10 /**< BTLELDOCTRL_TX_BP_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS)) /**< BTLELDOCTRL_TX_BP_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 10 /**< BTLELDOCTRL_RF_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS 11 /**< BTLELDOCTRL_TX_DISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS)) /**< BTLELDOCTRL_TX_DISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 11 /**< BTLELDOCTRL_RF_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS 12 /**< BTLELDOCTRL_TX_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS)) /**< BTLELDOCTRL_TX_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 12 /**< BTLELDOCTRL_RF_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS 13 /**< BTLELDOCTRL_RX_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS)) /**< BTLELDOCTRL_RX_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 13 /**< BTLELDOCTRL_BB_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RX_BP_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RX_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_TX_BP_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_TX_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -601,11 +616,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BP_CNT_POS 0 /**< BTLELDODLY_BP_CNT Position */ #define MXC_F_GCR_BTLELDODLY_BP_CNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BP_CNT_POS)) /**< BTLELDODLY_BP_CNT Mask */ -#define MXC_F_GCR_BTLELDODLY_RX_CNT_POS 8 /**< BTLELDODLY_RX_CNT Position */ -#define MXC_F_GCR_BTLELDODLY_RX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RX_CNT_POS)) /**< BTLELDODLY_RX_CNT Mask */ +#define MXC_F_GCR_BTLELDODLY_BB_CNT_POS 8 /**< BTLELDODLY_BB_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_BB_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_BB_CNT_POS)) /**< BTLELDODLY_BB_CNT Mask */ -#define MXC_F_GCR_BTLELDODLY_TX_CNT_POS 20 /**< BTLELDODLY_TX_CNT Position */ -#define MXC_F_GCR_BTLELDODLY_TX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_TX_CNT_POS)) /**< BTLELDODLY_TX_CNT Mask */ +#define MXC_F_GCR_BTLELDODLY_RF_CNT_POS 20 /**< BTLELDODLY_RF_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_RF_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RF_CNT_POS)) /**< BTLELDODLY_RF_CNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index 4a64475eb77..e7691d55499 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -84,8 +84,8 @@ typedef struct { __R uint32_t rsv_0x104_0x1ff[63]; __IO uint32_t way; /**< \b 0x0200: ICC WAY Register */ __IO uint32_t regctrl; /**< \b 0x0204: ICC REGCTRL Register */ - __IO mxc_icc_reg_regs_t region[15]; /**< \b 0x0208: ICC REGION Register */ - __R uint32_t rsv_0x244_0x2ff[47]; + __IO mxc_icc_reg_regs_t region[4]; /**< \b 0x0208: ICC REGION Register */ + __R uint32_t rsv_0x228_0x2ff[54]; __IO uint32_t pfmctrl; /**< \b 0x0300: ICC PFMCTRL Register */ __IO uint32_t pfmcnt; /**< \b 0x0304: ICC PFMCNT Register */ __R uint32_t rsv_0x308_0x6ff[254]; @@ -164,7 +164,13 @@ typedef struct { * @{ */ #define MXC_F_ICC_WAY_WAY_POS 0 /**< WAY_WAY Position */ -#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x1UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ +#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x7UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ +#define MXC_V_ICC_WAY_WAY_1 ((uint32_t)0x1UL) /**< WAY_WAY_1 Value */ +#define MXC_S_ICC_WAY_WAY_1 (MXC_V_ICC_WAY_WAY_1 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_1 Setting */ +#define MXC_V_ICC_WAY_WAY_2 ((uint32_t)0x2UL) /**< WAY_WAY_2 Value */ +#define MXC_S_ICC_WAY_WAY_2 (MXC_V_ICC_WAY_WAY_2 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_2 Setting */ +#define MXC_V_ICC_WAY_WAY_4 ((uint32_t)0x4UL) /**< WAY_WAY_4 Value */ +#define MXC_S_ICC_WAY_WAY_4 (MXC_V_ICC_WAY_WAY_4 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_4 Setting */ /**@} end of group ICC_WAY_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 7a0956884b3..33e54632702 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -123,11 +123,11 @@ typedef enum { BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ - BTLE_XXXX_IRQn, /* 0x3E 0x00F8 62: BTLE XXXX TODO(ME30): Verify BTLE IRQs */ + BTLE_RX_CRC_IRQn, /* 0x3E 0x00F8 62: BTLE RX CRC */ RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ - RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ + FRQCNT_IRQn, /* 0x42 0x0108 66: Frequency Counter */ RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ @@ -148,58 +148,80 @@ typedef enum { #define __SAUREGION_PRESENT 1U /**< Presence of FPU */ #define __TZ_PRESENT 1U /**< Presence of TrustZone */ #define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ -#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ #include +#include #include + +#if defined(__GNUC__) #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_SECURE_ENVIRONMENT 1 -#else -#define IS_SECURE_ENVIRONMENT 0 +// Type used for secure code to call non-secure code. +#define __ns_call __attribute((cmse_nonsecure_call)) +typedef void __ns_call (*mxc_ns_call_t) (void); +// Type used for non-secure code to call secure code. +#define __ns_entry __attribute((cmse_nonsecure_entry)) +#endif #endif /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ -/* Non-secure Regions */ -#define MXC_FLASH_NS_MEM_BASE 0x01000000UL -#define MXC_FLASH_NS_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_NS_MEM_SIZE 0x00100000UL -#define MXC_SRAM_NS_MEM_BASE 0x20000000UL -#define MXC_SRAM_NS_MEM_SIZE 0x00040000UL +/* Physical Memory Definitions */ +/* Bit 28 (security alias bit) of address is cleared. */ +#define MXC_PHY_FLASH_MEM_BASE 0x01000000UL +#define MXC_PHY_FLASH_MEM_SIZE 0x00100000UL +#define MXC_PHY_FLASH_PAGE_SIZE 0x00002000UL + +#define MXC_PHY_SRAM_MEM_BASE 0x20000000UL +#define MXC_PHY_SRAM_MEM_SIZE 0x00040000UL + +#define MXC_PHY_SRAM0_MEM_BASE 0x20000000UL +#define MXC_PHY_SRAM0_MEM_SIZE 0x00008000UL // 32KB +#define MXC_PHY_SRAM1_MEM_BASE 0x20008000UL +#define MXC_PHY_SRAM1_MEM_SIZE 0x00008000UL // 32KB +#define MXC_PHY_SRAM2_MEM_BASE 0x20010000UL +#define MXC_PHY_SRAM2_MEM_SIZE 0x00010000UL // 64KB +#define MXC_PHY_SRAM3_MEM_BASE 0x20020000UL +#define MXC_PHY_SRAM3_MEM_SIZE 0x00010000UL // 64KB +#define MXC_PHY_SRAM4_MEM_BASE 0x20030000UL +#define MXC_PHY_SRAM4_MEM_SIZE 0x00010000UL // 64KB + +/** + * Memory settings are defined accordingly by build system: max32657_memory.mk + * + * Definitions that start with the '__' are defined by the build system. + * For example, '__MXC_FLASH_MEM_BASE' + */ + +#if CONFIG_TRUSTED_EXECUTION_SECURE +/* Non-secure Regions that secure code knows about. */ +#define MXC_FLASH_NS_MEM_BASE __MXC_FLASH_NS_MEM_BASE +#define MXC_FLASH_NS_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE +#define MXC_FLASH_NS_MEM_SIZE __MXC_FLASH_NS_MEM_SIZE +#define MXC_SRAM_NS_MEM_BASE __MXC_SRAM_NS_MEM_BASE +#define MXC_SRAM_NS_MEM_SIZE __MXC_SRAM_NS_MEM_SIZE /* Secure Regions */ /* ROM is always in secure region. */ #define MXC_ROM_MEM_BASE 0x00000000UL #define MXC_ROM_MEM_SIZE 0x00010000UL -#define MXC_FLASH_S_MEM_BASE 0x11000000UL -#define MXC_FLASH_S_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_S_MEM_SIZE 0x00100000UL /* Flash info is always in secure region */ #define MXC_INFO_S_MEM_BASE 0x12000000UL #define MXC_INFO_S_MEM_SIZE 0x00004000UL -#define MXC_SRAM_S_MEM_BASE 0x30000000UL -#define MXC_SRAM_S_MEM_SIZE 0x00040000UL #define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE #define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE - -#if IS_SECURE_ENVIRONMENT -#define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE -#define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE -#define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE -#define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE -#define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE -#else -#define MXC_FLASH_MEM_BASE MXC_FLASH_NS_MEM_BASE -#define MXC_FLASH_PAGE_SIZE MXC_FLASH_NS_PAGE_SIZE -#define MXC_FLASH_MEM_SIZE MXC_FLASH_NS_MEM_SIZE -#define MXC_SRAM_MEM_BASE MXC_SRAM_NS_MEM_BASE -#define MXC_SRAM_MEM_SIZE MXC_SRAM_NS_MEM_SIZE #endif +#define MXC_FLASH_MEM_BASE __MXC_FLASH_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE __MXC_FLASH_MEM_SIZE +#define MXC_SRAM_MEM_BASE __MXC_SRAM_MEM_BASE +#define MXC_SRAM_MEM_SIZE __MXC_SRAM_MEM_SIZE + /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ @@ -219,7 +241,7 @@ typedef enum { #define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) #define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_GCR MXC_GCR_S #else #define MXC_GCR MXC_GCR_NS @@ -236,7 +258,7 @@ typedef enum { #define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) #define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_SIR MXC_BASE_SIR_S #define MXC_SIR MXC_SIR_S #else @@ -255,7 +277,7 @@ typedef enum { #define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) #define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_FCR MXC_BASE_FCR_S #define MXC_FCR MXC_FCR_S #else @@ -275,7 +297,7 @@ typedef enum { #define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) #define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_WDT MXC_BASE_WDT_S #define MXC_WDT MXC_WDT_S #else @@ -284,22 +306,22 @@ typedef enum { #endif /******************************************************************************/ -/* SVM Controller */ +/* RSTZ Controller */ /* Non-secure Mapping */ -#define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) -#define MXC_SVM_NS 0 //TODO(ME30): Add SVM controller registers. +#define MXC_BASE_RSTZ_NS ((uint32_t)0x40004800UL) +#define MXC_RSTZ_NS ((mxc_rstz_regs_t *)MXC_BASE_RSTZ_NS) /* Secure Mapping */ -#define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) -#define MXC_SVM_S 0 //TODO(ME30): Add SVM controller registers. +#define MXC_BASE_RSTZ_S ((uint32_t)0x50004800UL) +#define MXC_RSTZ_S ((mxc_rstz_regs_t *)MXC_BASE_RSTZ_S) -#if IS_SECURE_ENVIRONMENT -#define MXC_BASE_SVM MXC_BASE_SVM_S -#define MXC_SVM MXC_SVM_S //TODO(ME30): Add SVM controller registers +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_RSTZ MXC_BASE_RSTZ_S +#define MXC_RSTZ MXC_RSTZ_S //TODO(ME30): Add SVM controller registers #else -#define MXC_BASE_SVM MXC_BASE_SVM_NS -#define MXC_SVM MXC_SVM_NS +#define MXC_BASE_RSTZ MXC_BASE_RSTZ_NS +#define MXC_RSTZ MXC_RSTZ_NS #endif /******************************************************************************/ @@ -307,13 +329,13 @@ typedef enum { /* Non-secure Mapping */ #define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) -#define MXC_BOOST_NS 0 //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_NS ((mxc_boost_regs_t *)MXC_BASE_BOOST_NS) /* Secure Mapping */ #define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) -#define MXC_BOOST_S 0 //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_S ((mxc_boost_regs_t *)MXC_BASE_BOOST_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_BOOST MXC_BASE_BOOST_S #define MXC_BOOST MXC_BOOST_S #else @@ -332,7 +354,7 @@ typedef enum { #define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) #define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S #define MXC_TRIMSIR MXC_TRIMSIR_S #else @@ -351,7 +373,7 @@ typedef enum { #define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) #define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_RTC MXC_BASE_RTC_S #define MXC_RTC MXC_RTC_S #else @@ -375,7 +397,7 @@ typedef enum { #define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) #define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_WUT0 MXC_BASE_WUT0_S #define MXC_WUT0 MXC_WUT0_S #define MXC_BASE_WUT1 MXC_BASE_WUT1_S @@ -398,7 +420,7 @@ typedef enum { #define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) #define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S #define MXC_PWRSEQ MXC_PWRSEQ_S #else @@ -417,7 +439,7 @@ typedef enum { #define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) #define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_MCR MXC_BASE_MCR_S #define MXC_MCR MXC_MCR_S #else @@ -434,9 +456,9 @@ typedef enum { /* Secure Mapping */ #define MXC_BASE_AES_S ((uint32_t)0x50007400UL) -#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) +#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_AES MXC_BASE_AES_S #define MXC_AES MXC_AES_S #else @@ -455,7 +477,7 @@ typedef enum { #define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) #define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S #define MXC_AESKEYS MXC_AESKEYS_S #else @@ -479,7 +501,7 @@ typedef enum { #define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #define MXC_GPIO0 MXC_GPIO0_S #else @@ -509,7 +531,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) #define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_CRC MXC_BASE_CRC_S #define MXC_CRC MXC_CRC_S #else @@ -553,7 +575,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TMR5_S ((uint32_t)0x50015000UL) #define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_TMR0 MXC_TMR0_S #define MXC_TMR1 MXC_TMR1_S #define MXC_TMR2 MXC_TMR2_S @@ -611,14 +633,14 @@ We may want to handle GET_IRQ better... #define MXC_I3C_FIFO_DEPTH (8) /* Non-secure Mapping */ -#define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) +#define MXC_BASE_I3C_NS ((uint32_t)0x40018000UL) #define MXC_I3C_NS ((mxc_i3c_regs_t *)MXC_BASE_I3C_NS) /* Secure Mapping */ -#define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) +#define MXC_BASE_I3C_S ((uint32_t)0x50018000UL) #define MXC_I3C_S ((mxc_i3c_regs_t *)MXC_BASE_I3C_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_I3C MXC_BASE_I3C_S #define MXC_I3C MXC_I3C_S #else @@ -634,68 +656,66 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_DMA_INSTANCES (2) #else #define MXC_DMA_INSTANCES (1) #endif /* Non-secure Mapping */ +/* DMA0 Security Attribution hardwired to Non-Secure and not configurable via SPC. */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) #define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) /* Secure Mapping */ -// TODO(ME30): Is there actuall a secure mapping for DMA0? -// -Yes, DMA0 can be accessed from secure mode. Realizing this, I think -// we would still have to define two DMA instances. -// DMA0 can only access the non-secure mappings of the peripherals, -// but DMA0 can be accessed in both Non-secure and Secure code. -// DMA1 can access both secure and non-secure addresses of the peripherals, -// but DMA1 can Only be accessed in Secure code. -#define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) -#define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) +/* DMA1 Security Attribution hardwired to Secure and not configurable via SPC. */ #define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) #define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) -#if IS_SECURE_ENVIRONMENT -#define MXC_BASE_DMA0 MXC_BASE_DMA0_S -#define MXC_DMA0 MXC_DMA0_S +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S +/** + * MXC_DMA0 is not defined because DMA0 has no Secure mapping. + * Following ARM naming convention: if Secure world wants to access Non-Secure DMA (DMAO), + * then use MXC_DMA0_NS. Similar to how the Secure world accesses the Non-Secure MSP + * and VTOR registers using 'MSP_NS' and 'VTOR_NS', respectively. + */ +#ifdef MXC_DMA0 +#warning "Non-Secure DMA (DMA0) has no secure mapping. Please use MXC_DMA0_NS from Secure world." +#endif #define MXC_DMA_CH_GET_IRQ(p, i) \ - ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ - ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ - ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ - ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ - ((p) == MXC_DMA1 && (i) == 0) ? DMA1_CH0_IRQn : \ - ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \ - ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \ - ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \ + ((IRQn_Type)(((p) == MXC_DMA0_NS && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 3) ? DMA0_CH3_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 0) ? DMA1_CH0_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 1) ? DMA1_CH1_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 2) ? DMA1_CH2_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 3) ? DMA1_CH3_IRQn : \ 0)) #else #define MXC_BASE_DMA0 MXC_BASE_DMA0_NS #define MXC_DMA0 MXC_DMA0_NS -// TODO(DMA1): Not entirely show how to handle access to MXC_DMA1 in non-secure mode. -// A secure fault should be generated when non-secure code accesses -// a secure peripheral mapping, so it'd be best if a build time warning -// or error was thrown when using MXCX_DMA1. -#define MXC_BASE_DMA1 0 -#define MXC_DMA1 0 +/* MXC_DMA1 is not defined because Non-Secure Code can only access DMA0. */ +#if MXC_DMA1 +#warning "Secure DMA (DMA1) is not accessible from Non-Secure world." +#endif /* DMA1 IRQs not usable in Non-Secure state. */ #define MXC_DMA_CH_GET_IRQ(p, i) \ - ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ - ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ - ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ - ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ + ((IRQn_Type)(((p) == MXC_DMA0_NS && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 3) ? DMA0_CH3_IRQn : \ 0)) -#endif // IS_SECURE_ENVIRONMENT +#endif // CONFIG_TRUSTED_EXECUTION_SECURE -#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) +#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0_NS ? 0 : (p) == MXC_BASE_DMA1_S ? 1 : -1) -#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0_NS ? 0 : (p) == MXC_DMA1_S ? 1 : -1) /******************************************************************************/ /* Flash Controller */ @@ -740,7 +760,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_UART_S ((uint32_t)0x50042000UL) #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S #else @@ -767,7 +787,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) #define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_S #else @@ -791,7 +811,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) #define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) -#if IS_SECURE_ENVIRONMENT +#if CONFIG_TRUSTED_EXECUTION_SECURE #define MXC_BASE_TRNG MXC_BASE_TRNG_S #define MXC_TRNG MXC_TRNG_S #else @@ -800,64 +820,90 @@ We may want to handle GET_IRQ better... #endif /******************************************************************************/ -/* BTLE */ -// TODO(ME30): Verify with bluetooth team. This section does not exist in our prev -// bluetooth-supported parts. -/* Non-secure Mapping */ -#define MXC_BASE_BTLE_NS ((uint32_t)0x40050000UL) -#define MXC_BTLE_NS // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. - -/* Secure Mapping */ -#define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) -#define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. - -#if IS_SECURE_ENVIRONMENT -// TODO(ME30): Does this have registers? -#define MXC_BASE_BTLE MXC_BASE_BTLE_S -#define MXC_BTLE MXC_BTLE_S -#else -#define MXC_BASE_BTLE MXC_BASE_BTLE_NS -#define MXC_BTLE MXC_BTLE_NS -#endif +/* Non-Secure and Secure Privilege Controller (NSPC/SPC TZ) */ -/******************************************************************************/ -/* Secure Privilege Control (SPC TZ) */ +#if CONFIG_TRUSTED_EXECUTION_SECURE /* Secure Mapping Only */ #define MXC_BASE_SPC ((uint32_t)0x50090000UL) -#define MXC_SPC // TODO(ME30): Does this have registers? -#define MXC_SPC_S // TODO(ME30): Does this have registers? +#define MXC_SPC ((mxc_spc_regs_t *)MXC_BASE_SPC) +#define MXC_SPC_S MXC_SPC + +#endif + +/* Non-Secure Mapping Only */ +#define MXC_BASE_NSPC ((uint32_t)0x40090000UL) +#define MXC_NSPC ((mxc_nspc_regs_t *)MXC_BASE_NSPC) +#define MXC_NSPC_NS MXC_NSPC /******************************************************************************/ /* MPC */ /* Secure Mapping Only */ #define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) -#define MXC_MPC_SRAM0 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM0 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM0) #define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) -#define MXC_MPC_SRAM1 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM1 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM1) #define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) -#define MXC_MPC_SRAM2 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM2 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM2) #define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) -#define MXC_MPC_SRAM3 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM3 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM3) #define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) -#define MXC_MPC_SRAM4 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM4 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM4) #define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) -#define MXC_MPC_FLASH // TODO(ME30): Does this have registers? +#define MXC_MPC_FLASH ((mxc_mpc_regs_t *)MXC_BASE_MPC_FLASH) /* Added for consistency and explicitness */ #define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 -#define MXC_MPC_SRAM0_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM0_S MXC_MPC_SRAM0 #define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 -#define MXC_MPC_SRAM1_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM1_S MXC_MPC_SRAM1 #define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 -#define MXC_MPC_SRAM2_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM2_S MXC_MPC_SRAM2 #define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 -#define MXC_MPC_SRAM3_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM3_S MXC_MPC_SRAM3 #define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 -#define MXC_MPC_SRAM4_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM4_S MXC_MPC_SRAM4 #define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH -#define MXC_MPC_FLASH_S // TODO(ME30): Does this have registers? +#define MXC_MPC_FLASH_S MXC_MPC_FLASH + +/* Grab the index associated with each memory region. */ +#define MXC_MPC_GET_PHY_MEM_BASE(p) \ + ((p) == MXC_MPC_FLASH ? MXC_PHY_FLASH_MEM_BASE : \ + (p) == MXC_MPC_SRAM0 ? MXC_PHY_SRAM0_MEM_BASE : \ + (p) == MXC_MPC_SRAM1 ? MXC_PHY_SRAM1_MEM_BASE : \ + (p) == MXC_MPC_SRAM2 ? MXC_PHY_SRAM2_MEM_BASE : \ + (p) == MXC_MPC_SRAM3 ? MXC_PHY_SRAM3_MEM_BASE : \ + (p) == MXC_MPC_SRAM4 ? MXC_PHY_SRAM4_MEM_BASE : \ + 0) + +#define MXC_MPC_GET_PHY_MEM_SIZE(p) \ + ((p) == MXC_MPC_FLASH ? MXC_PHY_FLASH_MEM_SIZE : \ + (p) == MXC_MPC_SRAM0 ? MXC_PHY_SRAM0_MEM_SIZE : \ + (p) == MXC_MPC_SRAM1 ? MXC_PHY_SRAM1_MEM_SIZE : \ + (p) == MXC_MPC_SRAM2 ? MXC_PHY_SRAM2_MEM_SIZE : \ + (p) == MXC_MPC_SRAM3 ? MXC_PHY_SRAM3_MEM_SIZE : \ + (p) == MXC_MPC_SRAM4 ? MXC_PHY_SRAM4_MEM_SIZE : \ + 0) + +#define MXC_MPC_GET_IDX(p) \ + ((p) == MXC_MPC_FLASH ? 0 : \ + (p) == MXC_MPC_SRAM0 ? 0 : \ + (p) == MXC_MPC_SRAM1 ? 1 : \ + (p) == MXC_MPC_SRAM2 ? 2 : \ + (p) == MXC_MPC_SRAM3 ? 3 : \ + (p) == MXC_MPC_SRAM4 ? 4 : \ + -1) + +#define MXC_MPC_FLASH_GET_BASE(i) ((i) == 0 ? MXC_MPC_FLASH : 0) + +#define MXC_MPC_SRAM_GET_BASE(i) \ + ((i) == 0 ? MXC_MPC_SRAM0 : \ + (i) == 1 ? MXC_MPC_SRAM1 : \ + (i) == 2 ? MXC_MPC_SRAM2 : \ + (i) == 3 ? MXC_MPC_SRAM3 : \ + (i) == 4 ? MXC_MPC_SRAM4 : \ + 0) /******************************************************************************/ /* Bit Shifting */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 224e007b628..5643d3b4c73 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -25,7 +25,7 @@ AESKEYS AES Key Registers. - 0x40007800 + 0x50007800 0x00 0x400 @@ -86,7 +86,7 @@ AES AES Keys. - 0x40007400 + 0x50007400 0x00 0x400 @@ -293,10 +293,165 @@ + + BOOST + Boost Controller + 0x50004C00 + + 0x00 + 0x400 + registers + + + BOOST + 46 + + + + DISABLE + Boost Disable Register. + 0x000 + 32 + + + DIS + This bit allows softwaree to disable the boost regulator for the VDD18 supply. + [0:0] + read-write + + + + + VREGCTRL + Boost Voltage Regulator Control Register. + 0x004 + + + SET + Sets the target voltage for the boost regulator output. + [4:0] + read-write + + + + + IPEAK + Low Side FET Peak Current Register. + 0x008 + read-only + + + SET + Sets the peak current threshold for the regulator. + [2:0] + read-only + + + + + MAXTON + Maximum Low Side FET Time-On Register. + 0x00C + read-only + + + THD + Sets a threshold for when time-on out toggles. + [3:0] + read-only + + + + + ILOAD + Boost Cycle Count Register. + 0x010 + read-only + + + CNT + Indicates the last load cycle count value. + [7:0] + read-only + + + + + ALERT + Boost Cycle Count Alert Register. + 0x014 + + + THD + Determines the threshold for when the boost alert interruptis fired. + [7:0] + read-write + + + + + RDY + Boost Output Ready Register. + 0x018 + read-only + + + OUT + Indicates ready out status for boost regulator. + [0:0] + read-only + + + + + ZXCAL + Zero Cross Calibration Register. + 0x01C + read-only + + + VAL + Read back of auto-calibration values. + [4:0] + read-only + + + + + INTEN + Boost Alert Interrupt Enable Register. + 0x020 + read-write + + + ALERT + Boost alert enable/ + [0:0] + read-write + + + + + INTFL + Boost Alert Interrupt Status Register. + 0x024 + read-write + + + ALERT + Boost alert has occurred. + [0:0] + read-write + + + + + + CRC CRC Registers. - 0x4000F000 + 0x5000F000 0x00 0x1000 @@ -424,7 +579,7 @@ DMA DMA Controller Fully programmable, chaining capable DMA channels. - 0x40028000 + 0x50028000 32 0x00 @@ -432,20 +587,20 @@ registers - DMA0 - 28 + DMA0_CH0 + 32 - DMA1 - 29 + DMA0_CH1 + 33 - DMA2 - 30 + DMA0_CH2 + 34 - DMA3 - 31 + DMA0_CH3 + 35 @@ -620,46 +775,56 @@ Memory To Memory 0x00 + + SPIRX + SPI RX + 0x01 + UARTRX UART RX 0x04 - I3CRX - I3C RX + I3CRX_CONT + I3C RX Controller 0x07 - SPIRX - SPI RX - 0x0F + I3CRX_TARG + I3C RX Target + 0x08 AESRX AES RX 0x10 + + SPITX + SPI TX + 0x21 + UARTTX UART TX 0x24 - I3CTX + I3CTX_CONT I3C TX 0x27 + + I3CTX_TARG + I3C TX + 0x28 + CRCTX CRC TX 0x2C - - SPITX - SPI TX - 0x2F - AESTX AES TX @@ -1058,10 +1223,36 @@ + + DMA1 + DMA Controller Fully programmable, chaining capable DMA channels. 1 + 0x50035000 + + DMA1_CH0 + DMA1_CH0 + 36 + + + DMA1_CH1 + DMA1_CH1 + 37 + + + DMA1_CH2 + DMA1_CH2 + 38 + + + DMA1_CH3 + DMA1_CH3 + 39 + + + FCR Function Control Register. - 0x40000800 + 0x50000800 0x00 0x400 @@ -1069,20 +1260,20 @@ - FCTRL0 - Register 0. + CTRL + Function Control 0 Register. 0x00 read-write - BTLELDO_TX - BTLE LDO TX Trim. + BTLELDO_RF + BTLE LDO RF Trim. 0 5 - BTLELDO_RX - BTLE LDO RX Trim. + BTLELDO_BB + BTLE LDO BB Trim. 8 5 @@ -1125,13 +1316,13 @@ - FCTRL1 - Register 1. + AUTOCAL0 + Automatic Calibration 0 Register. 0x04 read-write - AC_EN + EN Auto-calibration Enable. 0 1 @@ -1149,7 +1340,7 @@ - AC_RUN + RUN Autocalibration Run. 1 1 @@ -1215,7 +1406,7 @@ 12 - AC_TRIM_OUT + TRIM_OUT IPO Auto Calibration Trim 23 9 @@ -1223,13 +1414,13 @@ - FCTRL2 - Register 2. + AUTOCAL1 + Automatic Calibration 1 Register. 0x08 read-write - AC_INIT_TRIM + INIT_TRIM IPO Trim Automatic Calibration Initial Trim. 0 9 @@ -1237,19 +1428,19 @@ - FCTRL3 - Register 3. + AUTOCAL2 + Automatic Calibration 2 Register. 0x0C read-write - AC_RUNTIME + RUNTIME IPO Trim Autocal Run Time 0 8 - AC_DIV + DIV IPO Trim Automatic Calibration Divide Factor. 8 13 @@ -1306,6 +1497,125 @@ + + INTFL + Interrupt Flag Register. + 0x1C + read-write + + + ERTOC_RDY + ERTCO 32K Ready. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Flag. + 1 + 1 + + + + + INTEN + Interrupt Enable Register. + 0x20 + read-write + + + ERTOC_RDY + ERTCO 32K Ready Interrupt Enable. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Enable. + 1 + 1 + + + + + FRQCNTCTRL + Frequency Counter Control Register. + 0x28 + read-write + + + START + Start Compare. + 0 + 1 + + + CMP_CLKSEL + Compared Clock Select. + 1 + 2 + + + RTC + RTC. + 0 + + + EXT_GPIO + External GPIO. + 2 + + + INRO + INRO. + 3 + + + + + + + FRQCNTCMP + Frequency Counter Compared Target Register. + 0x2C + read-write + + + TARGET + Compared Clock Target. + 0 + 14 + + + + + REFCLK + Reference Clock Result Register. + 0x30 + read-only + + + RESULT + Reference Clock Result. + 0 + 20 + + + + + CMPCLK + Compared Clock Result Register. + 0x34 + read-only + + + RESULT + Compared Clock Result. + 0 + 14 + + + @@ -1313,15 +1623,16 @@ FLC Flash Memory Control. FLSH_ - 0x40029000 + 0x50029000 0x00 0x400 registers - Flash_Controller - Flash Controller interrupt. + FLC + + FLC Interrupt. 23 @@ -1572,76 +1883,24 @@ + + + + + GCR + Global Control Registers. + 0x50000000 + + 0 + 0x400 + registers + + - WELR0 - WELR0 - 0x80 - - - WELR0 - Access control. - 0 - 32 - - - - - WELR1 - WELR1 - 0x88 - - - WELR1 - Access control. - 0 - 32 - - - - - RLR0 - RLR0 - 0x90 - - - RLR0 - Access control. - 0 - 32 - - - - - RLR1 - RLR1 - 0x98 - - - RLR1 - Access control. - 0 - 32 - - - - - - - - GCR - Global Control Registers. - 0x40000000 - - 0 - 0x400 - registers - - - - SYSCTRL - System Control. - 0x00 - 0xFFFFFFFE + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE ICC_FLUSH @@ -1788,12 +2047,6 @@ 17 1 - - BTLE - BTLE Reset. - 18 - 1 - TRNG TRNG Reset. @@ -2036,14 +2289,14 @@ 4 - active + ACTIVE Active Mode. 0 - backup + BACKUP Backup Mode. - 9 + 4 PDM @@ -2298,6 +2551,18 @@ 10 1 + + AUTOCAL + Auto calibration Reset. + 12 + 1 + + + BTLE + BTLE Reset. + 18 + 1 + @@ -2335,12 +2600,6 @@ 15 1 - - SPI - SPI Clock Disable - 16 - 1 - DMA1 DMA1 Clock Disable @@ -2432,6 +2691,19 @@ + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + ECCINTEN ECC Interrupt Enable Register @@ -2440,7 +2712,7 @@ FLASH ECC Flash0 Interrupt Enable. - 11 + 0 1 @@ -2494,86 +2766,86 @@ 0x74 - TX_EN - LDOTX enable. + RF_EN + LDO RF enable. 0 1 - TX_PD_EN - LDOTX Pull Down. + RF_PD_EN + LDO RF Pull Down. 1 1 - TX_VSEL - Voltage Selection for NFC LDO + RF_VSEL + Voltage Selection for RF LDO 2 2 - RX_EN - LDORX enable. + BB_EN + LDOBB enable. 4 1 - RX_PD_EN - LDORX Pull DOwn. + BB_PD_EN + LDO BB Pull DOwn. 5 1 - RX_VSEL - LDORX Voltage Setting. + BB_VSEL + LDO BB Voltage Setting. 6 2 - RX_BP_EN - LDORX Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 8 1 - RX_DISCH - LDORX Discharge. + BB_DISCH + LDO BB Discharge. 9 1 - TX_BP_EN - LDOTX Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 10 1 - TX_DISCH - LDOTX Discharge. + RF_DISCH + LDO RF Discharge. 11 1 - TX_EN_DLY - LDOTX Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 12 1 - RX_EN_DLY - LDORX Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 13 1 - RX_BP_EN_DLY - LDORX Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 14 1 - TX_BP_EN_DLY - LDOTX Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 15 1 @@ -2591,19 +2863,24 @@ 8 - RX_CNT - RX delay count. + BB_CNT + BB delay count. 8 9 - TX_CNT - TX delay count. + RF_CNT + RF delay count. 20 9 + + GPR + General Purpose Register 0. + 0x80 + @@ -2611,7 +2888,7 @@ GPIO0 Individual I/O for each GPIO GPIO - 0x40008000 + 0x50008000 0x00 0x1000 @@ -5771,10 +6048,10 @@ ICC Instruction Cache Controller Registers - 0x4002A000 + 0x5002A000 0x00 - 0x800 + 0x1000 registers @@ -5783,6 +6060,7 @@ Cache ID Register. 0x0000 read-only + 32 RELNUM @@ -5810,6 +6088,7 @@ 0x0004 read-only 0x00080008 + 32 CCH @@ -5829,6 +6108,7 @@ CTRL Cache Control and Status Register. 0x0100 + 32 EN @@ -5873,27 +6153,28 @@ WAY Cache Way Control Register. 0x0200 + 32 WAY Number of cache way, default is always 2. Allowed values are 1,2,4. 0 - 1 + 3 1 1 - 0 + 1 2 2 - 1 + 2 4 4 - 2 + 4 @@ -5903,6 +6184,7 @@ REGCTRL Regional Control Register. 0x0204 + 32 EN @@ -5919,17 +6201,19 @@ - 15 - 0x20 + 4 + 8 REGION[%s] Regional Low and High Bound Registers. icc_reg 0x0208 + 64 read-write LBOUND Regional Low Bound Register. 0x0000 + 32 BOUND @@ -5943,6 +6227,7 @@ HBOUND DMA Channel Status Register. 0x004 + 32 BOUND @@ -5957,6 +6242,7 @@ PFMCTRL Performance Control Register. 0x0300 + 32 EN @@ -5970,6 +6256,7 @@ PFMCNT Performance Counter Register. 0x0304 + 32 CNT @@ -5984,6 +6271,7 @@ Invalidate All Registers. 0x0700 read-write + 32 INVALID @@ -5999,7 +6287,7 @@ MCR Misc Control. - 0x40006C00 + 0x50006C00 0x00 0x400 @@ -6007,16 +6295,22 @@ - ECCEN - ECC Enable Register - 0x00 + RST + Reset Register. + 0x04 - FLASH - ECC Flash Enable. + BOOST + Reset BOOST Controller. 0 1 + + RSTZ + Reset RSTZ Controller. + 1 + 1 + @@ -6030,12 +6324,6 @@ 0 1 - - PDOWN_EN - Power Down Output Enable. - 1 - 1 - @@ -6044,92 +6332,61 @@ 0x10 - ERTCO_EN - Enable ERTCO 4KHz. - 3 - 1 + CLKSEL + Clock select for RTC, WUTs, and Timers. + 0 + 2 + + + ERTCO + ERTCO as clock source. + 0 + + + INRO + INRO as clock source. + 1 + + + EXTCLK + P0.12 div 8 as clock source. + 2 + + ERTCO_32KHZ_EN Enable ERTCO 32KHz while ERTCO_EN. - 5 - 1 - - - - - GPIO1_CTRL - GPIO1 Pin Control Register. - 0x20 - - - P1_0_OUT - GPIO1 Pin 0 Data Output. - 0 - 1 - - - P1_0_OUTEN - GPIO1 Pin 0 Output Enable. - 1 - 1 - - - P1_0_PUPEN - GPIO1 Pin 0 Pull-up Enable. - 2 - 1 - - - P1_0_IN - GPIO1 Pin 0 Input Status. 3 1 - P1_1_OUT - GPIO1 Pin 1 Data Output. - 4 - 1 - - - P1_1_OUTEN - GPIO1 Pin 1 Output Enable. + ERTCO_EN + Enable ERTCO 4KHz. 5 1 - - P1_1_PUPEN - GPIO1 Pin 1 Pull-up Enable. - 6 - 1 - - - P1_1_IN - GPIO1 Pin 1 Input Status. - 7 - 1 - - RTCTRIM - User RTC Trim Register. - 0x24 - - - X2 - RTC X2 Trim. - 0 - 5 - - - X1 - RTC X1 Trim. - 5 - 5 - - + BBREG0 + Battery Back Reg0. + 0x30 + + + BBREG1 + Battery Back Reg1. + 0x34 + + + BBDATA0 + Battery Back Data0 Register. + 0x40 + + + BBDATA1 + Battery Back Data1 Register. + 0x44 @@ -6137,7 +6394,7 @@ PWRSEQ Power Sequencer / Low Power Control Register. - 0x40006800 + 0x50006800 0x00 0x400 @@ -6156,37 +6413,55 @@ 5 - FAST - Fast mode. - 8 + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + RETLDO_EN + Retention LDO Enable. + 12 1 dis - Disabled. + Disable. 0 en - Enabled. + Enable. 1 - BG_DIS - Bandgap OFF. This controls the System Bandgap in DeepSleep mode. - 11 + LDO_EN_DLY + Core LDO Enable Delay. + 13 1 - on - Bandgap is always ON. + dis + Disable. 0 - off - Bandgap is OFF in DeepSleep mode (default). + en + Enable delay LDO power up to smooth LDO voltage drop. 1 @@ -6225,32 +6500,6 @@ - - LPWKFL1 - Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. - 0x0C - - - PINS - Wakeup Flags. - 0 - 12 - - - - - LPWKEN1 - Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. - 0x10 - - - PINS - Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. - 0 - 2 - - - LPPWST Low Power Peripheral Wakeup Status Register. @@ -6284,686 +6533,934 @@ - RTC - Real Time Clock and Alarm. - 0x40006000 + MPC + Memory Protection Controller. + 0x50091000 0x00 - 0x400 + 0x1000 registers - - RTC - RTC interrupt. - 3 - - SEC - RTC Second Counter. This register contains the 32-bit second counter. - 0x00 - 0x00000000 + CTRL + Control Register. + 0x0000 + 32 - SEC - Seconds Counter. + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. 0 32 - SSEC - RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. - 0x04 - 0x00000000 + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only - SSEC - Sub-Seconds Counter (12-bit). + SIZE + Block Size. 0 - 12 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 - TODA - Time-of-day Alarm. - 0x08 - 0x00000000 + BLK_IDX + Block Index Register. + 0x0018 - TOD_ALARM - Time-of-day Alarm. + IDX + Index value for accessing block-based lookup table. 0 - 20 + 32 - SSECA - RTC sub-second alarm. This register contains the reload value for the sub-second alarm. - 0x0C - 0x00000000 + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C - SSEC_ALARM - This register contains the reload value for the sub-second alarm. + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. 0 32 - CTRL - RTC Control Register. - 0x10 - 0x00000008 - 0xFFFFFF38 + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only - EN - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + MPC_IRQ + MPC IRQ triggered. 0 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + - TOD_ALARM_IE - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. - 1 + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR5 + Peripheral ID 5 Register. + 0x0FD4 + read-only + + + PIDR6 + Peripheral ID 6 Register. + 0x0FD8 + read-only + + + PIDR7 + Peripheral ID 6 Register. + 0x0FDC + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + CIDR0 + Component ID register. + 0x0FF0 + read-only + + + CIDR1 + Component ID register. + 0x0FF4 + read-only + + + CIDR2 + Component ID register. + 0x0FF8 + read-only + + + CIDR3 + Component ID register. + 0x0FFC + read-only + + + + + + MPC1 + Memory Protection Controller. 1 + 0x50092000 + + + + MPC2 + Memory Protection Controller. 2 + 0x50093000 + + + + MPC3 + Memory Protection Controller. 3 + 0x50094000 + + + + MPC4 + Memory Protection Controller. 4 + 0x50095000 + + + + MPC5 + Memory Protection Controller. 5 + 0x50096000 + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 - dis - Disable. - 0 + GCR + Privilege setting for GCR. + 0x01 - en - Enable. - 1 + SIR + Privilege setting for SIR. + 0x02 - - - - SSEC_ALARM_IE - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. - 2 - 1 - - dis - Disable. - 0 + FCR + Privilege setting for FCR. + 0x04 - en - Enable. - 1 + WDT + Privilege setting for WDT. + 0x08 - - - - BUSY - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. - 3 - 1 - read-only - - idle - Idle. - 0 + AES + Privilege setting for AES. + 0x010 - busy - Busy. - 1 + AESKEYS + Privilege setting for AESKEYS. + 0x020 - - - - RDY - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. - 4 - 1 - - busy - Register has not updated. - 0 + CRC + Privilege setting for CRC. + 0x040 - ready - Ready. - 1 + GPIO0 + Privilege setting for GPIO0. + 0x080 - - - - RDY_IE - RTC Ready Interrupt Enable. - 5 - 1 - - dis - Disable. - 0 + TMR0 + Privilege setting for TMR0. + 0x0100 - en - Enable. - 1 + TMR1 + Privilege setting for TMR1. + 0x0200 - - - - TOD_ALARM_IF - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. - 6 - 1 - read-only - - inactive - Not active. - 0 + TMR2 + Privilege setting for TMR2. + 0x0400 - pending - Active. - 1 + TMR3 + Privilege setting for TMR3. + 0x0800 - - - - SSEC_ALARM_IF - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. - 7 - 1 - read-only - - inactive - Not active. - 0 + TMR4 + Privilege setting for TMR4. + 0x01000 - pending - Active. - 1 + TMR5 + Privilege setting for TMR5. + 0x02000 - - - - SQW_EN - Square Wave Output Enable. - 8 - 1 - - dis - Disable. - 0 + I3C + Privilege setting for I3C. + 0x04000 - en - Enable. - 1 + UART + Privilege setting for UART. + 0x08000 - - - - SQW_SEL - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. - 9 - 2 - - freq1Hz - 1 Hz (Compensated). - 0 + SPI + Privilege setting for SPI. + 0x010000 - freq512Hz - 512 Hz (Compensated). - 1 + TRNG + Privilege setting for TRNG. + 0x020000 - freq4KHz - 4 KHz. - 2 + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 - - - - RD_EN - Asynchronous Counter Read Enable. - 14 - 1 - - sync - Synchronous. - 0 + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 - async - Asynchronous. - 1 + RSTZ + Privilege setting for RSTZ. + 0x0100000 - - - - WR_EN - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. - 15 - 1 - - ignore - Ignored. - 0 + BOOST + Privilege setting for Boost Controller. + 0x0200000 - allow - Allowed. - 1 + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 - - - - - - TRIM - RTC Trim Register. - 0x14 - 0x00000000 - - - TRIM - RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. - 0 - 8 - - - VBAT_TMR - VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. - 8 - 24 - - - - - OSCCTRL - RTC Oscillator Control Register. - 0x18 - 0x00000000 - - - FILTER_EN - Enable Filter. - 0 - 1 - - - IBIAS_SEL - IBIAS Select. - 1 - 1 - - 2x - 2x - 0 + RTC + Privilege setting for RTC. + 0x01000000 - 4x - 4x - 1 + WUT0 + Privilege setting for WUT0. + 0x02000000 - - - - HYST_EN - RTC Hysteresis Enable. - 2 - 1 - - - IBIAS_EN - RTC IBIAS Enable. - 3 - 1 - - - BYPASS - RTC Crystal Bypass - 4 - 1 - - dis - Disable. - 0 + WUT1 + Privilege setting for WUT1. + 0x04000000 - en - Enable. - 1 + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 - - - - SQW_32K - RTC 32kHz Square Wave Output - 5 - 1 - - dis - Disable. - 0 + MCR + Privilege setting for MCR. + 0x10000000 - en - Enable. - 1 + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + - SEMA - The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. - The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software - architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be - - modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. - 0x4003E000 + RSTZ + RSTZ Controller + 0x50004800 0x00 - 0x1000 + 0x400 registers - 8 - 4 - SEMAPHORES[%s] - Read to test and set, returns prior value. Write 0 to clear semaphore. - 0x00 + CTRL + RSTZ Control Register. + 0x000 32 - sema - 0 - 1 + EN + Enable channels. + [0:0] + read-write + + + SVC_EN + Enable the SVC. + [1:1] + read-write + + + CH_SEL + Channel Select. + [4:2] + read-write + + + CAL_EN + Calibration mode enable. + [5:5] + read-write + + + DMEASURE_EN + Direct Measure mode enable. + [6:6] + read-write + + + OFFTR_P + Offset Trim for positive comparator. + [11:7] + read-write + + + OFFTR_N + Offset Trim for negative comparator. + [16:12] + read-write + + + DOUT + Comparator Result. + [17:17] + read-write + + + CAL_DOUT_POL + Calibration DOUT Polarity. + [18:18] + read-write + + + NUM_SAMP + Number of captures per sample. + [27:24] + read-write + + + TRIP_TOL + Number of failed DOUT captures (tolerance) before corresponding RSTZ signal is tripped. + [31:28] + read-write - irq0 - Semaphore IRQ0 register. - 0x40 - 32 + BOOST_CLKCTRL + Boost Clock Control Register. + 0x004 - en - 0 - 1 + EXIT_NUM_SAMP + Defines how many samples needed of boost output channel to perform when exiting low-power mode before returning to normal active operation. + [1:0] + read-write - cm4_irq - 16 - 1 + CH_SEL + Select when channel the output of the boost converter is monitored on. + [4:2] + read-write - mail0 - Semaphore Mailbox 0 register. - 0x44 + 8 + 4 + STATUS_CH[%s] + Channel X Status Register. + 0x028 32 + read-write - data + RSTZ + Result of most recent sample result. + [0:0] + read-only + + + DOUT + Store the most recent DOUT capture for a given channel. + [1:1] + read-only + + + RSTZ_FL + RSTZ Flag indicates the RSTZ was tripped at some point since the last time being cleared. + [31:31] + read-write + + + + + + + + RTC + Real Time Clock and Alarm. + 0x50006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. 0 32 - irq1 - Semaphore IRQ1 register. - 0x48 - 32 + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 - en + SSEC + Sub-Seconds Counter (12-bit). 0 - 1 + 12 + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + - rv32_irq - 16 - 1 + TOD_ALARM + Time-of-day Alarm. + 0 + 20 - mail1 - Semaphore Mailbox 1 register. - 0x4C - 32 + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 - data + SSEC_ALARM + This register contains the reload value for the sub-second alarm. 0 32 - status - Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. - 0x100 - 32 + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 - status0 + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. 0 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - status1 + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 1 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - status2 + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. 2 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - status3 + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. 3 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + - status4 + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. 4 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + - status5 + RDY_IE + RTC Ready Interrupt Enable. 5 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - status6 + TOD_ALARM_IF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 6 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + - status7 - 7 - 1 - - - - - - - - SIMO - Single Inductor Multiple Output Switching Converter - 0x40004400 - - 0x00 - 0x400 - registers - - - - VREGO_A - Buck Voltage Regulator A Control Register - 0x0004 - read-write - - - VSETA - Regulator Output Voltage Setting - 0 - 7 - - - RANGEA - Regulator Output Range Set + SSEC_ALARM_IF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. 7 1 + read-only - low - Low output voltage range + inactive + Not active. 0 - high - High output voltage range + pending + Active. 1 - - - - VREGO_B - Buck Voltage Regulator B Control Register - 0x0008 - read-write - - - VSETB - Regulator Output Voltage Setting - 0 - 7 - - RANGEB - Regulator Output Range Set - 7 + SQW_EN + Square Wave Output Enable. + 8 1 - low - Low output voltage range + dis + Disable. 0 - high - High output voltage range + en + Enable. 1 - - - - VREGO_C - Buck Voltage Regulator C Control Register - 0x000C - read-write - - VSETC - Regulator Output Voltage Setting - 0 - 7 + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + - RANGEC - Regulator Output Range Set - 7 + RD_EN + Asynchronous Counter Read Enable. + 14 1 - low - Low output voltage range + sync + Synchronous. 0 - high - High output voltage range + async + Asynchronous. 1 - - - - VREGO_D - Buck Voltage Regulator D Control Register - 0x0010 - read-write - - - VSETD - Regulator Output Voltage Setting - 0 - 7 - - RANGED - Regulator Output Range Set - 7 + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 1 - low - Low output voltage range + ignore + Ignored. 0 - high - High output voltage range + allow + Allowed. 1 @@ -6971,269 +7468,103 @@ - IPKA - High Side FET Peak Current VREGO_A/VREGO_B Register - 0x0014 - read-write - - - IPKSETA - Voltage Regulator Peak Current Setting - 0 - 4 - - - IPKSETB - Voltage Regulator Peak Current Setting - 4 - 4 - - - - - IPKB - High Side FET Peak Current VREGO_C/VREGO_D Register - 0x0018 - read-write - - - IPKSETC - Voltage Regulator Peak Current Setting - 0 - 4 - - - IPKSETD - Voltage Regulator Peak Current Setting - 4 - 4 - - - - - MAXTON - Maximum High Side FET Time On Register - 0x001C - read-write - - - TONSET - Sets the maximum on time for the high side FET, each increment represents 500ns - 0 - 4 - - - - - ILOAD_A - Buck Cycle Count VREGO_A Register - 0x0020 - read-only - - - ILOADA - Number of buck cycles that occur within the cycle clock - 0 - 8 - - - - - ILOAD_B - Buck Cycle Count VREGO_B Register - 0x0024 - read-only + TRIM + RTC Trim Register. + 0x14 + 0x00000000 - ILOADB - Number of buck cycles that occur within the cycle clock + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. 0 8 - - - - ILOAD_C - Buck Cycle Count VREGO_C Register - 0x0028 - read-only - - ILOADC - Number of buck cycles that occur within the cycle clock - 0 - 8 + VBAT_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 - ILOAD_D - Buck Cycle Count VREGO_D Register - 0x002C - read-only + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 - ILOADD - Number of buck cycles that occur within the cycle clock + FILTER_EN + Enable Filter. 0 - 8 + 1 - - - - BUCK_ALERT_THR_A - Buck Cycle Count Alert VERGO_A Register - 0x0030 - read-write - - BUCKTHRA - Threshold for ILOADA to generate the BUCK_ALERT - 0 - 8 + IBIAS_SEL + IBIAS Select. + 1 + 1 + + + 2x + 2x + 0 + + + 4x + 4x + 1 + + - - - - BUCK_ALERT_THR_B - Buck Cycle Count Alert VERGO_B Register - 0x0034 - read-write - - BUCKTHRB - Threshold for ILOADB to generate the BUCK_ALERT - 0 - 8 + HYST_EN + RTC Hysteresis Enable. + 2 + 1 - - - - BUCK_ALERT_THR_C - Buck Cycle Count Alert VERGO_C Register - 0x0038 - read-write - - BUCKTHRC - Threshold for ILOADC to generate the BUCK_ALERT - 0 - 8 + IBIAS_EN + RTC IBIAS Enable. + 3 + 1 - - - - BUCK_ALERT_THR_D - Buck Cycle Count Alert VERGO_D Register - 0x003C - read-write - - BUCKTHRD - Threshold for ILOADD to generate the BUCK_ALERT - 0 - 8 + BYPASS + RTC Crystal Bypass + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - - - - BUCK_OUT_READY - Buck Regulator Output Ready Register - 0x0040 - read-only - - BUCKOUTRDYA - When set, indicates that the output voltage has reached its regulated value - 0 + SQW_32K + RTC 32kHz Square Wave Output + 5 1 - notrdy - Output voltage not in range + dis + Disable. 0 - rdy - Output voltage in range + en + Enable. 1 - - BUCKOUTRDYB - When set, indicates that the output voltage has reached its regulated value - 1 - 1 - - - BUCKOUTRDYC - When set, indicates that the output voltage has reached its regulated value - 2 - 1 - - - BUCKOUTRDYD - When set, indicates that the output voltage has reached its regulated value - 3 - 1 - - - - - ZERO_CROSS_CAL_A - Zero Cross Calibration VERGO_A Register - 0x0044 - read-only - - - ZXCALA - Zero Cross Calibrartion Value VREGO_A - 0 - 4 - - - - - ZERO_CROSS_CAL_B - Zero Cross Calibration VERGO_B Register - 0x0048 - read-only - - - ZXCALB - Zero Cross Calibrartion Value VREGO_B - 0 - 4 - - - - - ZERO_CROSS_CAL_C - Zero Cross Calibration VERGO_C Register - 0x004C - read-only - - - ZXCALC - Zero Cross Calibrartion Value VREGO_C - 0 - 4 - - - - - ZERO_CROSS_CAL_D - Zero Cross Calibration VERGO_D Register - 0x0050 - read-only - - - ZXCALD - Zero Cross Calibrartion Value VREGO_D - 0 - 4 - @@ -7242,7 +7573,7 @@ SIR System Initialization Registers. - 0x40000400 + 0x50000400 read-only 0x00 @@ -7253,7 +7584,7 @@ SISTAT System Initialization Status Register. - 0x00 + 0x000 read-only @@ -7301,7 +7632,7 @@ ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). - 0x04 + 0x004 read-only @@ -7311,6 +7642,32 @@ + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + SFSTAT Security function status register. @@ -7470,7 +7827,7 @@ APBPPC Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -7484,7 +7841,7 @@ APBPPC Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -7497,7 +7854,7 @@ APBPPC Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -7554,18 +7911,6 @@ Lock Security Attribution Unit (SAU). 4 1 - - - DIS - TX DMA requests are disabled, andy pending DMA requests are cleared. - 0 - - - en - TX DMA requests are enabled. - 1 - - @@ -7579,6 +7924,153 @@ Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. 0 32 + + + GCR + Security Access for GCR. + 0x01 + + + SIR + Security Access for SIR. + 0x02 + + + FCR + Security Access for FCR. + 0x04 + + + WDT + Security Access for WDT. + 0x08 + + + AES + Security Access for AES. + 0x010 + + + AESKEYS + Security Access for AESKEYS. + 0x020 + + + CRC + Security Access for CRC. + 0x040 + + + GPIO0 + Security Access for GPIO0. + 0x080 + + + TMR0 + Security Access for TMR0. + 0x0100 + + + TMR1 + Security Access for TMR1. + 0x0200 + + + TMR2 + Security Access for TMR2. + 0x0400 + + + TMR3 + Security Access for TMR3. + 0x0800 + + + TMR4 + Security Access for TMR4. + 0x01000 + + + TMR5 + Security Access for TMR5. + 0x02000 + + + I3C + Security Access for I3C. + 0x04000 + + + UART + Security Access for UART. + 0x08000 + + + SPI + Security Access for SPI. + 0x010000 + + + TRNG + Security Access for TRNG. + 0x020000 + + + BTLE_DBB + Security Access for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Security Access for BTLE RFFE. + 0x080000 + + + RSTZ + Security Access for RSTZ. + 0x0100000 + + + BOOST + Security Access for Boost Controller. + 0x0200000 + + + TRIMSIR + Security Access for TRIMSIR. + 0x0400000 + + + RTC + Security Access for RTC. + 0x01000000 + + + WUT0 + Security Access for WUT0. + 0x02000000 + + + WUT1 + Security Access for WUT1. + 0x04000000 + + + PWRSEQ + Security Access for Power Sequencer. + 0x08000000 + + + MCR + Security Access for MCR. + 0x10000000 + + + ALL + Security Access for all peripherals. + 0x1F7FFFFF + + @@ -7592,58 +8084,179 @@ Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. 0 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + - GPIO0 - Secure GPIO0 Configuration Register. - 0x0180 + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 - PINS - Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + DMA + Controls access of transactions coming from the Secure DMA. 0 - 12 + 1 - GPIO1 - Secure GPIO1 Configuration Register. - 0x0184 + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 PINS - Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. - 0 - 2 - - - - - - - - NSPC - Non-Secure Privilege Controller. - 0x40090000 - - 0x00 - 0x1000 - registers - - - - APBPRIV - APB Tartet Privileged/Non-privileged PPC Access Register. - 0x0160 - - - PERIPH - Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + Each bit configures a GPIO pin as secure or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. 0 - 32 + 14 @@ -7653,7 +8266,7 @@ SPI SPI peripheral. - 0x400BE000 + 0x500BE000 0x00 0x1000 @@ -7740,7 +8353,7 @@ - CTRLR_MODE + CONT_MODE Controller Mode Enable. 1 1 @@ -8407,7 +9020,7 @@ - CTRLR_DONE + CONT_DONE Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -8624,7 +9237,7 @@ - CTRLR_DONE + CONT_DONE Controller Done interrupt enable. 11 1 @@ -8887,7 +9500,7 @@ TMR Low-Power Configurable Timer - 0x40010000 + 0x50010000 0x00 0x1000 @@ -9544,7 +10157,7 @@ TMR1 Low-Power Configurable Timer 1 - 0x40011000 + 0x50011000 TMR1 TMR1 IRQ @@ -9555,7 +10168,7 @@ TMR2 Low-Power Configurable Timer 2 - 0x40012000 + 0x50012000 TMR2 TMR2 IRQ @@ -9566,7 +10179,7 @@ TMR3 Low-Power Configurable Timer 3 - 0x40013000 + 0x50013000 TMR3 TMR3 IRQ @@ -9577,7 +10190,7 @@ TMR4 Low-Power Configurable Timer 4 - 0x40080C00 + 0x50080C00 TMR4 TMR4 IRQ @@ -9588,7 +10201,7 @@ TMR5 Low-Power Configurable Timer 5 - 0x40081000 + 0x50081000 TMR5 TMR5 IRQ @@ -9599,7 +10212,7 @@ TRIMSIR Trim System Initilazation Registers - 0x40005400 + 0x50005400 0x00 0x400 @@ -9777,7 +10390,7 @@ TRNG Random Number Generator. - 0x4004D000 + 0x5004D000 0x00 0x1000 @@ -10123,7 +10736,7 @@ UART UART Low Power Registers - 0x40042000 + 0x50042000 0x00 0x1000 @@ -10236,25 +10849,15 @@ 2 - Peripheral_Clock - apb clock + PERIPHERAL_CLOCK + APB Clock. 0 - External_Clock - Clock 1 + CLK1 + IBRO clock. 1 - - CLK2 - Clock 2 - 2 - - - CLK3 - Clock 3 - 3 - @@ -10602,7 +11205,7 @@ WDT Windowed Watchdog Timer - 0x40003000 + 0x50003000 0x00 0x0400 @@ -11193,7 +11796,7 @@ WUT 32-bit reloadable timer that can be used for timing and wakeup. - 0x40006400 + 0x50006400 0x00 0x400 @@ -11449,4 +12052,4 @@ - + \ No newline at end of file diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index e019ecbf94b..0334c6801eb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -72,14 +72,17 @@ extern "C" { * Structure type to access the MCR Registers. */ typedef struct { - __IO uint32_t eccen; /**< \b 0x00: MCR ECCEN Register */ - __R uint32_t rsv_0x4; + __R uint32_t rsv_0x0; + __IO uint32_t rst; /**< \b 0x04: MCR RST Register */ __IO uint32_t outen; /**< \b 0x08: MCR OUTEN Register */ __R uint32_t rsv_0xc; __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ - __R uint32_t rsv_0x14_0x1f[3]; - __IO uint32_t gpio1_ctrl; /**< \b 0x20: MCR GPIO1_CTRL Register */ - __IO uint32_t rtctrim; /**< \b 0x24: MCR RTCTRIM Register */ + __R uint32_t rsv_0x14_0x2f[7]; + __IO uint32_t bbreg0; /**< \b 0x30: MCR BBREG0 Register */ + __IO uint32_t bbreg1; /**< \b 0x34: MCR BBREG1 Register */ + __R uint32_t rsv_0x38_0x3f[2]; + __IO uint32_t bbdata0; /**< \b 0x40: MCR BBDATA0 Register */ + __IO uint32_t bbdata1; /**< \b 0x44: MCR BBDATA1 Register */ } mxc_mcr_regs_t; /* Register offsets for module MCR */ @@ -89,23 +92,28 @@ typedef struct { * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. * @{ */ -#define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: 0x0000 */ +#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ -#define MXC_R_MCR_GPIO1_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: 0x0020 */ -#define MXC_R_MCR_RTCTRIM ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: 0x0024 */ +#define MXC_R_MCR_BBREG0 ((uint32_t)0x00000030UL) /**< Offset from MCR Base Address: 0x0030 */ +#define MXC_R_MCR_BBREG1 ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: 0x0034 */ +#define MXC_R_MCR_BBDATA0 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: 0x0040 */ +#define MXC_R_MCR_BBDATA1 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: 0x0044 */ /**@} end of group mcr_registers */ /** * @ingroup mcr_registers - * @defgroup MCR_ECCEN MCR_ECCEN - * @brief ECC Enable Register + * @defgroup MCR_RST MCR_RST + * @brief Reset Register. * @{ */ -#define MXC_F_MCR_ECCEN_FLASH_POS 0 /**< ECCEN_FLASH Position */ -#define MXC_F_MCR_ECCEN_FLASH ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FLASH_POS)) /**< ECCEN_FLASH Mask */ +#define MXC_F_MCR_RST_BOOST_POS 0 /**< RST_BOOST Position */ +#define MXC_F_MCR_RST_BOOST ((uint32_t)(0x1UL << MXC_F_MCR_RST_BOOST_POS)) /**< RST_BOOST Mask */ -/**@} end of group MCR_ECCEN_Register */ +#define MXC_F_MCR_RST_RSTZ_POS 1 /**< RST_RSTZ Position */ +#define MXC_F_MCR_RST_RSTZ ((uint32_t)(0x1UL << MXC_F_MCR_RST_RSTZ_POS)) /**< RST_RSTZ Mask */ + +/**@} end of group MCR_RST_Register */ /** * @ingroup mcr_registers @@ -116,9 +124,6 @@ typedef struct { #define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0 /**< OUTEN_SQWOUT_EN Position */ #define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) /**< OUTEN_SQWOUT_EN Mask */ -#define MXC_F_MCR_OUTEN_PDOWN_EN_POS 1 /**< OUTEN_PDOWN_EN Position */ -#define MXC_F_MCR_OUTEN_PDOWN_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_EN_POS)) /**< OUTEN_PDOWN_EN Mask */ - /**@} end of group MCR_OUTEN_Register */ /** @@ -127,59 +132,22 @@ typedef struct { * @brief Control Register * @{ */ -#define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ -#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ - -#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS 5 /**< CTRL_ERTCO_32KHZ_EN Position */ +#define MXC_F_MCR_CTRL_CLKSEL_POS 0 /**< CTRL_CLKSEL Position */ +#define MXC_F_MCR_CTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ +#define MXC_V_MCR_CTRL_CLKSEL_ERTCO ((uint32_t)0x0UL) /**< CTRL_CLKSEL_ERTCO Value */ +#define MXC_S_MCR_CTRL_CLKSEL_ERTCO (MXC_V_MCR_CTRL_CLKSEL_ERTCO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ERTCO Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_INRO ((uint32_t)0x1UL) /**< CTRL_CLKSEL_INRO Value */ +#define MXC_S_MCR_CTRL_CLKSEL_INRO (MXC_V_MCR_CTRL_CLKSEL_INRO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_INRO Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_EXTCLK ((uint32_t)0x2UL) /**< CTRL_CLKSEL_EXTCLK Value */ +#define MXC_S_MCR_CTRL_CLKSEL_EXTCLK (MXC_V_MCR_CTRL_CLKSEL_EXTCLK << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_EXTCLK Setting */ + +#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS 3 /**< CTRL_ERTCO_32KHZ_EN Position */ #define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS)) /**< CTRL_ERTCO_32KHZ_EN Mask */ -/**@} end of group MCR_CTRL_Register */ - -/** - * @ingroup mcr_registers - * @defgroup MCR_GPIO1_CTRL MCR_GPIO1_CTRL - * @brief GPIO1 Pin Control Register. - * @{ - */ -#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUT_POS 0 /**< GPIO1_CTRL_P1_0_OUT Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_OUT_POS)) /**< GPIO1_CTRL_P1_0_OUT Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN_POS 1 /**< GPIO1_CTRL_P1_0_OUTEN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN_POS)) /**< GPIO1_CTRL_P1_0_OUTEN Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN_POS 2 /**< GPIO1_CTRL_P1_0_PUPEN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN_POS)) /**< GPIO1_CTRL_P1_0_PUPEN Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_0_IN_POS 3 /**< GPIO1_CTRL_P1_0_IN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_0_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_IN_POS)) /**< GPIO1_CTRL_P1_0_IN Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUT_POS 4 /**< GPIO1_CTRL_P1_1_OUT Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_OUT_POS)) /**< GPIO1_CTRL_P1_1_OUT Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN_POS 5 /**< GPIO1_CTRL_P1_1_OUTEN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN_POS)) /**< GPIO1_CTRL_P1_1_OUTEN Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN_POS 6 /**< GPIO1_CTRL_P1_1_PUPEN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN_POS)) /**< GPIO1_CTRL_P1_1_PUPEN Mask */ - -#define MXC_F_MCR_GPIO1_CTRL_P1_1_IN_POS 7 /**< GPIO1_CTRL_P1_1_IN Position */ -#define MXC_F_MCR_GPIO1_CTRL_P1_1_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_IN_POS)) /**< GPIO1_CTRL_P1_1_IN Mask */ - -/**@} end of group MCR_GPIO1_CTRL_Register */ - -/** - * @ingroup mcr_registers - * @defgroup MCR_RTCTRIM MCR_RTCTRIM - * @brief User RTC Trim Register. - * @{ - */ -#define MXC_F_MCR_RTCTRIM_X2_POS 0 /**< RTCTRIM_X2 Position */ -#define MXC_F_MCR_RTCTRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X2_POS)) /**< RTCTRIM_X2 Mask */ - -#define MXC_F_MCR_RTCTRIM_X1_POS 5 /**< RTCTRIM_X1 Position */ -#define MXC_F_MCR_RTCTRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X1_POS)) /**< RTCTRIM_X1 Mask */ +#define MXC_F_MCR_CTRL_ERTCO_EN_POS 5 /**< CTRL_ERTCO_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ -/**@} end of group MCR_RTCTRIM_Register */ +/**@} end of group MCR_CTRL_Register */ #ifdef __cplusplus } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h new file mode 100644 index 00000000000..5944ce49d4e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h @@ -0,0 +1,280 @@ +/** + * @file mpc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @note This file is @generated. + * @ingroup mpc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup mpc + * @defgroup mpc_registers MPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @details Memory Protection Controller. + */ + +/** + * @ingroup mpc_registers + * Structure type to access the MPC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: MPC CTRL Register */ + __R uint32_t rsv_0x4_0xf[3]; + __I uint32_t blk_max; /**< \b 0x0010: MPC BLK_MAX Register */ + __I uint32_t blk_cfg; /**< \b 0x0014: MPC BLK_CFG Register */ + __IO uint32_t blk_idx; /**< \b 0x0018: MPC BLK_IDX Register */ + __IO uint32_t blk_lut; /**< \b 0x001C: MPC BLK_LUT Register */ + __I uint32_t int_stat; /**< \b 0x0020: MPC INT_STAT Register */ + __O uint32_t int_clear; /**< \b 0x0024: MPC INT_CLEAR Register */ + __IO uint32_t int_en; /**< \b 0x0028: MPC INT_EN Register */ + __I uint32_t int_info1; /**< \b 0x002C: MPC INT_INFO1 Register */ + __I uint32_t int_info2; /**< \b 0x0030: MPC INT_INFO2 Register */ + __O uint32_t int_set; /**< \b 0x0034: MPC INT_SET Register */ + __R uint32_t rsv_0x38_0xfcf[998]; + __I uint32_t pidr4; /**< \b 0x0FD0: MPC PIDR4 Register */ + __I uint32_t pidr5; /**< \b 0x0FD4: MPC PIDR5 Register */ + __I uint32_t pidr6; /**< \b 0x0FD8: MPC PIDR6 Register */ + __I uint32_t pidr7; /**< \b 0x0FDC: MPC PIDR7 Register */ + __I uint32_t pidr0; /**< \b 0x0FE0: MPC PIDR0 Register */ + __I uint32_t pidr1; /**< \b 0x0FE4: MPC PIDR1 Register */ + __I uint32_t pidr2; /**< \b 0x0FE8: MPC PIDR2 Register */ + __I uint32_t pidr3; /**< \b 0x0FEC: MPC PIDR3 Register */ + __I uint32_t cidr0; /**< \b 0x0FF0: MPC CIDR0 Register */ + __I uint32_t cidr1; /**< \b 0x0FF4: MPC CIDR1 Register */ + __I uint32_t cidr2; /**< \b 0x0FF8: MPC CIDR2 Register */ + __I uint32_t cidr3; /**< \b 0x0FFC: MPC CIDR3 Register */ +} mxc_mpc_regs_t; + +/* Register offsets for module MPC */ +/** + * @ingroup mpc_registers + * @defgroup MPC_Register_Offsets Register Offsets + * @brief MPC Peripheral Register Offsets from the MPC Base Peripheral Address. + * @{ + */ +#define MXC_R_MPC_CTRL ((uint32_t)0x00000000UL) /**< Offset from MPC Base Address: 0x0000 */ +#define MXC_R_MPC_BLK_MAX ((uint32_t)0x00000010UL) /**< Offset from MPC Base Address: 0x0010 */ +#define MXC_R_MPC_BLK_CFG ((uint32_t)0x00000014UL) /**< Offset from MPC Base Address: 0x0014 */ +#define MXC_R_MPC_BLK_IDX ((uint32_t)0x00000018UL) /**< Offset from MPC Base Address: 0x0018 */ +#define MXC_R_MPC_BLK_LUT ((uint32_t)0x0000001CUL) /**< Offset from MPC Base Address: 0x001C */ +#define MXC_R_MPC_INT_STAT ((uint32_t)0x00000020UL) /**< Offset from MPC Base Address: 0x0020 */ +#define MXC_R_MPC_INT_CLEAR ((uint32_t)0x00000024UL) /**< Offset from MPC Base Address: 0x0024 */ +#define MXC_R_MPC_INT_EN ((uint32_t)0x00000028UL) /**< Offset from MPC Base Address: 0x0028 */ +#define MXC_R_MPC_INT_INFO1 ((uint32_t)0x0000002CUL) /**< Offset from MPC Base Address: 0x002C */ +#define MXC_R_MPC_INT_INFO2 ((uint32_t)0x00000030UL) /**< Offset from MPC Base Address: 0x0030 */ +#define MXC_R_MPC_INT_SET ((uint32_t)0x00000034UL) /**< Offset from MPC Base Address: 0x0034 */ +#define MXC_R_MPC_PIDR4 ((uint32_t)0x00000FD0UL) /**< Offset from MPC Base Address: 0x0FD0 */ +#define MXC_R_MPC_PIDR5 ((uint32_t)0x00000FD4UL) /**< Offset from MPC Base Address: 0x0FD4 */ +#define MXC_R_MPC_PIDR6 ((uint32_t)0x00000FD8UL) /**< Offset from MPC Base Address: 0x0FD8 */ +#define MXC_R_MPC_PIDR7 ((uint32_t)0x00000FDCUL) /**< Offset from MPC Base Address: 0x0FDC */ +#define MXC_R_MPC_PIDR0 ((uint32_t)0x00000FE0UL) /**< Offset from MPC Base Address: 0x0FE0 */ +#define MXC_R_MPC_PIDR1 ((uint32_t)0x00000FE4UL) /**< Offset from MPC Base Address: 0x0FE4 */ +#define MXC_R_MPC_PIDR2 ((uint32_t)0x00000FE8UL) /**< Offset from MPC Base Address: 0x0FE8 */ +#define MXC_R_MPC_PIDR3 ((uint32_t)0x00000FECUL) /**< Offset from MPC Base Address: 0x0FEC */ +#define MXC_R_MPC_CIDR0 ((uint32_t)0x00000FF0UL) /**< Offset from MPC Base Address: 0x0FF0 */ +#define MXC_R_MPC_CIDR1 ((uint32_t)0x00000FF4UL) /**< Offset from MPC Base Address: 0x0FF4 */ +#define MXC_R_MPC_CIDR2 ((uint32_t)0x00000FF8UL) /**< Offset from MPC Base Address: 0x0FF8 */ +#define MXC_R_MPC_CIDR3 ((uint32_t)0x00000FFCUL) /**< Offset from MPC Base Address: 0x0FFC */ +/**@} end of group mpc_registers */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_CTRL MPC_CTRL + * @brief Control Register. + * @{ + */ +#define MXC_F_MPC_CTRL_SEC_ERR_POS 4 /**< CTRL_SEC_ERR Position */ +#define MXC_F_MPC_CTRL_SEC_ERR ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_ERR_POS)) /**< CTRL_SEC_ERR Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_REQ_POS 6 /**< CTRL_DATAIF_REQ Position */ +#define MXC_F_MPC_CTRL_DATAIF_REQ ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_REQ_POS)) /**< CTRL_DATAIF_REQ Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_ACK_POS 7 /**< CTRL_DATAIF_ACK Position */ +#define MXC_F_MPC_CTRL_DATAIF_ACK ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_ACK_POS)) /**< CTRL_DATAIF_ACK Mask */ + +#define MXC_F_MPC_CTRL_AUTO_INC_POS 8 /**< CTRL_AUTO_INC Position */ +#define MXC_F_MPC_CTRL_AUTO_INC ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_AUTO_INC_POS)) /**< CTRL_AUTO_INC Mask */ + +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS 31 /**< CTRL_SEC_LOCKDOWN Position */ +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS)) /**< CTRL_SEC_LOCKDOWN Mask */ + +/**@} end of group MPC_CTRL_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_MAX MPC_BLK_MAX + * @brief Maximum value of block-based index register. + * @{ + */ +#define MXC_F_MPC_BLK_MAX_VAL_POS 0 /**< BLK_MAX_VAL Position */ +#define MXC_F_MPC_BLK_MAX_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_MAX_VAL_POS)) /**< BLK_MAX_VAL Mask */ + +/**@} end of group MPC_BLK_MAX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_CFG MPC_BLK_CFG + * @brief Block Control Register. + * @{ + */ +#define MXC_F_MPC_BLK_CFG_SIZE_POS 0 /**< BLK_CFG_SIZE Position */ +#define MXC_F_MPC_BLK_CFG_SIZE ((uint32_t)(0xFUL << MXC_F_MPC_BLK_CFG_SIZE_POS)) /**< BLK_CFG_SIZE Mask */ + +#define MXC_F_MPC_BLK_CFG_INIT_ST_POS 31 /**< BLK_CFG_INIT_ST Position */ +#define MXC_F_MPC_BLK_CFG_INIT_ST ((uint32_t)(0x1UL << MXC_F_MPC_BLK_CFG_INIT_ST_POS)) /**< BLK_CFG_INIT_ST Mask */ + +/**@} end of group MPC_BLK_CFG_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_IDX MPC_BLK_IDX + * @brief Block Index Register. + * @{ + */ +#define MXC_F_MPC_BLK_IDX_IDX_POS 0 /**< BLK_IDX_IDX Position */ +#define MXC_F_MPC_BLK_IDX_IDX ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_IDX_IDX_POS)) /**< BLK_IDX_IDX Mask */ + +/**@} end of group MPC_BLK_IDX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_LUT MPC_BLK_LUT + * @brief Block-based gating Look Up Table Register. + * @{ + */ +#define MXC_F_MPC_BLK_LUT_ACCESS_POS 0 /**< BLK_LUT_ACCESS Position */ +#define MXC_F_MPC_BLK_LUT_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_LUT_ACCESS_POS)) /**< BLK_LUT_ACCESS Mask */ + +/**@} end of group MPC_BLK_LUT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_STAT MPC_INT_STAT + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ_POS 0 /**< INT_STAT_MPC_IRQ Position */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_STAT_MPC_IRQ_POS)) /**< INT_STAT_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_STAT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_CLEAR MPC_INT_CLEAR + * @brief Interrupt Clear Register. + * @{ + */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS 0 /**< INT_CLEAR_MPC_IRQ Position */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS)) /**< INT_CLEAR_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_CLEAR_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_EN MPC_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_MPC_INT_EN_MPC_IRQ_POS 0 /**< INT_EN_MPC_IRQ Position */ +#define MXC_F_MPC_INT_EN_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_EN_MPC_IRQ_POS)) /**< INT_EN_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_EN_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO1 MPC_INT_INFO1 + * @brief Interrupt Info 1 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO1_HADDR_POS 0 /**< INT_INFO1_HADDR Position */ +#define MXC_F_MPC_INT_INFO1_HADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_INT_INFO1_HADDR_POS)) /**< INT_INFO1_HADDR Mask */ + +/**@} end of group MPC_INT_INFO1_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO2 MPC_INT_INFO2 + * @brief Interrupt Info 2 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO2_HMASTER_POS 0 /**< INT_INFO2_HMASTER Position */ +#define MXC_F_MPC_INT_INFO2_HMASTER ((uint32_t)(0xFFFFUL << MXC_F_MPC_INT_INFO2_HMASTER_POS)) /**< INT_INFO2_HMASTER Mask */ + +#define MXC_F_MPC_INT_INFO2_HNONSEC_POS 16 /**< INT_INFO2_HNONSEC Position */ +#define MXC_F_MPC_INT_INFO2_HNONSEC ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_HNONSEC_POS)) /**< INT_INFO2_HNONSEC Mask */ + +#define MXC_F_MPC_INT_INFO2_CFG_NS_POS 17 /**< INT_INFO2_CFG_NS Position */ +#define MXC_F_MPC_INT_INFO2_CFG_NS ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_CFG_NS_POS)) /**< INT_INFO2_CFG_NS Mask */ + +/**@} end of group MPC_INT_INFO2_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_SET MPC_INT_SET + * @brief Interrupt Set Debug Register. + * @{ + */ +#define MXC_F_MPC_INT_SET_MPC_IRQ_POS 0 /**< INT_SET_MPC_IRQ Position */ +#define MXC_F_MPC_INT_SET_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_SET_MPC_IRQ_POS)) /**< INT_SET_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_SET_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h index b5505f3d114..fd2b7bb166f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h @@ -74,6 +74,8 @@ extern "C" { typedef struct { __R uint32_t rsv_0x0_0x15f[88]; __IO uint32_t apbpriv; /**< \b 0x0160: NSPC APBPRIV Register */ + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: NSPC AHBMPRIV Register */ } mxc_nspc_regs_t; /* Register offsets for module NSPC */ @@ -84,6 +86,7 @@ typedef struct { * @{ */ #define MXC_R_NSPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from NSPC Base Address: 0x0160 */ +#define MXC_R_NSPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from NSPC Base Address: 0x0170 */ /**@} end of group nspc_registers */ /** @@ -94,9 +97,78 @@ typedef struct { */ #define MXC_F_NSPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ #define MXC_F_NSPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_NSPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ +#define MXC_V_NSPC_APBPRIV_PERIPH_GCR ((uint32_t)0x1UL) /**< APBPRIV_PERIPH_GCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_GCR (MXC_V_NSPC_APBPRIV_PERIPH_GCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_SIR ((uint32_t)0x2UL) /**< APBPRIV_PERIPH_SIR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_SIR (MXC_V_NSPC_APBPRIV_PERIPH_SIR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SIR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_FCR ((uint32_t)0x4UL) /**< APBPRIV_PERIPH_FCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_FCR (MXC_V_NSPC_APBPRIV_PERIPH_FCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_FCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WDT ((uint32_t)0x8UL) /**< APBPRIV_PERIPH_WDT Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WDT (MXC_V_NSPC_APBPRIV_PERIPH_WDT << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WDT Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_AES ((uint32_t)0x10UL) /**< APBPRIV_PERIPH_AES Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_AES (MXC_V_NSPC_APBPRIV_PERIPH_AES << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AES Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBPRIV_PERIPH_AESKEYS Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_AESKEYS (MXC_V_NSPC_APBPRIV_PERIPH_AESKEYS << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AESKEYS Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_CRC ((uint32_t)0x40UL) /**< APBPRIV_PERIPH_CRC Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_CRC (MXC_V_NSPC_APBPRIV_PERIPH_CRC << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_CRC Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBPRIV_PERIPH_GPIO0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_GPIO0 (MXC_V_NSPC_APBPRIV_PERIPH_GPIO0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GPIO0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBPRIV_PERIPH_TMR0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR0 (MXC_V_NSPC_APBPRIV_PERIPH_TMR0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBPRIV_PERIPH_TMR1 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR1 (MXC_V_NSPC_APBPRIV_PERIPH_TMR1 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR1 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBPRIV_PERIPH_TMR2 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR2 (MXC_V_NSPC_APBPRIV_PERIPH_TMR2 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR2 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBPRIV_PERIPH_TMR3 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR3 (MXC_V_NSPC_APBPRIV_PERIPH_TMR3 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR3 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBPRIV_PERIPH_TMR4 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR4 (MXC_V_NSPC_APBPRIV_PERIPH_TMR4 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR4 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBPRIV_PERIPH_TMR5 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR5 (MXC_V_NSPC_APBPRIV_PERIPH_TMR5 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR5 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBPRIV_PERIPH_I3C Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_I3C (MXC_V_NSPC_APBPRIV_PERIPH_I3C << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_I3C Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_UART ((uint32_t)0x8000UL) /**< APBPRIV_PERIPH_UART Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_UART (MXC_V_NSPC_APBPRIV_PERIPH_UART << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_UART Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBPRIV_PERIPH_SPI Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_SPI (MXC_V_NSPC_APBPRIV_PERIPH_SPI << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SPI Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBPRIV_PERIPH_TRNG Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TRNG (MXC_V_NSPC_APBPRIV_PERIPH_TRNG << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRNG Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBPRIV_PERIPH_BTLE_DBB Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BTLE_DBB (MXC_V_NSPC_APBPRIV_PERIPH_BTLE_DBB << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_DBB Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBPRIV_PERIPH_BTLE_RFFE Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BTLE_RFFE (MXC_V_NSPC_APBPRIV_PERIPH_BTLE_RFFE << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBPRIV_PERIPH_RSTZ Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_RSTZ (MXC_V_NSPC_APBPRIV_PERIPH_RSTZ << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RSTZ Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBPRIV_PERIPH_BOOST Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BOOST (MXC_V_NSPC_APBPRIV_PERIPH_BOOST << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BOOST Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBPRIV_PERIPH_TRIMSIR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TRIMSIR (MXC_V_NSPC_APBPRIV_PERIPH_TRIMSIR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRIMSIR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBPRIV_PERIPH_RTC Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_RTC (MXC_V_NSPC_APBPRIV_PERIPH_RTC << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RTC Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBPRIV_PERIPH_WUT0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WUT0 (MXC_V_NSPC_APBPRIV_PERIPH_WUT0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBPRIV_PERIPH_WUT1 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WUT1 (MXC_V_NSPC_APBPRIV_PERIPH_WUT1 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT1 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBPRIV_PERIPH_PWRSEQ Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_PWRSEQ (MXC_V_NSPC_APBPRIV_PERIPH_PWRSEQ << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_PWRSEQ Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBPRIV_PERIPH_MCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_MCR (MXC_V_NSPC_APBPRIV_PERIPH_MCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_MCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBPRIV_PERIPH_ALL Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_ALL (MXC_V_NSPC_APBPRIV_PERIPH_ALL << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_ALL Setting */ /**@} end of group NSPC_APBPRIV_Register */ +/** + * @ingroup nspc_registers + * @defgroup NSPC_AHBMPRIV NSPC_AHBMPRIV + * @brief AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + * @{ + */ +#define MXC_F_NSPC_AHBMPRIV_DMA_POS 1 /**< AHBMPRIV_DMA Position */ +#define MXC_F_NSPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_NSPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ + +/**@} end of group NSPC_AHBMPRIV_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h deleted file mode 100644 index a948716c809..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ /dev/null @@ -1,1286 +0,0 @@ -/***************************************************************************** - * @file partition_max32657.h - * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for - * MAX32657 - * @version V1.0.0 - * @date 20. January 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * Portions Copyright (C) 2024 Analog Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ - -#include "max32657.h" - -// clang-format off -#if IS_SECURE_ENVIRONMENT - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -/** - * Analog Devices, Inc. - * 4 Regions in the MAX32657. - * 1. Non-Secure Flash - * 2. Secure Flash - * 3. Non-Secure SRAM - * 4. Secure SRAM - * - * Finer grain control can be achieved depending on the application - * requirements by updating the regions of this file. - * - * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF - * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF - * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF - * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF - * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF - * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF - * - * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF - * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF - * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF - * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF - * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF - * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF - */ -#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 (Secure Flash) -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x11000000 /* start address of SAU region 0 (ROM) */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x110FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 (Non-Secure Flash) -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x01000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x010FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 (Secure SRAM) -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x30000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x3003FFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 1 -/* -// -*/ - -/* -// Initialize SAU Region 3 (Non-Secure SRAM) -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x20000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x2003FFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// ICE Unlock <0=> Secure state <1=> Non-Secure state -// Watchdog Timer <0=> Secure state <1=> Non-Secure state -// Real Time Clock <0=> Secure state <1=> Non-Secure state -// True Random Number Generator <0=> Secure state <1=> Non-Secure state -// Timer 0 <0=> Secure state <1=> Non-Secure state -// Timer 1 <0=> Secure state <1=> Non-Secure state -// Timer 2 <0=> Secure state <1=> Non-Secure state -// Timer 3 <0=> Secure state <1=> Non-Secure state -// Timer 4 <0=> Secure state <1=> Non-Secure state -// Timer 5 <0=> Secure state <1=> Non-Secure state -// I3C <0=> Secure state <1=> Non-Secure state -// UART <0=> Secure state <1=> Non-Secure state -// SPI <0=> Secure state <1=> Non-Secure state -// Flash Controller <0=> Secure state <1=> Non-Secure state -// GPIO0 <0=> Secure state <1=> Non-Secure state -// Reserved (15) <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state -// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state -// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state -// GPIO Wake <0=> Secure state <1=> Non-Secure state -// CRC <0=> Secure state <1=> Non-Secure state -// AES <0=> Secure state <1=> Non-Secure state -// ERFO Ready <0=> Secure state <1=> Non-Secure state -// Boost Controller <0=> Secure state <1=> Non-Secure state -// ECC <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state -// BTLE XXXXA <0=> Secure state <1=> Non-Secure state -// BTLE XXXXB <0=> Secure state <1=> Non-Secure state -// BTLE XXXXC <0=> Secure state <1=> Non-Secure state -// BTLE XXXXD <0=> Secure state <1=> Non-Secure state -// BTLE XXXXE <0=> Secure state <1=> Non-Secure state -// Reserved (47) <0=> Secure state <1=> Non-Secure state -// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state -// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state -// Reserved (50) <0=> Secure state <1=> Non-Secure state -// Reserved (51) <0=> Secure state <1=> Non-Secure state -// Reserved (52) <0=> Secure state <1=> Non-Secure state -// Reserved (53) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif // IS_SECURE_EVIRONMENT - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index 2998417c6f6..216ede9b620 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -75,9 +75,7 @@ typedef struct { __IO uint32_t lpctrl; /**< \b 0x00: PWRSEQ LPCTRL Register */ __IO uint32_t lpwkfl0; /**< \b 0x04: PWRSEQ LPWKFL0 Register */ __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ - __IO uint32_t lpwkfl1; /**< \b 0x0C: PWRSEQ LPWKFL1 Register */ - __IO uint32_t lpwken1; /**< \b 0x10: PWRSEQ LPWKEN1 Register */ - __R uint32_t rsv_0x14_0x2f[7]; + __R uint32_t rsv_0xc_0x2f[9]; __IO uint32_t lppwst; /**< \b 0x30: PWRSEQ LPPWST Register */ __R uint32_t rsv_0x34_0x47[5]; __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ @@ -94,8 +92,6 @@ typedef struct { #define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ #define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ -#define MXC_R_PWRSEQ_LPWKFL1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ -#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ @@ -110,12 +106,15 @@ typedef struct { #define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS 0 /**< LPCTRL_SRAMRET_EN Position */ #define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN ((uint32_t)(0x1FUL << MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS)) /**< LPCTRL_SRAMRET_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_FAST_POS 8 /**< LPCTRL_FAST Position */ -#define MXC_F_PWRSEQ_LPCTRL_FAST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FAST_POS)) /**< LPCTRL_FAST Mask */ - #define MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS 11 /**< LPCTRL_BG_DIS Position */ #define MXC_F_PWRSEQ_LPCTRL_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS)) /**< LPCTRL_BG_DIS Mask */ +#define MXC_F_PWRSEQ_LPCTRL_RETLDO_EN_POS 12 /**< LPCTRL_RETLDO_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_RETLDO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETLDO_EN_POS)) /**< LPCTRL_RETLDO_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY_POS 13 /**< LPCTRL_LDO_EN_DLY Position */ +#define MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY_POS)) /**< LPCTRL_LDO_EN_DLY Mask */ + #define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS 31 /**< LPCTRL_LPWKFL_CLR Position */ #define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS)) /**< LPCTRL_LPWKFL_CLR Mask */ @@ -145,30 +144,6 @@ typedef struct { /**@} end of group PWRSEQ_LPWKEN0_Register */ -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKFL1 PWRSEQ_LPWKFL1 - * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power - * wakeup status for GPIO1. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKFL1_PINS_POS 0 /**< LPWKFL1_PINS Position */ -#define MXC_F_PWRSEQ_LPWKFL1_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKFL1_PINS_POS)) /**< LPWKFL1_PINS Mask */ - -/**@} end of group PWRSEQ_LPWKFL1_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 - * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup - * functionality for GPIO1. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKEN1_PINS_POS 0 /**< LPWKEN1_PINS Position */ -#define MXC_F_PWRSEQ_LPWKEN1_PINS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN1_PINS_POS)) /**< LPWKEN1_PINS Mask */ - -/**@} end of group PWRSEQ_LPWKEN1_Register */ - /** * @ingroup pwrseq_registers * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h new file mode 100644 index 00000000000..5920d77a627 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h @@ -0,0 +1,169 @@ +/** + * @file rstz_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RSTZ Peripheral Module. + * @note This file is @generated. + * @ingroup rstz_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rstz + * @defgroup rstz_registers RSTZ_Registers + * @brief Registers, Bit Masks and Bit Positions for the RSTZ Peripheral Module. + * @details RSTZ Controller + */ + +/** + * @ingroup rstz_registers + * Structure type to access the RSTZ Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: RSTZ CTRL Register */ + __IO uint32_t boost_clkctrl; /**< \b 0x004: RSTZ BOOST_CLKCTRL Register */ + __R uint32_t rsv_0x8_0x27[8]; + __IO uint32_t status_ch[8]; /**< \b 0x028: RSTZ STATUS_CH Register */ +} mxc_rstz_regs_t; + +/* Register offsets for module RSTZ */ +/** + * @ingroup rstz_registers + * @defgroup RSTZ_Register_Offsets Register Offsets + * @brief RSTZ Peripheral Register Offsets from the RSTZ Base Peripheral Address. + * @{ + */ +#define MXC_R_RSTZ_CTRL ((uint32_t)0x00000000UL) /**< Offset from RSTZ Base Address: 0x0000 */ +#define MXC_R_RSTZ_BOOST_CLKCTRL ((uint32_t)0x00000004UL) /**< Offset from RSTZ Base Address: 0x0004 */ +#define MXC_R_RSTZ_STATUS_CH ((uint32_t)0x00000028UL) /**< Offset from RSTZ Base Address: 0x0028 */ +/**@} end of group rstz_registers */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_CTRL RSTZ_CTRL + * @brief RSTZ Control Register. + * @{ + */ +#define MXC_F_RSTZ_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_RSTZ_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_RSTZ_CTRL_SVC_EN_POS 1 /**< CTRL_SVC_EN Position */ +#define MXC_F_RSTZ_CTRL_SVC_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_SVC_EN_POS)) /**< CTRL_SVC_EN Mask */ + +#define MXC_F_RSTZ_CTRL_CH_SEL_POS 2 /**< CTRL_CH_SEL Position */ +#define MXC_F_RSTZ_CTRL_CH_SEL ((uint32_t)(0x7UL << MXC_F_RSTZ_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ + +#define MXC_F_RSTZ_CTRL_CAL_EN_POS 5 /**< CTRL_CAL_EN Position */ +#define MXC_F_RSTZ_CTRL_CAL_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_CAL_EN_POS)) /**< CTRL_CAL_EN Mask */ + +#define MXC_F_RSTZ_CTRL_DMEASURE_EN_POS 6 /**< CTRL_DMEASURE_EN Position */ +#define MXC_F_RSTZ_CTRL_DMEASURE_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_DMEASURE_EN_POS)) /**< CTRL_DMEASURE_EN Mask */ + +#define MXC_F_RSTZ_CTRL_OFFTR_P_POS 7 /**< CTRL_OFFTR_P Position */ +#define MXC_F_RSTZ_CTRL_OFFTR_P ((uint32_t)(0x1FUL << MXC_F_RSTZ_CTRL_OFFTR_P_POS)) /**< CTRL_OFFTR_P Mask */ + +#define MXC_F_RSTZ_CTRL_OFFTR_N_POS 12 /**< CTRL_OFFTR_N Position */ +#define MXC_F_RSTZ_CTRL_OFFTR_N ((uint32_t)(0x1FUL << MXC_F_RSTZ_CTRL_OFFTR_N_POS)) /**< CTRL_OFFTR_N Mask */ + +#define MXC_F_RSTZ_CTRL_DOUT_POS 17 /**< CTRL_DOUT Position */ +#define MXC_F_RSTZ_CTRL_DOUT ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_DOUT_POS)) /**< CTRL_DOUT Mask */ + +#define MXC_F_RSTZ_CTRL_CAL_DOUT_POL_POS 18 /**< CTRL_CAL_DOUT_POL Position */ +#define MXC_F_RSTZ_CTRL_CAL_DOUT_POL ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_CAL_DOUT_POL_POS)) /**< CTRL_CAL_DOUT_POL Mask */ + +#define MXC_F_RSTZ_CTRL_NUM_SAMP_POS 24 /**< CTRL_NUM_SAMP Position */ +#define MXC_F_RSTZ_CTRL_NUM_SAMP ((uint32_t)(0xFUL << MXC_F_RSTZ_CTRL_NUM_SAMP_POS)) /**< CTRL_NUM_SAMP Mask */ + +#define MXC_F_RSTZ_CTRL_TRIP_TOL_POS 28 /**< CTRL_TRIP_TOL Position */ +#define MXC_F_RSTZ_CTRL_TRIP_TOL ((uint32_t)(0xFUL << MXC_F_RSTZ_CTRL_TRIP_TOL_POS)) /**< CTRL_TRIP_TOL Mask */ + +/**@} end of group RSTZ_CTRL_Register */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_BOOST_CLKCTRL RSTZ_BOOST_CLKCTRL + * @brief Boost Clock Control Register. + * @{ + */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP_POS 0 /**< BOOST_CLKCTRL_EXIT_NUM_SAMP Position */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP ((uint32_t)(0x3UL << MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP_POS)) /**< BOOST_CLKCTRL_EXIT_NUM_SAMP Mask */ + +#define MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL_POS 2 /**< BOOST_CLKCTRL_CH_SEL Position */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL ((uint32_t)(0x7UL << MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL_POS)) /**< BOOST_CLKCTRL_CH_SEL Mask */ + +/**@} end of group RSTZ_BOOST_CLKCTRL_Register */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_STATUS_CH RSTZ_STATUS_CH + * @brief Channel X Status Register. + * @{ + */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ_POS 0 /**< STATUS_CH_RSTZ Position */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_RSTZ_POS)) /**< STATUS_CH_RSTZ Mask */ + +#define MXC_F_RSTZ_STATUS_CH_DOUT_POS 1 /**< STATUS_CH_DOUT Position */ +#define MXC_F_RSTZ_STATUS_CH_DOUT ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_DOUT_POS)) /**< STATUS_CH_DOUT Mask */ + +#define MXC_F_RSTZ_STATUS_CH_RSTZ_FL_POS 31 /**< STATUS_CH_RSTZ_FL Position */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ_FL ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_RSTZ_FL_POS)) /**< STATUS_CH_RSTZ_FL Mask */ + +/**@} end of group RSTZ_STATUS_CH_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h deleted file mode 100644 index e9b763a0c1e..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - * @file sema_regs.h - * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. - * @note This file is @generated. - * @ingroup sema_registers - */ - -/****************************************************************************** - * - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup sema - * @defgroup sema_registers SEMA_Registers - * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. - * @details The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. - The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software - architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be - - modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. - */ - -/** - * @ingroup sema_registers - * Structure type to access the SEMA Registers. - */ -typedef struct { - __IO uint32_t semaphores[8]; /**< \b 0x00: SEMA SEMAPHORES Register */ - __R uint32_t rsv_0x20_0x3f[8]; - __IO uint32_t irq0; /**< \b 0x40: SEMA IRQ0 Register */ - __IO uint32_t mail0; /**< \b 0x44: SEMA MAIL0 Register */ - __IO uint32_t irq1; /**< \b 0x48: SEMA IRQ1 Register */ - __IO uint32_t mail1; /**< \b 0x4C: SEMA MAIL1 Register */ - __R uint32_t rsv_0x50_0xff[44]; - __IO uint32_t status; /**< \b 0x100: SEMA STATUS Register */ -} mxc_sema_regs_t; - -/* Register offsets for module SEMA */ -/** - * @ingroup sema_registers - * @defgroup SEMA_Register_Offsets Register Offsets - * @brief SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address. - * @{ - */ -#define MXC_R_SEMA_SEMAPHORES ((uint32_t)0x00000000UL) /**< Offset from SEMA Base Address: 0x0000 */ -#define MXC_R_SEMA_IRQ0 ((uint32_t)0x00000040UL) /**< Offset from SEMA Base Address: 0x0040 */ -#define MXC_R_SEMA_MAIL0 ((uint32_t)0x00000044UL) /**< Offset from SEMA Base Address: 0x0044 */ -#define MXC_R_SEMA_IRQ1 ((uint32_t)0x00000048UL) /**< Offset from SEMA Base Address: 0x0048 */ -#define MXC_R_SEMA_MAIL1 ((uint32_t)0x0000004CUL) /**< Offset from SEMA Base Address: 0x004C */ -#define MXC_R_SEMA_STATUS ((uint32_t)0x00000100UL) /**< Offset from SEMA Base Address: 0x0100 */ -/**@} end of group sema_registers */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_SEMAPHORES SEMA_SEMAPHORES - * @brief Read to test and set, returns prior value. Write 0 to clear semaphore. - * @{ - */ -#define MXC_F_SEMA_SEMAPHORES_SEMA_POS 0 /**< SEMAPHORES_SEMA Position */ -#define MXC_F_SEMA_SEMAPHORES_SEMA ((uint32_t)(0x1UL << MXC_F_SEMA_SEMAPHORES_SEMA_POS)) /**< SEMAPHORES_SEMA Mask */ - -/**@} end of group SEMA_SEMAPHORES_Register */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_IRQ0 SEMA_IRQ0 - * @brief Semaphore IRQ0 register. - * @{ - */ -#define MXC_F_SEMA_IRQ0_EN_POS 0 /**< IRQ0_EN Position */ -#define MXC_F_SEMA_IRQ0_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_EN_POS)) /**< IRQ0_EN Mask */ - -#define MXC_F_SEMA_IRQ0_CM4_IRQ_POS 16 /**< IRQ0_CM4_IRQ Position */ -#define MXC_F_SEMA_IRQ0_CM4_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_CM4_IRQ_POS)) /**< IRQ0_CM4_IRQ Mask */ - -/**@} end of group SEMA_IRQ0_Register */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_MAIL0 SEMA_MAIL0 - * @brief Semaphore Mailbox 0 register. - * @{ - */ -#define MXC_F_SEMA_MAIL0_DATA_POS 0 /**< MAIL0_DATA Position */ -#define MXC_F_SEMA_MAIL0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL0_DATA_POS)) /**< MAIL0_DATA Mask */ - -/**@} end of group SEMA_MAIL0_Register */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_IRQ1 SEMA_IRQ1 - * @brief Semaphore IRQ1 register. - * @{ - */ -#define MXC_F_SEMA_IRQ1_EN_POS 0 /**< IRQ1_EN Position */ -#define MXC_F_SEMA_IRQ1_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_EN_POS)) /**< IRQ1_EN Mask */ - -#define MXC_F_SEMA_IRQ1_RV32_IRQ_POS 16 /**< IRQ1_RV32_IRQ Position */ -#define MXC_F_SEMA_IRQ1_RV32_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_RV32_IRQ_POS)) /**< IRQ1_RV32_IRQ Mask */ - -/**@} end of group SEMA_IRQ1_Register */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_MAIL1 SEMA_MAIL1 - * @brief Semaphore Mailbox 1 register. - * @{ - */ -#define MXC_F_SEMA_MAIL1_DATA_POS 0 /**< MAIL1_DATA Position */ -#define MXC_F_SEMA_MAIL1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL1_DATA_POS)) /**< MAIL1_DATA Mask */ - -/**@} end of group SEMA_MAIL1_Register */ - -/** - * @ingroup sema_registers - * @defgroup SEMA_STATUS SEMA_STATUS - * @brief Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. - * @{ - */ -#define MXC_F_SEMA_STATUS_STATUS0_POS 0 /**< STATUS_STATUS0 Position */ -#define MXC_F_SEMA_STATUS_STATUS0 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS0_POS)) /**< STATUS_STATUS0 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS1_POS 1 /**< STATUS_STATUS1 Position */ -#define MXC_F_SEMA_STATUS_STATUS1 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS1_POS)) /**< STATUS_STATUS1 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS2_POS 2 /**< STATUS_STATUS2 Position */ -#define MXC_F_SEMA_STATUS_STATUS2 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS2_POS)) /**< STATUS_STATUS2 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS3_POS 3 /**< STATUS_STATUS3 Position */ -#define MXC_F_SEMA_STATUS_STATUS3 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS3_POS)) /**< STATUS_STATUS3 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS4_POS 4 /**< STATUS_STATUS4 Position */ -#define MXC_F_SEMA_STATUS_STATUS4 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS4_POS)) /**< STATUS_STATUS4 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS5_POS 5 /**< STATUS_STATUS5 Position */ -#define MXC_F_SEMA_STATUS_STATUS5 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS5_POS)) /**< STATUS_STATUS5 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS6_POS 6 /**< STATUS_STATUS6 Position */ -#define MXC_F_SEMA_STATUS_STATUS6 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS6_POS)) /**< STATUS_STATUS6 Mask */ - -#define MXC_F_SEMA_STATUS_STATUS7_POS 7 /**< STATUS_STATUS7 Position */ -#define MXC_F_SEMA_STATUS_STATUS7 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS7_POS)) /**< STATUS_STATUS7 Mask */ - -/**@} end of group SEMA_STATUS_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h deleted file mode 100644 index d6cfc8ccd04..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h +++ /dev/null @@ -1,378 +0,0 @@ -/** - * @file simo_regs.h - * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. - * @note This file is @generated. - * @ingroup simo_registers - */ - -/****************************************************************************** - * - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup simo - * @defgroup simo_registers SIMO_Registers - * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. - * @details Single Inductor Multiple Output Switching Converter - */ - -/** - * @ingroup simo_registers - * Structure type to access the SIMO Registers. - */ -typedef struct { - __R uint32_t rsv_0x0; - __IO uint32_t vrego_a; /**< \b 0x0004: SIMO VREGO_A Register */ - __IO uint32_t vrego_b; /**< \b 0x0008: SIMO VREGO_B Register */ - __IO uint32_t vrego_c; /**< \b 0x000C: SIMO VREGO_C Register */ - __IO uint32_t vrego_d; /**< \b 0x0010: SIMO VREGO_D Register */ - __IO uint32_t ipka; /**< \b 0x0014: SIMO IPKA Register */ - __IO uint32_t ipkb; /**< \b 0x0018: SIMO IPKB Register */ - __IO uint32_t maxton; /**< \b 0x001C: SIMO MAXTON Register */ - __I uint32_t iload_a; /**< \b 0x0020: SIMO ILOAD_A Register */ - __I uint32_t iload_b; /**< \b 0x0024: SIMO ILOAD_B Register */ - __I uint32_t iload_c; /**< \b 0x0028: SIMO ILOAD_C Register */ - __I uint32_t iload_d; /**< \b 0x002C: SIMO ILOAD_D Register */ - __IO uint32_t buck_alert_thr_a; /**< \b 0x0030: SIMO BUCK_ALERT_THR_A Register */ - __IO uint32_t buck_alert_thr_b; /**< \b 0x0034: SIMO BUCK_ALERT_THR_B Register */ - __IO uint32_t buck_alert_thr_c; /**< \b 0x0038: SIMO BUCK_ALERT_THR_C Register */ - __IO uint32_t buck_alert_thr_d; /**< \b 0x003C: SIMO BUCK_ALERT_THR_D Register */ - __I uint32_t buck_out_ready; /**< \b 0x0040: SIMO BUCK_OUT_READY Register */ - __I uint32_t zero_cross_cal_a; /**< \b 0x0044: SIMO ZERO_CROSS_CAL_A Register */ - __I uint32_t zero_cross_cal_b; /**< \b 0x0048: SIMO ZERO_CROSS_CAL_B Register */ - __I uint32_t zero_cross_cal_c; /**< \b 0x004C: SIMO ZERO_CROSS_CAL_C Register */ - __I uint32_t zero_cross_cal_d; /**< \b 0x0050: SIMO ZERO_CROSS_CAL_D Register */ -} mxc_simo_regs_t; - -/* Register offsets for module SIMO */ -/** - * @ingroup simo_registers - * @defgroup SIMO_Register_Offsets Register Offsets - * @brief SIMO Peripheral Register Offsets from the SIMO Base Peripheral Address. - * @{ - */ -#define MXC_R_SIMO_VREGO_A ((uint32_t)0x00000004UL) /**< Offset from SIMO Base Address: 0x0004 */ -#define MXC_R_SIMO_VREGO_B ((uint32_t)0x00000008UL) /**< Offset from SIMO Base Address: 0x0008 */ -#define MXC_R_SIMO_VREGO_C ((uint32_t)0x0000000CUL) /**< Offset from SIMO Base Address: 0x000C */ -#define MXC_R_SIMO_VREGO_D ((uint32_t)0x00000010UL) /**< Offset from SIMO Base Address: 0x0010 */ -#define MXC_R_SIMO_IPKA ((uint32_t)0x00000014UL) /**< Offset from SIMO Base Address: 0x0014 */ -#define MXC_R_SIMO_IPKB ((uint32_t)0x00000018UL) /**< Offset from SIMO Base Address: 0x0018 */ -#define MXC_R_SIMO_MAXTON ((uint32_t)0x0000001CUL) /**< Offset from SIMO Base Address: 0x001C */ -#define MXC_R_SIMO_ILOAD_A ((uint32_t)0x00000020UL) /**< Offset from SIMO Base Address: 0x0020 */ -#define MXC_R_SIMO_ILOAD_B ((uint32_t)0x00000024UL) /**< Offset from SIMO Base Address: 0x0024 */ -#define MXC_R_SIMO_ILOAD_C ((uint32_t)0x00000028UL) /**< Offset from SIMO Base Address: 0x0028 */ -#define MXC_R_SIMO_ILOAD_D ((uint32_t)0x0000002CUL) /**< Offset from SIMO Base Address: 0x002C */ -#define MXC_R_SIMO_BUCK_ALERT_THR_A ((uint32_t)0x00000030UL) /**< Offset from SIMO Base Address: 0x0030 */ -#define MXC_R_SIMO_BUCK_ALERT_THR_B ((uint32_t)0x00000034UL) /**< Offset from SIMO Base Address: 0x0034 */ -#define MXC_R_SIMO_BUCK_ALERT_THR_C ((uint32_t)0x00000038UL) /**< Offset from SIMO Base Address: 0x0038 */ -#define MXC_R_SIMO_BUCK_ALERT_THR_D ((uint32_t)0x0000003CUL) /**< Offset from SIMO Base Address: 0x003C */ -#define MXC_R_SIMO_BUCK_OUT_READY ((uint32_t)0x00000040UL) /**< Offset from SIMO Base Address: 0x0040 */ -#define MXC_R_SIMO_ZERO_CROSS_CAL_A ((uint32_t)0x00000044UL) /**< Offset from SIMO Base Address: 0x0044 */ -#define MXC_R_SIMO_ZERO_CROSS_CAL_B ((uint32_t)0x00000048UL) /**< Offset from SIMO Base Address: 0x0048 */ -#define MXC_R_SIMO_ZERO_CROSS_CAL_C ((uint32_t)0x0000004CUL) /**< Offset from SIMO Base Address: 0x004C */ -#define MXC_R_SIMO_ZERO_CROSS_CAL_D ((uint32_t)0x00000050UL) /**< Offset from SIMO Base Address: 0x0050 */ -/**@} end of group simo_registers */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_VREGO_A SIMO_VREGO_A - * @brief Buck Voltage Regulator A Control Register - * @{ - */ -#define MXC_F_SIMO_VREGO_A_VSETA_POS 0 /**< VREGO_A_VSETA Position */ -#define MXC_F_SIMO_VREGO_A_VSETA ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_A_VSETA_POS)) /**< VREGO_A_VSETA Mask */ - -#define MXC_F_SIMO_VREGO_A_RANGEA_POS 7 /**< VREGO_A_RANGEA Position */ -#define MXC_F_SIMO_VREGO_A_RANGEA ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_A_RANGEA_POS)) /**< VREGO_A_RANGEA Mask */ - -/**@} end of group SIMO_VREGO_A_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_VREGO_B SIMO_VREGO_B - * @brief Buck Voltage Regulator B Control Register - * @{ - */ -#define MXC_F_SIMO_VREGO_B_VSETB_POS 0 /**< VREGO_B_VSETB Position */ -#define MXC_F_SIMO_VREGO_B_VSETB ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_B_VSETB_POS)) /**< VREGO_B_VSETB Mask */ - -#define MXC_F_SIMO_VREGO_B_RANGEB_POS 7 /**< VREGO_B_RANGEB Position */ -#define MXC_F_SIMO_VREGO_B_RANGEB ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_B_RANGEB_POS)) /**< VREGO_B_RANGEB Mask */ - -/**@} end of group SIMO_VREGO_B_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_VREGO_C SIMO_VREGO_C - * @brief Buck Voltage Regulator C Control Register - * @{ - */ -#define MXC_F_SIMO_VREGO_C_VSETC_POS 0 /**< VREGO_C_VSETC Position */ -#define MXC_F_SIMO_VREGO_C_VSETC ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_C_VSETC_POS)) /**< VREGO_C_VSETC Mask */ - -#define MXC_F_SIMO_VREGO_C_RANGEC_POS 7 /**< VREGO_C_RANGEC Position */ -#define MXC_F_SIMO_VREGO_C_RANGEC ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_C_RANGEC_POS)) /**< VREGO_C_RANGEC Mask */ - -/**@} end of group SIMO_VREGO_C_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_VREGO_D SIMO_VREGO_D - * @brief Buck Voltage Regulator D Control Register - * @{ - */ -#define MXC_F_SIMO_VREGO_D_VSETD_POS 0 /**< VREGO_D_VSETD Position */ -#define MXC_F_SIMO_VREGO_D_VSETD ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_D_VSETD_POS)) /**< VREGO_D_VSETD Mask */ - -#define MXC_F_SIMO_VREGO_D_RANGED_POS 7 /**< VREGO_D_RANGED Position */ -#define MXC_F_SIMO_VREGO_D_RANGED ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_D_RANGED_POS)) /**< VREGO_D_RANGED Mask */ - -/**@} end of group SIMO_VREGO_D_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_IPKA SIMO_IPKA - * @brief High Side FET Peak Current VREGO_A/VREGO_B Register - * @{ - */ -#define MXC_F_SIMO_IPKA_IPKSETA_POS 0 /**< IPKA_IPKSETA Position */ -#define MXC_F_SIMO_IPKA_IPKSETA ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETA_POS)) /**< IPKA_IPKSETA Mask */ - -#define MXC_F_SIMO_IPKA_IPKSETB_POS 4 /**< IPKA_IPKSETB Position */ -#define MXC_F_SIMO_IPKA_IPKSETB ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETB_POS)) /**< IPKA_IPKSETB Mask */ - -/**@} end of group SIMO_IPKA_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_IPKB SIMO_IPKB - * @brief High Side FET Peak Current VREGO_C/VREGO_D Register - * @{ - */ -#define MXC_F_SIMO_IPKB_IPKSETC_POS 0 /**< IPKB_IPKSETC Position */ -#define MXC_F_SIMO_IPKB_IPKSETC ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETC_POS)) /**< IPKB_IPKSETC Mask */ - -#define MXC_F_SIMO_IPKB_IPKSETD_POS 4 /**< IPKB_IPKSETD Position */ -#define MXC_F_SIMO_IPKB_IPKSETD ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETD_POS)) /**< IPKB_IPKSETD Mask */ - -/**@} end of group SIMO_IPKB_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_MAXTON SIMO_MAXTON - * @brief Maximum High Side FET Time On Register - * @{ - */ -#define MXC_F_SIMO_MAXTON_TONSET_POS 0 /**< MAXTON_TONSET Position */ -#define MXC_F_SIMO_MAXTON_TONSET ((uint32_t)(0xFUL << MXC_F_SIMO_MAXTON_TONSET_POS)) /**< MAXTON_TONSET Mask */ - -/**@} end of group SIMO_MAXTON_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ILOAD_A SIMO_ILOAD_A - * @brief Buck Cycle Count VREGO_A Register - * @{ - */ -#define MXC_F_SIMO_ILOAD_A_ILOADA_POS 0 /**< ILOAD_A_ILOADA Position */ -#define MXC_F_SIMO_ILOAD_A_ILOADA ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_A_ILOADA_POS)) /**< ILOAD_A_ILOADA Mask */ - -/**@} end of group SIMO_ILOAD_A_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ILOAD_B SIMO_ILOAD_B - * @brief Buck Cycle Count VREGO_B Register - * @{ - */ -#define MXC_F_SIMO_ILOAD_B_ILOADB_POS 0 /**< ILOAD_B_ILOADB Position */ -#define MXC_F_SIMO_ILOAD_B_ILOADB ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_B_ILOADB_POS)) /**< ILOAD_B_ILOADB Mask */ - -/**@} end of group SIMO_ILOAD_B_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ILOAD_C SIMO_ILOAD_C - * @brief Buck Cycle Count VREGO_C Register - * @{ - */ -#define MXC_F_SIMO_ILOAD_C_ILOADC_POS 0 /**< ILOAD_C_ILOADC Position */ -#define MXC_F_SIMO_ILOAD_C_ILOADC ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_C_ILOADC_POS)) /**< ILOAD_C_ILOADC Mask */ - -/**@} end of group SIMO_ILOAD_C_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ILOAD_D SIMO_ILOAD_D - * @brief Buck Cycle Count VREGO_D Register - * @{ - */ -#define MXC_F_SIMO_ILOAD_D_ILOADD_POS 0 /**< ILOAD_D_ILOADD Position */ -#define MXC_F_SIMO_ILOAD_D_ILOADD ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_D_ILOADD_POS)) /**< ILOAD_D_ILOADD Mask */ - -/**@} end of group SIMO_ILOAD_D_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_BUCK_ALERT_THR_A SIMO_BUCK_ALERT_THR_A - * @brief Buck Cycle Count Alert VERGO_A Register - * @{ - */ -#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS 0 /**< BUCK_ALERT_THR_A_BUCKTHRA Position */ -#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS)) /**< BUCK_ALERT_THR_A_BUCKTHRA Mask */ - -/**@} end of group SIMO_BUCK_ALERT_THR_A_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_BUCK_ALERT_THR_B SIMO_BUCK_ALERT_THR_B - * @brief Buck Cycle Count Alert VERGO_B Register - * @{ - */ -#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS 0 /**< BUCK_ALERT_THR_B_BUCKTHRB Position */ -#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS)) /**< BUCK_ALERT_THR_B_BUCKTHRB Mask */ - -/**@} end of group SIMO_BUCK_ALERT_THR_B_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_BUCK_ALERT_THR_C SIMO_BUCK_ALERT_THR_C - * @brief Buck Cycle Count Alert VERGO_C Register - * @{ - */ -#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS 0 /**< BUCK_ALERT_THR_C_BUCKTHRC Position */ -#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS)) /**< BUCK_ALERT_THR_C_BUCKTHRC Mask */ - -/**@} end of group SIMO_BUCK_ALERT_THR_C_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_BUCK_ALERT_THR_D SIMO_BUCK_ALERT_THR_D - * @brief Buck Cycle Count Alert VERGO_D Register - * @{ - */ -#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS 0 /**< BUCK_ALERT_THR_D_BUCKTHRD Position */ -#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS)) /**< BUCK_ALERT_THR_D_BUCKTHRD Mask */ - -/**@} end of group SIMO_BUCK_ALERT_THR_D_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_BUCK_OUT_READY SIMO_BUCK_OUT_READY - * @brief Buck Regulator Output Ready Register - * @{ - */ -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS 0 /**< BUCK_OUT_READY_BUCKOUTRDYA Position */ -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYA Mask */ - -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS 1 /**< BUCK_OUT_READY_BUCKOUTRDYB Position */ -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYB Mask */ - -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS 2 /**< BUCK_OUT_READY_BUCKOUTRDYC Position */ -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYC Mask */ - -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS 3 /**< BUCK_OUT_READY_BUCKOUTRDYD Position */ -#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYD Mask */ - -/**@} end of group SIMO_BUCK_OUT_READY_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ZERO_CROSS_CAL_A SIMO_ZERO_CROSS_CAL_A - * @brief Zero Cross Calibration VERGO_A Register - * @{ - */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS 0 /**< ZERO_CROSS_CAL_A_ZXCALA Position */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS)) /**< ZERO_CROSS_CAL_A_ZXCALA Mask */ - -/**@} end of group SIMO_ZERO_CROSS_CAL_A_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ZERO_CROSS_CAL_B SIMO_ZERO_CROSS_CAL_B - * @brief Zero Cross Calibration VERGO_B Register - * @{ - */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS 0 /**< ZERO_CROSS_CAL_B_ZXCALB Position */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS)) /**< ZERO_CROSS_CAL_B_ZXCALB Mask */ - -/**@} end of group SIMO_ZERO_CROSS_CAL_B_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ZERO_CROSS_CAL_C SIMO_ZERO_CROSS_CAL_C - * @brief Zero Cross Calibration VERGO_C Register - * @{ - */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS 0 /**< ZERO_CROSS_CAL_C_ZXCALC Position */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS)) /**< ZERO_CROSS_CAL_C_ZXCALC Mask */ - -/**@} end of group SIMO_ZERO_CROSS_CAL_C_Register */ - -/** - * @ingroup simo_registers - * @defgroup SIMO_ZERO_CROSS_CAL_D SIMO_ZERO_CROSS_CAL_D - * @brief Zero Cross Calibration VERGO_D Register - * @{ - */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS 0 /**< ZERO_CROSS_CAL_D_ZXCALD Position */ -#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS)) /**< ZERO_CROSS_CAL_D_ZXCALD Mask */ - -/**@} end of group SIMO_ZERO_CROSS_CAL_D_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 400ce986434..8be7861a5a4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -72,9 +72,13 @@ extern "C" { * Structure type to access the SIR Registers. */ typedef struct { - __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ - __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ - __R uint32_t rsv_0x8_0x103[63]; + __I uint32_t sistat; /**< \b 0x000: SIR SISTAT Register */ + __I uint32_t addr; /**< \b 0x004: SIR ADDR Register */ + __R uint32_t rsv_0x8_0x1b[5]; + __IO uint32_t btleldo_bb; /**< \b 0x01C: SIR BTLELDO_BB Register */ + __R uint32_t rsv_0x20_0x2b[3]; + __IO uint32_t btleldo_rf; /**< \b 0x002C: SIR BTLELDO_RF Register */ + __R uint32_t rsv_0x30_0x103[53]; __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ } mxc_sir_regs_t; @@ -87,6 +91,8 @@ typedef struct { */ #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_BTLELDO_BB ((uint32_t)0x0000001CUL) /**< Offset from SIR Base Address: 0x001C */ +#define MXC_R_SIR_BTLELDO_RF ((uint32_t)0x0000002CUL) /**< Offset from SIR Base Address: 0x002C */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ /**@} end of group sir_registers */ @@ -117,6 +123,28 @@ typedef struct { /**@} end of group SIR_ADDR_Register */ +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_BB SIR_BTLELDO_BB + * @brief BTLE LDO TRIM BB Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_BB_TRIM_POS 0 /**< BTLELDO_BB_TRIM Position */ +#define MXC_F_SIR_BTLELDO_BB_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_BB_TRIM_POS)) /**< BTLELDO_BB_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_BB_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_RF SIR_BTLELDO_RF + * @brief BTLE LDO TRIM RF Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_RF_TRIM_POS 0 /**< BTLELDO_RF_TRIM Position */ +#define MXC_F_SIR_BTLELDO_RF_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_RF_TRIM_POS)) /**< BTLELDO_RF_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_RF_Register */ + /** * @ingroup sir_registers * @defgroup SIR_SFSTAT SIR_SFSTAT diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h index 0ad6d991de8..69408b70f41 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h @@ -91,9 +91,10 @@ typedef struct { __IO uint32_t apbsec; /**< \b 0x0120: SPC APBSEC Register */ __R uint32_t rsv_0x124_0x15f[15]; __IO uint32_t apbpriv; /**< \b 0x0160: SPC APBPRIV Register */ - __R uint32_t rsv_0x164_0x17f[7]; + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: SPC AHBMPRIV Register */ + __R uint32_t rsv_0x174_0x17f[3]; __IO uint32_t gpio0; /**< \b 0x0180: SPC GPIO0 Register */ - __IO uint32_t gpio1; /**< \b 0x0184: SPC GPIO1 Register */ } mxc_spc_regs_t; /* Register offsets for module SPC */ @@ -114,8 +115,8 @@ typedef struct { #define MXC_R_SPC_M33LOCK ((uint32_t)0x00000090UL) /**< Offset from SPC Base Address: 0x0090 */ #define MXC_R_SPC_APBSEC ((uint32_t)0x00000120UL) /**< Offset from SPC Base Address: 0x0120 */ #define MXC_R_SPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from SPC Base Address: 0x0160 */ +#define MXC_R_SPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from SPC Base Address: 0x0170 */ #define MXC_R_SPC_GPIO0 ((uint32_t)0x00000180UL) /**< Offset from SPC Base Address: 0x0180 */ -#define MXC_R_SPC_GPIO1 ((uint32_t)0x00000184UL) /**< Offset from SPC Base Address: 0x0184 */ /**@} end of group spc_registers */ /** @@ -199,7 +200,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_STATUS_APBPPC_POS 0 /**< PPC_STATUS_APBPPC Position */ -#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ +#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ /**@} end of group SPC_PPC_STATUS_Register */ @@ -210,7 +211,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_INTCLR_APBPPC_POS 0 /**< PPC_INTCLR_APBPPC Position */ -#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ /**@} end of group SPC_PPC_INTCLR_Register */ @@ -221,7 +222,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_INTEN_APBPPC_POS 0 /**< PPC_INTEN_APBPPC Position */ -#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ +#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ /**@} end of group SPC_PPC_INTEN_Register */ @@ -270,6 +271,64 @@ typedef struct { */ #define MXC_F_SPC_APBSEC_PERIPH_POS 0 /**< APBSEC_PERIPH Position */ #define MXC_F_SPC_APBSEC_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBSEC_PERIPH_POS)) /**< APBSEC_PERIPH Mask */ +#define MXC_V_SPC_APBSEC_PERIPH_GCR ((uint32_t)0x1UL) /**< APBSEC_PERIPH_GCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_GCR (MXC_V_SPC_APBSEC_PERIPH_GCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_GCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_SIR ((uint32_t)0x2UL) /**< APBSEC_PERIPH_SIR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_SIR (MXC_V_SPC_APBSEC_PERIPH_SIR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_SIR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_FCR ((uint32_t)0x4UL) /**< APBSEC_PERIPH_FCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_FCR (MXC_V_SPC_APBSEC_PERIPH_FCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_FCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WDT ((uint32_t)0x8UL) /**< APBSEC_PERIPH_WDT Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WDT (MXC_V_SPC_APBSEC_PERIPH_WDT << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WDT Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_AES ((uint32_t)0x10UL) /**< APBSEC_PERIPH_AES Value */ +#define MXC_S_SPC_APBSEC_PERIPH_AES (MXC_V_SPC_APBSEC_PERIPH_AES << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_AES Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBSEC_PERIPH_AESKEYS Value */ +#define MXC_S_SPC_APBSEC_PERIPH_AESKEYS (MXC_V_SPC_APBSEC_PERIPH_AESKEYS << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_AESKEYS Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_CRC ((uint32_t)0x40UL) /**< APBSEC_PERIPH_CRC Value */ +#define MXC_S_SPC_APBSEC_PERIPH_CRC (MXC_V_SPC_APBSEC_PERIPH_CRC << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_CRC Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBSEC_PERIPH_GPIO0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_GPIO0 (MXC_V_SPC_APBSEC_PERIPH_GPIO0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_GPIO0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBSEC_PERIPH_TMR0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR0 (MXC_V_SPC_APBSEC_PERIPH_TMR0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBSEC_PERIPH_TMR1 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR1 (MXC_V_SPC_APBSEC_PERIPH_TMR1 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR1 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBSEC_PERIPH_TMR2 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR2 (MXC_V_SPC_APBSEC_PERIPH_TMR2 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR2 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBSEC_PERIPH_TMR3 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR3 (MXC_V_SPC_APBSEC_PERIPH_TMR3 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR3 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBSEC_PERIPH_TMR4 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR4 (MXC_V_SPC_APBSEC_PERIPH_TMR4 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR4 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBSEC_PERIPH_TMR5 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR5 (MXC_V_SPC_APBSEC_PERIPH_TMR5 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR5 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBSEC_PERIPH_I3C Value */ +#define MXC_S_SPC_APBSEC_PERIPH_I3C (MXC_V_SPC_APBSEC_PERIPH_I3C << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_I3C Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_UART ((uint32_t)0x8000UL) /**< APBSEC_PERIPH_UART Value */ +#define MXC_S_SPC_APBSEC_PERIPH_UART (MXC_V_SPC_APBSEC_PERIPH_UART << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_UART Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBSEC_PERIPH_SPI Value */ +#define MXC_S_SPC_APBSEC_PERIPH_SPI (MXC_V_SPC_APBSEC_PERIPH_SPI << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_SPI Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBSEC_PERIPH_TRNG Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TRNG (MXC_V_SPC_APBSEC_PERIPH_TRNG << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TRNG Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBSEC_PERIPH_BTLE_DBB Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BTLE_DBB (MXC_V_SPC_APBSEC_PERIPH_BTLE_DBB << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BTLE_DBB Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBSEC_PERIPH_BTLE_RFFE Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BTLE_RFFE (MXC_V_SPC_APBSEC_PERIPH_BTLE_RFFE << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBSEC_PERIPH_RSTZ Value */ +#define MXC_S_SPC_APBSEC_PERIPH_RSTZ (MXC_V_SPC_APBSEC_PERIPH_RSTZ << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_RSTZ Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBSEC_PERIPH_BOOST Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BOOST (MXC_V_SPC_APBSEC_PERIPH_BOOST << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BOOST Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBSEC_PERIPH_TRIMSIR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TRIMSIR (MXC_V_SPC_APBSEC_PERIPH_TRIMSIR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TRIMSIR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBSEC_PERIPH_RTC Value */ +#define MXC_S_SPC_APBSEC_PERIPH_RTC (MXC_V_SPC_APBSEC_PERIPH_RTC << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_RTC Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBSEC_PERIPH_WUT0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WUT0 (MXC_V_SPC_APBSEC_PERIPH_WUT0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WUT0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBSEC_PERIPH_WUT1 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WUT1 (MXC_V_SPC_APBSEC_PERIPH_WUT1 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WUT1 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBSEC_PERIPH_PWRSEQ Value */ +#define MXC_S_SPC_APBSEC_PERIPH_PWRSEQ (MXC_V_SPC_APBSEC_PERIPH_PWRSEQ << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_PWRSEQ Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBSEC_PERIPH_MCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_MCR (MXC_V_SPC_APBSEC_PERIPH_MCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_MCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBSEC_PERIPH_ALL Value */ +#define MXC_S_SPC_APBSEC_PERIPH_ALL (MXC_V_SPC_APBSEC_PERIPH_ALL << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_ALL Setting */ /**@} end of group SPC_APBSEC_Register */ @@ -281,30 +340,88 @@ typedef struct { */ #define MXC_F_SPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ #define MXC_F_SPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ +#define MXC_V_SPC_APBPRIV_PERIPH_GCR ((uint32_t)0x1UL) /**< APBPRIV_PERIPH_GCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_GCR (MXC_V_SPC_APBPRIV_PERIPH_GCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_SIR ((uint32_t)0x2UL) /**< APBPRIV_PERIPH_SIR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_SIR (MXC_V_SPC_APBPRIV_PERIPH_SIR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SIR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_FCR ((uint32_t)0x4UL) /**< APBPRIV_PERIPH_FCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_FCR (MXC_V_SPC_APBPRIV_PERIPH_FCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_FCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WDT ((uint32_t)0x8UL) /**< APBPRIV_PERIPH_WDT Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WDT (MXC_V_SPC_APBPRIV_PERIPH_WDT << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WDT Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_AES ((uint32_t)0x10UL) /**< APBPRIV_PERIPH_AES Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_AES (MXC_V_SPC_APBPRIV_PERIPH_AES << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AES Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBPRIV_PERIPH_AESKEYS Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_AESKEYS (MXC_V_SPC_APBPRIV_PERIPH_AESKEYS << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AESKEYS Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_CRC ((uint32_t)0x40UL) /**< APBPRIV_PERIPH_CRC Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_CRC (MXC_V_SPC_APBPRIV_PERIPH_CRC << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_CRC Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBPRIV_PERIPH_GPIO0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_GPIO0 (MXC_V_SPC_APBPRIV_PERIPH_GPIO0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GPIO0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBPRIV_PERIPH_TMR0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR0 (MXC_V_SPC_APBPRIV_PERIPH_TMR0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBPRIV_PERIPH_TMR1 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR1 (MXC_V_SPC_APBPRIV_PERIPH_TMR1 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR1 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBPRIV_PERIPH_TMR2 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR2 (MXC_V_SPC_APBPRIV_PERIPH_TMR2 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR2 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBPRIV_PERIPH_TMR3 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR3 (MXC_V_SPC_APBPRIV_PERIPH_TMR3 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR3 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBPRIV_PERIPH_TMR4 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR4 (MXC_V_SPC_APBPRIV_PERIPH_TMR4 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR4 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBPRIV_PERIPH_TMR5 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR5 (MXC_V_SPC_APBPRIV_PERIPH_TMR5 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR5 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBPRIV_PERIPH_I3C Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_I3C (MXC_V_SPC_APBPRIV_PERIPH_I3C << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_I3C Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_UART ((uint32_t)0x8000UL) /**< APBPRIV_PERIPH_UART Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_UART (MXC_V_SPC_APBPRIV_PERIPH_UART << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_UART Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBPRIV_PERIPH_SPI Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_SPI (MXC_V_SPC_APBPRIV_PERIPH_SPI << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SPI Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBPRIV_PERIPH_TRNG Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TRNG (MXC_V_SPC_APBPRIV_PERIPH_TRNG << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRNG Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBPRIV_PERIPH_BTLE_DBB Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BTLE_DBB (MXC_V_SPC_APBPRIV_PERIPH_BTLE_DBB << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_DBB Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBPRIV_PERIPH_BTLE_RFFE Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BTLE_RFFE (MXC_V_SPC_APBPRIV_PERIPH_BTLE_RFFE << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBPRIV_PERIPH_RSTZ Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_RSTZ (MXC_V_SPC_APBPRIV_PERIPH_RSTZ << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RSTZ Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBPRIV_PERIPH_BOOST Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BOOST (MXC_V_SPC_APBPRIV_PERIPH_BOOST << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BOOST Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBPRIV_PERIPH_TRIMSIR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TRIMSIR (MXC_V_SPC_APBPRIV_PERIPH_TRIMSIR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRIMSIR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBPRIV_PERIPH_RTC Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_RTC (MXC_V_SPC_APBPRIV_PERIPH_RTC << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RTC Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBPRIV_PERIPH_WUT0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WUT0 (MXC_V_SPC_APBPRIV_PERIPH_WUT0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBPRIV_PERIPH_WUT1 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WUT1 (MXC_V_SPC_APBPRIV_PERIPH_WUT1 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT1 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBPRIV_PERIPH_PWRSEQ Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_PWRSEQ (MXC_V_SPC_APBPRIV_PERIPH_PWRSEQ << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_PWRSEQ Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBPRIV_PERIPH_MCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_MCR (MXC_V_SPC_APBPRIV_PERIPH_MCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_MCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBPRIV_PERIPH_ALL Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_ALL (MXC_V_SPC_APBPRIV_PERIPH_ALL << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_ALL Setting */ /**@} end of group SPC_APBPRIV_Register */ /** * @ingroup spc_registers - * @defgroup SPC_GPIO0 SPC_GPIO0 - * @brief Secure GPIO0 Configuration Register. + * @defgroup SPC_AHBMPRIV SPC_AHBMPRIV + * @brief AHB Privileged/Non-privileged Secure DMA Access. * @{ */ -#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ -#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0xFFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ +#define MXC_F_SPC_AHBMPRIV_DMA_POS 0 /**< AHBMPRIV_DMA Position */ +#define MXC_F_SPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_SPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ -/**@} end of group SPC_GPIO0_Register */ +/**@} end of group SPC_AHBMPRIV_Register */ /** * @ingroup spc_registers - * @defgroup SPC_GPIO1 SPC_GPIO1 - * @brief Secure GPIO1 Configuration Register. + * @defgroup SPC_GPIO0 SPC_GPIO0 + * @brief Secure GPIO0 Configuration Register. * @{ */ -#define MXC_F_SPC_GPIO1_PINS_POS 0 /**< GPIO1_PINS Position */ -#define MXC_F_SPC_GPIO1_PINS ((uint32_t)(0x3UL << MXC_F_SPC_GPIO1_PINS_POS)) /**< GPIO1_PINS Mask */ +#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ +#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0x3FFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ -/**@} end of group SPC_GPIO1_Register */ +/**@} end of group SPC_GPIO0_Register */ #ifdef __cplusplus } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index e965112191c..c9443d1da82 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -156,8 +156,8 @@ typedef struct { #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ -#define MXC_F_SPI_CTRL0_CTRLR_MODE_POS 1 /**< CTRL0_CTRLR_MODE Position */ -#define MXC_F_SPI_CTRL0_CTRLR_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CTRLR_MODE_POS)) /**< CTRL0_CTRLR_MODE Mask */ +#define MXC_F_SPI_CTRL0_CONT_MODE_POS 1 /**< CTRL0_CONT_MODE Position */ +#define MXC_F_SPI_CTRL0_CONT_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CONT_MODE_POS)) /**< CTRL0_CONT_MODE Mask */ #define MXC_F_SPI_CTRL0_TS_IO_POS 4 /**< CTRL0_TS_IO Position */ #define MXC_F_SPI_CTRL0_TS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_IO_POS)) /**< CTRL0_TS_IO Mask */ @@ -383,8 +383,8 @@ typedef struct { #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ -#define MXC_F_SPI_INTFL_CTRLR_DONE_POS 11 /**< INTFL_CTRLR_DONE Position */ -#define MXC_F_SPI_INTFL_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CTRLR_DONE_POS)) /**< INTFL_CTRLR_DONE Mask */ +#define MXC_F_SPI_INTFL_CONT_DONE_POS 11 /**< INTFL_CONT_DONE Position */ +#define MXC_F_SPI_INTFL_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CONT_DONE_POS)) /**< INTFL_CONT_DONE Mask */ #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ @@ -430,8 +430,8 @@ typedef struct { #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ -#define MXC_F_SPI_INTEN_CTRLR_DONE_POS 11 /**< INTEN_CTRLR_DONE Position */ -#define MXC_F_SPI_INTEN_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CTRLR_DONE_POS)) /**< INTEN_CTRLR_DONE Mask */ +#define MXC_F_SPI_INTEN_CONT_DONE_POS 11 /**< INTEN_CONT_DONE Position */ +#define MXC_F_SPI_INTEN_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CONT_DONE_POS)) /**< INTEN_CONT_DONE Mask */ #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h index a0a5f81ca15..0a086a133b4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -84,6 +84,24 @@ void SystemInit(void); */ void SystemCoreClockUpdate(void); +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief This function is called in Secure code just before control + * is transferred to non-secure world. Only available when + * trustzone feature is used. + * + * You may over-ride this function in your program by defining a custom + * NonSecure_Init(), but care should be taken to reproduce the initialization + * steps to non-secure code. + * + * Caller must be aware of configuring MPC, SPC, and NSPC before this + * function is called. + * + * @return Should not return if successful. If Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int NonSecure_Init(void); +#endif + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h index 7b4b85265a4..831c2a57deb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -162,12 +162,8 @@ typedef struct { #define MXC_F_UART_CTRL_CLK_SEL ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CLK_SEL_POS)) /**< CTRL_CLK_SEL Mask */ #define MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Value */ #define MXC_S_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Setting */ -#define MXC_V_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_CLK_SEL_EXTERNAL_CLOCK Value */ -#define MXC_S_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK (MXC_V_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_EXTERNAL_CLOCK Setting */ -#define MXC_V_UART_CTRL_CLK_SEL_CLK2 ((uint32_t)0x2UL) /**< CTRL_CLK_SEL_CLK2 Value */ -#define MXC_S_UART_CTRL_CLK_SEL_CLK2 (MXC_V_UART_CTRL_CLK_SEL_CLK2 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK2 Setting */ -#define MXC_V_UART_CTRL_CLK_SEL_CLK3 ((uint32_t)0x3UL) /**< CTRL_CLK_SEL_CLK3 Value */ -#define MXC_S_UART_CTRL_CLK_SEL_CLK3 (MXC_V_UART_CTRL_CLK_SEL_CLK3 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK3 Setting */ +#define MXC_V_UART_CTRL_CLK_SEL_CLK1 ((uint32_t)0x1UL) /**< CTRL_CLK_SEL_CLK1 Value */ +#define MXC_S_UART_CTRL_CLK_SEL_CLK1 (MXC_V_UART_CTRL_CLK_SEL_CLK1 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK1 Setting */ #define MXC_F_UART_CTRL_CLK_RDY_POS 19 /**< CTRL_CLK_RDY Position */ #define MXC_F_UART_CTRL_CLK_RDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_RDY_POS)) /**< CTRL_CLK_RDY Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c new file mode 100644 index 00000000000..35f1e05cab8 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/***** Includes *****/ +#include +#include + +extern uint32_t _application_end; + +#define SLA_HEADER_MAGIC0 0xBF1421E4 +#define SLA_HEADER_MAGIC1 0x461A8CF5 +#define SLA_HEADER_VERSION 0x00000001 +#define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001 +#define SLA_HEADER_RESERVED 0x00000000 + +typedef struct +{ + uint32_t magic0; + uint32_t magic1; + uint32_t version; + uint32_t verifytype; + uint32_t sigaddress; + uint32_t reserved5; + uint32_t reserved6; + uint32_t reserved7; +} flash_app_header_t; + +__attribute__ ((section(".sla_header"))) __attribute__ ((__used__)) +const flash_app_header_t sla_header = +{ + .magic0 = SLA_HEADER_MAGIC0, + .magic1 = SLA_HEADER_MAGIC1, + .version = SLA_HEADER_VERSION, + .verifytype = SLA_HEADER_ALGORITHM_ECDSA, + .sigaddress = (uint32_t)&_application_end, + .reserved5 = SLA_HEADER_RESERVED, + .reserved6 = SLA_HEADER_RESERVED, + .reserved7 = SLA_HEADER_RESERVED +}; + diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index ac9719da57d..5a6f5805554 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -21,10 +21,23 @@ #include #include #include "mxc_sys.h" +#include "mxc_errors.h" #include "max32657.h" #include "system_max32657.h" -#include "partition_max32657.h" #include "gcr_regs.h" +#include "mpc.h" + + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include "partition_max32657.h" + +// From linker script. +extern uint32_t _nonsecure_start, _nonsecure_end; + +#define VECTOR_TABLE_START_ADDR_NS (uint32_t)(&_nonsecure_start) // Now setting the start of the vector table using a linker symbol +#define MXC_Reset_Handler_NS (mxc_ns_call_t)*((uint32_t*)(VECTOR_TABLE_START_ADDR_NS + 4)) +#define MXC_MSP_NS *((uint32_t*)(VECTOR_TABLE_START_ADDR_NS)) +#endif extern void (*const __isr_vector[])(void); @@ -84,7 +97,8 @@ __weak void SystemCoreClockUpdate(void) SystemCoreClock = base_freq >> div; } -/* This function is called before C runtime initialization and can be +/** + * This function is called before C runtime initialization and can be * implemented by the application for early initializations. If a value other * than '0' is returned, the C runtime initialization will be skipped. * @@ -95,12 +109,11 @@ __weak void SystemCoreClockUpdate(void) __weak int PreInit(void) { /* Do nothing */ - // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. - // (SW): Correct, different power HW. return 0; } -/* This function is called before the Board_Init function. This weak +/** + * This function is called before the Board_Init function. This weak * implementation does nothing, but you may over-ride this function in your * program if you want to configure the state of all pins prior to the * application running. This is useful when using external tools (like a @@ -118,7 +131,8 @@ __weak int Board_Init(void) return 0; } -/* This function is called just before control is transferred to main(). +/** + * This function is called just before control is transferred to main(). * * You may over-ride this function in your program by defining a custom * SystemInit(), but care should be taken to reproduce the initialization @@ -135,19 +149,20 @@ __weak void SystemInit(void) SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; #endif /* __FPU_PRESENT check */ - /* - Enable Unaligned Access Trapping to throw an exception when there is an - unaligned memory access while unaligned access support is disabled. - - Note: ARMv8-M without the Main Extension disables unaligned access by default. - */ + /** + * Enable Unaligned Access Trapping to throw an exception when there is an + * unaligned memory access while unaligned access support is disabled. + * + * Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ #if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; #endif /* Security Extension Features */ -#if IS_SECURE_ENVIRONMENT +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ + /* Set up secure and non-secure regions with SAU. */ TZ_SAU_Setup(); #endif /* TrustZone */ @@ -168,3 +183,65 @@ __weak void SystemInit(void) PinInit(); Board_Init(); } + + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * This function is called in Secure code just before control + * is transferred to non-secure world. Only available when + * trustzone feature is used. + * + * You may over-ride this function in your program by defining a custom + * NonSecure_Init(), but care should be taken to reproduce the initialization + * steps to non-secure code. + * + * Caller must be aware of configuring MPC, SPC, and NSPC before this + * function is called. + * + * Function should never return if successful. + */ +__weak int NonSecure_Init(void) +{ + int error; + mxc_ns_call_t Reset_Handler_NS; + + // Secure world must enable FPU for non-secure world. (Turned off by default). +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB_NS->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + // Setup Non-Secure vector table. + // Global symbols defined in Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/nonsecure_load.S + // indicates the beginning of the nonsecure image, which starts at the vector table. + SCB_NS->VTOR = VECTOR_TABLE_START_ADDR_NS; + + // Setup Non-Secure Main Stack Pointer (MSP_NS). + // Start of vector table contains top of stack value. + __TZ_set_MSP_NS(MXC_MSP_NS); + + // Get Non-Secure Reset_Handler. + Reset_Handler_NS = MXC_Reset_Handler_NS; + + // Set MPCs for Non-Secure region. + // (Not setting up Secure regions as, by default, MPC regions are set as secure on startup). + error = MXC_MPC_SetNonSecure((uint32_t)(&_nonsecure_start), (uint32_t)(&_nonsecure_end)); + if (error != E_NO_ERROR) { + return error; + } + + // Lock MPCs. + MXC_MPC_Lock(MXC_MPC_FLASH); + MXC_MPC_Lock(MXC_MPC_SRAM0); + MXC_MPC_Lock(MXC_MPC_SRAM1); + MXC_MPC_Lock(MXC_MPC_SRAM2); + MXC_MPC_Lock(MXC_MPC_SRAM3); + MXC_MPC_Lock(MXC_MPC_SRAM4); + + // Start Non-Secure code. + Reset_Handler_NS(); + + // Should not reach here if switching to non-secure world was successful. + return E_FAIL; +} +#endif diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index b42a98f7519..5c3f123165b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -59,11 +59,13 @@ typedef enum { MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection MXC_DMA_REQUEST_SPIRX = MXC_S_DMA_CTRL_REQUEST_SPIRX, ///< SPI Receive DMA Request Selection MXC_DMA_REQUEST_UARTRX = MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection - MXC_DMA_REQUEST_I3CRX = MXC_S_DMA_CTRL_REQUEST_I3CRX, ///< I3C Receive DMA Request Selection + MXC_DMA_REQUEST_I3CRX_CONT = MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT, ///< I3C Receive Controller DMA Request Selection + MXC_DMA_REQUEST_I3CRX_TARG = MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG, ///< I3C Receive Target DMA Request Selection MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection MXC_DMA_REQUEST_SPITX = MXC_S_DMA_CTRL_REQUEST_SPITX, ///< SPI Transmit DMA Request Selection MXC_DMA_REQUEST_UARTTX = MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection - MXC_DMA_REQUEST_I3CTX = MXC_S_DMA_CTRL_REQUEST_I3CTX, ///< I3C Transmit DMA Request Selection + MXC_DMA_REQUEST_I3CTX_CONT = MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT, ///< I3C Transmit Controller DMA Request Selection + MXC_DMA_REQUEST_I3CTX_TARG = MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG, ///< I3C Transmit Target DMA Request Selection MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection } mxc_dma_reqsel_t; diff --git a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h index 8949a33e434..bbf449bd4cb 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h @@ -153,8 +153,8 @@ typedef enum { MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */ MXC_GPIO_PAD_PULL_UP, /**< Set pad to strong pull-up */ MXC_GPIO_PAD_PULL_DOWN, /**< Set pad to strong pull-down */ - MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */ - MXC_GPIO_PAD_WEAK_PULL_DOWN, /**< Set pad to weak pull-down */ + MXC_GPIO_PAD_WEAK_PULL_UP = MXC_GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ + MXC_GPIO_PAD_WEAK_PULL_DOWN = MXC_GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */ } mxc_gpio_pad_t; /** diff --git a/Libraries/PeriphDrivers/Include/MAX32657/i3c.h b/Libraries/PeriphDrivers/Include/MAX32657/i3c.h index 75a32ecf733..95a592f4693 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/i3c.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/i3c.h @@ -153,9 +153,9 @@ struct _i3c_ccc_req_t { }; /** - * @brief Private SDR/I2C request structure. + * @brief Private SDR request structure. * - * SDR/I2C read and write to an I3C target. + * SDR read and write to an I3C target. * */ struct _i3c_req_t { diff --git a/Libraries/PeriphDrivers/Include/MAX32657/icc.h b/Libraries/PeriphDrivers/Include/MAX32657/icc.h index 962cf0217be..252bd958920 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/icc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/icc.h @@ -53,22 +53,22 @@ typedef enum { * @param cid Enumeration type for Cache Id Register. * @retval Returns the contents of Cache Id Register. */ -int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid); +int MXC_ICC_ID(mxc_icc_info_t cid); /** * @brief Enable the instruction cache controller. */ -void MXC_ICC_Enable(mxc_icc_regs_t *icc); +void MXC_ICC_Enable(void); /** * @brief Disable the instruction cache controller. */ -void MXC_ICC_Disable(mxc_icc_regs_t *icc); +void MXC_ICC_Disable(void); /** * @brief Flush the instruction cache controller. */ -void MXC_ICC_Flush(mxc_icc_regs_t *icc); +void MXC_ICC_Flush(void); /**@} end of group icc */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/lp.h b/Libraries/PeriphDrivers/Include/MAX32657/lp.h index e4c53fce38b..0e4ea3bb688 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/lp.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/lp.h @@ -49,15 +49,6 @@ extern "C" { */ typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t; -/** - * @brief Enumeration type for PM Mode - * - */ -typedef enum { - MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, - MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD, -} mxc_lp_cfg_ds_pd_t; - /** * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mpc.h b/Libraries/PeriphDrivers/Include/MAX32657/mpc.h new file mode 100644 index 00000000000..d3cd04885d4 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mpc.h @@ -0,0 +1,97 @@ +/** + * @file mpc.h + * @brief Memory Protection Controller (MPC) Header File. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_TRUSTED_EXECUTION_SECURE + +/**** Includes ****/ +#include +#include "mxc_device.h" +#include "mpc_regs.h" + +/**** Defines ****/ + +/**** Function Prototypes ****/ + +/** + * @brief Checks whether a region fits within the constraints of physical + * memory (Flash or SRAM). + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_CheckPhyBoundaries(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Get the MPC register instance where the address is located. + * @param addr Address within memory. + * @return Pointer to MPC registers associated with the address. + */ +mxc_mpc_regs_t *MXC_MPC_GetInstance(uint32_t addr); + +/** + * @brief Gets the MPC block index that the register is located in which + * is associated to the bit location of MPC_BLK_LUT register. + * This function is NOT associated with the MPC_BLK_IDX register. + * @param mpc Pointer to MPC region associated with the addr (param[1]). + * @param addr Address within memory. + * @return The block index if successful. If Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_GetBlockIdx(mxc_mpc_regs_t *mpc, uint32_t addr); + +/** + * @brief Sets the region to Secure. + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_SetSecure(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Sets the region to Non-Secure. + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_SetNonSecure(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Locks the MPC registers. Prevents write access. + * @param mpc Pointer to MPC registers to lockdown. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_Lock(mxc_mpc_regs_t *mpc); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 840d2bf2b45..d705c0ca2ad 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -40,7 +40,7 @@ extern "C" { /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ typedef enum { - MXC_SYS_RESET0_DMA0 = MXC_F_GCR_RST0_DMA0_POS, /**< Reset DMA0 */ + MXC_SYS_RESET0_DMA0 = MXC_F_GCR_RST0_DMA0_POS, /**< Reset Non-Secure DMA0 */ MXC_SYS_RESET0_WDT = MXC_F_GCR_RST0_WDT_POS, /**< Reset WDT */ MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */ @@ -53,21 +53,21 @@ typedef enum { MXC_SYS_RESET0_SPI = MXC_F_GCR_RST0_SPI_POS, /**< Reset SPI */ MXC_SYS_RESET0_I3C = MXC_F_GCR_RST0_I3C, /**< Reset I2C/I3C */ MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ - // MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ - MXC_SYS_RESET0_DMA1 = MXC_F_GCR_RST0_DMA1_POS, /**< Reset DMA0 */ + MXC_SYS_RESET0_DMA1 = MXC_F_GCR_RST0_DMA1_POS, /**< Reset Secure DMA1 */ MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ + MXC_SYS_RESET1_AUTOCAL = (MXC_F_GCR_RST1_AUTOCAL_POS + 32), /**< Reset AUTOCAL */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_DMA0 = MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable DMA0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA0 = MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable Non-Secure DMA0 clock */ MXC_SYS_PERIPH_CLOCK_SPI = MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ MXC_SYS_PERIPH_CLOCK_UART = MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ MXC_SYS_PERIPH_CLOCK_I3C = MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ @@ -79,13 +79,9 @@ typedef enum { MXC_SYS_PERIPH_CLOCK_TMR5 = MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ - // MXC_SYS_PERIPH_CLOCK_SMPHR = - // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ - // MXC_SYS_PERIPH_CLOCK_SPI = - // (MXC_F_GCR_PCLKDIS1_SPI_POS + 32), /**< Disable SPI clock */ - // TODO(JC): The SPI clock disable is defined in both PCLKDIS0 and PCLKDIS1 + MXC_SYS_PERIPH_CLOCK_DMA1 = (MXC_F_GCR_PCLKDIS1_DMA1_POS + 32), /**< Disable Secure DMA1 clock */ MXC_SYS_PERIPH_CLOCK_WDT = (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ } mxc_sys_periph_clock_t; diff --git a/Libraries/PeriphDrivers/Include/MAX32657/nspc.h b/Libraries/PeriphDrivers/Include/MAX32657/nspc.h new file mode 100644 index 00000000000..b757c47fdeb --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/nspc.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ + + + +#include "mxc_device.h" +#include "nspc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nspc NSPC + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief NSPC Peripheral Definition for setting the Privilege State. + */ +typedef enum { + MXC_NSPC_PERIPH_GCR = MXC_S_NSPC_APBPRIV_PERIPH_GCR, /**< GCR */ + MXC_NSPC_PERIPH_SIR = MXC_S_NSPC_APBPRIV_PERIPH_SIR, /**< SIR */ + MXC_NSPC_PERIPH_FCR = MXC_S_NSPC_APBPRIV_PERIPH_FCR, /**< FCR */ + MXC_NSPC_PERIPH_WDT = MXC_S_NSPC_APBPRIV_PERIPH_WDT, /**< WDT */ + MXC_NSPC_PERIPH_AES = MXC_S_NSPC_APBPRIV_PERIPH_AES, /**< AES */ + MXC_NSPC_PERIPH_AESKEYS = MXC_S_NSPC_APBPRIV_PERIPH_AESKEYS, /**< AESKEYS */ + MXC_NSPC_PERIPH_GPIO0 = MXC_S_NSPC_APBPRIV_PERIPH_GPIO0, /**< GPIO0 */ + MXC_NSPC_PERIPH_CRC = MXC_S_NSPC_APBPRIV_PERIPH_CRC, /**< CRC */ + MXC_NSPC_PERIPH_TMR0 = MXC_S_NSPC_APBPRIV_PERIPH_TMR0, /**< TMR0 */ + MXC_NSPC_PERIPH_TMR1 = MXC_S_NSPC_APBPRIV_PERIPH_TMR1, /**< TMR1 */ + MXC_NSPC_PERIPH_TMR2 = MXC_S_NSPC_APBPRIV_PERIPH_TMR2, /**< TMR2 */ + MXC_NSPC_PERIPH_TMR3 = MXC_S_NSPC_APBPRIV_PERIPH_TMR3, /**< TMR3 */ + MXC_NSPC_PERIPH_TMR4 = MXC_S_NSPC_APBPRIV_PERIPH_TMR4, /**< TMR4 */ + MXC_NSPC_PERIPH_TMR5 = MXC_S_NSPC_APBPRIV_PERIPH_TMR5, /**< TMR5 */ + MXC_NSPC_PERIPH_I3C = MXC_S_NSPC_APBPRIV_PERIPH_I3C, /**< I3C */ + MXC_NSPC_PERIPH_UART = MXC_S_NSPC_APBPRIV_PERIPH_UART, /**< UART */ + MXC_NSPC_PERIPH_SPI = MXC_S_NSPC_APBPRIV_PERIPH_SPI, /**< SPI */ + MXC_NSPC_PERIPH_TRNG = MXC_S_NSPC_APBPRIV_PERIPH_TRNG, /**< TRNG */ + MXC_NSPC_PERIPH_BTLE_DBB = MXC_S_NSPC_APBPRIV_PERIPH_BTLE_DBB, /**< BTLE DBB */ + MXC_NSPC_PERIPH_BTLE_RFFE = MXC_S_NSPC_APBPRIV_PERIPH_BTLE_RFFE, /**< BTLE RFFE */ + MXC_NSPC_PERIPH_RSTZ = MXC_S_NSPC_APBPRIV_PERIPH_RSTZ, /**< RSTZ */ + MXC_NSPC_PERIPH_BOOST = MXC_S_NSPC_APBPRIV_PERIPH_BOOST, /**< BOOST */ + MXC_NSPC_PERIPH_TRIMSIR = MXC_S_NSPC_APBPRIV_PERIPH_TRIMSIR, /**< TRIMSIR */ + MXC_NSPC_PERIPH_RTC = MXC_S_NSPC_APBPRIV_PERIPH_RTC, /**< RTC */ + MXC_NSPC_PERIPH_WUT0 = MXC_S_NSPC_APBPRIV_PERIPH_WUT0, /**< WUT0 */ + MXC_NSPC_PERIPH_WUT1 = MXC_S_NSPC_APBPRIV_PERIPH_WUT1, /**< WUT1 */ + MXC_NSPC_PERIPH_PWRSEQ = MXC_S_NSPC_APBPRIV_PERIPH_PWRSEQ, /**< PWRSEQ */ + MXC_NSPC_PERIPH_MCR = MXC_S_NSPC_APBPRIV_PERIPH_MCR, /**< MCR */ + MXC_NSPC_PERIPH_ALL = MXC_S_NSPC_APBPRIV_PERIPH_ALL, /**< All */ +} mxc_nspc_periph_t; + +/** @brief Enumeration for ARM privilege settings. */ +typedef enum { + MXC_NSPC_PRIVILEGED = 0, + MXC_NSPC_UNPRIVILEGED = 1, +} mxc_nspc_priv_t; + +/***** Function Prototypes *****/ + +/** + * @brief Sets the privilege level for a Peripheral. + * @param periph Enumeration for desired peripheral. + * @param priv Enumeration for desired privilege level. + */ +void MXC_NSPC_SetPrivAccess(mxc_nspc_periph_t periph, mxc_nspc_priv_t priv); + +/** + * @brief Sets the privilege level for Non-Secure DMA. + * @param priv Enumeration for desired privilege level. + */ +void MXC_NSPC_DMA_SetPrivAccess(mxc_nspc_priv_t priv); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h index 0b96279aab5..6367d3ea35c 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h @@ -40,27 +40,6 @@ extern "C" { */ void MXC_NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)); -#if defined(__GNUC__) -#if __CM4_CMSIS_VERSION_MAIN == 0x03 -// NVIC_SetVector was custom-implemented in the PeriphDrivers library for -// CMSIS version 3. Newer versions of CMSIS provide an implementation of -// NVIC_SetVector with different functionality, so the Maxim implementation -// has been moved to MXC_NVIC_SetVector (above). - -// The MSDK will move to CMSIS version 5 in the future. - -// For CMSIS version 3, use MXC_NVIC_SetVector instead. -// For CMSIS version 5, you have the choice of using either. However, only -// MXC_NVIC_SetVector will work with legacy code. -inline __attribute__(( - deprecated("Use MXC_NVIC_SetVector instead. See nvic_table.h for more details."))) void -NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)) -{ - MXC_NVIC_SetVector(irqn, irq_callback); -} -#endif -#endif - /** * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. * @@ -77,27 +56,6 @@ void NVIC_SetRAM(void); */ uint32_t MXC_NVIC_GetVector(IRQn_Type IRQn); -#if defined(__GNUC__) -#if __CM4_CMSIS_VERSION_MAIN == 0x03 -// NVIC_GetVector was custom-implemented in the PeriphDrivers library for -// CMSIS version 3. Newer versions of CMSIS provide an implementation of -// NVIC_GetVector with different functionality, so the Maxim implementation -// has been moved to MXC_NVIC_GetVector (above). - -// The MSDK will move to CMSIS version 5 in the future. - -// For CMSIS version 3, use MXC_NVIC_SetVector instead. -// For CMSIS version 5, you have the choice of using either. However, only -// MXC_NVIC_GetVector will work with legacy code. -inline __attribute__(( - deprecated("Use MXC_NVIC_GetVector instead. See nvic_table.h for more details."))) void -NVIC_GetVector(IRQn_Type irqn) -{ - MXC_NVIC_GetVector(irqn); -} -#endif -#endif - #ifdef __cplusplus } #endif diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spc.h b/Libraries/PeriphDrivers/Include/MAX32657/spc.h new file mode 100644 index 00000000000..ab1c87ba6bf --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/spc.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ + +#include +#include +#include "mxc_device.h" +#include "spc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spc SPC + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief SPC Peripheral Definition for setting the Security and Privilege State. + * The SPC_APBSEC register definitions are used, but this can also be used + * for the SPC_APBPRIV register as well since the peripheral fields are a + * one-to-one match. + */ +typedef enum { + MXC_SPC_PERIPH_GCR = MXC_S_SPC_APBSEC_PERIPH_GCR, /**< GCR */ + MXC_SPC_PERIPH_SIR = MXC_S_SPC_APBSEC_PERIPH_SIR, /**< SIR */ + MXC_SPC_PERIPH_FCR = MXC_S_SPC_APBSEC_PERIPH_FCR, /**< FCR */ + MXC_SPC_PERIPH_WDT = MXC_S_SPC_APBSEC_PERIPH_WDT, /**< WDT */ + MXC_SPC_PERIPH_AES = MXC_S_SPC_APBSEC_PERIPH_AES, /**< AES */ + MXC_SPC_PERIPH_AESKEYS = MXC_S_SPC_APBSEC_PERIPH_AESKEYS, /**< AESKEYS */ + MXC_SPC_PERIPH_GPIO0 = MXC_S_SPC_APBSEC_PERIPH_GPIO0, /**< GPIO0 */ + MXC_SPC_PERIPH_CRC = MXC_S_SPC_APBSEC_PERIPH_CRC, /**< CRC */ + MXC_SPC_PERIPH_TMR0 = MXC_S_SPC_APBSEC_PERIPH_TMR0, /**< TMR0 */ + MXC_SPC_PERIPH_TMR1 = MXC_S_SPC_APBSEC_PERIPH_TMR1, /**< TMR1 */ + MXC_SPC_PERIPH_TMR2 = MXC_S_SPC_APBSEC_PERIPH_TMR2, /**< TMR2 */ + MXC_SPC_PERIPH_TMR3 = MXC_S_SPC_APBSEC_PERIPH_TMR3, /**< TMR3 */ + MXC_SPC_PERIPH_TMR4 = MXC_S_SPC_APBSEC_PERIPH_TMR4, /**< TMR4 */ + MXC_SPC_PERIPH_TMR5 = MXC_S_SPC_APBSEC_PERIPH_TMR5, /**< TMR5 */ + MXC_SPC_PERIPH_I3C = MXC_S_SPC_APBSEC_PERIPH_I3C, /**< I3C */ + MXC_SPC_PERIPH_UART = MXC_S_SPC_APBSEC_PERIPH_UART, /**< UART */ + MXC_SPC_PERIPH_SPI = MXC_S_SPC_APBSEC_PERIPH_SPI, /**< SPI */ + MXC_SPC_PERIPH_TRNG = MXC_S_SPC_APBSEC_PERIPH_TRNG, /**< TRNG */ + MXC_SPC_PERIPH_BTLE_DBB = MXC_S_SPC_APBSEC_PERIPH_BTLE_DBB, /**< BTLE DBB */ + MXC_SPC_PERIPH_BTLE_RFFE = MXC_S_SPC_APBSEC_PERIPH_BTLE_RFFE, /**< BTLE RFFE */ + MXC_SPC_PERIPH_RSTZ = MXC_S_SPC_APBSEC_PERIPH_RSTZ, /**< RSTZ */ + MXC_SPC_PERIPH_BOOST = MXC_S_SPC_APBSEC_PERIPH_BOOST, /**< BOOST */ + MXC_SPC_PERIPH_TRIMSIR = MXC_S_SPC_APBSEC_PERIPH_TRIMSIR, /**< TRIMSIR */ + MXC_SPC_PERIPH_RTC = MXC_S_SPC_APBSEC_PERIPH_RTC, /**< RTC */ + MXC_SPC_PERIPH_WUT0 = MXC_S_SPC_APBSEC_PERIPH_WUT0, /**< WUT0 */ + MXC_SPC_PERIPH_WUT1 = MXC_S_SPC_APBSEC_PERIPH_WUT1, /**< WUT1 */ + MXC_SPC_PERIPH_PWRSEQ = MXC_S_SPC_APBSEC_PERIPH_PWRSEQ, /**< PWRSEQ */ + MXC_SPC_PERIPH_MCR = MXC_S_SPC_APBSEC_PERIPH_MCR, /**< MCR */ + MXC_SPC_PERIPH_ALL = MXC_S_SPC_APBSEC_PERIPH_ALL, /**< All */ +} mxc_spc_periph_t; + +/** @brief Enumeration for ARM privilege settings. */ +typedef enum { + MXC_SPC_PRIVILEGED = 0, + MXC_SPC_UNPRIVILEGED = 1, +} mxc_spc_priv_t; + +/***** Function Prototypes *****/ + +/** + * @brief Locks the SPC registers related to setting the security + * or privilege states. Once locked, the affected SPC registers + * can not be unlocked until a reset. + */ +void MXC_SPC_Lock(void); + +/** + * @brief Locks the Cortex-M33 Core registers: + * - AIRCR and VTOR_S + * - VTOR_NS + * - MPU_S + * - MPU_NS + * - SAU + */ +void MXC_SPC_Core_Lock(void); + +/** + * @brief Unlocks the Cortex-M33 Core registers: + * - AIRCR and VTOR_S + * - VTOR_NS + * - MPU_S + * - MPU_NS + * - SAU + */ +void MXC_SPC_Core_UnLock(void); + +/** + * @brief Sets the privilege level of a peripheral. + * @param periph Enumeration for desired peripheral. + * @param priv Enumeration for desired privilege level. + */ +void MXC_SPC_SetPrivAccess(mxc_spc_periph_t periph, mxc_spc_priv_t priv); + +/** + * @brief Sets the peripheral to only be accessible from the Secure world. + * @param periph Enumeration for desired peripheral. + */ +void MXC_SPC_SetSecure(mxc_spc_periph_t periph); + +/** + * @brief Sets the peripheral to only be accessible from the Non-Secure world. + * @param periph Enumeration for desired peripheral. + */ +void MXC_SPC_SetNonSecure(mxc_spc_periph_t periph); + +/** + * @brief Sets the privilege level for Secure DMA. + * @param priv Enumeration for desired privilege level. + */ +void MXC_SPC_DMA_SetPrivAccess(mxc_spc_priv_t priv); + +/** + * @brief Sets the pins for a GPIO instance to only be accessible from the Secure world. + * @param gpio Pointer to the GPIO port's registers. + * @param pins mask of pins to set to Secure mode. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPC_GPIO_SetSecure(mxc_gpio_regs_t *gpio, uint32_t pins); + +/** + * @brief Sets the pins for a GPIO instance to only be accessible from the Non-Secure world. + * @param gpio Pointer to the GPIO port's registers. + * @param pins mask of pins to set to Non-Secure mode. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPC_GPIO_SetNonSecure(mxc_gpio_regs_t *gpio, uint32_t pins); + +/** + * @brief Enable the interrupts for each Memory Protection Controller (MPC) region. + * @param intr mask of MPC regions to interrupt for. + */ +void MXC_SPC_MPC_EnableInt(uint32_t intr); + +/** + * @brief Disable the interrupts for each Memory Protection Controller (MPC) region. + * @param intr mask of MPC regions to disable interrupt for. + */ +void MXC_SPC_MPC_DisableInt(uint32_t intr); + +/** + * @brief Gets the Memory Protection Controller (MPC) interrupt flags that are currently set. + * @return MPC interrupt flags. + */ +uint32_t MXC_SPC_MPC_GetFlags(void); + +/** + * @brief Enable the interrupts for Peripheral Protection Controllers (PPC). + * @param intr mask of PPC regions to disable interrupt for. + */ +void MXC_SPC_PPC_EnableInt(uint32_t intr); + +/** + * @brief Disable the interrupts for Peripheral Protection Controllers (PPC). + * @param intr mask of PPC regions to disable interrupt for. + */ +void MXC_SPC_PPC_DisableInt(uint32_t intr); + +/** + * @brief Gets the Peripheral Protection Controller (PPC) interrupt flags + * that are currently set. + * @return PPC interrupt flags. + */ +uint32_t MXC_SPC_PPC_GetFlags(void); + +/** + * @brief Clears the Peripheral Protection Controllers (PPC) Interrupt Flags. + * @param flags mask of PPC interrupt flags to clear. + */ +void MXC_SPC_PPC_ClearFlags(uint32_t flags); + +/** + * @brief Sets the CODE region to be Non-Secure Callable. + * @param isNSC Option to set CODE region as non-secure callable (True) or not (False). + */ +void MXC_SPC_SetCode_NSC(bool isNSC); + +/** + * @brief Sets the CODE region to be Non-Secure Callable. + * @param isNSC Option to set CODE region as non-secure callable (True) or not (False). + */ +void MXC_SPC_SetSRAM_NSC(bool isNSC); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/Libraries/PeriphDrivers/Include/MAX32657/spi.h index 45ddea845eb..7ddde948670 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -456,7 +456,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 30 inclusive. + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -484,7 +484,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 30 inclusive. + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd b/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd new file mode 100644 index 00000000000..aa7e5c55732 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd @@ -0,0 +1,159 @@ + + + + + BOOST + Boost Controller + 0x40004C00 + + 0x00 + 0x400 + registers + + + BOOST + 46 + + + + DISABLE + Boost Disable Register. + 0x000 + 32 + + + DIS + This bit allows softwaree to disable the boost regulator for the VDD18 supply. + [0:0] + read-write + + + + + VREGCTRL + Boost Voltage Regulator Control Register. + 0x004 + + + SET + Sets the target voltage for the boost regulator output. + [4:0] + read-write + + + + + IPEAK + Low Side FET Peak Current Register. + 0x008 + read-only + + + SET + Sets the peak current threshold for the regulator. + [2:0] + read-only + + + + + MAXTON + Maximum Low Side FET Time-On Register. + 0x00C + read-only + + + THD + Sets a threshold for when time-on out toggles. + [3:0] + read-only + + + + + ILOAD + Boost Cycle Count Register. + 0x010 + read-only + + + CNT + Indicates the last load cycle count value. + [7:0] + read-only + + + + + ALERT + Boost Cycle Count Alert Register. + 0x014 + + + THD + Determines the threshold for when the boost alert interruptis fired. + [7:0] + read-write + + + + + RDY + Boost Output Ready Register. + 0x018 + read-only + + + OUT + Indicates ready out status for boost regulator. + [0:0] + read-only + + + + + ZXCAL + Zero Cross Calibration Register. + 0x01C + read-only + + + VAL + Read back of auto-calibration values. + [4:0] + read-only + + + + + INTEN + Boost Alert Interrupt Enable Register. + 0x020 + read-write + + + ALERT + Boost alert enable/ + [0:0] + read-write + + + + + INTFL + Boost Alert Interrupt Status Register. + 0x024 + read-write + + + ALERT + Boost alert has occurred. + [0:0] + read-write + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index 7ae6aaddf1b..32bf4b3a689 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -35,18 +35,17 @@ int MXC_DMA_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (dma == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + if (dma == MXC_DMA0_NS && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); +#if CONFIG_TRUSTED_EXECUTION_SECURE + // DMA1 is only accessible from Secure world. + } else if (dma == MXC_DMA1_S && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); +#endif // CONFIG_TRUSTED_EXECUTION_SECURE } - // TODO(ME30): There is no periph clock enable register for DMA1 atm - // -Added but it's in feat/ME30 branch. - // Uncomment when merged. - // else if (dma == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) - // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); - // MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); - // } -#endif +#endif // MSDK_NO_GPIO_CLK_INIT return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd index 16ae2b95025..e2880fabe17 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd @@ -11,20 +11,20 @@ registers - DMA0 - 28 + DMA0_CH0 + 32 - DMA1 - 29 + DMA0_CH1 + 33 - DMA2 - 30 + DMA0_CH2 + 34 - DMA3 - 31 + DMA0_CH3 + 35 @@ -199,46 +199,56 @@ Memory To Memory 0x00 + + SPIRX + SPI RX + 0x01 + UARTRX UART RX 0x04 - I3CRX - I3C RX + I3CRX_CONT + I3C RX Controller 0x07 - SPIRX - SPI RX - 0x0F + I3CRX_TARG + I3C RX Target + 0x08 AESRX AES RX 0x10 + + SPITX + SPI TX + 0x21 + UARTTX UART TX 0x24 - I3CTX + I3CTX_CONT I3C TX 0x27 + + I3CTX_TARG + I3C TX + 0x28 + CRCTX CRC TX 0x2C - - SPITX - SPI TX - 0x2F - AESTX AES TX diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c index fa8f12b072e..bcd94c65de9 100644 --- a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c +++ b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c @@ -63,8 +63,10 @@ int MXC_FLC_ME30_GetPhysicalAddress(uint32_t addr, uint32_t *result) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { *result = addr & (MXC_FLASH_MEM_SIZE - 1); +#if CONFIG_TRUSTED_EXECUTION_SECURE } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE; +#endif } else { return E_BAD_PARAM; } @@ -251,40 +253,11 @@ int MXC_FLC_BlockPageRead(uint32_t address) //****************************************************************************** volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) { - uint32_t reg_num; - reg_num = page_num >> - 5; // Divide by 32 to get WELR register number containing the page lock bit - - if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { - return NULL; - } - - switch (reg_num) { - case 0: - return &(MXC_FLC->welr0); - case 1: - return &(MXC_FLC->welr1); - } - return NULL; } //****************************************************************************** volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) { - uint32_t reg_num; - reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit - - if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { - return NULL; - } - - switch (reg_num) { - case 0: - return &(MXC_FLC->rlr0); - case 1: - return &(MXC_FLC->rlr1); - } - return NULL; } diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_reva.c b/Libraries/PeriphDrivers/Source/FLC/flc_reva.c index e8252128e22..c645e92d47a 100644 --- a/Libraries/PeriphDrivers/Source/FLC/flc_reva.c +++ b/Libraries/PeriphDrivers/Source/FLC/flc_reva.c @@ -31,6 +31,8 @@ #include "flc_reva.h" #include "flc.h" +// TODO(CM33): Check for secure vs non-secure accesses here. + /** * @ingroup flc * @{ @@ -405,10 +407,12 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask) //****************************************************************************** int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { +#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || (TARGET_NUM != 32657) if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } +#endif /* Make sure the info block is locked */ flc->actrl = 0x1234; @@ -424,10 +428,12 @@ int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) //****************************************************************************** int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { +#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || (TARGET_NUM != 32657) if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } +#endif flc->actrl = 0xDEADBEEF; return E_NO_ERROR; diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd b/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd index 2b177533f80..78ff2ae0878 100644 --- a/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd +++ b/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd @@ -11,8 +11,9 @@ registers - Flash_Controller - Flash Controller interrupt. + FLC + + FLC Interrupt. 23 @@ -263,58 +264,6 @@ - - WELR0 - WELR0 - 0x80 - - - WELR0 - Access control. - 0 - 32 - - - - - WELR1 - WELR1 - 0x88 - - - WELR1 - Access control. - 0 - 32 - - - - - RLR0 - RLR0 - 0x90 - - - RLR0 - Access control. - 0 - 32 - - - - - RLR1 - RLR1 - 0x98 - - - RLR1 - Access control. - 0 - 32 - - - diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c index c027691f7e8..9bfab7be000 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -87,12 +87,6 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) return E_NO_ERROR; } - // Configure the vssel - error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); - if (error != E_NO_ERROR) { - return error; - } - // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -100,37 +94,19 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) } // Configure the pad - // TODO(ME30): "ps" (weak vs strong pull-up/down select) register field missing switch (cfg->pad) { case MXC_GPIO_PAD_NONE: gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - break; - - // Note: for "ps" field set 1 for weak and 0 for strong. - // As of 8-28-2024 most UG tables have this flipped the wrong way - case MXC_GPIO_PAD_WEAK_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - // gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - // gpio->ps &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - // gpio->ps |= cfg->mask; + gpio->pssel |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - // gpio->ps &= ~cfg->mask; + gpio->padctrl0 |= cfg->mask; + gpio->pssel &= ~cfg->mask; break; default: @@ -226,7 +202,7 @@ uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) /* ************************************************************************** */ int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { - return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); + return E_NOT_SUPPORTED; } /* ************************************************************************** */ diff --git a/Libraries/PeriphDrivers/Source/ICC/icc_me30.c b/Libraries/PeriphDrivers/Source/ICC/icc_me30.c index 1a9cc8cdda7..cace41e7eab 100644 --- a/Libraries/PeriphDrivers/Source/ICC/icc_me30.c +++ b/Libraries/PeriphDrivers/Source/ICC/icc_me30.c @@ -35,23 +35,22 @@ Maxim Internal Use * ****************************************************************************** */ -int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid) +int MXC_ICC_ID(mxc_icc_info_t cid) { - return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)icc, cid); + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid); } -void MXC_ICC_Enable(mxc_icc_regs_t *icc) +void MXC_ICC_Enable(void) { - MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)icc); + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Disable(mxc_icc_regs_t *icc) +void MXC_ICC_Disable(void) { - MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)icc); + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Flush(mxc_icc_regs_t *icc) +void MXC_ICC_Flush(void) { - MXC_ICC_Disable(icc); - MXC_ICC_Enable(icc); + MXC_ICC_Com_Flush(); } diff --git a/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd b/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd index eba1471e67f..b2e331cfda0 100644 --- a/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd @@ -6,7 +6,7 @@ 0x4002A000 0x00 - 0x800 + 0x1000 registers @@ -15,6 +15,7 @@ Cache ID Register. 0x0000 read-only + 32 RELNUM @@ -42,6 +43,7 @@ 0x0004 read-only 0x00080008 + 32 CCH @@ -61,6 +63,7 @@ CTRL Cache Control and Status Register. 0x0100 + 32 EN @@ -105,27 +108,28 @@ WAY Cache Way Control Register. 0x0200 + 32 WAY Number of cache way, default is always 2. Allowed values are 1,2,4. 0 - 1 + 3 1 1 - 0 + 1 2 2 - 1 + 2 4 4 - 2 + 4 @@ -135,6 +139,7 @@ REGCTRL Regional Control Register. 0x0204 + 32 EN @@ -151,18 +156,20 @@ - 15 - 0x20 + 4 + 8 REGION[%s] Regional Low and High Bound Registers. icc_reg 0x0208 + 64 read-write LBOUND Regional Low Bound Register. 0x0000 reg + 32 BOUND @@ -177,6 +184,7 @@ DMA Channel Status Register. 0x004 reg + 32 BOUND @@ -191,6 +199,7 @@ PFMCTRL Performance Control Register. 0x0300 + 32 EN @@ -204,6 +213,7 @@ PFMCNT Performance Counter Register. 0x0304 + 32 CNT @@ -218,6 +228,7 @@ Invalidate All Registers. 0x0700 read-write + 32 INVALID diff --git a/Libraries/PeriphDrivers/Source/LP/lp_me30.c b/Libraries/PeriphDrivers/Source/LP/lp_me30.c index b24173982eb..e900eba30e0 100644 --- a/Libraries/PeriphDrivers/Source/LP/lp_me30.c +++ b/Libraries/PeriphDrivers/Source/LP/lp_me30.c @@ -26,6 +26,8 @@ #define SET_SLEEPDEEP(X) (SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk) #define CLR_SLEEPDEEP(X) (SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk) +// TODO(SW): Update this. + void MXC_LP_EnterSleepMode(void) { MXC_LP_ClearWakeStatus(); @@ -39,41 +41,17 @@ void MXC_LP_EnterSleepMode(void) void MXC_LP_EnterLowPowerMode(void) { - MXC_LP_ClearWakeStatus(); - MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode - - /* Set SLEEPDEEP bit */ - SET_SLEEPDEEP(); - - /* Go into low power mode and wait for an interrupt to wake the processor */ - MXC_GCR->pm |= MXC_S_GCR_PM_MODE_LPM; - __WFI(); + return; } void MXC_LP_EnterMicroPowerMode(void) { - MXC_LP_ClearWakeStatus(); - MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode - - /* Set SLEEPDEEP bit */ - SET_SLEEPDEEP(); - - /* Go into Deepsleep mode and wait for an interrupt to wake the processor */ - MXC_GCR->pm |= MXC_S_GCR_PM_MODE_UPM; // UPM mode - __WFI(); + return; } void MXC_LP_EnterStandbyMode(void) { - MXC_LP_ClearWakeStatus(); - MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode - - /* Set SLEEPDEEP bit */ - SET_SLEEPDEEP(); - - /* Go into standby mode and wait for an interrupt to wake the processor */ - MXC_GCR->pm |= MXC_S_GCR_PM_MODE_STANDBY; // standby mode - __WFI(); + return; } void MXC_LP_EnterBackupMode(void) @@ -90,7 +68,7 @@ void MXC_LP_EnterBackupMode(void) void MXC_LP_EnterPowerDownMode(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; - MXC_GCR->pm |= MXC_S_GCR_PM_MODE_POWERDOWN; + MXC_GCR->pm |= MXC_V_GCR_PM_MODE_PDM; while (1) {} // Should never reach this line - device will reset on exit from shutdown mode. @@ -103,26 +81,23 @@ void MXC_LP_SetOVR(mxc_lp_ovr_t ovr) void MXC_LP_BandgapOn(void) { - MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_BG_DIS; + MXC_PWRSEQ->lpctrl &= ~MXC_F_PWRSEQ_LPCTRL_BG_DIS; } void MXC_LP_BandgapOff(void) { - MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_BG_DIS; + MXC_PWRSEQ->lpctrl |= MXC_F_PWRSEQ_LPCTRL_BG_DIS; } int MXC_LP_BandgapIsOn(void) { - return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_BG_DIS); + return (MXC_PWRSEQ->lpctrl & MXC_F_PWRSEQ_LPCTRL_BG_DIS); } void MXC_LP_ClearWakeStatus(void) { /* Write 1 to clear */ - MXC_PWRSEQ->lpwkst0 = 0xFFFFFFFF; - MXC_PWRSEQ->lpwkst1 = 0xFFFFFFFF; - MXC_PWRSEQ->lpwkst2 = 0xFFFFFFFF; - MXC_PWRSEQ->lpwkst3 = 0xFFFFFFFF; + MXC_PWRSEQ->lpwkfl0 = 0xFFFFFFFF; MXC_PWRSEQ->lppwst = 0xFFFFFFFF; } @@ -134,16 +109,6 @@ void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) case MXC_GPIO_PORT_0: MXC_PWRSEQ->lpwken0 |= wu_pins->mask; break; - - case MXC_GPIO_PORT_1: - MXC_PWRSEQ->lpwken1 |= wu_pins->mask; - break; - case MXC_GPIO_PORT_2: - MXC_PWRSEQ->lpwken2 |= wu_pins->mask; - break; - case MXC_GPIO_PORT_3: - MXC_PWRSEQ->lpwken3 |= wu_pins->mask; - break; } } @@ -153,20 +118,9 @@ void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) case MXC_GPIO_PORT_0: MXC_PWRSEQ->lpwken0 &= ~wu_pins->mask; break; - - case MXC_GPIO_PORT_1: - MXC_PWRSEQ->lpwken1 &= ~wu_pins->mask; - break; - case MXC_GPIO_PORT_2: - MXC_PWRSEQ->lpwken2 &= ~wu_pins->mask; - break; - case MXC_GPIO_PORT_3: - MXC_PWRSEQ->lpwken3 &= ~wu_pins->mask; - break; } - if (MXC_PWRSEQ->lpwken3 == 0 && MXC_PWRSEQ->lpwken2 == 0 && MXC_PWRSEQ->lpwken1 == 0 && - MXC_PWRSEQ->lpwken0 == 0) { + if (MXC_PWRSEQ->lpwken0 == 0) { MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIO_WE; } } @@ -183,24 +137,12 @@ void MXC_LP_DisableRTCAlarmWakeup(void) void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr) { - MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); - - if (tmr == MXC_TMR4) { - MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_TMR4; - } else { - MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_TMR5; - } + return; } void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr) { - MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); - - if (tmr == MXC_TMR4) { - MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_TMR4; - } else { - MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_TMR5; - } + return; } void MXC_LP_EnableWUTAlarmWakeup(void) @@ -215,10 +157,6 @@ void MXC_LP_DisableWUTAlarmWakeup(void) int MXC_LP_ConfigDeepSleepClocks(uint32_t mask) { - if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD))) { - return E_BAD_PARAM; - } - MXC_GCR->pm |= mask; return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd index 79fc6aad0fe..92fcda232bf 100644 --- a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd +++ b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd @@ -22,37 +22,55 @@ 5 - FAST - Fast mode. - 8 + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + RETLDO_EN + Retention LDO Enable. + 12 1 dis - Disabled. + Disable. 0 en - Enabled. + Enable. 1 - BG_DIS - Bandgap OFF. This controls the System Bandgap in DeepSleep mode. - 11 + LDO_EN_DLY + Core LDO Enable Delay. + 13 1 - on - Bandgap is always ON. + dis + Disable. 0 - off - Bandgap is OFF in DeepSleep mode (default). + en + Enable delay LDO power up to smooth LDO voltage drop. 1 @@ -91,32 +109,6 @@ - - LPWKFL1 - Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. - 0x0C - - - PINS - Wakeup Flags. - 0 - 12 - - - - - LPWKEN1 - Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. - 0x10 - - - PINS - Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. - 0 - 2 - - - LPPWST Low Power Peripheral Wakeup Status Register. diff --git a/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd b/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd new file mode 100644 index 00000000000..2e8615b2d9b --- /dev/null +++ b/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd @@ -0,0 +1,139 @@ + + + + + RSTZ + RSTZ Controller + 0x40004800 + + 0x00 + 0x400 + registers + + + + CTRL + RSTZ Control Register. + 0x000 + 32 + + + EN + Enable channels. + [0:0] + read-write + + + SVC_EN + Enable the SVC. + [1:1] + read-write + + + CH_SEL + Channel Select. + [4:2] + read-write + + + CAL_EN + Calibration mode enable. + [5:5] + read-write + + + DMEASURE_EN + Direct Measure mode enable. + [6:6] + read-write + + + OFFTR_P + Offset Trim for positive comparator. + [11:7] + read-write + + + OFFTR_N + Offset Trim for negative comparator. + [16:12] + read-write + + + DOUT + Comparator Result. + [17:17] + read-write + + + CAL_DOUT_POL + Calibration DOUT Polarity. + [18:18] + read-write + + + NUM_SAMP + Number of captures per sample. + [27:24] + read-write + + + TRIP_TOL + Number of failed DOUT captures (tolerance) before corresponding RSTZ signal is tripped. + [31:28] + read-write + + + + + BOOST_CLKCTRL + Boost Clock Control Register. + 0x004 + + + EXIT_NUM_SAMP + Defines how many samples needed of boost output channel to perform when exiting low-power mode before returning to normal active operation. + [1:0] + read-write + + + CH_SEL + Select when channel the output of the boost converter is monitored on. + [4:2] + read-write + + + + + 8 + 4 + STATUS_CH[%s] + Channel X Status Register. + 0x028 + 32 + read-write + + + RSTZ + Result of most recent sample result. + [0:0] + read-only + + + DOUT + Store the most recent DOUT capture for a given channel. + [1:1] + read-only + + + RSTZ_FL + RSTZ Flag indicates the RSTZ was tripped at some point since the last time being cleared. + [31:31] + read-write + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index a98afdde4d0..ac48b4f2b2d 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -347,14 +347,26 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPITX; - reqselRx = MXC_DMA_REQUEST_SPIRX; - break; + if (req->txData != NULL) { + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPITX; + break; - default: - return E_BAD_PARAM; + default: + return E_BAD_PARAM; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPIRX; + break; + + default: + return E_BAD_PARAM; + } } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); @@ -384,6 +396,17 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) switch (spi_num) { case 0: reqselTx = MXC_DMA_REQUEST_SPITX; + break; + + default: + return E_BAD_PARAM; + break; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: reqselRx = MXC_DMA_REQUEST_SPIRX; break; diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd index fb1b9851d5f..2f6efe4139a 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -90,7 +90,7 @@ - CTRLR_MODE + CONT_MODE Controller Mode Enable. 1 1 @@ -757,7 +757,7 @@ - CTRLR_DONE + CONT_DONE Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -974,7 +974,7 @@ - CTRLR_DONE + CONT_DONE Controller Done interrupt enable. 11 1 diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd index 2a8d1e3840a..b40c329b3ce 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -11,20 +11,20 @@ - FCTRL0 - Register 0. + CTRL + Function Control 0 Register. 0x00 read-write - BTLELDO_TX - BTLE LDO TX Trim. + BTLELDO_RF + BTLE LDO RF Trim. 0 5 - BTLELDO_RX - BTLE LDO RX Trim. + BTLELDO_BB + BTLE LDO BB Trim. 8 5 @@ -67,13 +67,13 @@ - FCTRL1 - Register 1. + AUTOCAL0 + Automatic Calibration 0 Register. 0x04 read-write - AC_EN + EN Auto-calibration Enable. 0 1 @@ -91,7 +91,7 @@ - AC_RUN + RUN Autocalibration Run. 1 1 @@ -157,7 +157,7 @@ 12 - AC_TRIM_OUT + TRIM_OUT IPO Auto Calibration Trim 23 9 @@ -165,13 +165,13 @@ - FCTRL2 - Register 2. + AUTOCAL1 + Automatic Calibration 1 Register. 0x08 read-write - AC_INIT_TRIM + INIT_TRIM IPO Trim Automatic Calibration Initial Trim. 0 9 @@ -179,19 +179,19 @@ - FCTRL3 - Register 3. + AUTOCAL2 + Automatic Calibration 2 Register. 0x0C read-write - AC_RUNTIME + RUNTIME IPO Trim Autocal Run Time 0 8 - AC_DIV + DIV IPO Trim Automatic Calibration Divide Factor. 8 13 @@ -248,7 +248,126 @@ + + INTFL + Interrupt Flag Register. + 0x1C + read-write + + + ERTOC_RDY + ERTCO 32K Ready. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Flag. + 1 + 1 + + + + + INTEN + Interrupt Enable Register. + 0x20 + read-write + + + ERTOC_RDY + ERTCO 32K Ready Interrupt Enable. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Enable. + 1 + 1 + + + + + FRQCNTCTRL + Frequency Counter Control Register. + 0x28 + read-write + + + START + Start Compare. + 0 + 1 + + + CMP_CLKSEL + Compared Clock Select. + 1 + 2 + + + RTC + RTC. + 0 + + + EXT_GPIO + External GPIO. + 2 + + + INRO + INRO. + 3 + + + + + + + FRQCNTCMP + Frequency Counter Compared Target Register. + 0x2C + read-write + + + TARGET + Compared Clock Target. + 0 + 14 + + + + + REFCLK + Reference Clock Result Register. + 0x30 + read-only + + + RESULT + Reference Clock Result. + 0 + 20 + + + + + CMPCLK + Compared Clock Result Register. + 0x34 + read-only + + + RESULT + Compared Clock Result. + 0 + 14 + + + - + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index 9485ad8c7c3..b499495b638 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -161,12 +161,6 @@ 17 1 - - BTLE - BTLE Reset. - 18 - 1 - TRNG TRNG Reset. @@ -409,14 +403,14 @@ 4 - active + ACTIVE Active Mode. 0 - backup + BACKUP Backup Mode. - 9 + 4 PDM @@ -671,6 +665,18 @@ 10 1 + + AUTOCAL + Auto calibration Reset. + 12 + 1 + + + BTLE + BTLE Reset. + 18 + 1 + @@ -708,12 +714,6 @@ 15 1 - - SPI - SPI Clock Disable - 16 - 1 - DMA1 DMA1 Clock Disable @@ -805,6 +805,19 @@ + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + ECCINTEN ECC Interrupt Enable Register @@ -813,7 +826,7 @@ FLASH ECC Flash0 Interrupt Enable. - 11 + 0 1 @@ -867,86 +880,86 @@ 0x74 - TX_EN - LDOTX enable. + RF_EN + LDO RF enable. 0 1 - TX_PD_EN - LDOTX Pull Down. + RF_PD_EN + LDO RF Pull Down. 1 1 - TX_VSEL - Voltage Selection for NFC LDO + RF_VSEL + Voltage Selection for RF LDO 2 2 - RX_EN - LDORX enable. + BB_EN + LDOBB enable. 4 1 - RX_PD_EN - LDORX Pull DOwn. + BB_PD_EN + LDO BB Pull DOwn. 5 1 - RX_VSEL - LDORX Voltage Setting. + BB_VSEL + LDO BB Voltage Setting. 6 2 - RX_BP_EN - LDORX Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 8 1 - RX_DISCH - LDORX Discharge. + BB_DISCH + LDO BB Discharge. 9 1 - TX_BP_EN - LDOTX Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 10 1 - TX_DISCH - LDOTX Discharge. + RF_DISCH + LDO RF Discharge. 11 1 - TX_EN_DLY - LDOTX Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 12 1 - RX_EN_DLY - LDORX Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 13 1 - RX_BP_EN_DLY - LDORX Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 14 1 - TX_BP_EN_DLY - LDOTX Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 15 1 @@ -964,19 +977,24 @@ 8 - RX_CNT - RX delay count. + BB_CNT + BB delay count. 8 9 - TX_CNT - TX delay count. + RF_CNT + RF delay count. 20 9 + + GPR + General Purpose Register 0. + 0x80 + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd index 7930cd67e3e..fcca217a795 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -11,16 +11,22 @@ - ECCEN - ECC Enable Register - 0x00 + RST + Reset Register. + 0x04 - FLASH - ECC Flash Enable. + BOOST + Reset BOOST Controller. 0 1 + + RSTZ + Reset RSTZ Controller. + 1 + 1 + @@ -34,12 +40,6 @@ 0 1 - - PDOWN_EN - Power Down Output Enable. - 1 - 1 - @@ -48,92 +48,61 @@ 0x10 - ERTCO_EN - Enable ERTCO 4KHz. - 3 - 1 + CLKSEL + Clock select for RTC, WUTs, and Timers. + 0 + 2 + + + ERTCO + ERTCO as clock source. + 0 + + + INRO + INRO as clock source. + 1 + + + EXTCLK + P0.12 div 8 as clock source. + 2 + + ERTCO_32KHZ_EN Enable ERTCO 32KHz while ERTCO_EN. - 5 - 1 - - - - - GPIO1_CTRL - GPIO1 Pin Control Register. - 0x20 - - - P1_0_OUT - GPIO1 Pin 0 Data Output. - 0 - 1 - - - P1_0_OUTEN - GPIO1 Pin 0 Output Enable. - 1 - 1 - - - P1_0_PUPEN - GPIO1 Pin 0 Pull-up Enable. - 2 - 1 - - - P1_0_IN - GPIO1 Pin 0 Input Status. 3 1 - P1_1_OUT - GPIO1 Pin 1 Data Output. - 4 - 1 - - - P1_1_OUTEN - GPIO1 Pin 1 Output Enable. + ERTCO_EN + Enable ERTCO 4KHz. 5 1 - - P1_1_PUPEN - GPIO1 Pin 1 Pull-up Enable. - 6 - 1 - - - P1_1_IN - GPIO1 Pin 1 Input Status. - 7 - 1 - - RTCTRIM - User RTC Trim Register. - 0x24 - - - X2 - RTC X2 Trim. - 0 - 5 - - - X1 - RTC X1 Trim. - 5 - 5 - - + BBREG0 + Battery Back Reg0. + 0x30 + + + BBREG1 + Battery Back Reg1. + 0x34 + + + BBDATA0 + Battery Back Data0 Register. + 0x40 + + + BBDATA1 + Battery Back Data1 Register. + 0x44 diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd index 84216c88245..330f128cdaf 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd @@ -14,7 +14,7 @@ SISTAT System Initialization Status Register. - 0x00 + 0x000 read-only @@ -62,7 +62,7 @@ ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). - 0x04 + 0x004 read-only @@ -72,6 +72,32 @@ + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + SFSTAT Security function status register. diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index c66b9bceed8..726bb9d249f 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -17,7 +17,7 @@ ******************************************************************************/ /** - * @file mxc_sys.c + * @file mxc_sys.c * @brief System layer driver. * @details This driver is used to control the system layer of the device. */ @@ -57,6 +57,7 @@ extern uint32_t _binary_riscv_bin_start; /* **** Functions **** */ /* ************************************************************************** */ +#if CONFIG_TRUSTED_EXECUTION_SECURE int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) { int err = E_NO_ERROR; @@ -93,9 +94,8 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); - // Info block only accessible for secure code. + // Info block only accessible from secure code. // Use Secure DMA1. - // TODO(DMA): Figure out access to "secure" functions when in non-secure code. err = MXC_AES_Init(MXC_DMA1); if (err) { MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); @@ -137,6 +137,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) return err; } +#endif /* ************************************************************************** */ int MXC_SYS_GetRevision(void) @@ -237,7 +238,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_TX_EN | MXC_F_GCR_BTLELDOCTRL_RX_EN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_RF_EN | MXC_F_GCR_BTLELDOCTRL_BB_EN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c index 868caf34d47..6b1c80e0aa3 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -119,8 +119,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) if (init_pins) { if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr2); - } else { - MXC_GPIO_Config(&gpio_cfg_tmr2b); } } diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c index 2995362a172..66a48854e1b 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c @@ -226,7 +226,7 @@ void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) while (!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))) {} tmr->cmp = (cfg->cmp_cnt << timerOffset); -#if TARGET_NUM == 32655 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 +#if TARGET_NUM == 32655 || TARGET_NUM == 32657 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #else tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); diff --git a/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c b/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c new file mode 100644 index 00000000000..37319b7bd6e --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c @@ -0,0 +1,249 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mpc_me30.c + * @brief Memory Protection Controller (MPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the security policy of each + * memory region (SRAM0-4 and Flash). + */ + +// TODO(MPC): Add Interrupt functionality. + +/** + * The MPC is only accessible from Secure World. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 1 + +/**** Includes ****/ + +#include +#include "mxc_device.h" +#include "mpc.h" +#include "spc.h" + +/**** Definitions ****/ +// Enumeration for security policy. +typedef enum { + MXC_MPC_STATE_SECURE = 0, + MXC_MPC_STATE_NONSECURE = 1 +} mxc_mpc_state_t; + +/**** Globals ****/ + +/**** Functions ****/ + +static int MXC_MPC_SetBlockSecurity(int start_addr, int end_addr, mxc_mpc_state_t state) +{ + int error; + uint32_t phy_start_addr, phy_end_addr; + + int i, j; + uint32_t curr_addr, start_mpc_region_addr, end_mpc_region_addr; + uint32_t start_block_idx; + uint32_t end_block_idx; + mxc_mpc_regs_t *start_mpc; + mxc_mpc_regs_t *end_mpc; + mxc_mpc_regs_t *curr_mpc; + + // Check for supported address ranges. + if (start_addr > end_addr) { + return E_BAD_PARAM; + } + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of address. + phy_start_addr = start_addr & ~(1 << 28); + phy_end_addr = end_addr & ~(1 << 28); + + // Ensure the start address is not past the end address. + if (phy_start_addr > phy_end_addr) { + return E_BAD_PARAM; + } + + // Check addresses are within usable memory regions. + error = MXC_MPC_CheckPhyBoundaries(phy_start_addr, phy_end_addr); + if (error != E_NO_ERROR) { + return error; + } + + // Set all blocks within each MPC of the given memory regions to Secure. + start_mpc = MXC_MPC_GetInstance(phy_start_addr); + end_mpc = MXC_MPC_GetInstance(phy_end_addr); + + if (start_mpc == NULL || end_mpc == NULL) { + // Given addresses are in memory space that doesn't support MPC. + return E_BAD_PARAM; + } + + curr_addr = phy_start_addr; + for (i = MXC_MPC_GET_IDX(start_mpc); i <= MXC_MPC_GET_IDX(end_mpc); i++) { + // Get current MPC, whether in Flash or SRAM. + curr_mpc = MXC_MPC_SRAM_GET_BASE(i); + if (curr_mpc == NULL) { + curr_mpc = MXC_MPC_FLASH_GET_BASE(i); + } + + // Get the address range of the current MPC region. + start_mpc_region_addr = curr_addr; + + // NOTE: Project Owner/Developer must be aware of the memory settings for Secure and Non-Secure + // boundaries do not share an MPC block. An MPC block can only be set to one security + // policy (Secure or Non-Secure). + if (i == MXC_MPC_GET_IDX(end_mpc)) { + // The physical ending address is within the final MPC region - stop there. + end_mpc_region_addr = phy_end_addr; + } else { + // -1 to get the last address of the current region. + end_mpc_region_addr = MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc) - 1; + } + + start_block_idx = MXC_MPC_GetBlockIdx(curr_mpc, start_mpc_region_addr); + end_block_idx = MXC_MPC_GetBlockIdx(curr_mpc, end_mpc_region_addr); + + // TODO(SW): Precautionary measure that needs to be confirmed - prevents the MPC_BLK_LUT[n] + // register from auto-incrementing after a full word read/write occurs. + // There is only 1 available index (n) (in MPC_BLK_IDX register) for the ME30 because memory + // size does not exceed a single full word length of the MPC_BLK_LUT[n] register. Each bit + // in the MPC_BLK_LUT[n] corresponds to a block of memory with the block size given by the + // MPC_BLK_CFG register. + // For example: + // - FLASH => 1MB; MPC_FLASH Block size => 32KB. + // 32KB * 32 (bits in MPC_BLK_LUT[n] register) = 1MB. + curr_mpc->ctrl &= ~MXC_F_MPC_CTRL_AUTO_INC; + + // Set the security state of each block. + for (j = start_block_idx; j <= end_block_idx; j++) { + if (state == MXC_MPC_STATE_NONSECURE) { + curr_mpc->blk_lut |= (1 << j); + } else { + curr_mpc->blk_lut &= ~(1 << j); + } + } + + // Update curr_addr to start at the beginning of the next MPC region for the next iteration of this for loop. + curr_addr = MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc); + } + + return E_NO_ERROR; +} + +int MXC_MPC_CheckPhyBoundaries(uint32_t start_addr, uint32_t end_addr) +{ + uint32_t phy_start_addr, phy_end_addr; + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of the address. + phy_start_addr = start_addr & ~(1 << 28); + phy_end_addr = end_addr & ~(1 << 28); + + // Check Flash Boundaries. + if ((phy_start_addr >= MXC_PHY_FLASH_MEM_BASE) && (phy_end_addr < (MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE))) { + return E_NO_ERROR; + } + + // Check SRAM Boundaries. + if ((phy_start_addr >= MXC_PHY_SRAM_MEM_BASE) && (phy_end_addr < (MXC_PHY_SRAM_MEM_BASE + MXC_PHY_SRAM_MEM_SIZE))) { + return E_NO_ERROR; + } + + // Addresses are located outside of available/usable memory spaces. + return E_BAD_PARAM; +} + +mxc_mpc_regs_t *MXC_MPC_GetInstance(uint32_t addr) +{ + uint32_t phy_addr; + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of the address. + phy_addr = addr & ~(1 << 28); + + if ((phy_addr >= MXC_PHY_FLASH_MEM_BASE) && (phy_addr < MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE)) { + return MXC_MPC_FLASH; + } else if ((phy_addr >= MXC_PHY_SRAM0_MEM_BASE) && (phy_addr < MXC_PHY_SRAM0_MEM_BASE + MXC_PHY_SRAM0_MEM_SIZE)) { + return MXC_MPC_SRAM0; + } else if ((phy_addr >= MXC_PHY_SRAM1_MEM_BASE) && (phy_addr < MXC_PHY_SRAM1_MEM_BASE + MXC_PHY_SRAM1_MEM_SIZE)) { + return MXC_MPC_SRAM1; + } else if ((phy_addr >= MXC_PHY_SRAM2_MEM_BASE) && (phy_addr < MXC_PHY_SRAM2_MEM_BASE + MXC_PHY_SRAM2_MEM_SIZE)) { + return MXC_MPC_SRAM2; + } else if ((phy_addr >= MXC_PHY_SRAM3_MEM_BASE) && (phy_addr < MXC_PHY_SRAM3_MEM_BASE + MXC_PHY_SRAM3_MEM_SIZE)) { + return MXC_MPC_SRAM3; + } else if ((phy_addr >= MXC_PHY_SRAM4_MEM_BASE) && (phy_addr < MXC_PHY_SRAM4_MEM_BASE + MXC_PHY_SRAM4_MEM_SIZE)) { + return MXC_MPC_SRAM4; + } else { + // Addresses are located outside of memory spaces that don't have an + // associated MPC. + return NULL; + } +} + +int MXC_MPC_GetBlockIdx(mxc_mpc_regs_t *mpc, uint32_t addr) +{ + uint32_t physical_addr; + uint32_t block_size; + uint32_t start_mpc_region_addr, mpc_region_size; + int base, block, remainder; + + if (mpc == NULL) { + return E_NO_DEVICE; + } + + start_mpc_region_addr = MXC_MPC_GET_PHY_MEM_BASE(mpc); + mpc_region_size = MXC_MPC_GET_PHY_MEM_SIZE(mpc); + if (!((addr >= start_mpc_region_addr) && (addr < start_mpc_region_addr + mpc_region_size))) { + // Given address is not within the MPC region. + return E_BAD_PARAM; + } + + // Block size = 1 << (BLK_CFG.size + 5) + block_size = 1 << ((mpc->blk_cfg & MXC_F_MPC_BLK_CFG_SIZE) + 5); + + // Clear bit 28 (Security State of Region) to get the physical memory address. + physical_addr &= ~(1<<28); + + base = addr - start_mpc_region_addr; + block = base / block_size; + remainder = base % block_size; + + // Get the current block if the address does not start at the beginning of a whole block. + if (remainder != 0) { + block += 1; + } + + return block; +} + +int MXC_MPC_SetSecure(uint32_t start_addr, uint32_t end_addr) +{ + return MXC_MPC_SetBlockSecurity(start_addr, end_addr, MXC_MPC_STATE_SECURE); +} + +int MXC_MPC_SetNonSecure(uint32_t start_addr, uint32_t end_addr) +{ + return MXC_MPC_SetBlockSecurity(start_addr, end_addr, MXC_MPC_STATE_NONSECURE); +} + +int MXC_MPC_Lock(mxc_mpc_regs_t *mpc) +{ + mpc->ctrl |= MXC_F_MPC_CTRL_SEC_LOCKDOWN; + + return E_NO_ERROR; +} + +#endif diff --git a/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd b/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd new file mode 100644 index 00000000000..f06322f9a21 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd @@ -0,0 +1,283 @@ + + + + MPC + Memory Protection Controller. + 0x50091000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + 32 + + + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. + 0 + 32 + + + + + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only + + + SIZE + Block Size. + 0 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 + + + + + BLK_IDX + Block Index Register. + 0x0018 + + + IDX + Index value for accessing block-based lookup table. + 0 + 32 + + + + + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C + + + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. + 0 + 32 + + + + + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only + + + MPC_IRQ + MPC IRQ triggered. + 0 + 1 + + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + + + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 + 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR5 + Peripheral ID 5 Register. + 0x0FD4 + read-only + + + PIDR6 + Peripheral ID 6 Register. + 0x0FD8 + read-only + + + PIDR7 + Peripheral ID 6 Register. + 0x0FDC + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + CIDR0 + Component ID register. + 0x0FF0 + read-only + + + CIDR1 + Component ID register. + 0x0FF4 + read-only + + + CIDR2 + Component ID register. + 0x0FF8 + read-only + + + CIDR3 + Component ID register. + 0x0FFC + read-only + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c b/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c new file mode 100644 index 00000000000..bc654e5db51 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c @@ -0,0 +1,63 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file nspc_me30.c + * @brief Non-Secure Privilege Controller (NSPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the privilege policy of data + * flowing to/from peripherals though the APB Peripheral Proection + * Controllers (PPC). + * The NSPC is only readable via Non-Secure Privileged access. + */ + +/** + * NSPC can only be accessed from the non-secure world. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 0 + +/**** Includes ****/ +#include +#include +#include "mxc_device.h" +#include "nspc.h" +#include "nspc_regs.h" + +/**** Definitions ****/ + +/**** Globals ****/ + +void MXC_NSPC_SetPrivAccess(mxc_nspc_periph_t periph, mxc_nspc_priv_t priv) +{ + if (priv == MXC_NSPC_UNPRIVILEGED) { + MXC_NSPC->apbpriv |= periph; + } else { + MXC_NSPC->apbpriv &= ~periph; + } +} + +// TODO(SW): Check function name. +void MXC_NSPC_DMA_SetPrivAccess(mxc_nspc_priv_t priv) +{ + if (priv == MXC_NSPC_UNPRIVILEGED) { + MXC_NSPC->ahbmpriv |= MXC_F_NSPC_AHBMPRIV_DMA; + } else { + MXC_NSPC->ahbmpriv &= ~MXC_F_NSPC_AHBMPRIV_DMA; + } +} + +#endif diff --git a/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd b/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd new file mode 100644 index 00000000000..aa3ae3d6b0c --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd @@ -0,0 +1,189 @@ + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TZ/spc_me30.c b/Libraries/PeriphDrivers/Source/TZ/spc_me30.c new file mode 100644 index 00000000000..2c17bc306f9 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/spc_me30.c @@ -0,0 +1,182 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file spc_me30.c + * @brief Secure Privilege Controller (SPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the security and privilege policy of data + * flowing to/from peripherals though the APB Peripheral Proection + * Controllers (PPC). + * The SPC is only readable via Secure Privileged access. + */ + +/** + * SPC can only be accessed from the secure world. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 1 + +/**** Includes ****/ +#include +#include +#include "mxc_device.h" +#include "mxc_errors.h" +#include "spc.h" +#include "spc_regs.h" +#include "gpio.h" + +/**** Definitions ****/ + +/**** Globals ****/ + +/**** Functions ****/ + +void MXC_SPC_Lock(void) +{ + // Note: Cannot unlock SPC registers except via a reset. + MXC_SPC->ctrl |= MXC_F_SPC_CTRL_LOCK; +} + +// TODO(SW): Need to verify if this prevents the Non-Secure world from +// accessing the VTOR register. Note: the suffix '_NS' means that +// the secure world is accessing a non-secure register +void MXC_SPC_Core_Lock(void) +{ + // Locks the Cortex-M33 Core Registers (VTOR, SAU, MPU, etc). + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_AIRCR_VTOR_S; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_VTOR_NS; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_MPU_S; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_MPU_NS; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_SAU; +} + +void MXC_SPC_Core_UnLock(void) +{ + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_AIRCR_VTOR_S; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_VTOR_NS; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_MPU_S; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_MPU_NS; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_SAU; +} + +void MXC_SPC_SetPrivAccess(mxc_spc_periph_t periph, mxc_spc_priv_t priv) +{ + if (priv == MXC_SPC_UNPRIVILEGED) { + MXC_SPC->apbpriv |= periph; + } else { + MXC_SPC->apbpriv &= ~periph; + } +} + +// TODO(SW): Check names. +void MXC_SPC_SetSecure(mxc_spc_periph_t periph) +{ + MXC_SPC->apbsec &= ~periph; +} + +void MXC_SPC_SetNonSecure(mxc_spc_periph_t periph) +{ + MXC_SPC->apbsec |= periph; +} + +// TODO(SW): Check function name. +void MXC_SPC_DMA_SetPrivAccess(mxc_spc_priv_t priv) +{ + if (priv == MXC_SPC_UNPRIVILEGED) { + MXC_SPC->ahbmpriv |= MXC_F_SPC_AHBMPRIV_DMA; + } else { + MXC_SPC->ahbmpriv &= ~MXC_F_SPC_AHBMPRIV_DMA; + } +} + +int MXC_SPC_GPIO_SetSecure(mxc_gpio_regs_t *gpio, uint32_t pins) +{ + // Added GPIO instance as a parameter to follow convention of future devices that could + // potentially have more than one GPIO port. + if (gpio == MXC_GPIO0) { + MXC_SPC->gpio0 &= ~pins; + return E_NO_ERROR; + } else { + return E_BAD_PARAM; + } +} + +int MXC_SPC_GPIO_SetNonSecure(mxc_gpio_regs_t *gpio, uint32_t pins) +{ + // Added GPIO instance as a parameter to follow convention of future devices that could + // potentially have more than one GPIO port. + if (gpio == MXC_GPIO0) { + MXC_SPC->gpio0 |= pins; + return E_NO_ERROR; + } else { + return E_BAD_PARAM; + } +} + +void MXC_SPC_MPC_EnableInt(uint32_t intr) +{ + MXC_SPC->mpc_inten |= intr; +} + +void MXC_SPC_MPC_DisableInt(uint32_t intr) +{ + MXC_SPC->mpc_inten &= ~intr; +} + +uint32_t MXC_SPC_MPC_GetFlags(void) +{ + return MXC_SPC->mpc_status; +} + +void MXC_SPC_PPC_EnableInt(uint32_t intr) +{ + MXC_SPC->ppc_inten |= intr; +} + +void MXC_SPC_PPC_DisableInt(uint32_t intr) +{ + MXC_SPC->ppc_inten &= ~intr; +} + +uint32_t MXC_SPC_PPC_GetFlags(void) +{ + return MXC_SPC->ppc_status; +} + +void MXC_SPC_PPC_ClearFlags(uint32_t flags) +{ + MXC_SPC->ppc_intclr |= flags; +} + +// TODO(SW): This requires testing. ICODE +void MXC_SPC_SetCode_NSC(bool isNSC) { + if (isNSC) { + MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_CODE; + } else { + MXC_SPC->nscidau &= ~MXC_F_SPC_NSCIDAU_CODE; + } +} + +void MXC_SPC_SetSRAM_NSC(bool isNSC) { + if (isNSC) { + MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_SRAM; + } else { + MXC_SPC->nscidau &= ~MXC_F_SPC_NSCIDAU_SRAM; + } +} + +#endif diff --git a/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd b/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd new file mode 100644 index 00000000000..a2cbc6159c1 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd @@ -0,0 +1,575 @@ + + + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Security Access for GCR. + 0x01 + + + SIR + Security Access for SIR. + 0x02 + + + FCR + Security Access for FCR. + 0x04 + + + WDT + Security Access for WDT. + 0x08 + + + AES + Security Access for AES. + 0x010 + + + AESKEYS + Security Access for AESKEYS. + 0x020 + + + CRC + Security Access for CRC. + 0x040 + + + GPIO0 + Security Access for GPIO0. + 0x080 + + + TMR0 + Security Access for TMR0. + 0x0100 + + + TMR1 + Security Access for TMR1. + 0x0200 + + + TMR2 + Security Access for TMR2. + 0x0400 + + + TMR3 + Security Access for TMR3. + 0x0800 + + + TMR4 + Security Access for TMR4. + 0x01000 + + + TMR5 + Security Access for TMR5. + 0x02000 + + + I3C + Security Access for I3C. + 0x04000 + + + UART + Security Access for UART. + 0x08000 + + + SPI + Security Access for SPI. + 0x010000 + + + TRNG + Security Access for TRNG. + 0x020000 + + + BTLE_DBB + Security Access for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Security Access for BTLE RFFE. + 0x080000 + + + RSTZ + Security Access for RSTZ. + 0x0100000 + + + BOOST + Security Access for Boost Controller. + 0x0200000 + + + TRIMSIR + Security Access for TRIMSIR. + 0x0400000 + + + RTC + Security Access for RTC. + 0x01000000 + + + WUT0 + Security Access for WUT0. + 0x02000000 + + + WUT1 + Security Access for WUT1. + 0x04000000 + + + PWRSEQ + Security Access for Power Sequencer. + 0x08000000 + + + MCR + Security Access for MCR. + 0x10000000 + + + ALL + Security Access for all peripherals. + 0x1F7FFFFF + + + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 + + + DMA + Controls access of transactions coming from the Secure DMA. + 0 + 1 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secure or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 14 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 03beef34428..d04301128bc 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -38,6 +38,25 @@ #define MXC_UART_REVB_ERRINT_FL \ (MXC_F_UART_REVB_INT_FL_RX_FERR | MXC_F_UART_REVB_INT_FL_RX_PAR | MXC_F_UART_REVB_INT_FL_RX_OV) +#if CONFIG_TRUSTED_EXECUTION_SECURE +#ifndef MXC_DMA0 +// TrustZone support to keep up with naming convention. +// For ME30, non-secure DMA (DMA0) is accessible from Secure code using non-secure mapping. +// Undecorated MXC_DMA0 definition for secure code is not defined as the undecorated +// definitions corresponds with the security attribution of an address. +// Because there is no secure mapping for DMA0, following ARM naming convention, it's +// recommend that secure code use the definition with '_NS' suffix (MXC_DMA0_NS). +// Placing this here to limit scope of this definition to this file. +#define MXC_DMA0 MXC_DMA0_NS +#endif +#else +#ifndef MXC_DMA1 +// Non-Secure world can not access Secure DMA (DMA1). +// Placing this here to limit scope of this definition to this file. +#define MXC_DMA1 NULL +#endif +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + /* **** Variable Declaration **** */ static void *AsyncTxRequests[MXC_UART_INSTANCES]; static void *AsyncRxRequests[MXC_UART_INSTANCES]; @@ -869,10 +888,12 @@ void MXC_UART_RevA_DMA0_Handler(void) MXC_DMA_Handler(MXC_DMA0); } +#if CONFIG_TRUSTED_EXECUTION_SECURE void MXC_UART_RevA_DMA1_Handler(void) { MXC_DMA_Handler(MXC_DMA1); } +#endif #endif @@ -881,6 +902,7 @@ DMA instance. */ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { +// Add RISCV support here for future parts with more than one DMA instance. #ifdef __arm__ #if (TARGET_NUM == 32657) NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); @@ -891,8 +913,11 @@ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ if (dma_instance == MXC_DMA0) { MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); +#if CONFIG_TRUSTED_EXECUTION_SECURE + // Only secure code has access to Secure DMA (DMA1). } else if (dma_instance == MXC_DMA1) { MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); +#endif // CONFIG_TRUSTED_EXECUTION_SECURE } #else NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); @@ -900,10 +925,6 @@ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); #endif // MXC_DMA_INSTANCES > 1 - -#else - // TODO(JC): RISC-V - #endif // __arm__ } diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd index d69d9ca2026..d88279c54ac 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd @@ -116,25 +116,15 @@ 2 - Peripheral_Clock - apb clock + PERIPHERAL_CLOCK + APB Clock. 0 - External_Clock - Clock 1 + CLK1 + IBRO clock. 1 - - CLK2 - Clock 2 - 2 - - - CLK3 - Clock 3 - 3 -