From a4e67de96f0a9833756b6c79fff3cd6ee459fee0 Mon Sep 17 00:00:00 2001 From: kkwli Date: Mon, 11 Dec 2023 12:32:13 -0500 Subject: [PATCH] [flang] update ppc-vec-store-elem-order.f90 after #74709 (NFC) (#75064) --- .../Lower/PowerPC/ppc-vec-store-elem-order.f90 | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 index 494ed21f4fe928..caf6d5463a8336 100644 --- a/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 +++ b/flang/test/Lower/PowerPC/ppc-vec-store-elem-order.f90 @@ -67,10 +67,10 @@ subroutine vec_xstd2_test(arg1, arg2, arg3, i) ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64 -! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1 -! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1 -! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1 -! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0 +! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1 +! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1 +! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1 +! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]] ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2 @@ -93,10 +93,10 @@ subroutine vec_xstw4_test(arg1, arg2, arg3, i) ! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4 ! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64 -! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1 -! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1 -! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1 -! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0 +! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1 +! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1 +! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1 +! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0 ! LLVMIR: %[[gep1:.*]] = getelementptr <4 x float>, ptr %2, i64 %[[iadd]] ! LLVMIR: %[[arg1:.*]] = load <4 x float>, ptr %0, align 16 ! LLVMIR: %[[arg2:.*]] = load i16, ptr %1, align 2