I2C Transaction Implementation Possibly Not According to Specification?

[fko-kuptec]

First of all, sorry for the many edits. I unfortunately hit [Ctrl+Enter] for a newline, but instead created an unfinished issue. Now it is done. 😅

The specification of the new I2c::transaction method does not directly mention this, but to me it would make sense to not send a SAD+R/W between multiple consecutive Write operations. The current implementation, however, does that. Is this just an oversight or on purpose?

Specification

Execute the provided operations on the I2C bus.

Transaction contract:
- Before executing the first operation an ST is sent automatically. This is followed by SAD+R/W as appropriate.
- Data from adjacent operations of the same type are sent after each other without an SP or SR.
- Between adjacent operations of a different type an SR and SAD+R/W is sent.
- After executing the last operation an SP is sent automatically.
- If the last operation is a `Read` the master does not send an acknowledge for the last byte.

- `ST` = start condition
- `SAD+R/W` = slave address followed by bit 1 to indicate reading or 0 to indicate writing
- `SR` = repeated start condition
- `SP` = stop condition

Example

fn write_register(slave_address: u8, register_address: u8, data: &[u8]) -> Result<(), Error> {
    let mut ops = [
        Operation::Write(&[register_address]),
        Operation::Write(data),
    ];
    
    i2c.transaction(slave_address, &mut ops);
}

As far as I could find out, this API call would produce with the current implementation the following sequence on the bus:

ST SAD+W [register_address] SP ST SAD+W [data] SP

I, however, would expect the following:

ST SAD+W [register_address] [data] SP

If this is indeed not intended behaviour, I could probably fix it and create a pull request. 😊

[jbeaurivage]

Closed via #741