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memory.flash.25xxxx.spin2
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{
----------------------------------------------------------------------------------------------------
Filename: memory.flash.25xxxx.spin2
Description: Driver for 25xxxx series SPI NOR flash
Author: Jesse Burt
Started: Nov 9, 2019
Updated: Sep 18, 2024
Copyright (c) 2024 - See end of file for terms of use.
----------------------------------------------------------------------------------------------------
}
#include "memory.common.spin2h" ' use code common to all memory drivers
CON
{ default I/O settings; these can be overridden in the parent object }
CS = 61
SCK = 60
MOSI = 59
MISO = 58
SPI_FREQ = 1_000_000
{ erase units }
SECTOR = 1 '4KB
BLK32 = 2 '32KB
BLK64 = 3 '64KB
CHIP = 4 'Entire chip
{ manufacturers }
WINBOND = $EF
ERASE_CELL = $FF
VAR
byte _CS
OBJ
spi: "com.spi.25mhz" ' SPI engine
core: "core.con.25xxxx" ' HW-specific constants
PUB null()
' This is not a top-level object
PUB start(): status
' Start driver using default I/O settings
return startx(CS, SCK, MOSI, MISO, SPI_FREQ)
PUB startx(CS_PIN, SCK_PIN, MOSI_PIN, MISO_PIN, SCK_HZ): status
' Start driver using custom I/O settings
' CS: SPI chip-select
' SCK: SPI SCK/clock pin
' MOSI: SPI MOSI/Propeller to Device
' MISO: SPI MISO/Device to Propeller
' All pin assignments must be unique and in the range 0..63
' SCK_FREQ: SPI bus frequency (device and SPI-engine specific)
if ( lookdown(CS_PIN: 0..63) and lookdown(SCK_PIN: 0..63) and lookdown(MOSI_PIN: 0..63) ...
and lookdown(MISO_PIN: 0..63) )
if ( status := spi.init(SCK_PIN, MOSI_PIN, MISO_PIN, core.SPI_MODE, SCK_HZ) )
waitus(core.T_POR) ' wait for device startup
_CS := CS
pinh(_CS)
return
' if this point is reached, something above failed
' Double check I/O pin assignments, connections, power
' Lastly - make sure you have at least one free core/cog
return FALSE
PUB stop()
' Stop the driver
spi.deinit()
pinf(_CS)
_CS := 0
PUB busy(): flag
' Flag indicating flash chip is busy executing an operation
' Returns:
' TRUE (-1) when flash chip is executing any of the following:
' Page program
' Erase
' Write status reg
' Erase/Program security reg
' FALSE (0) otherwise
return ( ( (rd_status(1) & core.FLAG_BUSY) ) == 1 )
PUB dev_id(): id
' Read the device ID from the flash chip
id := 0
readreg(core.MANUF_DEV_ID, 2, @id)
id >>= 8 ' grab MSByte only
PUB erase(addr, er_sz)
' Erase flash memory starting at addr, of size er_sz
' Valid values (er_sz):
' SECTOR (1) - Erase 4kBytes
' BLK32 (2) - Erase 32kBytes
' BLK64 (3) - Erase 64kBytes
' CHIP (4) - Erase entire chip
' Any other value is ignored
' NOTE: addr is ignored when er_sz is CHIP
' NOTE: Prior to calling this method, writes must be enabled with
' WritesEnabled(TRUE)
' NOTE: Erased state of a flash cell is $FF
case er_sz
SECTOR, BLK32, BLK64:
er_sz := lookup(er_sz: core.SECTOR_ERASE, core.BLK32_ERASE, core.BLK64_ERASE)
er_sz |= (addr << 8)
CHIP:
er_sz := core.CHIP_ERASE
other:
return
writereg(er_sz, 0, 0)
PUB global_lock(state)
' Enable write protection for all regions of the chip
' Valid values TRUE (non-zero), FALSE (0)
if ( state )
writereg(core.GLOBAL_BLK_LOCK, 0, 0)
else
writereg(core.GLOBAL_BLK_UNLOCK, 0, 0)
PUB jedec_id(): id
' Read the JEDEC ID from the flash chip
id := 0
readreg(core.JEDEC_ID, 3, @id)
PUB mfr_id(): id
' Read the Mfr ID from the flash chip
' Known values: $EF (Winbond)
id := 0
readreg(core.MANUF_DEV_ID, 1, @id)
PUB page_size(): p
' Size of a memory page, in bytes
if ( mfr_id() == WINBOND )
return 256
PUB rd_block_lsbf(ptr_buff, addr, nr_bytes) | byte cmd_pkt[4], tmp
' Read a block of bytes from the flash chip, LSB-first
' NOTE: If the operation reaches the end of the flash chip, the address will restart at 0 and
' continue reading
cmd_pkt[0] := core.READ_DATA ' Read Flash
cmd_pkt[1] := addr.byte[2] ' address A23..A16
cmd_pkt[2] := addr.byte[1] ' address A15..A8
cmd_pkt[3] := addr.byte[0] ' address A7..A0
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, 4)
spi.rdblock_lsbf(ptr_buff, nr_bytes)
pinh(_CS)
PUB rd_block_msbf(ptr_buff, addr, nr_bytes) | byte cmd_pkt[4], tmp
' Read a block of bytes from the flash chip, MSB-first
' NOTE: If the operation reaches the end of the flash chip, the address will restart at 0 and
' continue reading
cmd_pkt[0] := core.READ_DATA ' Read Flash
cmd_pkt[1] := addr.byte[2] ' address A23..A16
cmd_pkt[2] := addr.byte[1] ' address A15..A8
cmd_pkt[3] := addr.byte[0] ' address A7..A0
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, 4)
spi.rdblock_msbf(ptr_buff, nr_bytes)
pinh(_CS)
PUB rd_uid(ptr_buff)
' Read unique 64-bit ID/serial number
' NOTE: Buffer at ptr_buff must be at least 8 bytes in length
readreg(core.UNIQUE_ID, 8, ptr_buff)
PUB wr_block_lsbf(addr, ptr_buff, nr_bytes) | byte cmd_pkt[4]
' Write a block of data to the flash chip, LSB-first
cmd_pkt[0] := core.PAGE_PROG ' Write Flash
cmd_pkt[1] := addr.byte[2] ' address A23..A16
cmd_pkt[2] := addr.byte[1] ' address A15..A8
cmd_pkt[3] := addr.byte[0] ' address A7..A0
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, 4)
spi.wrblock_lsbf(ptr_buff, nr_bytes)
pinh(_CS)
PUB wr_block_msbf(addr, ptr_buff, nr_bytes) | byte cmd_pkt[4]
' Write a block of data to the flash chip, MSB-first
cmd_pkt[0] := core.PAGE_PROG ' Write Flash
cmd_pkt[1] := addr.byte[2] ' address A23..A16
cmd_pkt[2] := addr.byte[1] ' address A15..A8
cmd_pkt[3] := addr.byte[0] ' address A7..A0
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, 4)
spi.wrblock_msbf(ptr_buff, nr_bytes)
pinh(_CS)
PUB writes_ena(state=-2): curr_state
' Enable writes to flash chip (page programming, sector/block/chip erase, write status reg,
' erase/program security registers)
' Valid values: TRUE (-1 or 1), FALSE (0)
' Any other value polls the chip and returns the current setting
curr_state := 0
readreg(core.READ_STATUS1, 1, @curr_state)
case_fast abs(state)
0, 1:
state := lookupz(abs(state): core.WRITE_DISABLE, core.WRITE_ENABLE)
writereg(state, 0, 0)
other:
return ((curr_state >> 1) & 1) == 1
PRI readreg(reg_nr, nr_bytes, ptr_buff) | byte cmd_pkt[5], cmd_bytes
' Read nr_bytes from device into ptr_buff
case_fast reg_nr.byte[0] ' validate reg nr
core.MANUF_DEV_ID:
cmd_bytes := 4
cmd_pkt[0] := reg_nr
cmd_pkt[1] := $00 ' 3 required dummy bytes
cmd_pkt[2] := $00
cmd_pkt[3] := $00
core.UNIQUE_ID:
cmd_bytes := 5
cmd_pkt[0] := reg_nr
cmd_pkt[1] := $00
cmd_pkt[2] := $00
cmd_pkt[3] := $00
cmd_pkt[4] := $00
core.READ_STATUS1, core.READ_STATUS2, core.READ_STATUS3:
cmd_bytes := 1
cmd_pkt[0] := reg_nr.byte[0]
other:
cmd_bytes := 1
cmd_pkt[0] := reg_nr
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, cmd_bytes)
spi.rdblock_lsbf(ptr_buff, nr_bytes)
pinh(_CS)
PRI rd_status(reg_nr): status | tmp
' Read status register
' Valid values: 1, 2, 3
' Any other value polls the chip and returns the current setting
case_fast reg_nr
1, 2, 3:
reg_nr := lookup(reg_nr: core.READ_STATUS1, core.READ_STATUS2, core.READ_STATUS3)
other:
return
readreg(reg_nr, 1, @status)
PRI writereg(reg_nr, nr_bytes, ptr_buff) | byte cmd_pkt[4], cmd_bytes
' Write nr_bytes to device from ptr_buff
case reg_nr.byte[0]
core.WRITE_ENABLE, core.WRITE_DISABLE, core.GLOBAL_BLK_LOCK, core.GLOBAL_BLK_UNLOCK:
cmd_bytes := 1
cmd_pkt[0] := reg_nr.byte[0]
core.SECTOR_ERASE, core.BLK32_ERASE, core.BLK64_ERASE, core.CHIP_ERASE, core.CHIP_ERASE2:
cmd_bytes := 4
cmd_pkt[0] := reg_nr.byte[0] ' Erase Flash
cmd_pkt[1] := reg_nr.byte[3] ' address A23..A16
cmd_pkt[2] := reg_nr.byte[2] ' address A15..A8
cmd_pkt[3] := reg_nr.byte[1] ' address A7..A0
other:
pinl(_CS)
spi.wrblock_lsbf(@cmd_pkt, cmd_bytes)
if ( nr_bytes == 0 ) ' simple command, no data,
pinh(_CS) ' so just deselect and return
return
else
spi.wrblock_lsbf(ptr_buff, nr_bytes)
pinh(_CS)
DAT
{
Copyright 2024 Jesse Burt
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
associated documentation files (the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge, publish, distribute,
sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or
substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT
NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
}