diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail
index 2ab1771f7..4a5ab9205 100644
--- a/model/riscv_sys_regs.sail
+++ b/model/riscv_sys_regs.sail
@@ -371,7 +371,7 @@ bitfield Medeleg : xlenbits = {
   SAMO_Page_Fault   : 15,
   Load_Page_Fault   : 13,
   Fetch_Page_Fault  : 12,
-  MEnvCall          : 10,
+  MEnvCall          : 11,
   SEnvCall          : 9,
   UEnvCall          : 8,
   SAMO_Access_Fault : 7,