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New command &gen_hie to generate hierarchical designs.
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@alanminko
alanminko committed Sep 15, 2023
1 parent 79456fa commit 09013f3
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Showing 3 changed files with 260 additions and 8 deletions.
2 changes: 1 addition & 1 deletion src/aig/gia/gia.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1527,7 +1527,7 @@ extern void Gia_ManPrintStatsMiter( Gia_Man_t * p, int fVerbose )
extern void Gia_ManSetRegNum( Gia_Man_t * p, int nRegs );
extern void Gia_ManReportImprovement( Gia_Man_t * p, Gia_Man_t * pNew );
extern void Gia_ManPrintNpnClasses( Gia_Man_t * p );
extern void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter );
extern void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter, int fInterComb );
/*=== giaMem.c ===========================================================*/
extern Gia_MmFixed_t * Gia_MmFixedStart( int nEntrySize, int nEntriesMax );
extern void Gia_MmFixedStop( Gia_MmFixed_t * p, int fVerbose );
Expand Down
209 changes: 205 additions & 4 deletions src/aig/gia/giaMan.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1291,7 +1291,7 @@ void Gia_ManDumpModuleName( FILE * pFile, char * pName )
else
fprintf( pFile, "_" );
}
void Gia_ManDumpInterface( Gia_Man_t * p, FILE * pFile )
void Gia_ManDumpInterface2( Gia_Man_t * p, FILE * pFile )
{
int fPrintClk = 0;
fprintf( pFile, "module " );
Expand Down Expand Up @@ -1324,7 +1324,6 @@ void Gia_ManDumpInterface( Gia_Man_t * p, FILE * pFile )
fprintf( pFile, "endmodule\n\n" );
}


/**Function*************************************************************
Synopsis [Compute arrival/required times.]
Expand Down Expand Up @@ -1407,14 +1406,21 @@ void Gia_ManWriteNames( FILE * pFile, char c, int n, Vec_Ptr_t * vNames, int Sta
fFirst = 0;
}
}
void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter )
void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int fVerBufs, int fInter, int fInterComb )
{
Gia_Obj_t * pObj;
Vec_Bit_t * vInvs, * vUsed;
int nDigits = Abc_Base10Log( Gia_ManObjNum(p) );
int nDigitsI = Abc_Base10Log( Gia_ManPiNum(p) );
int nDigitsO = Abc_Base10Log( Gia_ManPoNum(p) );
int i, k, iObj, nRegs = Gia_ManRegNum(p);
if ( fInterComb )
{
extern void Gia_ManDumpInterface( Gia_Man_t * p, char * pFileName );
Gia_ManDumpInterface( p, pFileName );
return;
}

FILE * pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
Expand All @@ -1423,7 +1429,7 @@ void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int
}

if ( fInter || nRegs )
Gia_ManDumpInterface( p, pFile );
Gia_ManDumpInterface2( p, pFile );
//Gia_ManSetRegNum( p, 0 );
p->nRegs = 0;

Expand Down Expand Up @@ -1588,6 +1594,201 @@ void Gia_ManDumpVerilog( Gia_Man_t * p, char * pFileName, Vec_Int_t * vObjs, int
Gia_ManSetRegNum( p, nRegs );
}

/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManDumpInterface( Gia_Man_t * p, char * pFileName )
{
Gia_Obj_t * pObj;
Vec_Bit_t * vInvs, * vUsed;
int nDigits = Abc_Base10Log( Gia_ManObjNum(p) );
int nDigitsI = Abc_Base10Log( Gia_ManPiNum(p) );
int nDigitsO = Abc_Base10Log( Gia_ManPoNum(p) );
int i;

FILE * pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open output file \"%s\".\n", pFileName );
return;
}

vInvs = Gia_ManGenUsed( p, 0 );
vUsed = Gia_ManGenUsed( p, 1 );

fprintf( pFile, "module " );
Gia_ManDumpModuleName( pFile, p->pName );
fprintf( pFile, "_wrapper" );
fprintf( pFile, " ( _i_, _o_ );\n\n" );
fprintf( pFile, " input [%d:0] _i_;\n", Gia_ManCiNum(p)-1 );
fprintf( pFile, " output [%d:0] _o_;\n\n", Gia_ManCoNum(p)-1 );

fprintf( pFile, " wire " );
Gia_ManWriteNames( pFile, 'x', Gia_ManPiNum(p), p->vNamesIn, 8, 4, NULL );
fprintf( pFile, ";\n\n" );

fprintf( pFile, " wire " );
Gia_ManWriteNames( pFile, 'z', Gia_ManPoNum(p), p->vNamesOut, 9, 4, NULL );
fprintf( pFile, ";\n\n" );

fprintf( pFile, " assign { " );
Gia_ManWriteNames( pFile, 'x', Gia_ManCiNum(p), p->vNamesIn, 8, 4, NULL );
fprintf( pFile, " } = _i_;\n\n" );

fprintf( pFile, " assign _o_ = { " );
Gia_ManWriteNames( pFile, 'z', Gia_ManCoNum(p), p->vNamesOut, 9, 4, NULL );
fprintf( pFile, " };\n\n" );

if ( Vec_BitCount(vUsed) )
{
fprintf( pFile, " wire " );
Gia_ManWriteNames( pFile, 'n', Gia_ManObjNum(p), NULL, 7, 4, vUsed );
fprintf( pFile, ";\n\n" );
}

if ( Vec_BitCount(vInvs) )
{
fprintf( pFile, " wire " );
Gia_ManWriteNames( pFile, 'i', Gia_ManObjNum(p), NULL, 7, 4, vInvs );
fprintf( pFile, ";\n\n" );
}

// input inverters
Gia_ManForEachCi( p, pObj, i )
{
if ( Vec_BitEntry(vUsed, Gia_ObjId(p, pObj)) )
{
fprintf( pFile, " buf ( %s,", Gia_ObjGetDumpName(NULL, 'n', Gia_ObjId(p, pObj), nDigits) );
fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(p->vNamesIn, 'x', i, nDigitsI) );
}
if ( Vec_BitEntry(vInvs, Gia_ObjId(p, pObj)) )
{
fprintf( pFile, " not ( %s,", Gia_ObjGetDumpName(NULL, 'i', Gia_ObjId(p, pObj), nDigits) );
fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(p->vNamesIn, 'x', i, nDigitsI) );
}
}

// internal nodes and their inverters
fprintf( pFile, "\n" );
Gia_ManForEachAnd( p, pObj, i )
{
fprintf( pFile, " and ( %s,", Gia_ObjGetDumpName(NULL, 'n', i, nDigits) );
fprintf( pFile, " %s,", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC0(pObj)? 'i':'n'), Gia_ObjFaninId0(pObj, i), nDigits) );
fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC1(pObj)? 'i':'n'), Gia_ObjFaninId1(pObj, i), nDigits) );
if ( Vec_BitEntry(vInvs, i) )
{
fprintf( pFile, " not ( %s,", Gia_ObjGetDumpName(NULL, 'i', i, nDigits) );
fprintf( pFile, " %s );\n", Gia_ObjGetDumpName(NULL, 'n', i, nDigits) );
}
}

// output drivers
fprintf( pFile, "\n" );
Gia_ManForEachCo( p, pObj, i )
{
fprintf( pFile, " buf ( %s, ", Gia_ObjGetDumpName(p->vNamesOut, 'z', i, nDigitsO) );
if ( Gia_ObjIsConst0(Gia_ObjFanin0(pObj)) )
fprintf( pFile, "1\'b%d );\n", Gia_ObjFaninC0(pObj) );
else
fprintf( pFile, "%s );\n", Gia_ObjGetDumpName(NULL, (char)(Gia_ObjFaninC0(pObj)? 'i':'n'), Gia_ObjFaninId0p(p, pObj), nDigits) );
}

fprintf( pFile, "\nendmodule\n\n" );
fclose( pFile );

Vec_BitFree( vInvs );
Vec_BitFree( vUsed );
}


/**Function*************************************************************
Synopsis [Generate hierarchical design.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_FreeMany( Gia_Man_t ** pGias, int nGias )
{
int i;
for ( i = 0; i < nGias; i++ )
Gia_ManStopP( &pGias[i] );
}
void Gia_GenSandwich( char ** pFNames, int nFNames )
{
FILE * pFile = NULL;
char * pFileName = (char *)"sandwich.v";
Gia_Man_t * pGias[16] = {0};
int i, k;
assert( nFNames <= 16 );
for ( i = 0; i < nFNames; i++ )
{
FILE * pFile = fopen( pFNames[i], "rb" );
if ( pFile == NULL ) {
printf( "Cannot open input file \"%s\".\n", pFNames[i] );
Gia_FreeMany( pGias, nFNames );
return;
}
fclose( pFile );
pGias[i] = Gia_AigerRead( pFNames[i], 0, 0, 0 );
if ( pGias[i] == NULL ) {
printf( "Failed to read an AIG from file \"%s\".\n", pFNames[i] );
Gia_FreeMany( pGias, nFNames );
return;
}
}
for ( i = 0; i < nFNames-1; i++ )
if ( Gia_ManPoNum(pGias[i]) < Gia_ManPiNum(pGias[i+1]) ) {
printf( "AIG in file \"%s\" has fewer outputs than inputs of AIG in file \"%s\".\n", pFNames[i], pFNames[i+1] );
Gia_FreeMany( pGias, nFNames );
return;
}
pFile = fopen( pFileName, "wb" );
if ( pFile == NULL )
{
printf( "Cannot open output file \"%s\".\n", pFileName );
Gia_FreeMany( pGias, nFNames );
return;
}
fprintf( pFile, "\n" );
for ( i = 0; i < nFNames; i++ )
fprintf( pFile, "`include \"%s\"\n", Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v") );
fprintf( pFile, "\n" );
fprintf( pFile, "module sandwich ( in, out );\n" );
fprintf( pFile, " input [%3d:0] in;\n", Gia_ManPiNum(pGias[0])-1 );
fprintf( pFile, " output [%3d:0] out;\n", Gia_ManPoNum(pGias[nFNames-1])-1 );
fprintf( pFile, " wire [%3d:0] tmp0 = in;\n", Gia_ManPiNum(pGias[0])-1 );
for ( i = 0; i < nFNames; i++ ) {
fprintf( pFile, " wire [%3d:0] tmp%d; ", Gia_ManPoNum(pGias[i])-1, i+1 );
Gia_ManDumpModuleName( pFile, pGias[i]->pName );
fprintf( pFile, "_wrapper" );
for ( k = strlen(pGias[i]->pName); k < 24; k++ )
fprintf( pFile, " " );
fprintf( pFile, " i%d ( tmp%d, tmp%d );\n", i+1, i, i+1 );
}
fprintf( pFile, " assign out = tmp%d;\n", nFNames );
fprintf( pFile, "endmodule\n" );
fclose( pFile );
for ( i = 0; i < nFNames; i++ ) {
Gia_ManDumpVerilog( pGias[i], Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v"), NULL, 0, 0, 1 );
printf( "Dumped Verilog file \"%s\"\n", Extra_FileNameGenericAppend(pGias[i]->pSpec, ".v") );
}
Gia_FreeMany( pGias, nFNames );
printf( "Dumped hierarchical design into file \"%s\"\n", pFileName );
}

////////////////////////////////////////////////////////////////////////
/// END OF FILE ///
////////////////////////////////////////////////////////////////////////
Expand Down
57 changes: 54 additions & 3 deletions src/base/abci/abc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -595,6 +595,7 @@ static int Abc_CommandAbc9Cfs ( Abc_Frame_t * pAbc, int argc, cha
static int Abc_CommandAbc9ProdAdd ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandAbc9AddFlop ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandAbc9BMiter ( Abc_Frame_t * pAbc, int argc, char ** argv );
static int Abc_CommandAbc9GenHie ( Abc_Frame_t * pAbc, int argc, char ** argv );

static int Abc_CommandAbc9Test ( Abc_Frame_t * pAbc, int argc, char ** argv );

Expand Down Expand Up @@ -1364,6 +1365,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
Cmd_CommandAdd( pAbc, "ABC9", "&prodadd", Abc_CommandAbc9ProdAdd, 0 );
Cmd_CommandAdd( pAbc, "ABC9", "&addflop", Abc_CommandAbc9AddFlop, 0 );
Cmd_CommandAdd( pAbc, "ABC9", "&bmiter", Abc_CommandAbc9BMiter, 0 );
Cmd_CommandAdd( pAbc, "ABC9", "&gen_hie", Abc_CommandAbc9GenHie, 0 );

Cmd_CommandAdd( pAbc, "ABC9", "&test", Abc_CommandAbc9Test, 0 );
{
Expand Down Expand Up @@ -31762,13 +31764,14 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
int fUnique = 0;
int fVerilog = 0;
int fInter = 0;
int fInterComb = 0;
int fVerBufs = 0;
int fMiniAig = 0;
int fMiniLut = 0;
int fWriteNewLine = 0;
int fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "upibmlnvh" ) ) != EOF )
while ( ( c = Extra_UtilGetopt( argc, argv, "upicbmlnvh" ) ) != EOF )
{
switch ( c )
{
Expand All @@ -31781,6 +31784,9 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
case 'i':
fInter ^= 1;
break;
case 'c':
fInterComb ^= 1;
break;
case 'b':
fVerBufs ^= 1;
break;
Expand Down Expand Up @@ -31822,7 +31828,7 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
Gia_ManStop( pGia );
}
else if ( fVerilog )
Gia_ManDumpVerilog( pAbc->pGia, pFileName, NULL, fVerBufs, fInter );
Gia_ManDumpVerilog( pAbc->pGia, pFileName, NULL, fVerBufs, fInter, fInterComb );
else if ( fMiniAig )
Gia_ManWriteMiniAig( pAbc->pGia, pFileName );
else if ( fMiniLut )
Expand All @@ -31832,11 +31838,12 @@ int Abc_CommandAbc9Write( Abc_Frame_t * pAbc, int argc, char ** argv )
return 0;

usage:
Abc_Print( -2, "usage: &w [-upibmlnvh] <file>\n" );
Abc_Print( -2, "usage: &w [-upicbmlnvh] <file>\n" );
Abc_Print( -2, "\t writes the current AIG into the AIGER file\n" );
Abc_Print( -2, "\t-u : toggle writing canonical AIG structure [default = %s]\n", fUnique? "yes" : "no" );
Abc_Print( -2, "\t-p : toggle writing Verilog with 'and' and 'not' [default = %s]\n", fVerilog? "yes" : "no" );
Abc_Print( -2, "\t-i : toggle writing the interface module in Verilog [default = %s]\n", fInter? "yes" : "no" );
Abc_Print( -2, "\t-c : toggle writing the interface module in Verilog [default = %s]\n", fInterComb? "yes" : "no" );
Abc_Print( -2, "\t-b : toggle writing additional buffers in Verilog [default = %s]\n", fVerBufs? "yes" : "no" );
Abc_Print( -2, "\t-m : toggle writing MiniAIG rather than AIGER [default = %s]\n", fMiniAig? "yes" : "no" );
Abc_Print( -2, "\t-l : toggle writing MiniLUT rather than AIGER [default = %s]\n", fMiniLut? "yes" : "no" );
Expand Down Expand Up @@ -51569,6 +51576,50 @@ int Abc_CommandAbc9BMiter( Abc_Frame_t * pAbc, int argc, char ** argv )
return 1;
}


/**Function*************************************************************

Synopsis []

Description []

SideEffects []

SeeAlso []

***********************************************************************/
int Abc_CommandAbc9GenHie( Abc_Frame_t * pAbc, int argc, char ** argv )
{
extern void Gia_GenSandwich( char ** pFNames, int nFNames );
int c, fVerbose = 0;
Extra_UtilGetoptReset();
while ( ( c = Extra_UtilGetopt( argc, argv, "vh" ) ) != EOF )
{
switch ( c )
{
case 'v':
fVerbose ^= 1;
break;
case 'h':
goto usage;
default:
goto usage;
}
}
char ** pArgvNew = argv + globalUtilOptind;
int nArgcNew = argc - globalUtilOptind;
Gia_GenSandwich( pArgvNew, nArgcNew );
return 0;
usage:
Abc_Print( -2, "usage: &gen_hie [-vh] <file[1]> <file[2]> ... <file[N]>\n" );
Abc_Print( -2, "\t generates a hierarchical design\n" );
Abc_Print( -2, "\t-v : toggles printing verbose information [default = %s]\n", fVerbose? "yes": "no" );
Abc_Print( -2, "\t-h : print the command usage\n");
Abc_Print( -2, "\t<files> : the AIG files for the instance modules\n");
Abc_Print( -2, "\t (the PO count of <file[i]> should not be less than the PI count of <file[i+1]>)\n");
return 1;}


/**Function*************************************************************

Synopsis []
Expand Down

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