From aedb20a395dcb151ab8ef28a102cfb79d579174f Mon Sep 17 00:00:00 2001 From: dragonmux Date: Wed, 29 Nov 2023 17:53:17 +0000 Subject: [PATCH] riscv_debug: Fixed an issue in `riscv_hart_discover_triggers` which is triggered on WCH devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This re-implements the fix from fubbed PR #1576 with thanks to mean00 Co-Authored-By: Rafael Graça Silva Co-Authored-By: dragonmux --- src/target/riscv_debug.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/target/riscv_debug.c b/src/target/riscv_debug.c index edd2cb60d38..6fa13ef4e59 100644 --- a/src/target/riscv_debug.c +++ b/src/target/riscv_debug.c @@ -676,7 +676,12 @@ static void riscv_hart_discover_triggers(riscv_hart_s *const hart) riscv_csr_write(hart, RV_TRIG_SELECT | RV_CSR_FORCE_32_BIT, &trigger); /* Try reading the trigger info */ uint32_t info = 0; - if (!riscv_csr_read(hart, RV_TRIG_INFO | RV_CSR_FORCE_32_BIT, &info)) { + /* + * If the read succeeds but info is still 0, assume we're talking to something like a WCH device + * which'll do this despite not actually implementing the tinfo register. Handle it the same as + * the read explicitly failing. + */ + if (!riscv_csr_read(hart, RV_TRIG_INFO | RV_CSR_FORCE_32_BIT, &info) || !info) { /* * If that fails, it's probably because the tinfo register isn't implemented, so read * the tdata1 register instead and extract the type from the MSb and build the info bitset from that