From d26bf57ce092c4dd246008d119e59e4e52a6e500 Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Sat, 9 Sep 2023 13:44:45 +0100 Subject: [PATCH] align: rename enum to be more arch agnostic and clear --- src/include/align.h | 10 +++++----- src/platforms/hosted/dap.c | 12 ++++++------ src/platforms/hosted/stlinkv2.c | 8 ++++---- src/target/adiv5.c | 20 ++++++++++---------- src/target/stm32_common.h | 14 +++++++------- src/target/stm32f1.c | 12 ++++++------ src/target/stm32f4.c | 6 +++--- src/target/stm32h7.c | 6 +++--- 8 files changed, 44 insertions(+), 44 deletions(-) diff --git a/src/include/align.h b/src/include/align.h index aa759adb0da..51b91023805 100644 --- a/src/include/align.h +++ b/src/include/align.h @@ -34,13 +34,13 @@ #define INCLUDE_ALIGN_H typedef enum align { - ALIGN_BYTE = 0, /* 8 bit alignment */ - ALIGN_HALFWORD = 1, /* 16 bit alignment */ - ALIGN_WORD = 2, /* 32 bit alignment */ - ALIGN_DWORD = 3 /* 64 bit alignment */ + ALIGN_8BIT = 0U, + ALIGN_16BIT = 1U, + ALIGN_32BIT = 2U, + ALIGN_64BIT = 3U, } align_e; -#define ALIGN_OF(x) (((x)&3U) == 0 ? ALIGN_WORD : (((x)&1U) == 0 ? ALIGN_HALFWORD : ALIGN_BYTE)) +#define ALIGN_OF(x) (((x)&3U) == 0 ? ALIGN_32BIT : (((x)&1U) == 0 ? ALIGN_16BIT : ALIGN_8BIT)) #define MIN_ALIGN(x, y) MIN(ALIGN_OF(x), ALIGN_OF(y)) #define ALIGN(x, n) (((x) + (n)-1) & ~((n)-1)) diff --git a/src/platforms/hosted/dap.c b/src/platforms/hosted/dap.c index 48158e45d15..1a06cbe95fb 100644 --- a/src/platforms/hosted/dap.c +++ b/src/platforms/hosted/dap.c @@ -270,7 +270,7 @@ bool dap_read_block( return false; } - if (align > ALIGN_HALFWORD) + if (align > ALIGN_16BIT) memcpy(dest, data, len); else { for (size_t i = 0; i < blocks; ++i) { @@ -287,7 +287,7 @@ bool dap_write_block( const size_t blocks = len >> MAX(align, 2U); uint32_t data[256]; - if (align > ALIGN_HALFWORD) + if (align > ALIGN_16BIT) memcpy(data, src, len); else { for (size_t i = 0; i < blocks; ++i) { @@ -336,14 +336,14 @@ static void mem_access_setup(const adiv5_access_port_s *const target_ap, { uint32_t csw = target_ap->csw | ADIV5_AP_CSW_ADDRINC_SINGLE; switch (align) { - case ALIGN_BYTE: + case ALIGN_8BIT: csw |= ADIV5_AP_CSW_SIZE_BYTE; break; - case ALIGN_HALFWORD: + case ALIGN_16BIT: csw |= ADIV5_AP_CSW_SIZE_HALFWORD; break; - case ALIGN_DWORD: - case ALIGN_WORD: + case ALIGN_64BIT: + case ALIGN_32BIT: csw |= ADIV5_AP_CSW_SIZE_WORD; break; } diff --git a/src/platforms/hosted/stlinkv2.c b/src/platforms/hosted/stlinkv2.c index 53d9e664d9f..b8ec8ad29d1 100644 --- a/src/platforms/hosted/stlinkv2.c +++ b/src/platforms/hosted/stlinkv2.c @@ -741,14 +741,14 @@ static void stlink_mem_write( /* Now generate an appropriate access packet */ stlink_mem_command_s command; switch (align) { - case ALIGN_BYTE: + case ALIGN_8BIT: command = stlink_memory_access(STLINK_DEBUG_WRITEMEM_8BIT, addr, amount, ap->apsel); break; - case ALIGN_HALFWORD: + case ALIGN_16BIT: command = stlink_memory_access(STLINK_DEBUG_APIV2_WRITEMEM_16BIT, addr, amount, ap->apsel); break; - case ALIGN_WORD: - case ALIGN_DWORD: + case ALIGN_32BIT: + case ALIGN_64BIT: command = stlink_memory_access(STLINK_DEBUG_WRITEMEM_32BIT, addr, amount, ap->apsel); break; } diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 73cd3797833..84acdbfb3d0 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -995,14 +995,14 @@ void ap_mem_access_setup(adiv5_access_port_s *ap, uint32_t addr, align_e align) uint32_t csw = ap->csw | ADIV5_AP_CSW_ADDRINC_SINGLE; switch (align) { - case ALIGN_BYTE: + case ALIGN_8BIT: csw |= ADIV5_AP_CSW_SIZE_BYTE; break; - case ALIGN_HALFWORD: + case ALIGN_16BIT: csw |= ADIV5_AP_CSW_SIZE_HALFWORD; break; - case ALIGN_DWORD: - case ALIGN_WORD: + case ALIGN_64BIT: + case ALIGN_32BIT: csw |= ADIV5_AP_CSW_SIZE_WORD; break; } @@ -1014,7 +1014,7 @@ void ap_mem_access_setup(adiv5_access_port_s *ap, uint32_t addr, align_e align) void *adiv5_unpack_data(void *const dest, const uint32_t src, const uint32_t data, const align_e align) { switch (align) { - case ALIGN_BYTE: { + case ALIGN_8BIT: { /* * Mask off the bottom 2 bits of the address to figure out which byte of data to use * then multiply that by 8 and shift the data down by the result to pick one of the 4 possible bytes @@ -1024,7 +1024,7 @@ void *adiv5_unpack_data(void *const dest, const uint32_t src, const uint32_t dat memcpy(dest, &value, sizeof(value)); break; } - case ALIGN_HALFWORD: { + case ALIGN_16BIT: { /* * Mask off the 2nd bit of the address to figure out which 16 bits of data to use * then multiply that by 8 and shift the data down by the result to pick one of the 2 possible 16-bit blocks @@ -1034,8 +1034,8 @@ void *adiv5_unpack_data(void *const dest, const uint32_t src, const uint32_t dat memcpy(dest, &value, sizeof(value)); break; } - case ALIGN_DWORD: - case ALIGN_WORD: + case ALIGN_64BIT: + case ALIGN_32BIT: /* * When using 32- or 64-bit alignment, we don't have to do anything special, just memcpy() the data to the * destination buffer (this avoids issues with unaligned writes and UB casts) @@ -1050,7 +1050,7 @@ void *adiv5_unpack_data(void *const dest, const uint32_t src, const uint32_t dat const void *adiv5_pack_data(const uint32_t dest, const void *const src, uint32_t *const data, const align_e align) { switch (align) { - case ALIGN_BYTE: { + case ALIGN_8BIT: { uint8_t value; /* Copy the data to pack in from the source buffer */ memcpy(&value, src, sizeof(value)); @@ -1058,7 +1058,7 @@ const void *adiv5_pack_data(const uint32_t dest, const void *const src, uint32_t *data = (uint32_t)value << (8U * (dest & 3U)); break; } - case ALIGN_HALFWORD: { + case ALIGN_16BIT: { uint16_t value; /* Copy the data to pack in from the source buffer (avoids unaligned read issues) */ memcpy(&value, src, sizeof(value)); diff --git a/src/target/stm32_common.h b/src/target/stm32_common.h index 356087b1e7e..7352b79997b 100644 --- a/src/target/stm32_common.h +++ b/src/target/stm32_common.h @@ -28,11 +28,11 @@ static inline const char *stm32_psize_to_string(const align_e psize) { switch (psize) { - case ALIGN_DWORD: + case ALIGN_64BIT: return "x64"; - case ALIGN_WORD: + case ALIGN_32BIT: return "x32"; - case ALIGN_HALFWORD: + case ALIGN_16BIT: return "x16"; default: return "x8"; @@ -42,13 +42,13 @@ static inline const char *stm32_psize_to_string(const align_e psize) static inline bool stm32_psize_from_string(target_s *t, const char *const str, align_e *psize) { if (strcasecmp(str, "x8") == 0) - *psize = ALIGN_BYTE; + *psize = ALIGN_8BIT; else if (strcasecmp(str, "x16") == 0) - *psize = ALIGN_HALFWORD; + *psize = ALIGN_16BIT; else if (strcasecmp(str, "x32") == 0) - *psize = ALIGN_WORD; + *psize = ALIGN_32BIT; else if (strcasecmp(str, "x64") == 0) - *psize = ALIGN_DWORD; + *psize = ALIGN_64BIT; else { tc_printf(t, "usage: monitor psize (x8|x16|x32|x32)\n"); return false; diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index d99f55b289d..dd6a9d5112a 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -379,7 +379,7 @@ void mm32l0_mem_write_sized(adiv5_access_port_s *ap, uint32_t dest, const void * uint32_t tmp = 0; /* Pack data into correct data lane */ switch (align) { - case ALIGN_BYTE: { + case ALIGN_8BIT: { uint8_t value; memcpy(&value, src, sizeof(value)); /* copy byte to be written to all four bytes of the uint32_t */ @@ -388,7 +388,7 @@ void mm32l0_mem_write_sized(adiv5_access_port_s *ap, uint32_t dest, const void * tmp = tmp | tmp << 16U; break; } - case ALIGN_HALFWORD: { + case ALIGN_16BIT: { uint16_t value; memcpy(&value, src, sizeof(value)); /* copy halfword to be written to both halfwords of the uint32_t */ @@ -396,8 +396,8 @@ void mm32l0_mem_write_sized(adiv5_access_port_s *ap, uint32_t dest, const void * tmp = tmp | tmp << 16U; break; } - case ALIGN_DWORD: - case ALIGN_WORD: + case ALIGN_64BIT: + case ALIGN_32BIT: memcpy(&tmp, src, sizeof(tmp)); break; } @@ -700,7 +700,7 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const stm32f1_flash_clear_eop(target, FLASH_BANK1_OFFSET); target_mem_write32(target, FLASH_CR, FLASH_CR_PG); - cortexm_mem_write_sized(target, dest, src, offset, ALIGN_HALFWORD); + cortexm_mem_write_sized(target, dest, src, offset, ALIGN_16BIT); /* Wait for completion or an error */ if (!stm32f1_flash_busy_wait(target, FLASH_BANK1_OFFSET, NULL)) @@ -714,7 +714,7 @@ static bool stm32f1_flash_write(target_flash_s *flash, target_addr_t dest, const stm32f1_flash_clear_eop(target, FLASH_BANK2_OFFSET); target_mem_write32(target, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_PG); - cortexm_mem_write_sized(target, dest + offset, data + offset, remainder, ALIGN_HALFWORD); + cortexm_mem_write_sized(target, dest + offset, data + offset, remainder, ALIGN_16BIT); /* Wait for completion or an error */ if (!stm32f1_flash_busy_wait(target, FLASH_BANK2_OFFSET, NULL)) diff --git a/src/target/stm32f4.c b/src/target/stm32f4.c index 24479e3c211..54d3c2f4633 100644 --- a/src/target/stm32f4.c +++ b/src/target/stm32f4.c @@ -162,7 +162,7 @@ static void stm32f4_add_flash(target_s *const t, const uint32_t addr, const size f->erased = 0xffU; sf->base_sector = base_sector; sf->bank_split = split; - sf->psize = ALIGN_WORD; + sf->psize = ALIGN_32BIT; target_add_flash(t, f); } @@ -484,7 +484,7 @@ static bool stm32f4_flash_erase(target_flash_s *f, target_addr_t addr, size_t le stm32f4_flash_s *sf = (stm32f4_flash_s *)f; stm32f4_flash_unlock(t); - align_e psize = ALIGN_WORD; + align_e psize = ALIGN_32BIT; /* * XXX: What is this and why does it exist? * A dry-run walk-through says it'll pull out the psize for the Flash region added first by stm32f4_attach() @@ -761,7 +761,7 @@ static bool stm32f4_cmd_option(target_s *t, int argc, const char **argv) static bool stm32f4_cmd_psize(target_s *t, int argc, const char **argv) { if (argc == 1) { - align_e psize = ALIGN_WORD; + align_e psize = ALIGN_32BIT; /* * XXX: What is this and why does it exist? * A dry-run walk-through says it'll pull out the psize for the Flash region added first by stm32f4_attach() diff --git a/src/target/stm32h7.c b/src/target/stm32h7.c index a44d5b5d728..cacbb5eee67 100644 --- a/src/target/stm32h7.c +++ b/src/target/stm32h7.c @@ -182,7 +182,7 @@ static void stm32h7_add_flash(target_s *target, uint32_t addr, size_t length, si flash->regbase = FPEC1_BASE; else flash->regbase = FPEC2_BASE; - flash->psize = ALIGN_DWORD; + flash->psize = ALIGN_64BIT; target_add_flash(target, target_flash); } @@ -400,7 +400,7 @@ static bool stm32h7_check_bank(target_s *const target, const uint32_t reg_base) /* Both banks are erased in parallel.*/ static bool stm32h7_mass_erase(target_s *target) { - align_e psize = ALIGN_DWORD; + align_e psize = ALIGN_64BIT; /* * XXX: What is this and why does it exist? * A dry-run walk-through says it'll pull out the psize for the first Flash region added by stm32h7_probe() @@ -499,7 +499,7 @@ static bool stm32h7_crc(target_s *target, int argc, const char **argv) static bool stm32h7_cmd_psize(target_s *target, int argc, const char **argv) { if (argc == 1) { - align_e psize = ALIGN_DWORD; + align_e psize = ALIGN_64BIT; /* * XXX: What is this and why does it exist? * A dry-run walk-through says it'll pull out the psize for the first Flash region added by stm32h7_probe()