From 37c9adc7feceda03603046fbeb97f712f77320b1 Mon Sep 17 00:00:00 2001
From: Jack Koenig <koenig@sifive.com>
Date: Wed, 18 Dec 2024 13:25:44 -0800
Subject: [PATCH] Apply align.preset = some

---
 .../main/scala/chisel3/AggregateImpl.scala    |  12 +-
 core/src/main/scala/chisel3/BitsImpl.scala    |  36 ++---
 .../main/scala/chisel3/ChiselEnumImpl.scala   |  12 +-
 core/src/main/scala/chisel3/ClockImpl.scala   |   2 +-
 core/src/main/scala/chisel3/DataImpl.scala    | 112 ++++++-------
 core/src/main/scala/chisel3/Element.scala     |   6 +-
 core/src/main/scala/chisel3/IO.scala          |   8 +-
 core/src/main/scala/chisel3/Layer.scala       |  22 +--
 core/src/main/scala/chisel3/ModuleImpl.scala  |  20 +--
 core/src/main/scala/chisel3/Printable.scala   |  12 +-
 core/src/main/scala/chisel3/RawModule.scala   |  24 +--
 core/src/main/scala/chisel3/When.scala        |   4 +-
 core/src/main/scala/chisel3/Width.scala       |   2 +-
 .../scala/chisel3/connectable/Alignment.scala |  36 ++---
 .../chisel3/connectable/Connection.scala      |   8 +-
 core/src/main/scala/chisel3/dontTouch.scala   |   2 +-
 .../scala/chisel3/experimental/Analog.scala   |   2 +-
 .../SerializableModuleGenerator.scala         |  16 +-
 .../chisel3/experimental/SourceInfoImpl.scala |   2 +-
 .../experimental/dataview/package.scala       |  10 +-
 .../hierarchy/InstantiableClone.scala         |   2 +-
 .../hierarchy/InstantiateImpl.scala           |   4 +-
 .../experimental/hierarchy/ModuleClone.scala  |   2 +-
 .../hierarchy/core/Hierarchy.scala            |  12 +-
 .../hierarchy/core/Instance.scala             |  34 ++--
 .../hierarchy/core/Lookupable.scala           |  24 +--
 .../scala/chisel3/internal/BiConnect.scala    |  38 ++---
 .../main/scala/chisel3/internal/Binding.scala |   6 +-
 .../main/scala/chisel3/internal/Builder.scala |  88 +++++-----
 .../main/scala/chisel3/internal/Error.scala   |  18 +--
 .../scala/chisel3/internal/MonoConnect.scala  |  46 +++---
 .../chisel3/internal/firrtl/Converter.scala   |  38 ++---
 .../scala/chisel3/internal/firrtl/IR.scala    |  34 ++--
 .../main/scala/chisel3/internal/package.scala |   4 +-
 core/src/main/scala/chisel3/package.scala     |  14 +-
 .../main/scala/chisel3/probe/ProbeBase.scala  |   2 +-
 .../main/scala/chisel3/properties/Path.scala  |   8 +-
 .../scala/chisel3/properties/Property.scala   |   4 +-
 .../scala/chisel3/reflect/DataMirror.scala    |  16 +-
 firrtl/src/main/scala/firrtl/FileUtils.scala  |   2 +-
 firrtl/src/main/scala/firrtl/RenameMap.scala  |  20 +--
 firrtl/src/main/scala/firrtl/Utils.scala      |   2 +-
 .../firrtl/annotations/AnnotationUtils.scala  |  24 +--
 .../firrtl/annotations/JsonProtocol.scala     |   4 +-
 .../annotations/LoadMemoryAnnotation.scala    |   2 +-
 .../scala/firrtl/annotations/Target.scala     | 118 +++++++-------
 firrtl/src/main/scala/firrtl/ir/IR.scala      |  30 ++--
 .../src/main/scala/firrtl/ir/Serializer.scala | 110 ++++++-------
 .../firrtl/options/DependencyManager.scala    |  48 +++---
 .../src/main/scala/firrtl/options/Phase.scala |   8 +-
 .../scala/firrtl/options/StageOptions.scala   |   4 +-
 .../scala/firrtl/options/StageUtils.scala     |   2 +-
 .../main/scala/firrtl/options/package.scala   |   2 +-
 .../scala/firrtl/options/phases/Checks.scala  |   8 +-
 .../phases/WriteOutputAnnotations.scala       |  30 ++--
 .../main/scala/firrtl/passes/CheckTypes.scala |  22 +--
 .../firrtl/stage/FirrtlAnnotations.scala      |   4 +-
 .../src/main/scala/firrtl/stage/package.scala |   4 +-
 .../firrtl/stage/phases/AddDefaults.scala     |   2 +-
 .../scala/firrtl/stage/phases/Checks.scala    |  12 +-
 .../scala/firrtl/transforms/MustDedup.scala   |   4 +-
 firrtl/src/main/scala/logger/Logger.scala     |  18 +--
 firrtl/src/main/scala/logger/package.scala    |   8 +-
 .../src/main/scala/logger/phases/Checks.scala |   6 +-
 src/main/scala-2/chisel3/aop/Select.scala     |  14 +-
 src/main/scala-2/chisel3/ltl/LTL.scala        |   4 +-
 .../scala-2/chisel3/simulator/Simulator.scala |   4 +-
 .../scala-2/chisel3/simulator/package.scala   |   6 +-
 src/main/scala-2/chisel3/util/SRAM.scala      |  20 +--
 src/main/scala-2/chisel3/util/Switch.scala    |   2 +-
 .../experimental/util/algorithm/Bitwise.scala |   4 +-
 .../chisel3/stage/ChiselAnnotations.scala     |   4 +-
 src/main/scala/chisel3/stage/package.scala    |  14 +-
 .../phases/AddDedupGroupAnnotations.scala     |   6 +-
 .../scala/chisel3/stage/phases/Checks.scala   |  14 +-
 src/main/scala/chisel3/util/BitwiseImpl.scala |   6 +-
 src/main/scala/chisel3/util/Conditional.scala |   2 +-
 src/main/scala/chisel3/util/Counter.scala     |   2 +-
 src/main/scala/chisel3/util/Math.scala        |   4 +-
 src/main/scala/chisel3/util/SparseVec.scala   |   6 +-
 src/main/scala/chisel3/util/circt/DPI.scala   |   6 +-
 .../util/experimental/BoringUtils.scala       |   8 +-
 .../util/experimental/SlangUtils.scala        |   4 +-
 .../decode/EspressoMinimizer.scala            |  16 +-
 .../chisel3/util/random/GaloisLFSR.scala      |   2 +-
 src/main/scala/chisel3/util/random/LFSR.scala |   4 +-
 src/main/scala/chisel3/util/random/PRNG.scala |   2 +-
 src/main/scala/circt/stage/Annotations.scala  |  18 +--
 src/main/scala/circt/stage/ChiselStage.scala  |   2 +-
 src/main/scala/circt/stage/package.scala      |  16 +-
 src/main/scala/circt/stage/phases/CIRCT.scala |  44 ++---
 .../scala/circt/stage/phases/Checks.scala     |   2 +-
 .../experimental/decode/TruthTableSpec.scala  |  16 +-
 .../chiselTests/AnnotatingDiamondSpec.scala   |   6 +-
 src/test/scala/chiselTests/BlackBoxImpl.scala |  12 +-
 src/test/scala/chiselTests/ChiselEnum.scala   |  14 +-
 src/test/scala/chiselTests/ChiselSpec.scala   |   6 +-
 src/test/scala/chiselTests/DPISpec.scala      |  24 +--
 .../scala/chiselTests/DecoupledSpec.scala     |  12 +-
 .../scala/chiselTests/ExtModuleImpl.scala     |  12 +-
 src/test/scala/chiselTests/LayerSpec.scala    | 152 +++++++++---------
 src/test/scala/chiselTests/Math.scala         |   6 +-
 .../experimental/AutoBlackBoxSpec.scala       |   2 +-
 .../chiselTests/experimental/TraceSpec.scala  | 104 ++++++------
 .../hierarchy/InstantiateSpec.scala           |  10 +-
 .../chiselTests/simulator/SimulatorSpec.scala |  10 +-
 .../stage/WarningConfigurationSpec.scala      |  30 ++--
 .../scala/chiselTests/util/BitSetSpec.scala   |  26 +--
 .../circtTests/stage/ChiselStageSpec.scala    |  48 +++---
 .../examples/VendingMachineGenerator.scala    |   2 +-
 .../scala/examples/VendingMachineUtils.scala  |   2 +-
 svsim/src/test/scala/BackendSpec.scala        |   2 +-
 112 files changed, 984 insertions(+), 984 deletions(-)

diff --git a/core/src/main/scala/chisel3/AggregateImpl.scala b/core/src/main/scala/chisel3/AggregateImpl.scala
index 5eec5a28f40..79b54a207d3 100644
--- a/core/src/main/scala/chisel3/AggregateImpl.scala
+++ b/core/src/main/scala/chisel3/AggregateImpl.scala
@@ -357,7 +357,7 @@ private[chisel3] abstract class VecImpl[T <: Data] private[chisel3] (gen: => T,
     // We also don't want to warn on literals that are "too small"
     p.litOption match {
       case Some(idx) if idx < length => return this.apply(idx.intValue)
-      case _                         => // Fall through to control flow below
+      case _ => // Fall through to control flow below
     }
 
     if (length == 0) {
@@ -395,13 +395,13 @@ private[chisel3] abstract class VecImpl[T <: Data] private[chisel3] (gen: => T,
     // Reconstruct the resolvedDirection (in Aggregate.bind), since it's not stored.
     // It may not be exactly equal to that value, but the results are the same.
     val reconstructedResolvedDirection = direction match {
-      case ActualDirection.Input  => SpecifiedDirection.Input
+      case ActualDirection.Input => SpecifiedDirection.Input
       case ActualDirection.Output => SpecifiedDirection.Output
       case ActualDirection.Bidirectional.Default | ActualDirection.Unspecified =>
         SpecifiedDirection.Unspecified
       case ActualDirection.Bidirectional.Flipped => SpecifiedDirection.Flip
-      case ActualDirection.Empty                 => SpecifiedDirection.Unspecified
-      case dir                                   => throwException(s"Unexpected directionality: $dir")
+      case ActualDirection.Empty => SpecifiedDirection.Unspecified
+      case dir => throwException(s"Unexpected directionality: $dir")
     }
     // TODO port technically isn't directly child of this data structure, but the result of some
     // muxes / demuxes. However, this does make access consistent with the top-level bindings.
@@ -1254,8 +1254,8 @@ abstract class Bundle extends Record {
   override def className: String = try {
     this.getClass.getSimpleName match {
       case name if name.startsWith("$anon$") => "AnonymousBundle" // fallback for anonymous Bundle case
-      case ""                                => "AnonymousBundle" // ditto, but on other platforms
-      case name                              => name
+      case "" => "AnonymousBundle" // ditto, but on other platforms
+      case name => name
     }
   } catch {
     // This happens if you have nested objects which your class is defined in
diff --git a/core/src/main/scala/chisel3/BitsImpl.scala b/core/src/main/scala/chisel3/BitsImpl.scala
index cda6eb13d29..79621f1ebf7 100644
--- a/core/src/main/scala/chisel3/BitsImpl.scala
+++ b/core/src/main/scala/chisel3/BitsImpl.scala
@@ -43,7 +43,7 @@ private[chisel3] trait BitsImpl extends Element { self: Bits =>
   protected def _headImpl(n: Int)(implicit sourceInfo: SourceInfo): UInt = {
     this.width match {
       case KnownWidth(x) => require(x >= n, s"Can't head($n) for width $x < $n")
-      case UnknownWidth  => ()
+      case UnknownWidth => ()
     }
     binop(sourceInfo, UInt(Width(n)), HeadOp, n)
   }
@@ -62,7 +62,7 @@ private[chisel3] trait BitsImpl extends Element { self: Bits =>
       widthOption match {
         case Some(w) if w == 0 => Builder.error(s"Cannot extract from zero-width")
         case Some(w) if x >= w => Builder.error(s"High index $x is out of range [0, ${w - 1}]")
-        case _                 =>
+        case _ =>
       }
 
       pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
@@ -125,7 +125,7 @@ private[chisel3] trait BitsImpl extends Element { self: Bits =>
           case Some(w) if w == 0 => Builder.error(s"Cannot extract from zero-width")
           case Some(w) if y >= w => Builder.error(s"High and low indices $x and $y are both out of range [0, ${w - 1}]")
           case Some(w) if x >= w => Builder.error(s"High index $x is out of range [0, ${w - 1}]")
-          case _                 =>
+          case _ =>
         }
       }
 
@@ -169,8 +169,8 @@ private[chisel3] trait BitsImpl extends Element { self: Bits =>
 
   protected def _padImpl(that: Int)(implicit sourceInfo: SourceInfo): this.type = this.width match {
     case KnownWidth(w) if w >= that => this
-    case _ if this.isLit            => this._padLit(that)
-    case _                          => binop(sourceInfo, cloneTypeWidth(this.width.max(Width(that))), PadOp, that)
+    case _ if this.isLit => this._padLit(that)
+    case _ => binop(sourceInfo, cloneTypeWidth(this.width.max(Width(that))), PadOp, that)
   }
 
   protected def _impl_unary_~(implicit sourceInfo: SourceInfo): Bits
@@ -195,7 +195,7 @@ private[chisel3] trait BitsImpl extends Element { self: Bits =>
   protected def _asBoolImpl(implicit sourceInfo: SourceInfo): Bool = {
     this.width match {
       case KnownWidth(1) => this(0)
-      case _             => throwException(s"can't covert ${this.getClass.getSimpleName}${this.width} to Bool")
+      case _ => throwException(s"can't covert ${this.getClass.getSimpleName}${this.width} to Bool")
     }
   }
 
@@ -218,7 +218,7 @@ private[chisel3] trait UIntImpl extends BitsImpl with Num[UInt] { self: UInt =>
   override def toString: String = {
     litOption match {
       case Some(value) => s"UInt$width($value)"
-      case _           => stringAccessor(s"UInt$width")
+      case _ => stringAccessor(s"UInt$width")
     }
   }
 
@@ -328,18 +328,18 @@ private[chisel3] trait UIntImpl extends BitsImpl with Num[UInt] { self: UInt =>
     binop(sourceInfo, UInt(this.width), DynamicShiftRightOp, that)
 
   protected def _rotateLeftImpl(n: Int)(implicit sourceInfo: SourceInfo): UInt = width match {
-    case _ if (n == 0)             => this
+    case _ if (n == 0) => this
     case KnownWidth(w) if (w <= 1) => this
-    case KnownWidth(w) if n >= w   => do_rotateLeft(n % w)
-    case _ if (n < 0)              => do_rotateRight(-n)
-    case _                         => tail(n) ## head(n)
+    case KnownWidth(w) if n >= w => do_rotateLeft(n % w)
+    case _ if (n < 0) => do_rotateRight(-n)
+    case _ => tail(n) ## head(n)
   }
 
   protected def _rotateRightImpl(n: Int)(implicit sourceInfo: SourceInfo): UInt = width match {
-    case _ if (n <= 0)             => do_rotateLeft(-n)
+    case _ if (n <= 0) => do_rotateLeft(-n)
     case KnownWidth(w) if (w <= 1) => this
-    case KnownWidth(w) if n >= w   => do_rotateRight(n % w)
-    case _                         => this(n - 1, 0) ## (this >> n)
+    case KnownWidth(w) if n >= w => do_rotateRight(n % w)
+    case _ => this(n - 1, 0) ## (this >> n)
   }
 
   private def dynamicShift(
@@ -365,7 +365,7 @@ private[chisel3] trait UIntImpl extends BitsImpl with Num[UInt] { self: UInt =>
 
   protected def _zextImpl(implicit sourceInfo: SourceInfo): SInt = this.litOption match {
     case Some(value) => SInt.Lit(value, this.width + 1)
-    case None        => pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref))
+    case None => pushOp(DefPrim(sourceInfo, SInt(width + 1), ConvertOp, ref))
   }
 
   override protected def _asSIntImpl(implicit sourceInfo: SourceInfo): SInt = this.litOption match {
@@ -399,7 +399,7 @@ private[chisel3] trait SIntImpl extends BitsImpl with Num[SInt] { self: SInt =>
   override def toString: String = {
     litOption match {
       case Some(value) => s"SInt$width($value)"
-      case _           => stringAccessor(s"SInt$width")
+      case _ => stringAccessor(s"SInt$width")
     }
   }
 
@@ -595,7 +595,7 @@ private[chisel3] trait BoolImpl extends UIntImpl { self: Bool =>
   override def toString: String = {
     litToBooleanOption match {
       case Some(value) => s"Bool($value)"
-      case _           => stringAccessor("Bool")
+      case _ => stringAccessor("Bool")
     }
   }
 
@@ -608,7 +608,7 @@ private[chisel3] trait BoolImpl extends UIntImpl { self: Bool =>
   def litToBooleanOption: Option[Boolean] = litOption.map {
     case intVal if intVal == 1 => true
     case intVal if intVal == 0 => false
-    case intVal                => throwException(s"Boolean with unexpected literal value $intVal")
+    case intVal => throwException(s"Boolean with unexpected literal value $intVal")
   }
 
   /** Convert to a [[scala.Boolean]] */
diff --git a/core/src/main/scala/chisel3/ChiselEnumImpl.scala b/core/src/main/scala/chisel3/ChiselEnumImpl.scala
index a3782dbf945..991d49f368c 100644
--- a/core/src/main/scala/chisel3/ChiselEnumImpl.scala
+++ b/core/src/main/scala/chisel3/ChiselEnumImpl.scala
@@ -24,7 +24,7 @@ private[chisel3] abstract class EnumTypeImpl(private[chisel3] val factory: Chise
       case Some(value) =>
         factory.nameOfValue(value) match {
           case Some(name) => s"${factory.getClass.getSimpleName.init}($value=$name)"
-          case None       => stringAccessor(s"${factory.getClass.getSimpleName.init}($value=(invalid))")
+          case None => stringAccessor(s"${factory.getClass.getSimpleName.init}($value=(invalid))")
         }
       case _ => stringAccessor(s"${factory.getClass.getSimpleName.init}")
     }
@@ -162,9 +162,9 @@ private[chisel3] abstract class EnumTypeImpl(private[chisel3] val factory: Chise
       }
     case b: Record =>
       b.elements.collect {
-        case (name, e: EnumType) if this.typeEquivalent(e)              => Seq(Seq(name))
+        case (name, e: EnumType) if this.typeEquivalent(e) => Seq(Seq(name))
         case (name, v: Vec[_]) if this.typeEquivalent(v.sample_element) => Seq(Seq(name))
-        case (name, b2: Bundle)                                         => enumFields(b2).map(name +: _)
+        case (name, b2: Bundle) => enumFields(b2).map(name +: _)
       }.flatten.toSeq
   }
 
@@ -178,7 +178,7 @@ private[chisel3] abstract class EnumTypeImpl(private[chisel3] val factory: Chise
       case Some(ChildBinding(parent)) =>
         outerMostVec(parent) match {
           case outer @ Some(_) => outer
-          case None            => currentVecOpt
+          case None => currentVecOpt
         }
       case _ => currentVecOpt
     }
@@ -187,7 +187,7 @@ private[chisel3] abstract class EnumTypeImpl(private[chisel3] val factory: Chise
   private def annotateEnum(): Unit = {
     val anno = outerMostVec() match {
       case Some(v) => EnumVecChiselAnnotation(v, enumTypeName, enumFields(v))
-      case None    => EnumComponentChiselAnnotation(this, enumTypeName)
+      case None => EnumComponentChiselAnnotation(this, enumTypeName)
     }
 
     // Enum annotations are added every time a ChiselEnum is bound
@@ -310,7 +310,7 @@ private[chisel3] trait ChiselEnumImpl { self: ChiselEnum =>
     if (n.litOption.isDefined) {
       enumInstances.find(_.litValue == n.litValue) match {
         case Some(result) => result
-        case None         => throwException(s"${n.litValue} is not a valid value for $enumTypeName")
+        case None => throwException(s"${n.litValue} is not a valid value for $enumTypeName")
       }
     } else if (!n.isWidthKnown) {
       throwException(s"Non-literal UInts being cast to $enumTypeName must have a defined width")
diff --git a/core/src/main/scala/chisel3/ClockImpl.scala b/core/src/main/scala/chisel3/ClockImpl.scala
index afd8341b965..cf4e26b8d0e 100644
--- a/core/src/main/scala/chisel3/ClockImpl.scala
+++ b/core/src/main/scala/chisel3/ClockImpl.scala
@@ -18,7 +18,7 @@ private[chisel3] trait ClockImpl extends Element {
   override def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     that match {
       case _: Clock | DontCare => super.connect(that)(sourceInfo)
-      case _                   => super.badConnect(that)(sourceInfo)
+      case _ => super.badConnect(that)(sourceInfo)
     }
 
   override def litOption: Option[BigInt] = None
diff --git a/core/src/main/scala/chisel3/DataImpl.scala b/core/src/main/scala/chisel3/DataImpl.scala
index 84cf7c13407..d366775fb32 100644
--- a/core/src/main/scala/chisel3/DataImpl.scala
+++ b/core/src/main/scala/chisel3/DataImpl.scala
@@ -41,17 +41,17 @@ object SpecifiedDirection {
 
   private[chisel3] def fromByte(b: Byte): SpecifiedDirection = b match {
     case Unspecified.value => Unspecified
-    case Output.value      => Output
-    case Input.value       => Input
-    case Flip.value        => Flip
-    case _                 => throw new RuntimeException(s"Unexpected SpecifiedDirection value $b")
+    case Output.value => Output
+    case Input.value => Input
+    case Flip.value => Flip
+    case _ => throw new RuntimeException(s"Unexpected SpecifiedDirection value $b")
   }
 
   def flip(dir: SpecifiedDirection): SpecifiedDirection = dir match {
     case Unspecified => Flip
-    case Flip        => Unspecified
-    case Output      => Input
-    case Input       => Output
+    case Flip => Unspecified
+    case Output => Input
+    case Input => Output
   }
 
   /** Returns the effective SpecifiedDirection of this node given the parent's effective SpecifiedDirection
@@ -59,10 +59,10 @@ object SpecifiedDirection {
     */
   def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection): SpecifiedDirection =
     (parentDirection, thisDirection) match {
-      case (SpecifiedDirection.Output, _)                  => SpecifiedDirection.Output
-      case (SpecifiedDirection.Input, _)                   => SpecifiedDirection.Input
+      case (SpecifiedDirection.Output, _) => SpecifiedDirection.Output
+      case (SpecifiedDirection.Input, _) => SpecifiedDirection.Input
       case (SpecifiedDirection.Unspecified, thisDirection) => thisDirection
-      case (SpecifiedDirection.Flip, thisDirection)        => SpecifiedDirection.flip(thisDirection)
+      case (SpecifiedDirection.Flip, thisDirection) => SpecifiedDirection.flip(thisDirection)
     }
 
   private[chisel3] def specifiedDirection[T <: Data](
@@ -134,13 +134,13 @@ object ActualDirection {
   }
 
   private[chisel3] def fromByte(b: Byte): ActualDirection = b match {
-    case Empty.value                 => Empty
-    case Unspecified.value           => Unspecified
-    case Output.value                => Output
-    case Input.value                 => Input
+    case Empty.value => Empty
+    case Unspecified.value => Unspecified
+    case Output.value => Output
+    case Input.value => Input
     case Bidirectional.Default.value => Bidirectional.Default
     case Bidirectional.Flipped.value => Bidirectional.Flipped
-    case _                           => throwException(s"Unexpected ActualDirection value $b")
+    case _ => throwException(s"Unexpected ActualDirection value $b")
   }
 
   /** Converts a `SpecifiedDirection` to an `ActualDirection`
@@ -149,7 +149,7 @@ object ActualDirection {
     */
   def fromSpecified(direction: SpecifiedDirection): ActualDirection = direction match {
     case SpecifiedDirection.Output | SpecifiedDirection.Unspecified => ActualDirection.Output
-    case SpecifiedDirection.Input | SpecifiedDirection.Flip         => ActualDirection.Input
+    case SpecifiedDirection.Input | SpecifiedDirection.Flip => ActualDirection.Input
   }
 
   /** Determine the actual binding of a container given directions of its children.
@@ -162,7 +162,7 @@ object ActualDirection {
     if (childDirections == Set()) { // Sadly, Scala can't do set matching
       ActualDirection.fromSpecified(containerDirection) match {
         case ActualDirection.Unspecified => Some(ActualDirection.Empty) // empty direction if relative / no direction
-        case dir                         => Some(dir) // use assigned direction if specified
+        case dir => Some(dir) // use assigned direction if specified
       }
     } else if (childDirections == Set(ActualDirection.Unspecified)) {
       Some(ActualDirection.Unspecified)
@@ -182,8 +182,8 @@ object ActualDirection {
     ) {
       containerDirection match {
         case SpecifiedDirection.Unspecified => Some(ActualDirection.Bidirectional(ActualDirection.Default))
-        case SpecifiedDirection.Flip        => Some(ActualDirection.Bidirectional(ActualDirection.Flipped))
-        case _                              => throw new RuntimeException("Unexpected forced Input / Output")
+        case SpecifiedDirection.Flip => Some(ActualDirection.Bidirectional(ActualDirection.Flipped))
+        case _ => throw new RuntimeException("Unexpected forced Input / Output")
       }
     } else {
       None
@@ -339,7 +339,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
   private[chisel3] def flatten: IndexedSeq[Element] = {
     this match {
       case elt: Aggregate => elt.elementsIterator.toIndexedSeq.flatMap { _.flatten }
-      case elt: Element   => IndexedSeq(elt)
+      case elt: Element => IndexedSeq(elt)
       case elt => throwException(s"Cannot flatten type ${elt.getClass}")
     }
   }
@@ -365,17 +365,17 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
     topBindingOpt match {
       // Ports are special in that the autoSeed will keep the first name, not the last name
       case Some(PortBinding(m)) if hasSeed && Builder.currentModule.contains(m) => this
-      case _                                                                    => super.autoSeed(name)
+      case _ => super.autoSeed(name)
     }
   }
 
   // probeInfo only exists if this is a probe type
-  private var _probeInfoVar:      ProbeInfo = null
+  private var _probeInfoVar: ProbeInfo = null
   private[chisel3] def probeInfo: Option[ProbeInfo] = Option(_probeInfoVar)
   private[chisel3] def probeInfo_=(probeInfo: Option[ProbeInfo]) = _probeInfoVar = probeInfo.getOrElse(null)
 
   // If this Data is constant, it must hold a constant value
-  private var _isConst:         Boolean = false
+  private var _isConst: Boolean = false
   private[chisel3] def isConst: Boolean = _isConst
   private[chisel3] def isConst_=(isConst: Boolean) = _isConst = isConst
 
@@ -385,7 +385,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
 
   // User-specified direction, local at this node only.
   // Note that the actual direction of this node can differ from child and parent specifiedDirection.
-  private var _specifiedDirection:         Byte = SpecifiedDirection.Unspecified.value
+  private var _specifiedDirection: Byte = SpecifiedDirection.Unspecified.value
   private[chisel3] def specifiedDirection: SpecifiedDirection = SpecifiedDirection.fromByte(_specifiedDirection)
   private[chisel3] def specifiedDirection_=(direction: SpecifiedDirection) = {
     _specifiedDirection = direction.value
@@ -410,9 +410,9 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
     */
   private[chisel3] def _assignCompatibilityExplicitDirection: Unit = {
     (this, specifiedDirection) match {
-      case (_: Analog, _)                                            => // nothing to do
-      case (_, SpecifiedDirection.Unspecified)                       => specifiedDirection = SpecifiedDirection.Output
-      case (_, SpecifiedDirection.Flip)                              => specifiedDirection = SpecifiedDirection.Input
+      case (_: Analog, _) => // nothing to do
+      case (_, SpecifiedDirection.Unspecified) => specifiedDirection = SpecifiedDirection.Output
+      case (_, SpecifiedDirection.Flip) => specifiedDirection = SpecifiedDirection.Input
       case (_, SpecifiedDirection.Input | SpecifiedDirection.Output) => // nothing to do
     }
   }
@@ -421,7 +421,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
   // This information is supplemental (more than is necessary to generate FIRRTL) and is used to
   // perform checks in Chisel, where more informative error messages are possible.
   private var _bindingVar: Binding = null // using nullable var for better memory usage
-  private def _binding:    Option[Binding] = Option(_bindingVar)
+  private def _binding: Option[Binding] = Option(_bindingVar)
   // Only valid after node is bound (synthesizable), crashes otherwise
   protected[chisel3] def binding: Option[Binding] = _binding
   protected def binding_=(target: Binding): Unit = {
@@ -444,7 +444,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
   private[chisel3] def topBindingOpt: Option[TopBinding] = _binding.flatMap {
     case ChildBinding(parent) => parent.topBindingOpt
     case bindingVal: TopBinding => Some(bindingVal)
-    case SampleElementBinding(parent)                     => parent.topBindingOpt
+    case SampleElementBinding(parent) => parent.topBindingOpt
     case (_: MemTypeBinding[_] | _: FirrtlMemTypeBinding) => None
   }
 
@@ -461,7 +461,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
   private[chisel3] def maybeAddToParentIds(target: Binding): Unit = {
     // ConstrainedBinding means the thing actually corresponds to a Module, no need to add to _ids otherwise
     target match {
-      case c: SecretPortBinding  => // secret ports are handled differently, parent's don't need to know about that
+      case c: SecretPortBinding => // secret ports are handled differently, parent's don't need to know about that
       case c: ConstrainedBinding => _parent.foreach(_.addId(this))
       case _ =>
     }
@@ -500,17 +500,17 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
   // Data-subtype.
   private[chisel3] def _bindingToString(topBindingOpt: TopBinding): String =
     topBindingOpt match {
-      case OpBinding(_, _)           => "OpResult"
-      case MemoryPortBinding(_, _)   => "MemPort"
-      case PortBinding(_)            => "IO"
-      case SecretPortBinding(_)      => "IO"
-      case RegBinding(_, _)          => "Reg"
-      case WireBinding(_, _)         => "Wire"
-      case DontCareBinding()         => "(DontCare)"
+      case OpBinding(_, _) => "OpResult"
+      case MemoryPortBinding(_, _) => "MemPort"
+      case PortBinding(_) => "IO"
+      case SecretPortBinding(_) => "IO"
+      case RegBinding(_, _) => "Reg"
+      case WireBinding(_, _) => "Wire"
+      case DontCareBinding() => "(DontCare)"
       case ElementLitBinding(litArg) => "(unhandled literal)"
-      case BundleLitBinding(litMap)  => "(unhandled bundle literal)"
-      case VecLitBinding(litMap)     => "(unhandled vec literal)"
-      case _                         => ""
+      case BundleLitBinding(litMap) => "(unhandled bundle literal)"
+      case VecLitBinding(litMap) => "(unhandled vec literal)"
+      case _ => ""
     }
 
   private[chisel3] def earlyName: String = Arg.earlyLocalName(this)
@@ -567,7 +567,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
       case (_: ReadOnlyBinding, _: ReadOnlyBinding) => throwException(s"Both $this and $that are read-only")
       // DontCare cannot be a sink (LHS)
       case (_: DontCareBinding, _) => throw BiConnect.DontCareCantBeSink
-      case _                       => // fine
+      case _ => // fine
     }
     try {
       BiConnect.connect(sourceInfo, this, that, Builder.referenceUserModule)
@@ -639,7 +639,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
               if (r1._elements.size >= r2._elements.size) (r1, r2, "Left") else (r2, r1, "Right")
             larger._elements.flatMap { case (name, data) =>
               val recurse = smaller._elements.get(name) match {
-                case None        => Some(s": Dangling field on $msg")
+                case None => Some(s": Dangling field on $msg")
                 case Some(data2) => rec(data, data2)
               }
               recurse.map("." + name + _)
@@ -685,11 +685,11 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
       case Some(pb: PortBinding)
           if mod.flatMap(Builder.retrieveParent(_, Builder.currentModule.get)) == Builder.currentModule =>
         true
-      case Some(ViewBinding(target, _))           => target.isVisibleFromModule
+      case Some(ViewBinding(target, _)) => target.isVisibleFromModule
       case Some(AggregateViewBinding(mapping, _)) => mapping.values.forall(_.isVisibleFromModule)
-      case Some(pb: SecretPortBinding)            => true // Ignore secret to not require visibility
-      case Some(_: UnconstrainedBinding)          => true
-      case _                                      => false
+      case Some(pb: SecretPortBinding) => true // Ignore secret to not require visibility
+      case Some(_: UnconstrainedBinding) => true
+      case _ => false
     }
   }
   private[chisel3] def visibleFromBlock: Option[SourceInfo] = MonoConnect.checkBlockVisibility(this)
@@ -718,7 +718,7 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
         val writability = wr1.combine(wr2)
         writability.reportIfReadOnly(target2.lref)(Wire(chiselTypeOf(target2)).lref)
       case Some(binding: TopBinding) => Node(this)
-      case opt                       => throwException(s"internal error: unknown binding $opt in generating LHS ref")
+      case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref")
     }
   }
 
@@ -749,12 +749,12 @@ private[chisel3] trait DataImpl extends HasId with NamedComponent { self: Data =
       case Some(BundleLitBinding(litMap)) =>
         litMap.get(this) match {
           case Some(litArg) => litArg
-          case _            => materializeWire(true) // FIXME FIRRTL doesn't have Bundle literal expressions
+          case _ => materializeWire(true) // FIXME FIRRTL doesn't have Bundle literal expressions
         }
       case Some(VecLitBinding(litMap)) =>
         litMap.get(this) match {
           case Some(litArg) => litArg
-          case _            => materializeWire(true) // FIXME FIRRTL doesn't have Vec literal expressions
+          case _ => materializeWire(true) // FIXME FIRRTL doesn't have Vec literal expressions
         }
       case Some(DontCareBinding()) =>
         materializeWire() // FIXME FIRRTL doesn't have a DontCare expression so materialize a Wire
@@ -963,9 +963,9 @@ private[chisel3] trait ObjectDataImpl {
         */
       def matchingZipOfChildren(left: Option[Data], right: Option[Data]): Seq[(Option[Data], Option[Data])] =
         (left, right) match {
-          case (None, None)                            => Nil
+          case (None, None) => Nil
           case (lOpt, rOpt) if isDifferent(lOpt, rOpt) => Nil
-          case (lOpt, rOpt) if isProbe(lOpt, rOpt)     => Nil
+          case (lOpt, rOpt) if isProbe(lOpt, rOpt) => Nil
           case (lOpt: Option[Vec[Data] @unchecked], rOpt: Option[Vec[Data] @unchecked]) if isVec(lOpt, rOpt) =>
             (0 until (lOpt.size.max(rOpt.size))).map { i => (lOpt.grab(i), rOpt.grab(i)) }
           case (lOpt: Option[Record @unchecked], rOpt: Option[Record @unchecked]) if isRecord(lOpt, rOpt) =>
@@ -999,12 +999,12 @@ private[chisel3] trait ObjectDataImpl {
       */
     def ===(rhs: T): Bool = {
       (lhs, rhs) match {
-        case (thiz: UInt, that: UInt)             => thiz === that
-        case (thiz: SInt, that: SInt)             => thiz === that
+        case (thiz: UInt, that: UInt) => thiz === that
+        case (thiz: SInt, that: SInt) => thiz === that
         case (thiz: AsyncReset, that: AsyncReset) => thiz.asBool === that.asBool
-        case (thiz: Reset, that: Reset)           => thiz.asBool === that.asBool
-        case (thiz: EnumType, that: EnumType)     => thiz === that
-        case (thiz: Clock, that: Clock)           => thiz.asUInt === that.asUInt
+        case (thiz: Reset, that: Reset) => thiz.asBool === that.asBool
+        case (thiz: EnumType, that: EnumType) => thiz === that
+        case (thiz: Clock, that: Clock) => thiz.asUInt === that.asUInt
         case (thiz: Vec[_], that: Vec[_]) =>
           if (thiz.length != that.length) {
             throwException(s"Cannot compare Vecs $thiz and $that: Vec sizes differ")
diff --git a/core/src/main/scala/chisel3/Element.scala b/core/src/main/scala/chisel3/Element.scala
index 7385e947897..4ca5c1ee630 100644
--- a/core/src/main/scala/chisel3/Element.scala
+++ b/core/src/main/scala/chisel3/Element.scala
@@ -31,12 +31,12 @@ abstract class Element extends Data {
     case Some(BundleLitBinding(litMap)) =>
       litMap.get(this) match {
         case Some(litArg) => Some(ElementLitBinding(litArg))
-        case _            => Some(DontCareBinding())
+        case _ => Some(DontCareBinding())
       }
     case Some(VecLitBinding(litMap)) =>
       litMap.get(this) match {
         case Some(litArg) => Some(ElementLitBinding(litArg))
-        case _            => Some(DontCareBinding())
+        case _ => Some(DontCareBinding())
       }
     // TODO Do we even need this? Looking up things in the AggregateViewBinding is fine
     case Some(b @ AggregateViewBinding(viewMap, _)) =>
@@ -73,6 +73,6 @@ abstract class Element extends Data {
 
   override def containsAFlipped = specifiedDirection match {
     case SpecifiedDirection.Flip | SpecifiedDirection.Input => true
-    case _                                                  => false
+    case _ => false
   }
 }
diff --git a/core/src/main/scala/chisel3/IO.scala b/core/src/main/scala/chisel3/IO.scala
index 9a997684132..c0594d9ab86 100644
--- a/core/src/main/scala/chisel3/IO.scala
+++ b/core/src/main/scala/chisel3/IO.scala
@@ -86,10 +86,10 @@ object FlatIO {
     def coerceDirection(d: Data): Data = {
       import chisel3.{SpecifiedDirection => SD}
       specifiedDirectionOf(gen) match {
-        case SD.Flip   => Flipped(d)
-        case SD.Input  => Input(d)
+        case SD.Flip => Flipped(d)
+        case SD.Input => Input(d)
         case SD.Output => Output(d)
-        case _         => d
+        case _ => d
       }
     }
 
@@ -97,7 +97,7 @@ object FlatIO {
     gen match {
       case d if hasProbeTypeModifier(d) => IO(d)
       case _:      Element => IO(gen)
-      case _:      Vec[_]  => IO(gen)
+      case _:      Vec[_] => IO(gen)
       case record: R =>
         val ports: Seq[Data] =
           record._elements.toSeq.reverse.map { case (name, data) =>
diff --git a/core/src/main/scala/chisel3/Layer.scala b/core/src/main/scala/chisel3/Layer.scala
index df297fdeed4..c632c4201a1 100644
--- a/core/src/main/scala/chisel3/Layer.scala
+++ b/core/src/main/scala/chisel3/Layer.scala
@@ -109,9 +109,9 @@ object layer {
     private[chisel3] def name: String = simpleClassName(this.getClass())
 
     private[chisel3] val fullName: String = parent match {
-      case null       => "<root>"
+      case null => "<root>"
       case Layer.Root => name
-      case _          => s"${parent.fullName}.$name"
+      case _ => s"${parent.fullName}.$name"
     }
 
     /** The output directory of this layer.
@@ -126,19 +126,19 @@ object layer {
       */
     private[chisel3] final def outputDir: Option[Path] = {
       config match {
-        case LayerConfig.Root   => None
+        case LayerConfig.Root => None
         case LayerConfig.Inline => None
         case LayerConfig.Extract(outputDirBehavior) =>
           outputDirBehavior match {
-            case NoOutputDir          => None
+            case NoOutputDir => None
             case CustomOutputDir(dir) => Some(dir)
-            case DefaultOutputDir     => Some(defaultOutputDir)
+            case DefaultOutputDir => Some(defaultOutputDir)
           }
       }
     }
 
     private final def defaultOutputDir: Path = parentOutputDir match {
-      case None      => Paths.get(name)
+      case None => Paths.get(name)
       case Some(dir) => dir.resolve(name)
     }
 
@@ -146,17 +146,17 @@ object layer {
       @tailrec
       def outputDirOf(layer: Layer): Option[Path] = layer.config match {
         case LayerConfig.Extract(_) => layer.outputDir
-        case LayerConfig.Inline     => outputDirOf(layer.parent)
-        case LayerConfig.Root       => None
+        case LayerConfig.Inline => outputDirOf(layer.parent)
+        case LayerConfig.Root => None
       }
       outputDirOf(parent)
     }
 
     @tailrec
     final private[chisel3] def canWriteTo(that: Layer): Boolean = that match {
-      case null              => false
+      case null => false
       case _ if this == that => true
-      case _                 => this.canWriteTo(that.parent)
+      case _ => this.canWriteTo(that.parent)
     }
 
     /** Return a list containg this layer and all its parents, excluding the root
@@ -167,7 +167,7 @@ object layer {
     private[chisel3] def layerSeq: List[Layer] = {
       def rec(current: Layer, acc: List[Layer]): List[Layer] = current match {
         case Layer.root => acc
-        case _          => rec(current.parent, current :: acc)
+        case _ => rec(current.parent, current :: acc)
       }
       rec(this, Nil)
     }
diff --git a/core/src/main/scala/chisel3/ModuleImpl.scala b/core/src/main/scala/chisel3/ModuleImpl.scala
index 30b220148a1..dbf531798a7 100644
--- a/core/src/main/scala/chisel3/ModuleImpl.scala
+++ b/core/src/main/scala/chisel3/ModuleImpl.scala
@@ -48,7 +48,7 @@ private[chisel3] trait ObjectModuleImpl {
         case DefClass(_, name, _, _) =>
           Builder.referenceUserContainer match {
             case rm:  RawModule => rm.addCommand(DefObject(sourceInfo, module, name))
-            case cls: Class     => cls.addCommand(DefObject(sourceInfo, module, name))
+            case cls: Class => cls.addCommand(DefObject(sourceInfo, module, name))
           }
         case _ => pushCommand(DefInstance(sourceInfo, module, component.ports))
       }
@@ -158,7 +158,7 @@ private[chisel3] trait ObjectModuleImpl {
     */
   def disableOption(implicit sourceInfo: SourceInfo): Option[Disable] = {
     Builder.currentDisable match {
-      case Disable.Never       => None
+      case Disable.Never => None
       case Disable.BeforeReset => hasBeenReset.map(x => autoNameRecursively("disable")(!x))
     }
   }
@@ -281,8 +281,8 @@ private[chisel3] trait ModuleImpl extends RawModule with ImplicitClock with Impl
         val inferReset = (_parent.isDefined || Builder.inDefinition)
         if (inferReset) Reset() else Bool()
       }
-      case Module.ResetType.Uninferred   => Reset()
-      case Module.ResetType.Synchronous  => Bool()
+      case Module.ResetType.Uninferred => Reset()
+      case Module.ResetType.Synchronous => Bool()
       case Module.ResetType.Asynchronous => AsyncReset()
     }
   }
@@ -438,7 +438,7 @@ package experimental {
     _parent.foreach(_.addId(this))
 
     // Set if the returned top-level module of a nested call to the Chisel Builder, see Definition.apply
-    private var _circuitVar:       BaseModule = null // using nullable var for better memory usage
+    private var _circuitVar: BaseModule = null // using nullable var for better memory usage
     private[chisel3] def _circuit: Option[BaseModule] = Option(_circuitVar)
     private[chisel3] def _circuit_=(target: Option[BaseModule]): Unit = {
       _circuitVar = target.getOrElse(null)
@@ -477,8 +477,8 @@ package experimental {
     final val definitionIdentifier = _definitionIdentifier
 
     // Modules that contain bodies should override this.
-    protected def hasBody:        Boolean = false
-    protected val _body:          Block = if (hasBody) new Block(_sourceInfo) else null
+    protected def hasBody: Boolean = false
+    protected val _body: Block = if (hasBody) new Block(_sourceInfo) else null
     private[chisel3] def getBody: Option[Block] = Some(_body)
 
     // Current block at point of creation.
@@ -586,7 +586,7 @@ package experimental {
     // Returns the last id contained within a Module
     private[chisel3] def _lastId: Long = _ids.last match {
       case mod: BaseModule => mod._lastId
-      case agg: Aggregate  =>
+      case agg: Aggregate =>
         // Ideally we could just take .last._id, but Records store their elements in reverse order
         getRecursiveFields.lazily(agg, "").map(_._1._id).max
       case other => other._id
@@ -762,7 +762,7 @@ package experimental {
     final def toAbsoluteTarget: IsModule = {
       _parent match {
         case Some(parent) => parent.toAbsoluteTarget.instOf(this.instanceName, name)
-        case None         =>
+        case None =>
           // FIXME Special handling for Views - evidence of "weirdness" of .toAbsoluteTarget
           // In theory, .toAbsoluteTarget should not be necessary, .toTarget combined with the
           // target disambiguation in FIRRTL's deduplication transform should ensure that .toTarget
@@ -938,7 +938,7 @@ package experimental {
       if (_parent == None) name
       else
         _component match {
-          case None    => getRef.name
+          case None => getRef.name
           case Some(c) => getRef.fullName(c)
         }
 
diff --git a/core/src/main/scala/chisel3/Printable.scala b/core/src/main/scala/chisel3/Printable.scala
index 2b187dbdd7f..5e47e836b07 100644
--- a/core/src/main/scala/chisel3/Printable.scala
+++ b/core/src/main/scala/chisel3/Printable.scala
@@ -71,8 +71,8 @@ object Printable {
     def carrotAt(index: Int) = (" " * index) + "^"
     def errorMsg(index: Int) =
       s"""|    fmt = "$fmt"
-          |           ${carrotAt(index)}
-          |    data = ${data.mkString(", ")}""".stripMargin
+        |           ${carrotAt(index)}
+        |    data = ${data.mkString(", ")}""".stripMargin
 
     def checkArg(i: Int): Unit = {
       if (!args.hasNext) {
@@ -143,10 +143,10 @@ object Printable {
     def getData(x: Printable): Seq[Data] = {
       x match {
         case y: FirrtlFormat => Seq(y.bits)
-        case Name(d)       => Seq(d)
-        case FullName(d)   => Seq(d)
+        case Name(d) => Seq(d)
+        case FullName(d) => Seq(d)
         case Printables(p) => p.flatMap(getData(_)).toSeq
-        case _             => Seq() // Handles subtypes PString and Percent
+        case _ => Seq() // Handles subtypes PString and Percent
       }
     }
     getData(message).foreach(_.requireVisible())
@@ -199,7 +199,7 @@ object FirrtlFormat {
       case "x" => Hexadecimal(bits)
       case "b" => Binary(bits)
       case "c" => Character(bits)
-      case c   => throw new Exception(s"Illegal format specifier '$c'!")
+      case c => throw new Exception(s"Illegal format specifier '$c'!")
     }
   }
 }
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index f2234623a40..8545060a3bd 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -169,15 +169,15 @@ abstract class RawModule extends BaseModule {
     * @param id The id to finalize.
     */
   private def nameId(id: HasId) = id match {
-    case id: ModuleClone[_]   => id.setRefAndPortsRef(_namespace) // special handling
+    case id: ModuleClone[_] => id.setRefAndPortsRef(_namespace) // special handling
     case id: InstanceClone[_] => id.setAsInstanceRef()
-    case id: BaseModule       => id.forceName(default = id.desiredName, _namespace)
-    case id: MemBase[_]       => id.forceName(default = "MEM", _namespace)
-    case id: stop.Stop        => id.forceName(default = "stop", _namespace)
-    case id: assert.Assert    => id.forceName(default = "assert", _namespace)
-    case id: assume.Assume    => id.forceName(default = "assume", _namespace)
-    case id: cover.Cover      => id.forceName(default = "cover", _namespace)
-    case id: printf.Printf    => id.forceName(default = "printf", _namespace)
+    case id: BaseModule => id.forceName(default = id.desiredName, _namespace)
+    case id: MemBase[_] => id.forceName(default = "MEM", _namespace)
+    case id: stop.Stop => id.forceName(default = "stop", _namespace)
+    case id: assert.Assert => id.forceName(default = "assert", _namespace)
+    case id: assume.Assume => id.forceName(default = "assume", _namespace)
+    case id: cover.Cover => id.forceName(default = "cover", _namespace)
+    case id: printf.Printf => id.forceName(default = "printf", _namespace)
     case id: DynamicObject => {
       // Force name of the DynamicObject, and set its Property[ClassType] type's ref to the DynamicObject.
       // The type's ref can't be set upon instantiation, because the DynamicObject hasn't been named yet.
@@ -264,11 +264,11 @@ abstract class RawModule extends BaseModule {
 
     def computeConnection(left: Data, right: Data): Command = {
       (left.probeInfo.nonEmpty, right.probeInfo.nonEmpty) match {
-        case (true, true)                                 => ProbeDefine(si, left.lref, Node(right))
+        case (true, true) => ProbeDefine(si, left.lref, Node(right))
         case (true, false) if left.probeInfo.get.writable => ProbeDefine(si, left.lref, RWProbeExpr(Node(right)))
-        case (true, false)                                => ProbeDefine(si, left.lref, ProbeExpr(Node(right)))
-        case (false, true)                                => Connect(si, left.lref, ProbeRead(Node(right)))
-        case (false, false)                               =>
+        case (true, false) => ProbeDefine(si, left.lref, ProbeExpr(Node(right)))
+        case (false, true) => Connect(si, left.lref, ProbeRead(Node(right)))
+        case (false, false) =>
           // For non-probe, directly create Nodes for lhs, skipping visibility check to support BoringUtils.drive.
           (left, right) match {
             case (lhsOpaque: Record, rhsOpaque: Record)
diff --git a/core/src/main/scala/chisel3/When.scala b/core/src/main/scala/chisel3/When.scala
index 93676d94d3c..7b177b45e7d 100644
--- a/core/src/main/scala/chisel3/When.scala
+++ b/core/src/main/scala/chisel3/When.scala
@@ -104,9 +104,9 @@ final class WhenContext private[chisel3] (
       acc & !c()
     }
     scope match {
-      case Some(Scope.If)   => alt && cond()
+      case Some(Scope.If) => alt && cond()
       case Some(Scope.Else) => alt && !cond()
-      case None             => alt
+      case None => alt
     }
   }
 
diff --git a/core/src/main/scala/chisel3/Width.scala b/core/src/main/scala/chisel3/Width.scala
index 8e52a4a1e91..487e6a42d15 100644
--- a/core/src/main/scala/chisel3/Width.scala
+++ b/core/src/main/scala/chisel3/Width.scala
@@ -51,7 +51,7 @@ sealed case class KnownWidth private (value: Int) extends Width {
   def get:   Int = value
   def op(that: Width, f: (W, W) => W): Width = that match {
     case KnownWidth(x) => KnownWidth(f(value, x))
-    case _             => that
+    case _ => that
   }
   override def toString: String = s"<${value.toString}>"
   private[chisel3] def copy(value: Int = this.value) = new KnownWidth(value)
diff --git a/core/src/main/scala/chisel3/connectable/Alignment.scala b/core/src/main/scala/chisel3/connectable/Alignment.scala
index 022780bdce5..a8fcd0f020c 100644
--- a/core/src/main/scala/chisel3/connectable/Alignment.scala
+++ b/core/src/main/scala/chisel3/connectable/Alignment.scala
@@ -82,10 +82,10 @@ object Alignment {
   def isCoercing(member: Data): Boolean = {
     def recUp(x: Data): Boolean = x.binding match {
       case _ if isLocallyCoercing(x) => true
-      case None                      => false
-      case Some(t: TopBinding)       => false
-      case Some(ChildBinding(p))     => recUp(p)
-      case other                     => throw new Exception(s"Unexpected $other! $x, $member")
+      case None => false
+      case Some(t: TopBinding) => false
+      case Some(ChildBinding(p)) => recUp(p)
+      case other => throw new Exception(s"Unexpected $other! $x, $member")
     }
     def isLocallyCoercing(d: Data): Boolean = {
       val s = DataMirror.specifiedDirectionOf(d)
@@ -98,10 +98,10 @@ object Alignment {
   private[chisel3] def deriveChildAlignment(subMember: Data, parentAlignment: Alignment): Alignment = {
     (DataMirror.specifiedDirectionOf(subMember)) match {
       case (SpecifiedDirection.Unspecified) => parentAlignment.swap(subMember)
-      case (SpecifiedDirection.Flip)        => parentAlignment.invert.swap(subMember)
-      case (SpecifiedDirection.Output)      => parentAlignment.coerce.swap(subMember)
-      case (SpecifiedDirection.Input)       => parentAlignment.invert.coerce.swap(subMember)
-      case other                            => throw new Exception(s"Unexpected internal error! $other")
+      case (SpecifiedDirection.Flip) => parentAlignment.invert.swap(subMember)
+      case (SpecifiedDirection.Output) => parentAlignment.coerce.swap(subMember)
+      case (SpecifiedDirection.Input) => parentAlignment.invert.coerce.swap(subMember)
+      case other => throw new Exception(s"Unexpected internal error! $other")
     }
   }
 
@@ -124,12 +124,12 @@ private[chisel3] case class ConnectableAlignment(base: Connectable[Data], align:
   // Returns loc and roc
   final def computeLandR(c: Data, p: Data, op: Connection): Option[(Data, Data)] = {
     (c, p, this.align, op.connectToConsumer, op.connectToProducer, op.alwaysConnectToConsumer) match {
-      case (x: Analog, y: Analog, _, _, _, _)     => Some((x, y))
-      case (x: Analog, DontCare, _, _, _, _)      => Some((x, DontCare))
+      case (x: Analog, y: Analog, _, _, _, _) => Some((x, y))
+      case (x: Analog, DontCare, _, _, _, _) => Some((x, DontCare))
       case (x, y, _: AlignedWithRoot, true, _, _) => Some((c, p))
       case (x, y, _: FlippedWithRoot, _, true, _) => Some((p, c))
-      case (x, y, _, _, _, true)                  => Some((c, p))
-      case other                                  => None
+      case (x, y, _, _, _, true) => Some((c, p))
+      case other => None
     }
   }
 
@@ -141,10 +141,10 @@ private[chisel3] case class ConnectableAlignment(base: Connectable[Data], align:
         lAndROpt.map {
           case (l, r) if !(base.squeezed.contains(r) || o.base.squeezed.contains(r)) =>
             (l.widthOption, r.widthOption) match {
-              case (None, _)                       => None // l will infer a large enough width
-              case (Some(x), None)                 => Some(r) // r could infer a larger width than l's width
+              case (None, _) => None // l will infer a large enough width
+              case (Some(x), None) => Some(r) // r could infer a larger width than l's width
               case (Some(lw), Some(rw)) if lw < rw => Some(r)
-              case (Some(lw), Some(rw))            => None
+              case (Some(lw), Some(rw)) => None
             }
           case (l, r) => None
         }.getOrElse(None)
@@ -162,11 +162,11 @@ private[chisel3] case class ConnectableAlignment(base: Connectable[Data], align:
   // If erroring, determine the correct word to use
   final def errorWord(op: Connection): String =
     (align.isConsumer, op.connectToConsumer, op.connectToProducer, align.alignment) match {
-      case (true, true, _, "aligned")  => "unconnected"
+      case (true, true, _, "aligned") => "unconnected"
       case (false, _, true, "flipped") => "unconnected"
-      case (true, _, true, "flipped")  => "dangling"
+      case (true, _, true, "flipped") => "dangling"
       case (false, true, _, "aligned") => "dangling"
-      case other                       => "unmatched"
+      case other => "unmatched"
     }
 
   /// Expose some underlying Alignment methods for convenience.
diff --git a/core/src/main/scala/chisel3/connectable/Connection.scala b/core/src/main/scala/chisel3/connectable/Connection.scala
index 11bbf7cd654..21b491ce99b 100644
--- a/core/src/main/scala/chisel3/connectable/Connection.scala
+++ b/core/src/main/scala/chisel3/connectable/Connection.scala
@@ -120,8 +120,8 @@ private[chisel3] object Connection {
     try {
       (l, r) match {
         case (x: Analog, y: Analog) => connectAnalog(x, y)
-        case (x: Analog, DontCare)  => connectAnalog(x, DontCare)
-        case (_, _)                 => l := r
+        case (x: Analog, DontCare) => connectAnalog(x, DontCare)
+        case (_, _) => l := r
       }
     } catch {
       case e: Exception => Builder.error(e.getMessage)
@@ -220,7 +220,7 @@ private[chisel3] object Connection {
                 case (true, _, _) => conAlign
                 case (_, true, _) => conAlign
                 case (_, _, true) => proAlign
-                case other        => throw new Exception(other.toString)
+                case other => throw new Exception(other.toString)
               }
               val lAndROpt = alignment.computeLandR(consumer, producer, connectionOp)
               lAndROpt.foreach { case (l, r) => connect(l, r) }
@@ -250,7 +250,7 @@ private[chisel3] object Connection {
       }
     } catch { // convert Exceptions to Builder.error's so compilation can continue
       case attach.AttachException(message) => Builder.error(message)
-      case BiConnectException(message)     => Builder.error(message)
+      case BiConnectException(message) => Builder.error(message)
     }
   }
 
diff --git a/core/src/main/scala/chisel3/dontTouch.scala b/core/src/main/scala/chisel3/dontTouch.scala
index 3266b811543..283b59d600d 100644
--- a/core/src/main/scala/chisel3/dontTouch.scala
+++ b/core/src/main/scala/chisel3/dontTouch.scala
@@ -38,7 +38,7 @@ object dontTouch {
     data match {
       case d if DataMirror.hasProbeTypeModifier(d) => ()
       case _:   Property[_] => ()
-      case agg: Aggregate   => agg.getElements.foreach(dontTouch.apply)
+      case agg: Aggregate => agg.getElements.foreach(dontTouch.apply)
       case _:   Element =>
         annotate(new ChiselAnnotation { def toFirrtl: DontTouchAnnotation = DontTouchAnnotation(data.toNamed) })
       case _ => throw new ChiselException("Non-hardware dontTouch")
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
index 79ba0bbba93..fe16ae74ab5 100644
--- a/core/src/main/scala/chisel3/experimental/Analog.scala
+++ b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -54,7 +54,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
       case ChildBinding(parent) => parent.topBinding
       // See https://github.com/freechipsproject/chisel3/pull/946
       case SampleElementBinding(parent) => parent.topBinding
-      case a: MemTypeBinding[_]    => a
+      case a: MemTypeBinding[_] => a
       case a: FirrtlMemTypeBinding => a
     }
 
diff --git a/core/src/main/scala/chisel3/experimental/SerializableModuleGenerator.scala b/core/src/main/scala/chisel3/experimental/SerializableModuleGenerator.scala
index 31707e81b7d..10012d26e4c 100644
--- a/core/src/main/scala/chisel3/experimental/SerializableModuleGenerator.scala
+++ b/core/src/main/scala/chisel3/experimental/SerializableModuleGenerator.scala
@@ -66,22 +66,22 @@ case class SerializableModuleGenerator[M <: SerializableModule[P], P <: Serializ
     require(
       generator.getConstructors.length == 1,
       s"""only allow constructing SerializableModule from SerializableModuleParameter via class Module(val parameter: Parameter),
-         |you have ${generator.getConstructors.length} constructors
-         |""".stripMargin
+        |you have ${generator.getConstructors.length} constructors
+        |""".stripMargin
     )
     require(
       !generator.getConstructors.head.getParameterTypes.last.toString.contains("$"),
       s"""You define your ${generator.getConstructors.head.getParameterTypes.last} inside other class.
-         |This is a forbidden behavior, since we cannot serialize the out classes,
-         |for debugging, these are full parameter types of constructor:
-         |${generator.getConstructors.head.getParameterTypes.mkString("\n")}
-         |""".stripMargin
+        |This is a forbidden behavior, since we cannot serialize the out classes,
+        |for debugging, these are full parameter types of constructor:
+        |${generator.getConstructors.head.getParameterTypes.mkString("\n")}
+        |""".stripMargin
     )
     require(
       generator.getConstructors.head.getParameterCount == 1,
       s"""You define multiple constructors:
-         |${generator.getConstructors.head.getParameterTypes.mkString("\n")}
-         |""".stripMargin
+        |${generator.getConstructors.head.getParameterTypes.mkString("\n")}
+        |""".stripMargin
     )
     generator.getConstructors.head.newInstance(parameter).asInstanceOf[M with BaseModule]
   }
diff --git a/core/src/main/scala/chisel3/experimental/SourceInfoImpl.scala b/core/src/main/scala/chisel3/experimental/SourceInfoImpl.scala
index e01b0705ebb..1a665788071 100644
--- a/core/src/main/scala/chisel3/experimental/SourceInfoImpl.scala
+++ b/core/src/main/scala/chisel3/experimental/SourceInfoImpl.scala
@@ -54,6 +54,6 @@ private[chisel3] trait ObjectSourceInfoImpl {
   private[chisel3] def materializeFromStacktrace: SourceInfo =
     getUserLineNumber match {
       case Some(elt) => new SourceLine(elt.getFileName, elt.getLineNumber, 0)
-      case None      => UnlocatableSourceInfo
+      case None => UnlocatableSourceInfo
     }
 }
diff --git a/core/src/main/scala/chisel3/experimental/dataview/package.scala b/core/src/main/scala/chisel3/experimental/dataview/package.scala
index b5c911fd5cb..1aa8b10cb92 100644
--- a/core/src/main/scala/chisel3/experimental/dataview/package.scala
+++ b/core/src/main/scala/chisel3/experimental/dataview/package.scala
@@ -196,7 +196,7 @@ package object dataview {
         }
         getMatchedFields(aa, ba).foreach {
           case (aelt: Element, belt: Element) => onElt(aelt, belt)
-          case (t, v)                         => aggregateMappings += (v -> t)
+          case (t, v) => aggregateMappings += (v -> t)
         }
     }
 
@@ -313,10 +313,10 @@ package object dataview {
   ): Option[(T, ViewWriteability)] = {
     val candidate: Option[(Data, ViewWriteability)] =
       data.topBindingOpt match {
-        case None                                       => None
-        case Some(ViewBinding(target, wr))              => Some(target -> wr)
+        case None => None
+        case Some(ViewBinding(target, wr)) => Some(target -> wr)
         case Some(vb @ AggregateViewBinding(lookup, _)) => lookup.get(data).map(_ -> vb.lookupWritability(data))
-        case Some(_)                                    => Some(data -> ViewWriteability.Default)
+        case Some(_) => Some(data -> ViewWriteability.Default)
       }
     candidate.flatMap { case (d, wr) =>
       val wrx = wrAcc.combine(wr)
@@ -330,7 +330,7 @@ package object dataview {
   // Return all parents of a Data, including itself
   private def allParents(d: Data): List[Data] = d.binding match {
     case Some(ChildBinding(parent)) => d :: allParents(parent)
-    case _                          => List(d)
+    case _ => List(d)
   }
 
   /** Determine the target of a View if the view maps to a single `Data`.
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/InstantiableClone.scala b/core/src/main/scala/chisel3/experimental/hierarchy/InstantiableClone.scala
index ac870059410..d6aeef7ddcc 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/InstantiableClone.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/InstantiableClone.scala
@@ -7,6 +7,6 @@ import chisel3.experimental.BaseModule
 /** @note If we are cloning a non-module, we need another object which has the proper _parent set!
   */
 trait InstantiableClone[T <: IsInstantiable] extends core.IsClone[T] {
-  private[chisel3] def _innerContext:   Hierarchy[_]
+  private[chisel3] def _innerContext: Hierarchy[_]
   private[chisel3] def getInnerContext: Option[BaseModule] = _innerContext.getInnerDataContext
 }
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/InstantiateImpl.scala b/core/src/main/scala/chisel3/experimental/hierarchy/InstantiateImpl.scala
index aa052e5c870..d122ee0bd55 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/InstantiateImpl.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/InstantiateImpl.scala
@@ -25,7 +25,7 @@ private[chisel3] trait InstantiateImpl {
     private def convertDataForHashing(data: Data): Any = data match {
       // Using toString is a bit weird but it works
       case elt: Element => elt.toString
-      case rec: Record  =>
+      case rec: Record =>
         // Purely structural, actual class of Record isn't involved
         rec.elements.map { case (name, data) => name -> convertDataForHashing(data) }
       case vec: Vec[_] =>
@@ -67,7 +67,7 @@ private[chisel3] trait InstantiateImpl {
     case d: Data => new DataBox(d) // Must check this before Iterable because Vec is Iterable
     // Must check before Product, because many Iterables are Products, but can still be equal, eg. List(1) == Vector(1)
     case it: Iterable[_] => it.map(boxAllData(_))
-    case p:  Product     => Vector(p.getClass) ++ p.productIterator.map(boxAllData(_))
+    case p:  Product => Vector(p.getClass) ++ p.productIterator.map(boxAllData(_))
     case other => other
   }
 
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala b/core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
index ce0c6d302df..5ceb8695834 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala
@@ -55,7 +55,7 @@ private[chisel3] class ModuleClone[T <: BaseModule](val getProto: T)(implicit si
     // Now take the Ref that forceName set and convert it to the correct Arg
     val instName = record.getRef match {
       case Ref(name) => name
-      case bad       => throwException(s"Internal Error! Cloned-module Record $record has unexpected ref $bad")
+      case bad => throwException(s"Internal Error! Cloned-module Record $record has unexpected ref $bad")
     }
     // Set both the record and the module to have the same instance name
     val ref = ModuleCloneIO(getProto, instName)
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/core/Hierarchy.scala b/core/src/main/scala/chisel3/experimental/hierarchy/core/Hierarchy.scala
index 843e81a2e5f..78eba4b26f8 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/core/Hierarchy.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/core/Hierarchy.scala
@@ -18,7 +18,7 @@ import scala.annotation.implicitNotFound
 sealed trait Hierarchy[+A] {
   private[chisel3] def underlying: Underlying[A]
   private[chisel3] def proto: A = underlying match {
-    case Proto(value)         => value
+    case Proto(value) => value
     case Clone(i: IsClone[A]) => i.getProto
   }
 
@@ -49,7 +49,7 @@ sealed trait Hierarchy[+A] {
     if (clz != null) {
       clz.split('.').toList match {
         case "repl" :: "MdocSession" :: app :: rest => s"$app.this." + rest.mkString(".")
-        case other                                  => clz
+        case other => clz
       }
     } else clz
   }
@@ -104,7 +104,7 @@ object Hierarchy {
       */
     def toTarget: IsModule = i match {
       case d: Definition[T] => new Definition.DefinitionBaseModuleExtensions(d).toTarget
-      case i: Instance[T]   => new Instance.InstanceBaseModuleExtensions(i).toTarget
+      case i: Instance[T] => new Instance.InstanceBaseModuleExtensions(i).toTarget
       case _ => throw new InternalErrorException(s"Match error: toTarget i=$i")
     }
 
@@ -113,7 +113,7 @@ object Hierarchy {
       */
     def toAbsoluteTarget: IsModule = i match {
       case d: Definition[T] => new Definition.DefinitionBaseModuleExtensions(d).toAbsoluteTarget
-      case i: Instance[T]   => new Instance.InstanceBaseModuleExtensions(i).toAbsoluteTarget
+      case i: Instance[T] => new Instance.InstanceBaseModuleExtensions(i).toAbsoluteTarget
       case _ => throw new InternalErrorException(s"Match error: toAbsoluteTarget i=$i")
     }
 
@@ -122,7 +122,7 @@ object Hierarchy {
       */
     def toRelativeTarget(root: Option[BaseModule]): IsModule = i match {
       case d: Definition[T] => new Definition.DefinitionBaseModuleExtensions(d).toRelativeTarget(root)
-      case i: Instance[T]   => new Instance.InstanceBaseModuleExtensions(i).toRelativeTarget(root)
+      case i: Instance[T] => new Instance.InstanceBaseModuleExtensions(i).toRelativeTarget(root)
       case _ => throw new InternalErrorException(s"Match error: toAbsoluteTarget i=$i")
     }
 
@@ -131,7 +131,7 @@ object Hierarchy {
       */
     def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): IsModule = i match {
       case d: Definition[T] => new Definition.DefinitionBaseModuleExtensions(d).toRelativeTargetToHierarchy(root)
-      case i: Instance[T]   => new Instance.InstanceBaseModuleExtensions(i).toRelativeTargetToHierarchy(root)
+      case i: Instance[T] => new Instance.InstanceBaseModuleExtensions(i).toRelativeTargetToHierarchy(root)
       case _ => throw new InternalErrorException(s"Match error: toAbsoluteTarget i=$i")
     }
 
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala b/core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala
index 934fa8a8197..dfb1719c516 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/core/Instance.scala
@@ -23,24 +23,24 @@ final case class Instance[+A] private[chisel3] (private[chisel3] val underlying:
     extends SealedHierarchy[A] {
   underlying match {
     case Proto(p: IsClone[_]) => chisel3.internal.throwException("Cannot have a Proto with a clone!")
-    case other                => // Ok
+    case other => // Ok
   }
 
   /** @return the context of any Data's return from inside the instance */
   private[chisel3] def getInnerDataContext: Option[BaseModule] = underlying match {
-    case Proto(value: BaseModule)       => Some(value)
-    case Proto(value: IsInstantiable)   => None
-    case Clone(i: BaseModule)           => Some(i)
+    case Proto(value: BaseModule) => Some(value)
+    case Proto(value: IsInstantiable) => None
+    case Clone(i: BaseModule) => Some(i)
     case Clone(i: InstantiableClone[_]) => i.getInnerContext
-    case _                              => throw new InternalErrorException(s"Match error: underlying=$underlying")
+    case _ => throw new InternalErrorException(s"Match error: underlying=$underlying")
   }
 
   /** @return the context this instance. Note that for non-module clones, getInnerDataContext will be the same as getClonedParent */
   private[chisel3] def getClonedParent: Option[BaseModule] = underlying match {
-    case Proto(value: BaseModule)       => value._parent
-    case Clone(i: BaseModule)           => i._parent
+    case Proto(value: BaseModule) => value._parent
+    case Clone(i: BaseModule) => i._parent
     case Clone(i: InstantiableClone[_]) => i.getInnerContext
-    case _                              => throw new InternalErrorException(s"Match error: underlying=$underlying")
+    case _ => throw new InternalErrorException(s"Match error: underlying=$underlying")
   }
 
   /** Used by Chisel's internal macros. DO NOT USE in your normal Chisel code!!!
@@ -81,7 +81,7 @@ object Instance extends SourceInfoDoc {
       * @return target of this instance
       */
     def toTarget: IsModule = i.underlying match {
-      case Proto(x: BaseModule)                 => x.getTarget
+      case Proto(x: BaseModule) => x.getTarget
       case Clone(x: IsClone[_] with BaseModule) => x.getTarget
       case _ => throw new InternalErrorException(s"Match error: i.underlying=${i.underlying}")
     }
@@ -90,7 +90,7 @@ object Instance extends SourceInfoDoc {
       * @return absoluteTarget of this instance
       */
     def toAbsoluteTarget: IsModule = i.underlying match {
-      case Proto(x)                             => x.toAbsoluteTarget
+      case Proto(x) => x.toAbsoluteTarget
       case Clone(x: IsClone[_] with BaseModule) => x.toAbsoluteTarget
       case _ => throw new InternalErrorException(s"Match error: i.underlying=${i.underlying}")
     }
@@ -106,21 +106,21 @@ object Instance extends SourceInfoDoc {
       * @note This doesn't have special handling for Views.
       */
     def toRelativeTarget(root: Option[BaseModule]): IsModule = i.underlying match {
-      case Proto(x)                             => x.toRelativeTarget(root)
+      case Proto(x) => x.toRelativeTarget(root)
       case Clone(x: IsClone[_] with BaseModule) => x.toRelativeTarget(root)
       case _ => throw new InternalErrorException(s"Match error: i.underlying=${i.underlying}")
     }
 
     def toRelativeTargetToHierarchy(root: Option[Hierarchy[BaseModule]]): IsModule = i.underlying match {
-      case Proto(x)                             => x.toRelativeTargetToHierarchy(root)
+      case Proto(x) => x.toRelativeTargetToHierarchy(root)
       case Clone(x: IsClone[_] with BaseModule) => x.toRelativeTargetToHierarchy(root)
       case _ => throw new InternalErrorException(s"Match error: i.underlying=${i.underlying}")
     }
 
     def suggestName(name: String): Unit = i.underlying match {
       case Clone(m: BaseModule) => m.suggestName(name)
-      case Proto(m)             => m.suggestName(name)
-      case x                    => Builder.exception(s"Cannot call .suggestName on $x")(UnlocatableSourceInfo)
+      case Proto(m) => m.suggestName(name)
+      case x => Builder.exception(s"Cannot call .suggestName on $x")(UnlocatableSourceInfo)
     }
   }
 
@@ -136,9 +136,9 @@ object Instance extends SourceInfoDoc {
   ): Instance[T] = {
     // Check to see if the module is already defined internally or externally
     val existingMod = Builder.definitions.view.map(_.proto).exists {
-      case c: Class               => c == definition.proto
-      case c: RawModule           => c == definition.proto
-      case c: BaseBlackBox        => c.name == definition.proto.name
+      case c: Class => c == definition.proto
+      case c: RawModule => c == definition.proto
+      case c: BaseBlackBox => c.name == definition.proto.name
       case c: BaseIntrinsicModule => c.name == definition.proto.name
       case _ => false
     }
diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala b/core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
index d0792364662..2c36cf56597 100644
--- a/core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
+++ b/core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala
@@ -56,13 +56,13 @@ trait Lookupable[-B] {
     * @return
     */
   def definitionLookup[A](that:     A => B, definition: Definition[A]): C
-  protected def getProto[A](h:      Hierarchy[A]):                      A = h.proto
-  protected def getUnderlying[A](h: Hierarchy[A]):                      Underlying[A] = h.underlying
+  protected def getProto[A](h:      Hierarchy[A]): A = h.proto
+  protected def getUnderlying[A](h: Hierarchy[A]): Underlying[A] = h.underlying
 
   // Single method that may eventually replace instanceLookup and definitionLookup.
   private[chisel3] def hierarchyLookup[A](that: A => B, hierarchy: Hierarchy[A]): C = {
     hierarchy match {
-      case h: Instance[A]   => instanceLookup(that, h)
+      case h: Instance[A] => instanceLookup(that, h)
       case h: Definition[A] => definitionLookup(that, h)
       case h => throw new InternalErrorException(s"Match error: hierarchy=$hierarchy")
     }
@@ -222,7 +222,7 @@ object Lookupable {
   ): B = {
     def impl[C <: Data](d: C): C = d match {
       case x: Data if ioMap.nonEmpty && ioMap.get.contains(x) => ioMap.get(x).asInstanceOf[C]
-      case x: Data if cache.contains(x)                       => cache(x).asInstanceOf[C]
+      case x: Data if cache.contains(x) => cache(x).asInstanceOf[C]
       case _ =>
         assert(context.nonEmpty) // TODO is this even possible? Better error message here
         val ret = cloneDataToContext(d, context.get)
@@ -231,7 +231,7 @@ object Lookupable {
     }
     data.binding match {
       case Some(_: ChildBinding) => mapRootAndExtractSubField(data, impl)
-      case _                     => impl(data)
+      case _ => impl(data)
     }
   }
 
@@ -269,11 +269,11 @@ object Lookupable {
         if (coor.isEmpty) d
         else {
           val next = (coor.head, d) match {
-            case (Slot(_, name), rec: Record)     => rec._elements(name)
-            case (LitIndex(_, n), vec: Vec[_])    => vec.apply(n)
+            case (Slot(_, name), rec: Record) => rec._elements(name)
+            case (LitIndex(_, n), vec: Vec[_]) => vec.apply(n)
             case (Index(_, ILit(n)), vec: Vec[_]) => vec.apply(n.toInt)
             case (ModuleIO(_, name), rec: Record) => rec._elements(name)
-            case (arg, _)                         => err(s"Unexpected Arg '$arg' applied to '$d'! Root was '$start'.")
+            case (arg, _) => err(s"Unexpected Arg '$arg' applied to '$d'! Root was '$start'.")
           }
           applyCoordinates(coor.tail, next)
         }
@@ -377,9 +377,9 @@ object Lookupable {
         Clone(newChild)
       }
       (m, context) match {
-        case (c, ctx) if ctx == c                        => Proto(c)
+        case (c, ctx) if ctx == c => Proto(c)
         case (c, ctx: IsClone[_]) if ctx.hasSameProto(c) => Clone(ctx.asInstanceOf[IsClone[A]])
-        case (c, ctx) if c._parent.isEmpty               => Proto(c)
+        case (c, ctx) if c._parent.isEmpty => Proto(c)
         case (_, _) =>
           cloneModuleToContext(Proto(m._parent.get), context) match {
             case Proto(p) => Proto(m)
@@ -478,9 +478,9 @@ object Lookupable {
         def getIoMap(hierarchy: Hierarchy[_]): Option[Map[Data, Data]] = {
           hierarchy.underlying match {
             case Clone(x: ModuleClone[_]) => Some(x.ioMap)
-            case Proto(x: BaseModule)     => Some(x.getChiselPorts.map { case (_, data: Data) => data -> data }.toMap)
+            case Proto(x: BaseModule) => Some(x.getChiselPorts.map { case (_, data: Data) => data -> data }.toMap)
             case Clone(x: InstantiableClone[_]) => getIoMap(x._innerContext)
-            case Clone(x: InstanceClone[_])     => None
+            case Clone(x: InstanceClone[_]) => None
             case other => {
               Builder.exception(s"Internal Error! Unexpected case where we can't get IO Map: $other")
             }
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index 914a0c40125..a10f3876602 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -243,7 +243,7 @@ private[chisel3] object BiConnect {
       try {
         right_r._elements.get(field) match {
           case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
-          case None            => throw MissingRightFieldException(field)
+          case None => throw MissingRightFieldException(field)
         }
       } catch {
         case BiConnectException(message) => throw BiConnectException(s".$field$message")
@@ -300,8 +300,8 @@ private[chisel3] object BiConnect {
     // do not bulk connect source literals (results in infinite recursion from calling .ref)
     def sourceAndSinkNotLiteralOrViewCheck = List(source, sink).forall {
       _.topBinding match {
-        case _: LitBinding           => false
-        case _: ViewBinding          => false
+        case _: LitBinding => false
+        case _: ViewBinding => false
         case _: AggregateViewBinding => false
         case _ => true
       }
@@ -310,7 +310,7 @@ private[chisel3] object BiConnect {
     // do not bulk connect the 'io' pseudo-bundle of a BlackBox since it will be decomposed in FIRRTL
     def blackBoxCheck = Seq(source, sink).map(_._parent).forall {
       case Some(_: BlackBox) => false
-      case _                 => true
+      case _ => true
     }
 
     typeCheck && contextCheck && bindingCheck && flowSinkCheck && flowSourceCheck && sourceAndSinkNotLiteralOrViewCheck && blackBoxCheck
@@ -400,15 +400,15 @@ private[chisel3] object BiConnect {
       // Thus, right node better be a port node and thus have a direction hint
       ((left_direction, right_direction): @unchecked) match {
         //    CURRENT MOD   CHILD MOD
-        case (Input, Input)    => issueConnectL2R(left, lwr, right, rwr)
+        case (Input, Input) => issueConnectL2R(left, lwr, right, rwr)
         case (Internal, Input) => issueConnectL2R(left, lwr, right, rwr)
 
-        case (Output, Output)   => issueConnectR2L(left, lwr, right, rwr)
+        case (Output, Output) => issueConnectR2L(left, lwr, right, rwr)
         case (Internal, Output) => issueConnectR2L(left, lwr, right, rwr)
 
         case (Input, Output) => throw BothDriversException
         case (Output, Input) => throw NeitherDriverException
-        case (_, Internal)   => throw UnknownRelationException
+        case (_, Internal) => throw UnknownRelationException
       }
     }
 
@@ -417,15 +417,15 @@ private[chisel3] object BiConnect {
       // Thus, left node better be a port node and thus have a direction hint
       ((left_direction, right_direction): @unchecked) match {
         //    CHILD MOD     CURRENT MOD
-        case (Input, Input)    => issueConnectR2L(left, lwr, right, rwr)
+        case (Input, Input) => issueConnectR2L(left, lwr, right, rwr)
         case (Input, Internal) => issueConnectR2L(left, lwr, right, rwr)
 
-        case (Output, Output)   => issueConnectL2R(left, lwr, right, rwr)
+        case (Output, Output) => issueConnectL2R(left, lwr, right, rwr)
         case (Output, Internal) => issueConnectL2R(left, lwr, right, rwr)
 
         case (Input, Output) => throw NeitherDriverException
         case (Output, Input) => throw BothDriversException
-        case (Internal, _)   => throw UnknownRelationException
+        case (Internal, _) => throw UnknownRelationException
       }
     }
 
@@ -433,16 +433,16 @@ private[chisel3] object BiConnect {
     else if ((context_mod == left_mod) && (context_mod == right_mod)) {
       ((left_direction, right_direction): @unchecked) match {
         //    CURRENT MOD   CURRENT MOD
-        case (Input, Output)    => issueConnectL2R(left, lwr, right, rwr)
-        case (Input, Internal)  => issueConnectL2R(left, lwr, right, rwr)
+        case (Input, Output) => issueConnectL2R(left, lwr, right, rwr)
+        case (Input, Internal) => issueConnectL2R(left, lwr, right, rwr)
         case (Internal, Output) => issueConnectL2R(left, lwr, right, rwr)
 
-        case (Output, Input)    => issueConnectR2L(left, lwr, right, rwr)
+        case (Output, Input) => issueConnectR2L(left, lwr, right, rwr)
         case (Output, Internal) => issueConnectR2L(left, lwr, right, rwr)
-        case (Internal, Input)  => issueConnectR2L(left, lwr, right, rwr)
+        case (Internal, Input) => issueConnectR2L(left, lwr, right, rwr)
 
-        case (Input, Input)       => throw BothDriversException
-        case (Output, Output)     => throw BothDriversException
+        case (Input, Input) => throw BothDriversException
+        case (Output, Output) => throw BothDriversException
         case (Internal, Internal) => throw UnknownDriverException
       }
     }
@@ -457,10 +457,10 @@ private[chisel3] object BiConnect {
         case (Input, Output) => issueConnectR2L(left, lwr, right, rwr)
         case (Output, Input) => issueConnectL2R(left, lwr, right, rwr)
 
-        case (Input, Input)   => throw NeitherDriverException
+        case (Input, Input) => throw NeitherDriverException
         case (Output, Output) => throw BothDriversException
-        case (_, Internal)    => throw UnknownRelationException
-        case (Internal, _)    => throw UnknownRelationException
+        case (_, Internal) => throw UnknownRelationException
+        case (Internal, _) => throw UnknownRelationException
       }
     }
 
diff --git a/core/src/main/scala/chisel3/internal/Binding.scala b/core/src/main/scala/chisel3/internal/Binding.scala
index 55b4ff9c3c1..3f09c23d26c 100644
--- a/core/src/main/scala/chisel3/internal/Binding.scala
+++ b/core/src/main/scala/chisel3/internal/Binding.scala
@@ -34,8 +34,8 @@ private[chisel3] object binding {
         case _: PortBinding | _: SecretPortBinding =>
           direction match {
             case ActualDirection.Output => Output
-            case ActualDirection.Input  => Input
-            case dir                    => throw new RuntimeException(s"Unexpected port element direction '$dir'")
+            case ActualDirection.Input => Input
+            case dir => throw new RuntimeException(s"Unexpected port element direction '$dir'")
           }
         case _ => Internal
       }
@@ -58,7 +58,7 @@ private[chisel3] object binding {
   // Location will track where this Module is, and the bound object can be referenced in FIRRTL
   sealed trait ConstrainedBinding extends TopBinding {
     def enclosure: BaseModule
-    def location:  Option[BaseModule] = Some(enclosure)
+    def location: Option[BaseModule] = Some(enclosure)
   }
 
   // A binding representing a data that cannot be (re)assigned to.
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index f5ff2bd25f3..f7a6f38f3aa 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -116,7 +116,7 @@ private[chisel3] class IdGen {
 
 private[chisel3] trait HasId extends chisel3.InstanceId {
   // using nullable var for better memory usage
-  private var _parentVar:       BaseModule = Builder.currentModule.getOrElse(null)
+  private var _parentVar: BaseModule = Builder.currentModule.getOrElse(null)
   private[chisel3] def _parent: Option[BaseModule] = Option(_parentVar)
   private[chisel3] def _parent_=(target: Option[BaseModule]): Unit = {
     _parentVar = target.getOrElse(null)
@@ -132,7 +132,7 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
   private var _nameIsSuggested: Boolean = false
   // Contains name seed (either user suggested or generated by the plugin).
   private var suggested_seedVar: String = null // using nullable var for better memory usage
-  private def suggested_seed:    Option[String] = Option(suggested_seedVar)
+  private def suggested_seed: Option[String] = Option(suggested_seedVar)
 
   // Prefix for use in naming
   // - Defaults to prefix at time when object is created
@@ -252,7 +252,7 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
       naming_prefix = Nil
     }
 
-  private var _refVar:                   Arg = null // using nullable var for better memory usage
+  private var _refVar: Arg = null // using nullable var for better memory usage
   private def _ref:                      Option[Arg] = Option(_refVar)
   private[chisel3] def setRef(imm: Arg): Unit = setRef(imm, false)
   private[chisel3] def setRef(imm: Arg, force: Boolean): Unit = {
@@ -268,7 +268,7 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
   private[chisel3] def setRef(parent: Node, index: Int): Unit = setRef(LitIndex(parent, index))
   private[chisel3] def setRef(parent: Node, index: UInt): Unit = index.litOption match {
     case Some(lit) if lit.isValidInt => setRef(LitIndex(parent, lit.intValue))
-    case _                           => setRef(Index(parent, index.ref))
+    case _ => setRef(Index(parent, index.ref))
   }
   private[chisel3] def getRef:       Arg = _ref.get
   private[chisel3] def getOptionRef: Option[Arg] = _ref
@@ -285,13 +285,13 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
   private[chisel3] def _errorContext: String = {
     val nameGuess: String = _computeName(None) match {
       case Some(name) => s": '$name'"
-      case None       => ""
+      case None => ""
     }
 
     val parentGuess: String = _parent match {
       case Some(ViewParent) => s", in module '${reifyParent.pathName}'"
-      case Some(p)          => s", in module '${p.pathName}'"
-      case None             => ""
+      case Some(p) => s", in module '${p.pathName}'"
+      case None => ""
     }
 
     nameGuess + parentGuess
@@ -314,9 +314,9 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
     case Some(ViewParent) => reifyTarget.map(_.instanceName).getOrElse(this.refName(ViewParent.fakeComponent))
     case Some(p) =>
       (p._component, this) match {
-        case (Some(c), _)                                                   => refName(c)
+        case (Some(c), _) => refName(c)
         case (None, d: Data) if d.topBindingOpt == Some(CrossModuleBinding) => _ref.get.localName
-        case (None, _: MemBase[_])                                          => _ref.get.localName
+        case (None, _: MemBase[_]) => _ref.get.localName
         case (None, _) if _ref.isDefined => {
           // Support instance names for HasIds that don't have a _parent set yet, but do have a _ref set.
           // This allows HasIds to be named in atModuleBodyEnd, for example.
@@ -331,19 +331,19 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
     case None => throwException("this cannot happen")
   }
   def pathName: String = _parent match {
-    case None             => instanceName
+    case None => instanceName
     case Some(ViewParent) => s"${reifyParent.pathName}.$instanceName"
-    case Some(p)          => s"${p.pathName}.$instanceName"
+    case Some(p) => s"${p.pathName}.$instanceName"
   }
   def parentPathName: String = _parent match {
     case Some(ViewParent) => reifyParent.pathName
-    case Some(p)          => p.pathName
-    case None             => throwException(s"$instanceName doesn't have a parent")
+    case Some(p) => p.pathName
+    case None => throwException(s"$instanceName doesn't have a parent")
   }
   def parentModName: String = _parent match {
     case Some(ViewParent) => reifyParent.name
-    case Some(p)          => p.name
-    case None             => throwException(s"$instanceName doesn't have a parent")
+    case Some(p) => p.name
+    case None => throwException(s"$instanceName doesn't have a parent")
   }
   def circuitName: String = _parent match {
     case None =>
@@ -352,12 +352,12 @@ private[chisel3] trait HasId extends chisel3.InstanceId {
         case b: BaseModule =>
           b._circuit match {
             case Some(c) => c.circuitName
-            case None    => instanceName
+            case None => instanceName
           }
         case _ => instanceName
       }
     case Some(ViewParent) => reifyParent.circuitName
-    case Some(p)          => p.circuitName
+    case Some(p) => p.circuitName
   }
 }
 
@@ -382,7 +382,7 @@ private[chisel3] trait NamedComponent extends HasId {
     import _root_.firrtl.annotations.{Target, TargetToken}
     val root = _parent.map {
       case ViewParent => reifyParent
-      case other      => other
+      case other => other
     }.get.getTarget // All NamedComponents will have a parent, only the top module can have None here
     Target.toTargetTokens(name).toList match {
       case TargetToken.Ref(r) :: components => root.ref(r).copy(component = components)
@@ -396,8 +396,8 @@ private[chisel3] trait NamedComponent extends HasId {
     def makeTarget(p: BaseModule) = p.toAbsoluteTarget.ref(localTarget.ref).copy(component = localTarget.component)
     _parent match {
       case Some(ViewParent) => makeTarget(reifyParent)
-      case Some(parent)     => makeTarget(parent)
-      case None             => localTarget
+      case Some(parent) => makeTarget(parent)
+      case None => localTarget
     }
   }
 
@@ -417,8 +417,8 @@ private[chisel3] trait NamedComponent extends HasId {
       p.toRelativeTarget(root).ref(localTarget.ref).copy(component = localTarget.component)
     _parent match {
       case Some(ViewParent) => makeTarget(reifyParent)
-      case Some(parent)     => makeTarget(parent)
-      case None             => localTarget
+      case Some(parent) => makeTarget(parent)
+      case None => localTarget
     }
   }
 
@@ -438,8 +438,8 @@ private[chisel3] trait NamedComponent extends HasId {
       p.toRelativeTargetToHierarchy(root).ref(localTarget.ref).copy(component = localTarget.component)
     _parent match {
       case Some(ViewParent) => makeTarget(reifyParent)
-      case Some(parent)     => makeTarget(parent)
-      case None             => localTarget
+      case Some(parent) => makeTarget(parent)
+      case None => localTarget
     }
   }
 
@@ -447,7 +447,7 @@ private[chisel3] trait NamedComponent extends HasId {
     val isVecSubaccess = getOptionRef.map {
       case Index(_, _: ULit) => true // Vec literal indexing
       case Index(_, _: Node) => true // Vec dynamic indexing
-      case _                 => false
+      case _ => false
     }.getOrElse(false)
 
     if (isVecSubaccess) {
@@ -656,13 +656,13 @@ private[chisel3] object Builder extends LazyLogging {
   def pushPrefix(d: HasId): Boolean = {
     def buildAggName(id: HasId): Option[String] = {
       def getSubName(field: Data): Option[String] = field.getOptionRef.flatMap {
-        case Slot(_, field)       => Some(field) // Record
-        case OpaqueSlot(_)        => None // OpaqueSlots don't contribute to the name
-        case Index(_, ILit(n))    => Some(n.toString) // Vec static indexing
-        case LitIndex(_, n)       => Some(n.toString) // Vec static indexing
+        case Slot(_, field) => Some(field) // Record
+        case OpaqueSlot(_) => None // OpaqueSlots don't contribute to the name
+        case Index(_, ILit(n)) => Some(n.toString) // Vec static indexing
+        case LitIndex(_, n) => Some(n.toString) // Vec static indexing
         case Index(_, ULit(n, _)) => Some(n.toString) // Vec lit indexing
-        case Index(_, _: Node)    => None // Vec dynamic indexing
-        case ModuleIO(_, n)       => Some(n) // BlackBox port
+        case Index(_, _: Node) => None // Vec dynamic indexing
+        case ModuleIO(_, n) => Some(n) // BlackBox port
         case f =>
           throw new InternalErrorException(s"Match Error: field=$f")
       }
@@ -676,11 +676,11 @@ private[chisel3] object Builder extends LazyLogging {
             // And name of the field if we have one, we don't for dynamic indexing of Vecs
             getSubName(data).map(p + "_" + _).getOrElse(p)
           }
-        case SampleElementBinding(parent)                            => recData(parent)
+        case SampleElementBinding(parent) => recData(parent)
         case PortBinding(mod) if Builder.currentModule.contains(mod) => data.seedOpt
-        case PortBinding(mod)                                        => map2(mod.seedOpt, data.seedOpt)(_ + "_" + _)
-        case (_: LitBinding | _: DontCareBinding)                    => None
-        case _                                                       => Some("view_") // TODO implement
+        case PortBinding(mod) => map2(mod.seedOpt, data.seedOpt)(_ + "_" + _)
+        case (_: LitBinding | _: DontCareBinding) => None
+        case _ => Some("view_") // TODO implement
       }
       id match {
         case d: Data => recData(d)
@@ -719,7 +719,7 @@ private[chisel3] object Builder extends LazyLogging {
 
   def currentModule: Option[BaseModule] = dynamicContextVar.value match {
     case Some(dynamicContext) => dynamicContext.currentModule
-    case _                    => None
+    case _ => None
   }
   def currentModule_=(target: Option[BaseModule]): Unit = {
     dynamicContext.currentModule = target
@@ -755,7 +755,7 @@ private[chisel3] object Builder extends LazyLogging {
   def referenceUserContainer: BaseModule = {
     currentModule match {
       case Some(module: RawModule) => module
-      case Some(cls: Class)        => cls
+      case Some(cls: Class) => cls
       case _ =>
         throwException(
           "Error: Not in a RawModule or Class. Likely cause: Missed Module() or Definition() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox."
@@ -815,7 +815,7 @@ private[chisel3] object Builder extends LazyLogging {
 
   def currentBlock: Option[Block] = dynamicContextVar.value match {
     case Some(dc) => dc.blockStack.headOption
-    case _        => None
+    case _ => None
   }
 
   // Helper for reasonable errors when clock or reset value not yet initialized
@@ -918,7 +918,7 @@ private[chisel3] object Builder extends LazyLogging {
     case (id: Instance[_]) =>
       id.underlying match {
         case Clone(m: experimental.hierarchy.ModuleClone[_]) => namer(m.getPorts, prefix)
-        case _                                               =>
+        case _ =>
       }
     case (d: Data) =>
       // Views are often returned in lieu of the target, so name the target (as appropriate).
@@ -1021,7 +1021,7 @@ private[chisel3] object Builder extends LazyLogging {
       // If the aliased bundle is coerced and it has flipped signals, then they must be stripped
       val isCoerced = parentDirection match {
         case SpecifiedDirection.Input | SpecifiedDirection.Output => true
-        case other                                                => false
+        case other => false
       }
       val isStripped = isCoerced && record.containsAFlipped
 
@@ -1106,7 +1106,7 @@ private[chisel3] object Builder extends LazyLogging {
 
       val typeAliases = aliasMap.flatMap {
         case (name, (underlying: fir.Type, info: SourceInfo)) => Some(DefTypeAlias(info, underlying, name))
-        case _                                                => None
+        case _ => None
       }.toSeq
 
       /** Stores an adjacency list representation of layers.  Connections indicating children. */
@@ -1127,8 +1127,8 @@ private[chisel3] object Builder extends LazyLogging {
         val children = layerAdjacencyList(l)
         val config = l.config match {
           case layer.LayerConfig.Extract(_) => LayerConfig.Extract(l.outputDir.map(_.toString))
-          case layer.LayerConfig.Inline     => LayerConfig.Inline
-          case layer.LayerConfig.Root       => ???
+          case layer.LayerConfig.Inline => LayerConfig.Inline
+          case layer.LayerConfig.Root => ???
         }
         Layer(l.sourceInfo, l.name, config, children.map(foldLayers).toSeq, l)
       }
@@ -1210,7 +1210,7 @@ object DynamicNamingStack {
   def pushContext(): NamingContextInterface = {
     Builder.namingStackOption match {
       case Some(namingStack) => namingStack.pushContext()
-      case None              => DummyNamer
+      case None => DummyNamer
     }
   }
 
diff --git a/core/src/main/scala/chisel3/internal/Error.scala b/core/src/main/scala/chisel3/internal/Error.scala
index 13c6f35008a..32561ae700c 100644
--- a/core/src/main/scala/chisel3/internal/Error.scala
+++ b/core/src/main/scala/chisel3/internal/Error.scala
@@ -133,7 +133,7 @@ private[chisel3] case class WarningFilter(
         val filename = warning.info.filenameOption
         filename match {
           case Some(filename) => srcGlob.matches(Paths.get(filename))
-          case None           => false
+          case None => false
         }
     }
     idMatch && srcMatch
@@ -250,13 +250,13 @@ private[chisel3] object UseColor {
     case None =>
       val detect = System.console() != null && sys.env.get("TERM").exists(_ != "dumb")
       if (detect) Enabled else Disabled
-    case Some("true")  => Enabled
+    case Some("true") => Enabled
     case Some("false") => Disabled
-    case Some(other)   => Error(other)
+    case Some(other) => Error(other)
   }
 
   def useColor: Boolean = value match {
-    case Enabled  => true
+    case Enabled => true
     case Disabled => false
     case Error(_) => false
   }
@@ -284,9 +284,9 @@ private[chisel3] class ErrorLog(
     */
   private def errorLocationString(si: Option[SourceInfo]): String = {
     si match {
-      case Some(sl: SourceLine)  => sl.serialize
+      case Some(sl: SourceLine) => sl.serialize
       case Some(_: NoSourceInfo) => "(unknown)"
-      case None                  => ""
+      case None => ""
     }
   }
 
@@ -316,8 +316,8 @@ private[chisel3] class ErrorLog(
       warningFilters.collectFirst { case wf if wf.applies(warning) => wf.action }
         .getOrElse(WarningFilter.Warn) // Default is to warn
     val doReport: Option[Boolean] = action match {
-      case WarningFilter.Error    => Some(true)
-      case WarningFilter.Warn     => Some(false)
+      case WarningFilter.Error => Some(true)
+      case WarningFilter.Warn => Some(false)
       case WarningFilter.Suppress => None
     }
     doReport.foreach { isFatal =>
@@ -329,7 +329,7 @@ private[chisel3] class ErrorLog(
   def deprecated(m: String, location: Option[String]): Unit = {
     val sourceLoc = location match {
       case Some(loc) => loc
-      case None      => errorLocationString(Some(UnlocatableSourceInfo))
+      case None => errorLocationString(Some(UnlocatableSourceInfo))
     }
 
     val thisEntry = (m, sourceLoc)
diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
index 212ed379be1..53acbb64a8c 100644
--- a/core/src/main/scala/chisel3/internal/MonoConnect.scala
+++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -219,7 +219,7 @@ private[chisel3] object MonoConnect {
             try {
               source_r._elements.get(field) match {
                 case Some(source_sub) => connect(sourceInfo, sink_sub, source_sub, context_mod)
-                case None             => throw MissingFieldException(field)
+                case None => throw MissingFieldException(field)
               }
             } catch {
               case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
@@ -280,21 +280,21 @@ private[chisel3] object MonoConnect {
 
     val sink_is_port = sink.topBinding match {
       case PortBinding(_) => true
-      case _              => false
+      case _ => false
     }
     val source_is_port = source.topBinding match {
       case PortBinding(_) => true
-      case _              => false
+      case _ => false
     }
 
     checkBlockVisibility(sink) match {
       case Some(blockInfo) => throw SinkEscapedBlockScopeException(sink, blockInfo)
-      case None            => ()
+      case None => ()
     }
 
     checkBlockVisibility(source) match {
       case Some(blockInfo) => throw SourceEscapedBlockScopeException(source, blockInfo)
-      case None            => ()
+      case None => ()
     }
 
     // CASE: Context is same module that both sink node and source node are in
@@ -543,9 +543,9 @@ private[chisel3] object checkConnect {
       ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CURRENT MOD   CURRENT MOD
-        case (Output, _)   => ()
+        case (Output, _) => ()
         case (Internal, _) => ()
-        case (Input, _)    => throw UnwritableSinkException(sink, source)
+        case (Input, _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -556,12 +556,12 @@ private[chisel3] object checkConnect {
         //    SINK          SOURCE
         //    CURRENT MOD   CHILD MOD
         case (Internal, Output) => ()
-        case (Internal, Input)  => ()
-        case (Output, Output)   => ()
-        case (Output, Input)    => ()
-        case (_, Internal)      => throw UnreadableSourceException(sink, source)
-        case (Input, Output)    => ()
-        case (Input, _)         => throw UnwritableSinkException(sink, source)
+        case (Internal, Input) => ()
+        case (Output, Output) => ()
+        case (Output, Input) => ()
+        case (_, Internal) => throw UnreadableSourceException(sink, source)
+        case (Input, Output) => ()
+        case (Input, _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -571,8 +571,8 @@ private[chisel3] object checkConnect {
       ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CHILD MOD     CURRENT MOD
-        case (Input, _)    => ()
-        case (Output, _)   => throw UnwritableSinkException(sink, source)
+        case (Input, _) => ()
+        case (Output, _) => throw UnwritableSinkException(sink, source)
         case (Internal, _) => throw UnwritableSinkException(sink, source)
       }
     }
@@ -585,11 +585,11 @@ private[chisel3] object checkConnect {
       ((sink_direction, source_direction): @unchecked) match {
         //    SINK          SOURCE
         //    CHILD MOD     CHILD MOD
-        case (Input, Input)  => ()
+        case (Input, Input) => ()
         case (Input, Output) => ()
-        case (Output, _)     => throw UnwritableSinkException(sink, source)
-        case (_, Internal)   => throw UnreadableSourceException(sink, source)
-        case (Internal, _)   => throw UnwritableSinkException(sink, source)
+        case (Output, _) => throw UnwritableSinkException(sink, source)
+        case (_, Internal) => throw UnreadableSourceException(sink, source)
+        case (Internal, _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -599,12 +599,12 @@ private[chisel3] object checkConnect {
 
     checkBlockVisibility(sink) match {
       case Some(blockInfo) => throw SinkEscapedBlockScopeException(sink, blockInfo)
-      case None            => ()
+      case None => ()
     }
 
     checkBlockVisibility(source) match {
       case Some(blockInfo) => throw SourceEscapedBlockScopeException(source, blockInfo)
-      case None            => ()
+      case None => ()
     }
   }
 
@@ -614,13 +614,13 @@ private[chisel3] object checkConnect {
     // If source is a ClassType, get the source Property[ClassType] expected class name.
     val sourceClassNameOpt = source.getPropertyType match {
       case ClassPropertyType(name) => Some(name)
-      case _                       => None
+      case _ => None
     }
 
     // If sink is a ClassType, get the sink Property[ClassType] expected class name.
     val sinkClassNameOpt = sink.getPropertyType match {
       case ClassPropertyType(name) => Some(name)
-      case _                       => None
+      case _ => None
     }
 
     // We are guaranteed that source and sink are the same Property type by the Scala type system, but if they're both
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 81db0111c61..854024daf6e 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -22,9 +22,9 @@ private[chisel3] object Converter {
     case PString(str) => (str.replaceAll("%", "%%"), List.empty)
     case format: FirrtlFormat =>
       ("%" + format.specifier, List(format.bits.ref))
-    case Name(data)     => (data.ref.name, List.empty)
+    case Name(data) => (data.ref.name, List.empty)
     case FullName(data) => (data.ref.fullName(ctx), List.empty)
-    case Percent        => ("%%", List.empty)
+    case Percent => ("%%", List.empty)
   }
 
   private def reportInternalError(msg: String): Nothing = {
@@ -47,16 +47,16 @@ private[chisel3] object Converter {
 
   def convert(info: SourceInfo): fir.Info = info match {
     case _:  NoSourceInfo => fir.NoInfo
-    case sl: SourceLine   => fir.FileInfo.fromUnescaped(sl.serialize)
+    case sl: SourceLine => fir.FileInfo.fromUnescaped(sl.serialize)
   }
 
   def convert(op: PrimOp): fir.PrimOp = firrtl.PrimOps.fromString(op.name)
 
   def convert(dir: MemPortDirection): firrtl.MPortDir = dir match {
     case MemPortDirection.INFER => firrtl.MInfer
-    case MemPortDirection.READ  => firrtl.MRead
+    case MemPortDirection.READ => firrtl.MRead
     case MemPortDirection.WRITE => firrtl.MWrite
-    case MemPortDirection.RDWR  => firrtl.MReadWrite
+    case MemPortDirection.RDWR => firrtl.MReadWrite
   }
 
   // TODO
@@ -226,7 +226,7 @@ private[chisel3] object Converter {
       val firOp = op match {
         case Formal.Assert => fir.Formal.Assert
         case Formal.Assume => fir.Formal.Assume
-        case Formal.Cover  => fir.Formal.Cover
+        case Formal.Cover => fir.Formal.Cover
       }
       fir.Verification(
         firOp,
@@ -296,8 +296,8 @@ private[chisel3] object Converter {
     val commands = block.getCommands()
     val secretCommands = block.getSecretCommands()
     (commands.knownSize, secretCommands.knownSize) match {
-      case (-1, _)  => ()
-      case (s, -1)  => stmts.sizeHint(s)
+      case (-1, _) => ()
+      case (s, -1) => stmts.sizeHint(s)
       case (s1, s2) => stmts.sizeHint(s1 + s2)
     }
     for (cmd <- commands)
@@ -308,7 +308,7 @@ private[chisel3] object Converter {
   }
 
   def convert(width: Width): fir.Width = width match {
-    case UnknownWidth      => fir.UnknownWidth
+    case UnknownWidth => fir.UnknownWidth
     case KnownWidth(value) => fir.IntWidth(value)
   }
 
@@ -347,13 +347,13 @@ private[chisel3] object Converter {
     // extract underlying type for const
     case t: Data if (checkConst && t.isConst) =>
       fir.ConstType(extractType(t, clearDir, info, checkProbe, false, typeAliases))
-    case _: Clock      => fir.ClockType
+    case _: Clock => fir.ClockType
     case _: AsyncReset => fir.AsyncResetType
-    case _: ResetType  => fir.ResetType
-    case t: EnumType   => fir.UIntType(convert(t.width))
-    case t: UInt       => fir.UIntType(convert(t.width))
-    case t: SInt       => fir.SIntType(convert(t.width))
-    case t: Analog     => fir.AnalogType(convert(t.width))
+    case _: ResetType => fir.ResetType
+    case t: EnumType => fir.UIntType(convert(t.width))
+    case t: UInt => fir.UIntType(convert(t.width))
+    case t: SInt => fir.SIntType(convert(t.width))
+    case t: Analog => fir.AnalogType(convert(t.width))
     case t: Vec[_] =>
       val childClearDir = clearDir ||
         t.specifiedDirection == SpecifiedDirection.Input || t.specifiedDirection == SpecifiedDirection.Output
@@ -383,7 +383,7 @@ private[chisel3] object Converter {
   }
 
   def convert(name: String, param: Param): fir.Param = param match {
-    case IntParam(value)    => fir.IntParam(name, value)
+    case IntParam(value) => fir.IntParam(name, value)
     case DoubleParam(value) => fir.DoubleParam(name, value)
     case StringParam(value) => fir.StringParam(name, fir.StringLit(value))
     case PrintableParam(value, id) => {
@@ -409,10 +409,10 @@ private[chisel3] object Converter {
     val resolvedDir = SpecifiedDirection.fromParent(topDir, firrtlUserDirOf(port.id))
     val dir = resolvedDir match {
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Output => fir.Output
-      case SpecifiedDirection.Flip | SpecifiedDirection.Input         => fir.Input
+      case SpecifiedDirection.Flip | SpecifiedDirection.Input => fir.Input
     }
     val clearDir = resolvedDir match {
-      case SpecifiedDirection.Input | SpecifiedDirection.Output     => true
+      case SpecifiedDirection.Input | SpecifiedDirection.Output => true
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false
     }
     val tpe = extractType(port.id, clearDir, port.sourceInfo, true, true, typeAliases)
@@ -457,7 +457,7 @@ private[chisel3] object Converter {
   def convertLayer(layer: Layer): fir.Layer = {
     val config = layer.config match {
       case LayerConfig.Extract(outputDir) => fir.LayerConfig.Extract(outputDir)
-      case LayerConfig.Inline             => fir.LayerConfig.Inline
+      case LayerConfig.Inline => fir.LayerConfig.Inline
     }
     fir.Layer(convert(layer.sourceInfo), layer.name, config, layer.children.map(convertLayer))
   }
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0078fccc581..6cdb0b9ee38 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -73,21 +73,21 @@ private[chisel3] object ir {
     def localName:                      String = name
     def contextualName(ctx: Component): String = name
     def fullName(ctx:       Component): String = contextualName(ctx)
-    def name:                           String
+    def name: String
   }
 
   case class Node(id: HasId) extends Arg {
     override def contextualName(ctx: Component): String = id.getOptionRef match {
       case Some(arg) => arg.contextualName(ctx)
-      case None      => id.instanceName
+      case None => id.instanceName
     }
     override def localName: String = id.getOptionRef match {
       case Some(arg) => arg.localName
-      case None      => id.instanceName
+      case None => id.instanceName
     }
     def name: String = id.getOptionRef match {
       case Some(arg) => arg.name
-      case None      => id.instanceName
+      case None => id.instanceName
     }
   }
 
@@ -98,16 +98,16 @@ private[chisel3] object ir {
       case Some(Index(Node(imm), Node(value))) =>
         s"${earlyLocalName(imm, includeRoot)}[${earlyLocalName(value, includeRoot)}]"
       case Some(LitIndex(Node(imm), idx)) => s"${earlyLocalName(imm, includeRoot)}[$idx]"
-      case Some(Index(Node(imm), arg))    => s"${earlyLocalName(imm, includeRoot)}[${arg.localName}]"
-      case Some(Slot(Node(imm), name))    => s"${earlyLocalName(imm, includeRoot)}.$name"
-      case Some(OpaqueSlot(Node(imm)))    => s"${earlyLocalName(imm, includeRoot)}"
-      case Some(ProbeExpr(Node(ref)))     => s"${earlyLocalName(ref, includeRoot)}"
-      case Some(RWProbeExpr(Node(ref)))   => s"${earlyLocalName(ref, includeRoot)}"
-      case Some(ProbeRead(Node(ref)))     => s"${earlyLocalName(ref, includeRoot)}"
-      case Some(arg) if includeRoot       => arg.name
+      case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm, includeRoot)}[${arg.localName}]"
+      case Some(Slot(Node(imm), name)) => s"${earlyLocalName(imm, includeRoot)}.$name"
+      case Some(OpaqueSlot(Node(imm))) => s"${earlyLocalName(imm, includeRoot)}"
+      case Some(ProbeExpr(Node(ref))) => s"${earlyLocalName(ref, includeRoot)}"
+      case Some(RWProbeExpr(Node(ref))) => s"${earlyLocalName(ref, includeRoot)}"
+      case Some(ProbeRead(Node(ref))) => s"${earlyLocalName(ref, includeRoot)}"
+      case Some(arg) if includeRoot => arg.name
       case None if includeRoot =>
         id match {
-          case data: Data          => data._computeName(Some("?")).get
+          case data: Data => data._computeName(Some("?")).get
           case obj:  DynamicObject => obj._computeName(Some("?")).get
           case _ => "?"
         }
@@ -284,7 +284,7 @@ private[chisel3] object ir {
   }
 
   abstract class Definition extends Command {
-    def id:   HasId
+    def id: HasId
     def name: String = id.getRef.name
   }
 
@@ -384,7 +384,7 @@ private[chisel3] object ir {
   class When(val sourceInfo: SourceInfo, val pred: Arg) extends Command {
     val ifRegion = new Block(sourceInfo)
     private var _elseRegion: Block = null
-    def hasElse:             Boolean = _elseRegion != null
+    def hasElse: Boolean = _elseRegion != null
     def elseRegion: Block = {
       if (_elseRegion == null) {
         _elseRegion = new Block(sourceInfo)
@@ -469,9 +469,9 @@ private[chisel3] object ir {
   ) extends Definition
 
   abstract class Component extends Arg {
-    def id:          BaseModule
-    def name:        String
-    def ports:       Seq[Port]
+    def id:    BaseModule
+    def name:  String
+    def ports: Seq[Port]
     val secretPorts: mutable.ArrayBuffer[Port] = id.secretPorts
   }
 
diff --git a/core/src/main/scala/chisel3/internal/package.scala b/core/src/main/scala/chisel3/internal/package.scala
index b3c96c2398e..b282d542020 100644
--- a/core/src/main/scala/chisel3/internal/package.scala
+++ b/core/src/main/scala/chisel3/internal/package.scala
@@ -97,8 +97,8 @@ package object internal {
         else if (targetWidth > thatWidth) _padHandleBool(that, targetWidth, isUInt)
         else fromUInt(that.take(targetWidth))
       case (Some(targetWidth), None) => fromUInt(_padHandleBool(that, targetWidth, isUInt).take(targetWidth))
-      case (None, Some(thatWidth))   => that
-      case (None, None)              => that
+      case (None, Some(thatWidth)) => that
+      case (None, None) => that
     }
   }
 
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index 9bdf9109808..19ada792a68 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -107,10 +107,10 @@ package object chisel3 {
       val (base, num) = n.splitAt(1)
       val radix = base match {
         case "x" | "h" => 16
-        case "d"       => 10
-        case "o"       => 8
-        case "b"       => 2
-        case _         => Builder.error(s"Invalid base $base")(UnlocatableSourceInfo); 2
+        case "d" => 10
+        case "o" => 8
+        case "b" => 2
+        case _ => Builder.error(s"Invalid base $base")(UnlocatableSourceInfo); 2
       }
       BigInt(num.filterNot(_ == '_'), radix)
     }
@@ -281,8 +281,8 @@ package object chisel3 {
           val fmtArg: Printable = arg match {
             case d: Data => {
               fmt match {
-                case Some("%n")                          => Name(d)
-                case Some("%N")                          => FullName(d)
+                case Some("%n") => Name(d)
+                case Some("%N") => FullName(d)
                 case Some(fForm) if d.isInstanceOf[Bits] => FirrtlFormat(fForm.substring(1, 2), d)
                 case Some(x) => {
                   val msg = s"Illegal format specifier '$x' for Chisel Data type!\n"
@@ -334,7 +334,7 @@ package object chisel3 {
     private def getCauses(throwable: Throwable, acc: Seq[Throwable] = Seq.empty): Seq[Throwable] =
       throwable.getCause() match {
         case null => throwable +: acc
-        case a    => getCauses(a, throwable +: acc)
+        case a => getCauses(a, throwable +: acc)
       }
 
     /** Returns true if an exception contains */
diff --git a/core/src/main/scala/chisel3/probe/ProbeBase.scala b/core/src/main/scala/chisel3/probe/ProbeBase.scala
index fad54b1961c..915613a87bb 100644
--- a/core/src/main/scala/chisel3/probe/ProbeBase.scala
+++ b/core/src/main/scala/chisel3/probe/ProbeBase.scala
@@ -37,7 +37,7 @@ private[chisel3] trait ProbeBase {
     val color = _color.map(c =>
       Builder.inContext match {
         case false => c
-        case true  => Builder.layerMap.getOrElse(c, c)
+        case true => Builder.layerMap.getOrElse(c, c)
       }
     )
     // Record the layer in the builder if we are in a builder context.
diff --git a/core/src/main/scala/chisel3/properties/Path.scala b/core/src/main/scala/chisel3/properties/Path.scala
index f97a0284a49..0b0cce06d97 100644
--- a/core/src/main/scala/chisel3/properties/Path.scala
+++ b/core/src/main/scala/chisel3/properties/Path.scala
@@ -23,14 +23,14 @@ private[properties] sealed abstract class TargetPath extends Path {
     val target = toTarget()
     val targetType = if (isMemberPath) {
       target match {
-        case _: ModuleTarget    => "OMMemberInstanceTarget"
-        case _: InstanceTarget  => "OMMemberInstanceTarget"
+        case _: ModuleTarget => "OMMemberInstanceTarget"
+        case _: InstanceTarget => "OMMemberInstanceTarget"
         case _: ReferenceTarget => "OMMemberReferenceTarget"
       }
     } else {
       target match {
-        case _: ModuleTarget    => "OMInstanceTarget"
-        case _: InstanceTarget  => "OMInstanceTarget"
+        case _: ModuleTarget => "OMInstanceTarget"
+        case _: InstanceTarget => "OMInstanceTarget"
         case _: ReferenceTarget => "OMReferenceTarget"
       }
     }
diff --git a/core/src/main/scala/chisel3/properties/Property.scala b/core/src/main/scala/chisel3/properties/Property.scala
index af4f27042bf..08f1e1f10ae 100644
--- a/core/src/main/scala/chisel3/properties/Property.scala
+++ b/core/src/main/scala/chisel3/properties/Property.scala
@@ -62,7 +62,7 @@ private[chisel3] object RecursivePropertyType {
 private[chisel3] trait SimplePropertyType[T] extends RecursivePropertyType[T] {
   final type Type = T
   final type Underlying = T
-  def convert(value:           T):                                      fir.Expression
+  def convert(value:           T): fir.Expression
   def convert(value:           T, ctx: ir.Component, info: SourceInfo): fir.Expression = convert(value)
   def convertUnderlying(value: T):                                      T = value
 }
@@ -255,7 +255,7 @@ sealed trait Property[T] extends Element { self =>
     */
   override def isLit: Boolean = topBindingOpt match {
     case Some(PropertyValueBinding) => true
-    case _                          => false
+    case _ => false
   }
 
   def toPrintable: Printable = {
diff --git a/core/src/main/scala/chisel3/reflect/DataMirror.scala b/core/src/main/scala/chisel3/reflect/DataMirror.scala
index d54e351bdd7..b847f68fdbd 100644
--- a/core/src/main/scala/chisel3/reflect/DataMirror.scala
+++ b/core/src/main/scala/chisel3/reflect/DataMirror.scala
@@ -25,7 +25,7 @@ object DataMirror {
     import chisel3.SpecifiedDirection.{Flip, Input}
     target.specifiedDirection match {
       case Flip | Input => true
-      case _            => false
+      case _ => false
     }
   }
 
@@ -33,7 +33,7 @@ object DataMirror {
     // Cannot use isDefined because of the ClassTag
     target.topBindingOpt match {
       case Some(b: B) => true
-      case _          => false
+      case _ => false
     }
   }
 
@@ -448,7 +448,7 @@ object DataMirror {
         case (Some(l), Some(r)) =>
           collector.lift((l, r)) match {
             case Some(x) => Some((Some(x), None))
-            case None    => None
+            case None => None
           }
         case other => None
       }
@@ -457,7 +457,7 @@ object DataMirror {
       case (Some(l), Some(r)) =>
         collector.lift((l, r)) match {
           case Some(x) => Some((Some(x), None))
-          case None    => None
+          case None => None
         }
       case other => None
     }.collect {
@@ -480,7 +480,7 @@ object DataMirror {
     collectMembersOverAllForAnyFunction(Some(left), Some(right)) { case (lOpt: Option[D], rOpt: Option[D]) =>
       collector.lift((lOpt, rOpt)) match {
         case Some(x) => Some((Some(x), None))
-        case None    => None
+        case None => None
       }
     }.collect { case (Some(x), None) =>
       x
@@ -519,9 +519,9 @@ object DataMirror {
     right: Option[D]
   )(collector: ((Option[D], Option[D])) => Option[(Option[L], Option[R])]): Seq[(Option[L], Option[R])] = {
     val myItems = collector((left, right)) match {
-      case None               => Nil
+      case None => Nil
       case Some((None, None)) => Nil
-      case Some(other)        => Seq(other)
+      case Some(other) => Seq(other)
     }
     val matcher = implicitly[HasMatchingZipOfChildren[D]]
     val childItems = matcher.matchingZipOfChildren(left, right).flatMap { case (l, r) =>
@@ -534,7 +534,7 @@ object DataMirror {
   private[chisel3] def modulePath(h: HasId, until: Option[BaseModule]): Seq[BaseModule] = {
     val me = h match {
       case m: BaseModule => Seq(m)
-      case d: Data       => d.topBinding.location.toSeq
+      case d: Data => d.topBinding.location.toSeq
       case m: MemBase[_] => m._parent.toSeq
     }
     if (me == until.toSeq) Nil
diff --git a/firrtl/src/main/scala/firrtl/FileUtils.scala b/firrtl/src/main/scala/firrtl/FileUtils.scala
index c3f2f405252..b798fb0f2c1 100644
--- a/firrtl/src/main/scala/firrtl/FileUtils.scala
+++ b/firrtl/src/main/scala/firrtl/FileUtils.scala
@@ -35,7 +35,7 @@ object FileUtils {
     * @param pathName an absolute or relative path string
     */
   def getPath(pathName: String): os.Path = os.FilePath(pathName) match {
-    case path: os.Path    => path
+    case path: os.Path => path
     case sub:  os.SubPath => os.pwd / sub
     case rel:  os.RelPath => os.pwd / rel
   }
diff --git a/firrtl/src/main/scala/firrtl/RenameMap.scala b/firrtl/src/main/scala/firrtl/RenameMap.scala
index 4b04fea6ed2..432c8c6ccc6 100644
--- a/firrtl/src/main/scala/firrtl/RenameMap.scala
+++ b/firrtl/src/main/scala/firrtl/RenameMap.scala
@@ -55,10 +55,10 @@ sealed trait RenameMap {
 
   protected def _recordAll(map: collection.Map[CompleteTarget, Seq[CompleteTarget]]): Unit =
     map.foreach {
-      case (from: IsComponent, tos: Seq[_])   => completeRename(from, tos)
-      case (from: IsModule, tos: Seq[_])      => completeRename(from, tos)
+      case (from: IsComponent, tos: Seq[_]) => completeRename(from, tos)
+      case (from: IsModule, tos: Seq[_]) => completeRename(from, tos)
       case (from: CircuitTarget, tos: Seq[_]) => completeRename(from, tos)
-      case other                              => Utils.throwInternalError(s"Illegal rename: ${other._1} -> ${other._2}")
+      case other => Utils.throwInternalError(s"Illegal rename: ${other._1} -> ${other._2}")
     }
 
   /** Renames a [[firrtl.annotations.CompleteTarget CompleteTarget]]
@@ -208,7 +208,7 @@ sealed trait RenameMap {
               val parent = t.copy(component = t.component.dropRight(1))
               traverseTokens(parent).map(_.flatMap { x =>
                 (x, last) match {
-                  case (t2: InstanceTarget, Field(f))  => Some(t2.ref(f))
+                  case (t2: InstanceTarget, Field(f)) => Some(t2.ref(f))
                   case (t2: ReferenceTarget, Field(f)) => Some(t2.field(f))
                   case (t2: ReferenceTarget, Index(i)) => Some(t2.index(i))
                   case other =>
@@ -284,7 +284,7 @@ sealed trait RenameMap {
               val stripped = t.copy(path = t.path.tail, module = outerMod)
               traverseLeft(stripped).map(_.map {
                 case absolute if absolute.circuit == absolute.module => absolute
-                case relative                                        => relative.addHierarchy(t.module, outerInst)
+                case relative => relative.addHierarchy(t.module, outerInst)
               })
           }
         }
@@ -431,9 +431,9 @@ sealed trait RenameMap {
   private def recursiveGet(errors: mutable.ArrayBuffer[String])(key: CompleteTarget): Seq[CompleteTarget] = {
     // rename just the component portion; path/ref/component for ReferenceTargets or path/instance for InstanceTargets
     val componentRename = key match {
-      case t:   CircuitTarget                  => None
-      case t:   ModuleTarget                   => None
-      case t:   InstanceTarget                 => instanceGet(errors)(t)
+      case t:   CircuitTarget => None
+      case t:   ModuleTarget => None
+      case t:   InstanceTarget => instanceGet(errors)(t)
       case ref: ReferenceTarget if ref.isLocal => referenceGet(errors)(ref)
       case ref @ ReferenceTarget(c, m, p, r, t) =>
         val (Instance(inst), OfModule(ofMod)) = p.last
@@ -452,7 +452,7 @@ sealed trait RenameMap {
     } else {
       key match {
         case t: CircuitTarget => None
-        case t: ModuleTarget  => moduleGet(errors)(t)
+        case t: ModuleTarget => moduleGet(errors)(t)
         case t: IsComponent =>
           ofModuleGet(errors)(t) match {
             case AbsoluteOfModule(absolute) =>
@@ -519,7 +519,7 @@ sealed trait RenameMap {
           circuitGet(errors)(CircuitTarget(t.circuit)).map { case CircuitTarget(c) =>
             t match {
               case ref:  ReferenceTarget => ref.copy(circuit = c)
-              case inst: InstanceTarget  => inst.copy(circuit = c)
+              case inst: InstanceTarget => inst.copy(circuit = c)
             }
           }
       }
diff --git a/firrtl/src/main/scala/firrtl/Utils.scala b/firrtl/src/main/scala/firrtl/Utils.scala
index 1ee02c30e1a..441af1bcc66 100644
--- a/firrtl/src/main/scala/firrtl/Utils.scala
+++ b/firrtl/src/main/scala/firrtl/Utils.scala
@@ -69,7 +69,7 @@ object Utils extends LazyLogging {
     case vx: BundleType =>
       vx.fields.find(_.name == s) match {
         case Some(f) => f.tpe
-        case None    => UnknownType
+        case None => UnknownType
       }
     case vx => UnknownType
   }
diff --git a/firrtl/src/main/scala/firrtl/annotations/AnnotationUtils.scala b/firrtl/src/main/scala/firrtl/annotations/AnnotationUtils.scala
index 75562407cb7..7b6c69e4e2d 100644
--- a/firrtl/src/main/scala/firrtl/annotations/AnnotationUtils.scala
+++ b/firrtl/src/main/scala/firrtl/annotations/AnnotationUtils.scala
@@ -36,14 +36,14 @@ object AnnotationUtils {
   val SerializedModuleName = """([a-zA-Z_][a-zA-Z_0-9~!@#$%^*\-+=?/]*)""".r
   def validModuleName(s: String): Boolean = s match {
     case SerializedModuleName(name) => true
-    case _                          => false
+    case _ => false
   }
 
   /** Returns true if a valid component/subcomponent name */
   val SerializedComponentName = """([a-zA-Z_][a-zA-Z_0-9\[\]\.~!@#$%^*\-+=?/]*)""".r
   def validComponentName(s: String): Boolean = s match {
     case SerializedComponentName(name) => true
-    case _                             => false
+    case _ => false
   }
 
   /** Tokenizes a string with '[', ']', '.' as tokens, e.g.:
@@ -54,15 +54,15 @@ object AnnotationUtils {
       val i = s.indexWhere(c => "[].".contains(c))
       s.slice(0, i) match {
         case "" => s(i).toString +: tokenize(s.drop(i + 1))
-        case x  => x +: s(i).toString +: tokenize(s.drop(i + 1))
+        case x => x +: s(i).toString +: tokenize(s.drop(i + 1))
       }
     case None if s == "" => Nil
-    case None            => Seq(s)
+    case None => Seq(s)
   }
 
   def toNamed(s: String): Named = s.split("\\.", 3) match {
-    case Array(n)       => CircuitName(n)
-    case Array(c, m)    => ModuleName(m, CircuitName(c))
+    case Array(n) => CircuitName(n)
+    case Array(c, m) => ModuleName(m, CircuitName(c))
     case Array(c, m, x) => ComponentName(x, ModuleName(m, CircuitName(c)))
   }
 
@@ -73,9 +73,9 @@ object AnnotationUtils {
   def toSubComponents(s: String): Seq[TargetToken] = {
     import TargetToken._
     def exp2subcomp(e: ir.Expression): Seq[TargetToken] = e match {
-      case ir.Reference(name, _)      => Seq(Ref(name))
+      case ir.Reference(name, _) => Seq(Ref(name))
       case ir.SubField(expr, name, _) => exp2subcomp(expr) :+ Field(name)
-      case ir.SubIndex(expr, idx, _)  => exp2subcomp(expr) :+ Index(idx)
+      case ir.SubIndex(expr, idx, _) => exp2subcomp(expr) :+ Index(idx)
       case ir.SubAccess(expr, idx, _) =>
         Utils.throwInternalError(s"For string $s, cannot convert a subaccess $e into a Target")
     }
@@ -94,10 +94,10 @@ object AnnotationUtils {
           Utils.error("Cannot find closing bracket ]")
         } else
           tokens(index) match {
-            case "["               => findClose(tokens, index + 1, nOpen + 1)
+            case "[" => findClose(tokens, index + 1, nOpen + 1)
             case "]" if nOpen == 1 => tokens.slice(1, index)
-            case "]"               => findClose(tokens, index + 1, nOpen - 1)
-            case _                 => findClose(tokens, index + 1, nOpen)
+            case "]" => findClose(tokens, index + 1, nOpen - 1)
+            case _ => findClose(tokens, index + 1, nOpen)
           }
       }
       def buildup(e: Expression, tokens: Seq[String]): Expression = tokens match {
@@ -105,7 +105,7 @@ object AnnotationUtils {
           val indexOrAccess = findClose(tokens, 0, 0)
           val exp = indexOrAccess.head match {
             case DecPattern(d) => SubIndex(e, d.toInt, UnknownType)
-            case _             => SubAccess(e, parse(indexOrAccess), UnknownType)
+            case _ => SubAccess(e, parse(indexOrAccess), UnknownType)
           }
           buildup(exp, tokens.drop(2 + indexOrAccess.size))
         case "." :: tail =>
diff --git a/firrtl/src/main/scala/firrtl/annotations/JsonProtocol.scala b/firrtl/src/main/scala/firrtl/annotations/JsonProtocol.scala
index 87162b0b25a..513bba140d3 100644
--- a/firrtl/src/main/scala/firrtl/annotations/JsonProtocol.scala
+++ b/firrtl/src/main/scala/firrtl/annotations/JsonProtocol.scala
@@ -227,7 +227,7 @@ object JsonProtocol extends LazyLogging {
     def getAnnotationNameFromMappingException(mappingException: MappingException): String = {
       mappingException.getMessage match {
         case GetClassPattern(name) => name
-        case other                 => other
+        case other => other
       }
     }
 
@@ -243,7 +243,7 @@ object JsonProtocol extends LazyLogging {
             throw new InvalidAnnotationJSONException(s"Expected field 'class' not found! $fields")
           hint ++: findTypeHints(fields.map(_._2))
         case JArray(arr) => findTypeHints(arr)
-        case _           => Seq()
+        case _ => Seq()
       })
       .distinct
 
diff --git a/firrtl/src/main/scala/firrtl/annotations/LoadMemoryAnnotation.scala b/firrtl/src/main/scala/firrtl/annotations/LoadMemoryAnnotation.scala
index 8605662f702..66d689d18c8 100644
--- a/firrtl/src/main/scala/firrtl/annotations/LoadMemoryAnnotation.scala
+++ b/firrtl/src/main/scala/firrtl/annotations/LoadMemoryAnnotation.scala
@@ -21,7 +21,7 @@ object MemoryLoadFileType {
   def deserialize(s: String): MemoryLoadFileType = s match {
     case "h" => MemoryLoadFileType.Hex
     case "b" => MemoryLoadFileType.Binary
-    case _   => throw new FirrtlUserException(s"Unrecognized MemoryLoadFileType: $s")
+    case _ => throw new FirrtlUserException(s"Unrecognized MemoryLoadFileType: $s")
   }
 }
 
diff --git a/firrtl/src/main/scala/firrtl/annotations/Target.scala b/firrtl/src/main/scala/firrtl/annotations/Target.scala
index 87681be5ea6..738329d1a42 100644
--- a/firrtl/src/main/scala/firrtl/annotations/Target.scala
+++ b/firrtl/src/main/scala/firrtl/annotations/Target.scala
@@ -40,14 +40,14 @@ sealed trait Target extends Named {
     val circuitString = "~" + circuitOpt.getOrElse("???")
     val moduleString = "|" + moduleOpt.getOrElse("???")
     val tokensString = tokens.map {
-      case Ref(r)               => s">$r"
-      case Instance(i)          => s"/$i"
-      case OfModule(o)          => s":$o"
+      case Ref(r) => s">$r"
+      case Instance(i) => s"/$i"
+      case OfModule(o) => s":$o"
       case TargetToken.Field(f) => s".$f"
-      case Index(v)             => s"[$v]"
-      case Clock                => s"@clock"
-      case Reset                => s"@reset"
-      case Init                 => s"@init"
+      case Index(v) => s"[$v]"
+      case Clock => s"@clock"
+      case Reset => s"@reset"
+      case Init => s"@init"
     }.mkString("")
     if (moduleOpt.isEmpty && tokens.isEmpty) {
       circuitString
@@ -66,20 +66,20 @@ sealed trait Target extends Named {
     val moduleString = s"""\n$tab└── module ${moduleOpt.getOrElse("???")}:"""
     var depth = 4
     val tokenString = tokens.map {
-      case Ref(r)      => val rx = s"""\n$tab${" " * depth}└── $r"""; depth += 4; rx
+      case Ref(r) => val rx = s"""\n$tab${" " * depth}└── $r"""; depth += 4; rx
       case Instance(i) => val ix = s"""\n$tab${" " * depth}└── inst $i """; ix
       case OfModule(o) => val ox = s"of $o:"; depth += 4; ox
-      case Field(f)    => s".$f"
-      case Index(v)    => s"[$v]"
-      case Clock       => s"@clock"
-      case Reset       => s"@reset"
-      case Init        => s"@init"
+      case Field(f) => s".$f"
+      case Index(v) => s"[$v]"
+      case Clock => s"@clock"
+      case Reset => s"@reset"
+      case Init => s"@init"
     }.mkString("")
 
     (moduleOpt.isEmpty, tokens.isEmpty) match {
       case (true, true) => circuitString
-      case (_, true)    => circuitString + moduleString
-      case (_, _)       => circuitString + moduleString + tokenString
+      case (_, true) => circuitString + moduleString
+      case (_, _) => circuitString + moduleString + tokenString
     }
   }
 
@@ -114,13 +114,13 @@ sealed trait Target extends Named {
 object Target {
   def asTarget(m: ModuleTarget)(e: Expression): ReferenceTarget = e match {
     case r: ir.Reference => m.ref(r.name)
-    case s: ir.SubIndex  => asTarget(m)(s.expr).index(s.value)
-    case s: ir.SubField  => asTarget(m)(s.expr).field(s.name)
+    case s: ir.SubIndex => asTarget(m)(s.expr).index(s.value)
+    case s: ir.SubField => asTarget(m)(s.expr).field(s.name)
     case s: ir.SubAccess => asTarget(m)(s.expr).field("@" + s.index.serialize)
-    case d: DoPrim       => m.ref("@" + d.serialize)
-    case d: Mux          => m.ref("@" + d.serialize)
-    case d: ValidIf      => m.ref("@" + d.serialize)
-    case d: Literal      => m.ref("@" + d.serialize)
+    case d: DoPrim => m.ref("@" + d.serialize)
+    case d: Mux => m.ref("@" + d.serialize)
+    case d: ValidIf => m.ref("@" + d.serialize)
+    case d: Literal => m.ref("@" + d.serialize)
     case other => sys.error(s"Unsupported: $other")
   }
 
@@ -153,7 +153,7 @@ object Target {
       tokens.tail.zip(tokens.tail.tail).foreach {
         case (".", value: String) => subComps += Field(value)
         case ("[", value: String) => subComps += Index(value.toInt)
-        case other                =>
+        case other =>
       }
     }
     subComps.toSeq
@@ -179,15 +179,15 @@ object Target {
             if (value == "???") t else t.copy(circuitOpt = Some(value))
           case '|' if t.moduleOpt.isEmpty && t.tokens.isEmpty =>
             if (value == "???") t else t.copy(moduleOpt = Some(value))
-          case '/'                                  => t.add(Instance(value))
-          case ':'                                  => t.add(OfModule(value))
-          case '>'                                  => t.add(Ref(value))
-          case '.'                                  => t.add(Field(value))
+          case '/' => t.add(Instance(value))
+          case ':' => t.add(OfModule(value))
+          case '>' => t.add(Ref(value))
+          case '.' => t.add(Field(value))
           case '[' if value.dropRight(1).toInt >= 0 => t.add(Index(value.dropRight(1).toInt))
-          case '@' if value == "clock"              => t.add(Clock)
-          case '@' if value == "init"               => t.add(Init)
-          case '@' if value == "reset"              => t.add(Reset)
-          case other                                => throw NamedException(s"Cannot deserialize Target: $s")
+          case '@' if value == "clock" => t.add(Clock)
+          case '@' if value == "init" => t.add(Init)
+          case '@' if value == "reset" => t.add(Reset)
+          case other => throw NamedException(s"Cannot deserialize Target: $s")
         }
       }
       .tryToComplete
@@ -201,15 +201,15 @@ object Target {
     * @note This differs from [[InstanceTarget.pathlessTarget]] which refers to the module instantiating the instance.
     */
   def referringModule(a: IsMember): ModuleTarget = a match {
-    case b: ModuleTarget    => b
-    case b: InstanceTarget  => b.ofModuleTarget
+    case b: ModuleTarget => b
+    case b: InstanceTarget => b.ofModuleTarget
     case b: ReferenceTarget => b.pathlessTarget.moduleTarget
   }
 
   def getPathlessTarget(t: Target): Target = {
     t.tryToComplete match {
       case c: CircuitTarget => c
-      case m: IsMember      => m.pathlessTarget
+      case m: IsMember => m.pathlessTarget
       case t: GenericTarget if t.isLegal =>
         val newTokens = t.tokens.dropWhile(x => x.isInstanceOf[Instance] || x.isInstanceOf[OfModule])
         GenericTarget(t.circuitOpt, t.moduleOpt, newTokens)
@@ -225,7 +225,7 @@ object Target {
             case x: Field => true
             case x: Index => true
             case Clock => true
-            case Init  => true
+            case Init => true
             case Reset => true
             case other => false
           })
@@ -248,16 +248,16 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
 
   override def toNamed: Named = getComplete match {
     case Some(c: IsComponent) if c.isLocal => c.toNamed
-    case Some(c: ModuleTarget)             => c.toNamed
-    case Some(c: CircuitTarget)            => c.toNamed
-    case other                             => throw Target.NamedException(s"Cannot convert $this to [[Named]]")
+    case Some(c: ModuleTarget) => c.toNamed
+    case Some(c: CircuitTarget) => c.toNamed
+    case other => throw Target.NamedException(s"Cannot convert $this to [[Named]]")
   }
 
   override def toTarget: CompleteTarget = getComplete.get
 
   override def getComplete: Option[CompleteTarget] = this match {
-    case GenericTarget(Some(c), None, Vector())               => Some(CircuitTarget(c))
-    case GenericTarget(Some(c), Some(m), Vector())            => Some(ModuleTarget(c, m))
+    case GenericTarget(Some(c), None, Vector()) => Some(CircuitTarget(c))
+    case GenericTarget(Some(c), Some(m), Vector()) => Some(ModuleTarget(c, m))
     case GenericTarget(Some(c), Some(m), Ref(r) +: component) => Some(ReferenceTarget(c, m, Nil, r, component))
     case GenericTarget(Some(c), Some(m), Instance(i) +: OfModule(o) +: Vector()) =>
       Some(InstanceTarget(c, m, Nil, i, o))
@@ -265,7 +265,7 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
       val path = getPath.getOrElse(Nil)
       ((getRef, getInstanceOf): @unchecked) match {
         case (Some((r, comps)), _) => Some(ReferenceTarget(c, m, path, r, comps))
-        case (None, Some((i, o)))  => Some(InstanceTarget(c, m, path, i, o))
+        case (None, Some((i, o))) => Some(InstanceTarget(c, m, path, i, o))
       }
     case _ /* the target is not Complete */ => None
   }
@@ -293,9 +293,9 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
     */
   def getRef: Option[(String, Seq[TargetToken])] = if (isComplete) {
     val (optRef, comps) = tokens.foldLeft((None: Option[String], Vector.empty[TargetToken])) {
-      case ((None, v), Ref(r))           => (Some(r), v)
+      case ((None, v), Ref(r)) => (Some(r), v)
       case ((r: Some[String], comps), c) => (r, comps :+ c)
-      case ((r, v), other)               => (None, v)
+      case ((r, v), other) => (None, v)
     }
     optRef.map(x => (x, comps))
   } else {
@@ -308,7 +308,7 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
   def getInstanceOf: Option[(String, String)] = if (isComplete) {
     tokens.grouped(2).foldLeft(None: Option[(String, String)]) {
       case (instOf, Seq(i: Instance, o: OfModule)) => Some((i.value, o.value))
-      case (instOf, _)                             => None
+      case (instOf, _) => None
     }
   } else {
     None
@@ -331,10 +331,10 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
     token match {
       case _: Instance => requireLast(true, "inst", "of")
       case _: OfModule => requireLast(false, "inst")
-      case _: Ref      => requireLast(true, "inst", "of")
-      case _: Field    => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
-      case _: Index    => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
-      case Init  => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
+      case _: Ref => requireLast(true, "inst", "of")
+      case _: Field => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
+      case _: Index => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
+      case Init => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
       case Clock => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
       case Reset => requireLast(true, "ref", "[]", ".", "init", "clock", "reset")
     }
@@ -375,9 +375,9 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
   def isComplete: Boolean = {
     isLegal && (isCircuitTarget || isModuleTarget || (isComponentTarget && tokens.tails.forall {
       case Instance(_) +: OfModule(_) +: tail => true
-      case Instance(_) +: x +: tail           => false
-      case x +: OfModule(_) +: tail           => false
-      case _                                  => true
+      case Instance(_) +: x +: tail => false
+      case x +: OfModule(_) +: tail => false
+      case _ => true
     }))
   }
 
@@ -386,7 +386,7 @@ case class GenericTarget(circuitOpt: Option[String], moduleOpt: Option[String],
   def isComponentTarget: Boolean = circuitOpt.nonEmpty && moduleOpt.nonEmpty && tokens.nonEmpty
 
   lazy val (parentModule: Option[String], astModule: Option[String]) = path match {
-    case Seq()                 => (None, moduleOpt)
+    case Seq() => (None, moduleOpt)
     case Seq((i, OfModule(o))) => (moduleOpt, Some(o))
     case seq =>
       val reversed = seq.reverse
@@ -508,10 +508,10 @@ trait IsComponent extends IsMember {
         case Seq(Ref(name)) => ComponentName(name, mn)
         case Ref(_) :: tail if Target.isOnly(tail, ".", "[]") =>
           val name = tokens.foldLeft("") {
-            case ("", Ref(name))        => name
+            case ("", Ref(name)) => name
             case (string, Field(value)) => s"$string.$value"
             case (string, Index(value)) => s"$string[$value]"
-            case (_, token)             => Utils.error(s"Unexpected token: $token")
+            case (_, token) => Utils.error(s"Unexpected token: $token")
           }
           ComponentName(name, mn)
         case Seq(Instance(name), OfModule(o)) => ComponentName(name, mn)
@@ -654,7 +654,7 @@ case class ReferenceTarget(
       baseType
     } else {
       val headType = tokens.head match {
-        case Index(idx)   => sub_type(baseType)
+        case Index(idx) => sub_type(baseType)
         case Field(field) => field_type(baseType, field)
         case _: Ref => baseType
         case token => Utils.error(s"Unexpected token $token")
@@ -718,15 +718,15 @@ case class ReferenceTarget(
   def leafSubTargets(tpe: firrtl.ir.Type): Seq[ReferenceTarget] = tpe match {
     case _: firrtl.ir.GroundType => Vector(this)
     case firrtl.ir.VectorType(t, size) => (0 until size).flatMap { i => index(i).leafSubTargets(t) }
-    case firrtl.ir.BundleType(fields)  => fields.flatMap { f => field(f.name).leafSubTargets(f.tpe) }
-    case other                         => sys.error(s"Error! Unexpected type $other")
+    case firrtl.ir.BundleType(fields) => fields.flatMap { f => field(f.name).leafSubTargets(f.tpe) }
+    case other => sys.error(s"Error! Unexpected type $other")
   }
 
   def allSubTargets(tpe: firrtl.ir.Type): Seq[ReferenceTarget] = tpe match {
     case _: firrtl.ir.GroundType => Vector(this)
     case firrtl.ir.VectorType(t, size) => this +: (0 until size).flatMap { i => index(i).allSubTargets(t) }
-    case firrtl.ir.BundleType(fields)  => this +: fields.flatMap { f => field(f.name).allSubTargets(f.tpe) }
-    case other                         => sys.error(s"Error! Unexpected type $other")
+    case firrtl.ir.BundleType(fields) => this +: fields.flatMap { f => field(f.name).allSubTargets(f.tpe) }
+    case other => sys.error(s"Error! Unexpected type $other")
   }
 
   override def leafModule: String = encapsulatingModule
@@ -838,7 +838,7 @@ final case class ComponentName(name: String, module: ModuleName) extends Named {
   def toTarget: ReferenceTarget = {
     Target.toTargetTokens(name).toList match {
       case Ref(r) :: components => ReferenceTarget(module.circuit.name, module.name, Nil, r, components)
-      case other                => throw Target.NamedException(s"Cannot convert $this into [[ReferenceTarget]]: $other")
+      case other => throw Target.NamedException(s"Cannot convert $this into [[ReferenceTarget]]: $other")
     }
   }
 }
diff --git a/firrtl/src/main/scala/firrtl/ir/IR.scala b/firrtl/src/main/scala/firrtl/ir/IR.scala
index b58f61f29ea..d6aa60601a1 100644
--- a/firrtl/src/main/scala/firrtl/ir/IR.scala
+++ b/firrtl/src/main/scala/firrtl/ir/IR.scala
@@ -140,12 +140,12 @@ object StringLit {
   /** Maps characters to ASCII for Verilog emission */
   private def toASCII(char: Char): List[Char] = char match {
     case nonASCII if !nonASCII.isValidByte => List('?')
-    case '"'                               => List('\\', '"')
-    case '\\'                              => List('\\', '\\')
-    case c if c >= ' ' && c <= '~'         => List(c)
-    case '\n'                              => List('\\', 'n')
-    case '\t'                              => List('\\', 't')
-    case _                                 => List('?')
+    case '"' => List('\\', '"')
+    case '\\' => List('\\', '\\')
+    case c if c >= ' ' && c <= '~' => List(c)
+    case '\n' => List('\\', 'n')
+    case '\t' => List('\\', 't')
+    case _ => List('?')
   }
 
   /** Create a StringLit from a raw parsed String */
@@ -163,8 +163,8 @@ abstract class PrimOp extends FirrtlNode {
   def apply(args: Any*): DoPrim = {
     val groups = args.groupBy {
       case x: Expression => "exp"
-      case x: BigInt     => "int"
-      case x: Int        => "int"
+      case x: BigInt => "int"
+      case x: Int => "int"
       case other => "other"
     }
     val exprs = groups.getOrElse("exp", Nil).collect { case e: Expression =>
@@ -173,11 +173,11 @@ abstract class PrimOp extends FirrtlNode {
     val consts = groups.getOrElse("int", Nil).map {
       _ match {
         case i: BigInt => i
-        case i: Int    => BigInt(i)
+        case i: Int => BigInt(i)
       }
     }
     groups.get("other") match {
-      case None    =>
+      case None =>
       case Some(x) => sys.error(s"Shouldn't be here: $x")
     }
     DoPrim(this, exprs, consts, UnknownType)
@@ -404,7 +404,7 @@ final case class Layer(info: Info, name: String, config: LayerConfig, body: Seq[
     with UseSerializer {
   def outputDir: Option[String] = config match {
     case LayerConfig.Extract(outputDir) => outputDir
-    case _                              => None
+    case _ => None
   }
 }
 
@@ -456,19 +456,19 @@ case object EmptyStmt extends Statement with UseSerializer
 abstract class Width extends FirrtlNode {
   def +(x: Width): Width = (this, x) match {
     case (a: IntWidth, b: IntWidth) => IntWidth(a.width + b.width)
-    case _                          => UnknownWidth
+    case _ => UnknownWidth
   }
   def -(x: Width): Width = (this, x) match {
     case (a: IntWidth, b: IntWidth) => IntWidth(a.width - b.width)
-    case _                          => UnknownWidth
+    case _ => UnknownWidth
   }
   def max(x: Width): Width = (this, x) match {
     case (a: IntWidth, b: IntWidth) => IntWidth(a.width.max(b.width))
-    case _                          => UnknownWidth
+    case _ => UnknownWidth
   }
   def min(x: Width): Width = (this, x) match {
     case (a: IntWidth, b: IntWidth) => IntWidth(a.width.min(b.width))
-    case _                          => UnknownWidth
+    case _ => UnknownWidth
   }
 }
 
diff --git a/firrtl/src/main/scala/firrtl/ir/Serializer.scala b/firrtl/src/main/scala/firrtl/ir/Serializer.scala
index 89c0c2715e0..a004c2a6963 100644
--- a/firrtl/src/main/scala/firrtl/ir/Serializer.scala
+++ b/firrtl/src/main/scala/firrtl/ir/Serializer.scala
@@ -28,19 +28,19 @@ object Serializer {
   def serialize(node: FirrtlNode, indent: Int): String = {
     val builder = new StringBuilder()
     node match {
-      case n: Info             => s(n)(builder, indent)
-      case n: StringLit        => s(n)(builder, indent)
-      case n: Expression       => s(n)(builder, indent)
-      case n: Statement        => builder ++= lazily(n, indent).mkString
-      case n: Width            => s(n)(builder, indent)
-      case n: Orientation      => s(n)(builder, indent)
-      case n: Field            => s(n)(builder, indent)
-      case n: Type             => s(n)(builder, indent)
-      case n: Direction        => s(n)(builder, indent)
-      case n: Port             => s(n)(builder, indent)
-      case n: Param            => s(n)(builder, indent)
-      case n: DefModule        => builder ++= lazily(n, indent).mkString
-      case n: Circuit          => builder ++= lazily(n, indent).mkString
+      case n: Info => s(n)(builder, indent)
+      case n: StringLit => s(n)(builder, indent)
+      case n: Expression => s(n)(builder, indent)
+      case n: Statement => builder ++= lazily(n, indent).mkString
+      case n: Width => s(n)(builder, indent)
+      case n: Orientation => s(n)(builder, indent)
+      case n: Field => s(n)(builder, indent)
+      case n: Type => s(n)(builder, indent)
+      case n: Direction => s(n)(builder, indent)
+      case n: Port => s(n)(builder, indent)
+      case n: Param => s(n)(builder, indent)
+      case n: DefModule => builder ++= lazily(n, indent).mkString
+      case n: Circuit => builder ++= lazily(n, indent).mkString
       case n: CircuitWithAnnos => builder ++= lazily(n, indent).mkString
       case other => builder ++= other.serialize // Handle user-defined nodes
     }
@@ -63,9 +63,9 @@ object Serializer {
     */
   def lazily(node: FirrtlNode, indent: Int): Iterable[String] = new Iterable[String] {
     def iterator = node match {
-      case n: Statement        => sIt(n)(indent)
-      case n: DefModule        => sIt(n)(indent)
-      case n: Circuit          => sIt(n)(indent)
+      case n: Statement => sIt(n)(indent)
+      case n: DefModule => sIt(n)(indent)
+      case n: Circuit => sIt(n)(indent)
       case n: CircuitWithAnnos => sIt(n)(indent)
       case other => Iterator(serialize(other, indent))
     }
@@ -79,7 +79,7 @@ object Serializer {
   private def s(node: Info)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case f: FileInfo => b ++= " @["; b ++= f.escaped; b ++= "]"
     case NoInfo => // empty string
-    case other  => b ++= other.serialize // Handle user-defined nodes
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   /** Hash map containing names that were changed due to legalization. */
@@ -89,7 +89,7 @@ object Serializer {
   private def legalize(name: String): String = name match {
     // If the name starts with a digit, then escape it with backticks.
     case _ if name.head.isDigit => legalizedNames.getOrElseUpdate(name, s"`$name`")
-    case _                      => name
+    case _ => name
   }
 
   private def s(str: StringLit)(implicit b: StringBuilder, indent: Int): Unit = b ++= str.serialize
@@ -100,8 +100,8 @@ object Serializer {
       b ++= op.toString; b += '('; s(args, ", ", consts.isEmpty); s(consts, ", "); b += ')'
     case UIntLiteral(value, width) =>
       b ++= "UInt"; s(width); b ++= "(0h"; b ++= value.toString(16); b ++= ")"
-    case SubField(expr, name, _)   => s(expr); b += '.'; b ++= legalize(name)
-    case SubIndex(expr, value, _)  => s(expr); b += '['; b ++= value.toString; b += ']'
+    case SubField(expr, name, _) => s(expr); b += '.'; b ++= legalize(name)
+    case SubIndex(expr, value, _) => s(expr); b += '['; b ++= value.toString; b += ']'
     case SubAccess(expr, index, _) => s(expr); b += '['; s(index); b += ']'
     case Mux(cond, tval, fval, _) =>
       b ++= "mux("; s(cond); b ++= ", "; s(tval); b ++= ", "; s(fval); b += ')'
@@ -126,11 +126,11 @@ object Serializer {
         if (idx != lastIdx) b ++= ", "
       }
       b += ')'
-    case ProbeExpr(expr, _)                          => b ++= "probe("; s(expr); b += ')'
-    case RWProbeExpr(expr, _)                        => b ++= "rwprobe("; s(expr); b += ')'
-    case ProbeRead(expr, _)                          => b ++= "read("; s(expr); b += ')'
+    case ProbeExpr(expr, _) => b ++= "probe("; s(expr); b += ')'
+    case RWProbeExpr(expr, _) => b ++= "rwprobe("; s(expr); b += ')'
+    case ProbeRead(expr, _) => b ++= "read("; s(expr); b += ')'
     case IntrinsicExpr(intrinsic, args, params, tpe) => sIntrinsic(NoInfo, intrinsic, args, params, Some(tpe))
-    case other                                       => b ++= other.serialize // Handle user-defined nodes
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   // Helper for some not-real Statements that only exist for Serialization
@@ -269,8 +269,8 @@ object Serializer {
   }
 
   private def s(node: Statement)(implicit b: StringBuilder, indent: Int): Unit = node match {
-    case DefNode(info, name, value)  => b ++= "node "; b ++= legalize(name); b ++= " = "; s(value); s(info)
-    case Connect(info, loc, expr)    => b ++= "connect "; s(loc); b ++= ", "; s(expr); s(info)
+    case DefNode(info, name, value) => b ++= "node "; b ++= legalize(name); b ++= " = "; s(value); s(info)
+    case Connect(info, loc, expr) => b ++= "connect "; s(loc); b ++= ", "; s(expr); s(info)
     case PropAssign(info, loc, expr) => b ++= "propassign "; s(loc); b ++= ", "; s(expr); s(info)
     case c: Conditionally => b ++= sIt(c).mkString
     case EmptyStmt => b ++= "skip"
@@ -282,7 +282,7 @@ object Serializer {
       b ++= "printf("; s(clk); b ++= ", "; s(en); b ++= ", "; b ++= string.escape
       if (args.nonEmpty) b ++= ", "; s(args, ", "); b += ')'
       sStmtName(print.name); s(info)
-    case IsInvalid(info, expr)    => b ++= "invalidate "; s(expr); s(info)
+    case IsInvalid(info, expr) => b ++= "invalidate "; s(expr); s(info)
     case DefWire(info, name, tpe) => b ++= "wire "; b ++= legalize(name); b ++= " : "; s(tpe); s(info)
     case DefRegister(info, name, tpe, clock) =>
       b ++= "reg "; b ++= legalize(name); b ++= " : "; s(tpe); b ++= ", "; s(clock); s(info)
@@ -354,7 +354,7 @@ object Serializer {
     case ProbeRelease(info, clock, cond, probe) =>
       b ++= "release("; s(clock); b ++= ", "; s(cond); b ++= ", "; s(probe); b += ')'; s(info)
     case IntrinsicStmt(info, intrinsic, args, params, tpe) => sIntrinsic(info, intrinsic, args, params, tpe)
-    case other                                             => b ++= other.serialize // Handle user-defined nodes
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def sStmtName(lbl: String)(implicit b: StringBuilder): Unit = {
@@ -396,20 +396,20 @@ object Serializer {
 
   private def s(node: Width)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case IntWidth(width) => b += '<'; b ++= width.toString(); b += '>'
-    case UnknownWidth    => // empty string
-    case other           => b ++= other.serialize // Handle user-defined nodes
+    case UnknownWidth => // empty string
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def sPoint(node: Width)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case IntWidth(width) => b ++= "<<"; b ++= width.toString(); b ++= ">>"
-    case UnknownWidth    => // empty string
-    case other           => b ++= other.serialize // Handle user-defined nodes
+    case UnknownWidth => // empty string
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def s(node: Orientation)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case Default => // empty string
-    case Flip    => b ++= "flip "
-    case other   => b ++= other.serialize // Handle user-defined nodes
+    case Flip => b ++= "flip "
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def s(node: Field)(implicit b: StringBuilder, indent: Int): Unit = node match {
@@ -437,31 +437,31 @@ object Serializer {
       }
       s(underlying, true)(b, indent)
     }
-    case UIntType(width: Width)    => b ++= "UInt"; s(width)
-    case SIntType(width: Width)    => b ++= "SInt"; s(width)
-    case BundleType(fields)        => b ++= "{ "; sField(fields, ", "); b += '}'
-    case VectorType(tpe, size)     => s(tpe, lastEmittedConst); b += '['; b ++= size.toString; b += ']'
-    case ClockType                 => b ++= "Clock"
-    case ResetType                 => b ++= "Reset"
-    case AsyncResetType            => b ++= "AsyncReset"
-    case AnalogType(width)         => b ++= "Analog"; s(width)
-    case IntegerPropertyType       => b ++= "Integer"
-    case DoublePropertyType        => b ++= "Double"
-    case StringPropertyType        => b ++= "String"
-    case BooleanPropertyType       => b ++= "Bool"
-    case PathPropertyType          => b ++= "Path"
+    case UIntType(width: Width) => b ++= "UInt"; s(width)
+    case SIntType(width: Width) => b ++= "SInt"; s(width)
+    case BundleType(fields) => b ++= "{ "; sField(fields, ", "); b += '}'
+    case VectorType(tpe, size) => s(tpe, lastEmittedConst); b += '['; b ++= size.toString; b += ']'
+    case ClockType => b ++= "Clock"
+    case ResetType => b ++= "Reset"
+    case AsyncResetType => b ++= "AsyncReset"
+    case AnalogType(width) => b ++= "Analog"; s(width)
+    case IntegerPropertyType => b ++= "Integer"
+    case DoublePropertyType => b ++= "Double"
+    case StringPropertyType => b ++= "String"
+    case BooleanPropertyType => b ++= "Bool"
+    case PathPropertyType => b ++= "Path"
     case SequencePropertyType(tpe) => b ++= "List<"; s(tpe, lastEmittedConst); b += '>'
-    case ClassPropertyType(name)   => b ++= "Inst<"; b ++= name; b += '>'
-    case AnyRefPropertyType        => b ++= "AnyRef"
-    case AliasType(name)           => b ++= name
-    case UnknownType               => b += '?'
-    case other                     => b ++= other.serialize // Handle user-defined nodes
+    case ClassPropertyType(name) => b ++= "Inst<"; b ++= name; b += '>'
+    case AnyRefPropertyType => b ++= "AnyRef"
+    case AliasType(name) => b ++= name
+    case UnknownType => b += '?'
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def s(node: Direction)(implicit b: StringBuilder, indent: Int): Unit = node match {
-    case Input  => b ++= "input"
+    case Input => b ++= "input"
     case Output => b ++= "output"
-    case other  => b ++= other.serialize // Handle user-defined nodes
+    case other => b ++= other.serialize // Handle user-defined nodes
   }
 
   private def s(node: Port)(implicit b: StringBuilder, indent: Int): Unit = node match {
@@ -470,7 +470,7 @@ object Serializer {
   }
 
   private def s(node: Param)(implicit b: StringBuilder, indent: Int): Unit = node match {
-    case IntParam(name, value)    => b ++= name; b ++= " = "; b ++= value.toString
+    case IntParam(name, value) => b ++= name; b ++= " = "; b ++= value.toString
     case DoubleParam(name, value) => b ++= name; b ++= " = "; b ++= value.toString
     case StringParam(name, value) => b ++= name; b ++= " = "; b ++= value.escape
     case RawStringParam(name, value) =>
diff --git a/firrtl/src/main/scala/firrtl/options/DependencyManager.scala b/firrtl/src/main/scala/firrtl/options/DependencyManager.scala
index 71da96c4e1b..19447e6280f 100644
--- a/firrtl/src/main/scala/firrtl/options/DependencyManager.scala
+++ b/firrtl/src/main/scala/firrtl/options/DependencyManager.scala
@@ -187,7 +187,7 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
     case e: CyclicException =>
       throw new DependencyManagerException(
         s"""|No transform ordering possible due to cyclic dependency in $a with cycles:
-            |${diGraph.findSCCs.filter(_.size > 1).mkString("    - ", "\n    - ", "")}""".stripMargin,
+          |${diGraph.findSCCs.filter(_.size > 1).mkString("    - ", "\n    - ", "")}""".stripMargin,
         e
       )
   }
@@ -268,8 +268,8 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
       if (!t.prerequisites.toSet.subsetOf(state)) {
         throw new DependencyManagerException(
           s"""|Tried to execute '$t' for which run-time prerequisites were not satisfied:
-              |  state: ${state.mkString("\n    -", "\n    -", "")}
-              |  prerequisites: ${prerequisites.mkString("\n    -", "\n    -", "")}""".stripMargin
+            |  state: ${state.mkString("\n    -", "\n    -", "")}
+            |  prerequisites: ${prerequisites.mkString("\n    -", "\n    -", "")}""".stripMargin
         )
       }
       val logger = t.getLogger
@@ -305,8 +305,8 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
       else {
         Some(
           s"""|  { $attributes
-              |${edges.mkString(tab, "\n" + tab, "")}
-              |  }""".stripMargin
+            |${edges.mkString(tab, "\n" + tab, "")}
+            |  }""".stripMargin
         )
       }
     }
@@ -325,20 +325,20 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
         .map(v => s"""${transformName(v)} [label="${v.name}"]""")
 
     s"""|digraph DependencyManager {
-        |  graph [rankdir=BT]
-        |  node [fillcolor="${colormap(0)}",style=filled,shape=box]
-        |${nodes.mkString("  ", "\n" + "  ", "")}
-        |$connections
-        |}
-        |""".stripMargin
+      |  graph [rankdir=BT]
+      |  node [fillcolor="${colormap(0)}",style=filled,shape=box]
+      |${nodes.mkString("  ", "\n" + "  ", "")}
+      |$connections
+      |}
+      |""".stripMargin
   }
 
   def transformOrderToGraphviz(colormap: Seq[String] = colormap): String = {
 
     def rotate[A](a: Seq[A]): Seq[A] = a match {
-      case Nil        => Nil
+      case Nil => Nil
       case car :: cdr => cdr :+ car
-      case car        => car
+      case car => car
     }
 
     val sorted = ArrayBuffer.empty[String]
@@ -350,9 +350,9 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
       val state = pm._currentState.toSeq.map(_.name).mkString(", ")
 
       val header = s"""|${tab}subgraph cluster_$id {
-                       |$tab  label="targets: $targets\\nstate: $state"
-                       |$tab  labeljust=l
-                       |$tab  node [fillcolor="${cm.head}"]""".stripMargin
+        |$tab  label="targets: $targets\\nstate: $state"
+        |$tab  labeljust=l
+        |$tab  node [fillcolor="${cm.head}"]""".stripMargin
 
       val body = pm.transformOrder.map {
         case a: DependencyManager[A, B] =>
@@ -369,11 +369,11 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
     }
 
     s"""|digraph DependencyManagerTransformOrder {
-        |  graph [rankdir=TB]
-        |  node [style=filled,shape=box]
-        |${rec(this, colormap, "  ")._1}
-        |  ${sorted.mkString(" -> ")}
-        |}""".stripMargin
+      |  graph [rankdir=TB]
+      |  node [style=filled,shape=box]
+      |${rec(this, colormap, "  ")._1}
+      |  ${sorted.mkString(" -> ")}
+      |}""".stripMargin
   }
 
   /** A method that can be overridden to define custom print handling. This is useful if you would like to make some
@@ -402,13 +402,13 @@ trait DependencyManager[A, B <: TransformLike[A] with DependencyAPI[B]] extends
       case (a: DependencyManager[_, _], `last`) =>
         Seq(s"$tab$l ${a.name}") ++ a.prettyPrintRec(s"""$tab${" " * c.size} """, charSet)
       case (a: DependencyManager[_, _], _) => Seq(s"$tab$n ${a.name}") ++ a.prettyPrintRec(s"$tab$c ", charSet)
-      case (a, `last`)                     => Seq(s"$tab$l ${a.name}")
-      case (a, _)                          => Seq(s"$tab$n ${a.name}")
+      case (a, `last`) => Seq(s"$tab$l ${a.name}")
+      case (a, _) => Seq(s"$tab$n ${a.name}")
     }
 
     val handling = customPrintHandling(tab, charSet, transformOrder.size) match {
       case Some(a) => a.orElse(defaultHandling)
-      case None    => defaultHandling
+      case None => defaultHandling
     }
 
     transformOrder.zipWithIndex
diff --git a/firrtl/src/main/scala/firrtl/options/Phase.scala b/firrtl/src/main/scala/firrtl/options/Phase.scala
index 0a643c5dfbe..11f43c76314 100644
--- a/firrtl/src/main/scala/firrtl/options/Phase.scala
+++ b/firrtl/src/main/scala/firrtl/options/Phase.scala
@@ -38,17 +38,17 @@ object Dependency {
 
 case class Dependency[+A <: DependencyAPI[_]](id: Either[Class[_ <: A], A with Singleton]) {
   def getObject(): A = id match {
-    case Left(c)  => safeConstruct(c)
+    case Left(c) => safeConstruct(c)
     case Right(o) => o
   }
 
   def getSimpleName: String = id match {
-    case Left(c)  => c.getSimpleName
+    case Left(c) => c.getSimpleName
     case Right(o) => o.getClass.getSimpleName
   }
 
   def getName: String = id match {
-    case Left(c)  => c.getName
+    case Left(c) => c.getName
     case Right(o) => o.getClass.getName
   }
 
@@ -126,7 +126,7 @@ trait DependencyAPI[A <: DependencyAPI[A]] { this: TransformLike[_] =>
   /** All transform that must run before this transform
     * $seqNote
     */
-  def prerequisites:                        Seq[Dependency[A]] = Seq.empty
+  def prerequisites: Seq[Dependency[A]] = Seq.empty
   private[options] lazy val _prerequisites: LinkedHashSet[Dependency[A]] = new LinkedHashSet() ++ prerequisites
 
   /** All transforms that, if a prerequisite of *another* transform, will run before this transform.
diff --git a/firrtl/src/main/scala/firrtl/options/StageOptions.scala b/firrtl/src/main/scala/firrtl/options/StageOptions.scala
index fa65ac6a412..5599558089c 100644
--- a/firrtl/src/main/scala/firrtl/options/StageOptions.scala
+++ b/firrtl/src/main/scala/firrtl/options/StageOptions.scala
@@ -62,9 +62,9 @@ class StageOptions private[firrtl] (
     }.toPath.normalize.toFile
 
     file.getParentFile match {
-      case null                       =>
+      case null =>
       case parent if (!parent.exists) => parent.mkdirs()
-      case _                          =>
+      case _ =>
     }
 
     file.toString
diff --git a/firrtl/src/main/scala/firrtl/options/StageUtils.scala b/firrtl/src/main/scala/firrtl/options/StageUtils.scala
index c3867c7ed3b..b2e875df073 100644
--- a/firrtl/src/main/scala/firrtl/options/StageUtils.scala
+++ b/firrtl/src/main/scala/firrtl/options/StageUtils.scala
@@ -29,6 +29,6 @@ object StageUtils {
     */
   def dramaticUsageError(message: String): Unit =
     dramaticError(s"""|$message
-                      |Try --help for more information.""".stripMargin)
+      |Try --help for more information.""".stripMargin)
 
 }
diff --git a/firrtl/src/main/scala/firrtl/options/package.scala b/firrtl/src/main/scala/firrtl/options/package.scala
index bfb774fcbef..37bba52507e 100644
--- a/firrtl/src/main/scala/firrtl/options/package.scala
+++ b/firrtl/src/main/scala/firrtl/options/package.scala
@@ -10,7 +10,7 @@ package object options {
         x match {
           case TargetDirAnnotation(a) => c.copy(targetDir = a)
           /* Insert input files at the head of the Seq for speed and because order shouldn't matter */
-          case InputAnnotationFileAnnotation(a)  => c.copy(annotationFilesIn = a +: c.annotationFilesIn)
+          case InputAnnotationFileAnnotation(a) => c.copy(annotationFilesIn = a +: c.annotationFilesIn)
           case OutputAnnotationFileAnnotation(a) => c.copy(annotationFileOut = Some(a))
           /* Do NOT reorder program args. The order may matter. */
           case ProgramArgsAnnotation(a) => c.copy(programArgs = c.programArgs :+ a)
diff --git a/firrtl/src/main/scala/firrtl/options/phases/Checks.scala b/firrtl/src/main/scala/firrtl/options/phases/Checks.scala
index 4fcd90225d1..2d8a08ea830 100644
--- a/firrtl/src/main/scala/firrtl/options/phases/Checks.scala
+++ b/firrtl/src/main/scala/firrtl/options/phases/Checks.scala
@@ -25,7 +25,7 @@ class Checks extends Phase {
 
     val td, outA = collection.mutable.ListBuffer[Annotation]()
     annotations.foreach {
-      case a: TargetDirAnnotation            => td += a
+      case a: TargetDirAnnotation => td += a
       case a: OutputAnnotationFileAnnotation => outA += a
       case _ =>
     }
@@ -34,8 +34,8 @@ class Checks extends Phase {
       val d = td.map { case TargetDirAnnotation(x) => x }
       throw new OptionsException(
         s"""|Exactly one target directory must be specified, but found `${d.mkString(", ")}` specified via:
-            |    - explicit target directory: -td, --target-dir, TargetDirAnnotation
-            |    - fallback default value""".stripMargin
+          |    - explicit target directory: -td, --target-dir, TargetDirAnnotation
+          |    - fallback default value""".stripMargin
       )
     }
 
@@ -43,7 +43,7 @@ class Checks extends Phase {
       val x = outA.map { case OutputAnnotationFileAnnotation(x) => x }
       throw new OptionsException(
         s"""|At most one output annotation file can be specified, but found '${x.mkString(", ")}' specified via:
-            |    - an option or annotation: -foaf, --output-annotation-file, OutputAnnotationFileAnnotation""".stripMargin
+          |    - an option or annotation: -foaf, --output-annotation-file, OutputAnnotationFileAnnotation""".stripMargin
       )
     }
 
diff --git a/firrtl/src/main/scala/firrtl/options/phases/WriteOutputAnnotations.scala b/firrtl/src/main/scala/firrtl/options/phases/WriteOutputAnnotations.scala
index 93ea8b04686..28b848c2956 100644
--- a/firrtl/src/main/scala/firrtl/options/phases/WriteOutputAnnotations.scala
+++ b/firrtl/src/main/scala/firrtl/options/phases/WriteOutputAnnotations.scala
@@ -61,13 +61,13 @@ class WriteOutputAnnotations extends Phase {
             case Some(first) =>
               val msg =
                 s"""|Multiple CustomFileEmission annotations would be serialized to the same file, '$canonical'
-                    |  - first writer:
-                    |      class: ${first.getClass.getName}
-                    |      trimmed serialization: ${first.serialize.take(80)}
-                    |  - second writer:
-                    |      class: ${a.getClass.getName}
-                    |      trimmed serialization: ${a.serialize.take(80)}
-                    |""".stripMargin
+                  |  - first writer:
+                  |      class: ${first.getClass.getName}
+                  |      trimmed serialization: ${first.serialize.take(80)}
+                  |  - second writer:
+                  |      class: ${a.getClass.getName}
+                  |      trimmed serialization: ${a.serialize.take(80)}
+                  |""".stripMargin
               throw new PhaseException(msg)
           }
           filesToWrite(canonical) = a
@@ -82,14 +82,14 @@ class WriteOutputAnnotations extends Phase {
             val Some((firstFN, firstWCA)) = circuitAnnoOpt
             val msg =
               s"""|Multiple circuit annotations found--only 1 is supported
-                  | - first circuit:
-                  |     filename: $firstFN
-                  |     trimmed serialization: ${firstWCA.serialize.take(80)}
-                  | - second circuit:
-                  |     filename: $filename
-                  |     trimmed serialization: ${wca.serialize.take(80)}
-                  |
-                  |""".stripMargin
+                | - first circuit:
+                |     filename: $firstFN
+                |     trimmed serialization: ${firstWCA.serialize.take(80)}
+                | - second circuit:
+                |     filename: $filename
+                |     trimmed serialization: ${wca.serialize.take(80)}
+                |
+                |""".stripMargin
             throw new PhaseException(msg)
           }
           circuitAnnoOpt = Some(filename -> wca)
diff --git a/firrtl/src/main/scala/firrtl/passes/CheckTypes.scala b/firrtl/src/main/scala/firrtl/passes/CheckTypes.scala
index 95ca0cec6b7..d2d19022c0f 100644
--- a/firrtl/src/main/scala/firrtl/passes/CheckTypes.scala
+++ b/firrtl/src/main/scala/firrtl/passes/CheckTypes.scala
@@ -7,9 +7,9 @@ import firrtl.ir._
 object CheckTypes {
   def legalResetType(tpe: Type): Boolean = tpe match {
     case UIntType(IntWidth(w)) if w == 1 => true
-    case AsyncResetType                  => true
-    case ResetType                       => true
-    case UIntType(UnknownWidth)          =>
+    case AsyncResetType => true
+    case ResetType => true
+    case UIntType(UnknownWidth) =>
       // cannot catch here, though width may ultimately be wrong
       true
     case _ => false
@@ -20,12 +20,12 @@ object CheckTypes {
   //   it cannot drive Bool nor AsyncResetType
   private def compare(sink: Type, source: Type): Boolean =
     (sink, source) match {
-      case (_: UIntType, _: UIntType)       => true
-      case (_: SIntType, _: SIntType)       => true
-      case (ClockType, ClockType)           => true
+      case (_: UIntType, _: UIntType) => true
+      case (_: SIntType, _: SIntType) => true
+      case (ClockType, ClockType) => true
       case (AsyncResetType, AsyncResetType) => true
-      case (ResetType, tpe)                 => legalResetType(tpe)
-      case (tpe, ResetType)                 => legalResetType(tpe)
+      case (ResetType, tpe) => legalResetType(tpe)
+      case (tpe, ResetType) => legalResetType(tpe)
       // Analog totally skips out of the Firrtl type system.
       // The only way Analog can play with another Analog component is through Attach.
       // Otherwise, we'd need to special case it during lowering.
@@ -43,9 +43,9 @@ object CheckTypes {
         }
       // Const connection validity is checked later on in the Firrtl compiler.
       case (sink: ConstType, source: ConstType) => compare(sink.underlying, source.underlying)
-      case (sink, source: ConstType)            => compare(sink, source.underlying)
-      case (sink: ConstType, source)            => compare(sink.underlying, source)
-      case _                                    => false
+      case (sink, source: ConstType) => compare(sink, source.underlying)
+      case (sink: ConstType, source) => compare(sink.underlying, source)
+      case _ => false
     }
 
   def validConnect(locTpe: Type, expTpe: Type): Boolean = {
diff --git a/firrtl/src/main/scala/firrtl/stage/FirrtlAnnotations.scala b/firrtl/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
index 38b429c96d2..2ffb30de6fa 100644
--- a/firrtl/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
+++ b/firrtl/src/main/scala/firrtl/stage/FirrtlAnnotations.scala
@@ -46,12 +46,12 @@ case class InfoModeAnnotation(modeName: String = "use") extends NoTargetAnnotati
     * @param infoSource the name of a file to use for "gen" or "append" info modes
     */
   def toInfoMode(infoSource: Option[String] = None): Parser.InfoMode = modeName match {
-    case "use"    => Parser.UseInfo
+    case "use" => Parser.UseInfo
     case "ignore" => Parser.IgnoreInfo
     case _ =>
       val a = infoSource.getOrElse("unknown source")
       modeName match {
-        case "gen"    => Parser.GenInfo(a)
+        case "gen" => Parser.GenInfo(a)
         case "append" => Parser.AppendInfo(a)
       }
   }
diff --git a/firrtl/src/main/scala/firrtl/stage/package.scala b/firrtl/src/main/scala/firrtl/stage/package.scala
index 63f301f67dc..21ec472b45c 100644
--- a/firrtl/src/main/scala/firrtl/stage/package.scala
+++ b/firrtl/src/main/scala/firrtl/stage/package.scala
@@ -20,8 +20,8 @@ package object stage {
     def view(options: AnnotationSeq): FirrtlOptions = options.collect { case a: FirrtlOption => a }
       .foldLeft(new FirrtlOptions()) { (c, x) =>
         x match {
-          case OutputFileAnnotation(f)      => c.copy(outputFileName = Some(f))
-          case InfoModeAnnotation(i)        => c.copy(infoModeName = i)
+          case OutputFileAnnotation(f) => c.copy(outputFileName = Some(f))
+          case InfoModeAnnotation(i) => c.copy(infoModeName = i)
           case FirrtlCircuitAnnotation(cir) => c.copy(firrtlCircuit = Some(cir))
           case AllowUnrecognizedAnnotations => c
         }
diff --git a/firrtl/src/main/scala/firrtl/stage/phases/AddDefaults.scala b/firrtl/src/main/scala/firrtl/stage/phases/AddDefaults.scala
index 2fc5253173d..cc8b480b7b1 100644
--- a/firrtl/src/main/scala/firrtl/stage/phases/AddDefaults.scala
+++ b/firrtl/src/main/scala/firrtl/stage/phases/AddDefaults.scala
@@ -21,7 +21,7 @@ class AddDefaults extends Phase {
     var bb, im = true
     annotations.foreach {
       case _: BlackBoxTargetDirAnno => bb = false
-      case _: InfoModeAnnotation    => im = false
+      case _: InfoModeAnnotation => im = false
       case _ =>
     }
 
diff --git a/firrtl/src/main/scala/firrtl/stage/phases/Checks.scala b/firrtl/src/main/scala/firrtl/stage/phases/Checks.scala
index f4d82abcf97..94b0e712e3e 100644
--- a/firrtl/src/main/scala/firrtl/stage/phases/Checks.scala
+++ b/firrtl/src/main/scala/firrtl/stage/phases/Checks.scala
@@ -32,8 +32,8 @@ class Checks extends Phase {
   def transform(annos: AnnotationSeq): AnnotationSeq = {
     val outF, im, inC = collection.mutable.ListBuffer[Annotation]()
     annos.foreach(_ match {
-      case a: OutputFileAnnotation    => a +=: outF
-      case a: InfoModeAnnotation      => a +=: im
+      case a: OutputFileAnnotation => a +=: outF
+      case a: InfoModeAnnotation => a +=: im
       case a: FirrtlCircuitAnnotation => a +=: inC
       case _ =>
     })
@@ -42,7 +42,7 @@ class Checks extends Phase {
     if (inC.isEmpty) {
       throw new OptionsException(
         s"""|Unable to determine FIRRTL source to read. None of the following were found:
-            |    - FIRRTL circuit:                        FirrtlCircuitAnnotation""".stripMargin
+          |    - FIRRTL circuit:                        FirrtlCircuitAnnotation""".stripMargin
       )
     }
 
@@ -50,7 +50,7 @@ class Checks extends Phase {
     if (inC.size > 1) {
       throw new OptionsException(
         s"""|Multiply defined input FIRRTL sources. More than one of the following was found:
-            |    - FIRRTL circuit (${inC.size} times):                        FirrtlCircuitAnnotation""".stripMargin
+          |    - FIRRTL circuit (${inC.size} times):                        FirrtlCircuitAnnotation""".stripMargin
       )
     }
 
@@ -59,7 +59,7 @@ class Checks extends Phase {
       val x = outF.map { case OutputFileAnnotation(x) => x }
       throw new OptionsException(
         s"""|No more than one output file can be specified, but found '${x.mkString(", ")}' specified via:
-            |    - option or annotation: -o, --output-file, OutputFileAnnotation""".stripMargin
+          |    - option or annotation: -o, --output-file, OutputFileAnnotation""".stripMargin
       )
     }
 
@@ -69,7 +69,7 @@ class Checks extends Phase {
       val (msg, suggest) = if (im.size == 0) { ("none found", "forget one of") }
       else { (s"""found '${x.mkString(", ")}'""", "use multiple of") }
       throw new OptionsException(s"""|Exactly one info mode must be specified, but $msg. Did you $suggest the following?
-                                     |    - an option or annotation: --info-mode, InfoModeAnnotation""".stripMargin)
+        |    - an option or annotation: --info-mode, InfoModeAnnotation""".stripMargin)
     }
 
     annos
diff --git a/firrtl/src/main/scala/firrtl/transforms/MustDedup.scala b/firrtl/src/main/scala/firrtl/transforms/MustDedup.scala
index 294fa558835..f33ced1773b 100644
--- a/firrtl/src/main/scala/firrtl/transforms/MustDedup.scala
+++ b/firrtl/src/main/scala/firrtl/transforms/MustDedup.scala
@@ -11,8 +11,8 @@ case class MustDeduplicateAnnotation(modules: Seq[IsModule]) extends Annotation
   def update(renames: RenameMap): Seq[MustDeduplicateAnnotation] = {
     val newModules: Seq[IsModule] = modules.flatMap { m =>
       renames.get(m) match {
-        case None                     => Seq(m)
-        case Some(Seq())              => Seq()
+        case None => Seq(m)
+        case Some(Seq()) => Seq()
         case Some(Seq(one: IsModule)) => Seq(one)
         case Some(many) =>
           val msg = "Something went wrong! This anno's targets should only rename to IsModules! " +
diff --git a/firrtl/src/main/scala/logger/Logger.scala b/firrtl/src/main/scala/logger/Logger.scala
index 74a3abe9d3c..043c4384c8b 100644
--- a/firrtl/src/main/scala/logger/Logger.scala
+++ b/firrtl/src/main/scala/logger/Logger.scala
@@ -35,11 +35,11 @@ object LogLevel extends Enumeration {
 
   def apply(s: String): LogLevel.Value = s.toLowerCase match {
     case "error" => LogLevel.Error
-    case "warn"  => LogLevel.Warn
-    case "info"  => LogLevel.Info
+    case "warn" => LogLevel.Warn
+    case "info" => LogLevel.Info
     case "debug" => LogLevel.Debug
     case "trace" => LogLevel.Trace
-    case level   => throw new Exception(s"Unknown LogLevel '$level'")
+    case level => throw new Exception(s"Unknown LogLevel '$level'")
   }
 }
 
@@ -215,7 +215,7 @@ object Logger {
       }
     }
     testPackageNameMatch(className, level) match {
-      case Some(true)  => logIt()
+      case Some(true) => logIt()
       case Some(false) =>
       case None =>
         if (getGlobalLevel >= level) {
@@ -227,7 +227,7 @@ object Logger {
   def getGlobalLevel: LogLevel.Value = state.globalLevel match {
     // None means "not set" so use default in that case
     case LogLevel.None => LogLevel.default
-    case other         => other
+    case other => other
   }
 
   /**
@@ -292,7 +292,7 @@ object Logger {
   def clearStringBuffer(): Unit = {
     state.stringBufferOption match {
       case Some(x) => x.byteArrayOutputStream.reset()
-      case None    =>
+      case None =>
     }
   }
 
@@ -346,9 +346,9 @@ object Logger {
   def setOptions(options: LoggerOptions): Unit = {
     state.globalLevel = (state.globalLevel, options.globalLogLevel) match {
       case (LogLevel.None, LogLevel.None) => LogLevel.None
-      case (x, LogLevel.None)             => x
-      case (LogLevel.None, x)             => x
-      case (_, x)                         => x
+      case (x, LogLevel.None) => x
+      case (LogLevel.None, x) => x
+      case (_, x) => x
     }
     setClassLogLevels(options.classLogLevels)
 
diff --git a/firrtl/src/main/scala/logger/package.scala b/firrtl/src/main/scala/logger/package.scala
index 4a70d912b6c..b885cea0d47 100644
--- a/firrtl/src/main/scala/logger/package.scala
+++ b/firrtl/src/main/scala/logger/package.scala
@@ -9,11 +9,11 @@ package object logger {
     def view(options: AnnotationSeq): LoggerOptions = options
       .foldLeft(new LoggerOptions()) { (c, x) =>
         x match {
-          case LogLevelAnnotation(logLevel)         => c.copy(globalLogLevel = logLevel)
+          case LogLevelAnnotation(logLevel) => c.copy(globalLogLevel = logLevel)
           case ClassLogLevelAnnotation(name, level) => c.copy(classLogLevels = c.classLogLevels + (name -> level))
-          case LogFileAnnotation(f)                 => c.copy(logFileName = f)
-          case LogClassNamesAnnotation              => c.copy(logClassNames = true)
-          case _                                    => c
+          case LogFileAnnotation(f) => c.copy(logFileName = f)
+          case LogClassNamesAnnotation => c.copy(logClassNames = true)
+          case _ => c
         }
       }
   }
diff --git a/firrtl/src/main/scala/logger/phases/Checks.scala b/firrtl/src/main/scala/logger/phases/Checks.scala
index 78ecc8bba24..b325077cf53 100644
--- a/firrtl/src/main/scala/logger/phases/Checks.scala
+++ b/firrtl/src/main/scala/logger/phases/Checks.scala
@@ -29,20 +29,20 @@ object Checks extends Phase {
     val ll, lf = mutable.ListBuffer[Annotation]()
     annotations.foreach(_ match {
       case a: LogLevelAnnotation => ll += a
-      case a: LogFileAnnotation  => lf += a
+      case a: LogFileAnnotation => lf += a
       case _ =>
     })
     if (ll.size > 1) {
       val l = ll.map { case LogLevelAnnotation(x) => x }
       throw new LoggerException(
         s"""|At most one log level can be specified, but found '${l.mkString(", ")}' specified via:
-            |    - an option or annotation: -ll, --log-level, LogLevelAnnotation""".stripMargin
+          |    - an option or annotation: -ll, --log-level, LogLevelAnnotation""".stripMargin
       )
     }
     if (lf.size > 1) {
       throw new LoggerException(
         s"""|At most one log file can be specified, but found ${lf.size} combinations of:
-            |    - an options or annotation: -ltf, --log-to-file, --log-file, LogFileAnnotation""".stripMargin
+          |    - an options or annotation: -ltf, --log-to-file, --log-file, LogFileAnnotation""".stripMargin
       )
     }
     annotations
diff --git a/src/main/scala-2/chisel3/aop/Select.scala b/src/main/scala-2/chisel3/aop/Select.scala
index 25858d3dc79..bdaf4b876d5 100644
--- a/src/main/scala-2/chisel3/aop/Select.scala
+++ b/src/main/scala-2/chisel3/aop/Select.scala
@@ -45,7 +45,7 @@ object Select {
         val head = f.lift(cmd).toSeq
         head ++ collect(region)(f)
       case cmd if f.isDefinedAt(cmd) => Some(f(cmd))
-      case _                         => None
+      case _ => None
     }
   }
 
@@ -271,7 +271,7 @@ object Select {
   def registers(module: BaseModule): Seq[Data] = {
     check(module)
     collect(module._component.get.asInstanceOf[DefModule].block.getCommands()) {
-      case r: DefReg     => r.id
+      case r: DefReg => r.id
       case r: DefRegInit => r.id
     }
   }
@@ -487,11 +487,11 @@ object Select {
 
   // Given a loc, return all subcomponents of id that could be assigned to in connect
   private def getEffected(a: Arg): Seq[Data] = a match {
-    case Node(id: Data)        => DataMirror.collectAllMembers(id)
+    case Node(id: Data) => DataMirror.collectAllMembers(id)
     case Slot(imm: Node, name) => Seq(imm.id.asInstanceOf[Record].elements(name))
-    case Index(imm, _)         => getEffected(imm)
-    case LitIndex(imm, _)      => getEffected(imm)
-    case _                     => throw new InternalErrorException(s"Match error: a=$a")
+    case Index(imm, _) => getEffected(imm)
+    case LitIndex(imm, _) => getEffected(imm)
+    case _ => throw new InternalErrorException(s"Match error: a=$a")
   }
 
   // Given an arg, return the corresponding id. Don't use on a loc of a connect.
@@ -543,7 +543,7 @@ object Select {
         searchCommands(ifRegion, pred +: preds, processCommand)
         searchCommands(elseRegion, pred.not +: preds, processCommand)
       case LayerBlock(_, _, region) => searchCommands(region, preds, processCommand)
-      case cmd                      => processCommand(cmd, preds)
+      case cmd => processCommand(cmd, preds)
     }
 
     searchCommands(module._component.get.asInstanceOf[DefModule].block.getCommands(), Seq.empty, processCommand)
diff --git a/src/main/scala-2/chisel3/ltl/LTL.scala b/src/main/scala-2/chisel3/ltl/LTL.scala
index 65259f82941..9dd06580095 100644
--- a/src/main/scala-2/chisel3/ltl/LTL.scala
+++ b/src/main/scala-2/chisel3/ltl/LTL.scala
@@ -268,8 +268,8 @@ object Sequence {
     }
     atoms.head match {
       case seq: Sequence if atoms.tail.nonEmpty => seq.concat(Sequence(atoms.tail: _*))
-      case seq: Sequence                        => seq
-      case DelayAtom(min, None)      => needDelayTail.delayAtLeast(min)
+      case seq: Sequence => seq
+      case DelayAtom(min, None) => needDelayTail.delayAtLeast(min)
       case DelayAtom(min, Some(max)) => needDelayTail.delayRange(min, max)
     }
   }
diff --git a/src/main/scala-2/chisel3/simulator/Simulator.scala b/src/main/scala-2/chisel3/simulator/Simulator.scala
index b319c7a8b9a..57200efc0b7 100644
--- a/src/main/scala-2/chisel3/simulator/Simulator.scala
+++ b/src/main/scala-2/chisel3/simulator/Simulator.scala
@@ -22,7 +22,7 @@ final object Simulator {
   ) {
     def result = outcome match {
       case SimulationDigest(_, _, outcome) => outcome.get
-      case CompilationFailed(error)        => throw error
+      case CompilationFailed(error) => throw error
     }
   }
   sealed trait BackendInvocationOutcome[T]
@@ -99,7 +99,7 @@ trait Simulator {
   def customSimulationWorkingDirectory: Option[String] = None
   def verbose:                          Boolean = false
   def firtoolArgs:                      Seq[String] = Seq()
-  def commonCompilationSettings:        CommonCompilationSettings
+  def commonCompilationSettings: CommonCompilationSettings
 
   private[simulator] def processBackends(
     processor:                 Simulator.BackendProcessor,
diff --git a/src/main/scala-2/chisel3/simulator/package.scala b/src/main/scala-2/chisel3/simulator/package.scala
index 9026960a963..2b258690b15 100644
--- a/src/main/scala-2/chisel3/simulator/package.scala
+++ b/src/main/scala-2/chisel3/simulator/package.scala
@@ -162,7 +162,7 @@ package object simulator {
       // filelist does not exist.
       def maybeMoveFiles(filelist: Path): Unit = filelist match {
         case _ if Files.exists(filelist) => moveFiles(filelist)
-        case _                           =>
+        case _ =>
       }
 
       // Move files indicated by 'filelist.f' (which must exist).  Move files
@@ -204,7 +204,7 @@ package object simulator {
                   case ActualDirection.Input =>
                     Seq((element, ModuleInfo.Port(name, isGettable = true, isSettable = true)))
                   case ActualDirection.Output => Seq((element, ModuleInfo.Port(name, isGettable = true)))
-                  case _                      => Seq()
+                  case _ => Seq()
                 }
               } else {
                 Seq()
@@ -214,7 +214,7 @@ package object simulator {
         // Chisel ports can be Data or Property, but there is no ABI for Property ports, so we only return Data.
         DataMirror.modulePorts(dut).flatMap {
           case (name, data: Data) => leafPorts(data, name)
-          case _                  => Nil
+          case _ => Nil
         }
       }
       workspace.elaborate(
diff --git a/src/main/scala-2/chisel3/util/SRAM.scala b/src/main/scala-2/chisel3/util/SRAM.scala
index 2751f500950..e551b6889d4 100644
--- a/src/main/scala-2/chisel3/util/SRAM.scala
+++ b/src/main/scala-2/chisel3/util/SRAM.scala
@@ -307,11 +307,11 @@ class SRAMBlackbox(parameter: CIRCTSRAMParameter)
   setInline(
     desiredName + ".sv",
     s"""module ${parameter.moduleName}(
-       |${verilogInterface}
-       |);
-       |${logic}
-       |endmodule
-       |""".stripMargin
+      |${verilogInterface}
+      |);
+      |${logic}
+      |endmodule
+      |""".stripMargin
   )
 }
 
@@ -690,7 +690,7 @@ object SRAM {
       sramWritePort.enable := intfWritePort.enable
       sramWritePort.mask match {
         case Some(mask) => mask := intfWritePort.mask.get.asUInt
-        case None       => assert(intfWritePort.mask.isEmpty)
+        case None => assert(intfWritePort.mask.isEmpty)
       }
     }
     out.readwritePorts.zip(sramReadwritePorts).zip(readwritePortClocks).map {
@@ -703,7 +703,7 @@ object SRAM {
         sramReadwritePort.writeEnable := intfReadwritePort.isWrite
         sramReadwritePort.writeMask match {
           case Some(mask) => mask := intfReadwritePort.mask.get.asUInt
-          case None       => assert(intfReadwritePort.mask.isEmpty)
+          case None => assert(intfReadwritePort.mask.isEmpty)
         }
     }
 
@@ -869,7 +869,7 @@ object SRAM {
   // specific mitigation did not seem to work.  As a workaround, we simply write the extension methods
   // that are generated by the @instantiable macro so that we can use them here.
   implicit class SRAMDescriptionInstanceMethods(underlying: Instance[SRAMDescription]) {
-    implicit val mg:       internal.MacroGenerated = new chisel3.internal.MacroGenerated {}
+    implicit val mg: internal.MacroGenerated = new chisel3.internal.MacroGenerated {}
     def depthIn:           Property[BigInt] = underlying._lookup(_.depthIn)
     def widthIn:           Property[Int] = underlying._lookup(_.widthIn)
     def maskedIn:          Property[Boolean] = underlying._lookup(_.maskedIn)
@@ -930,8 +930,8 @@ private[chisel3] class SramMask(gen: Data) extends Record with OpaqueType {
 
   val elements = gen match {
     case e: Element => ListMap("" -> Bool())
-    case v: Vec[_]  => ListMap("" -> Vec(v.length, new SramMask(v.sample_element)))
-    case r: Record  => r.elements.map { case (name, tpe) => name -> new SramMask(tpe) }
+    case v: Vec[_] => ListMap("" -> Vec(v.length, new SramMask(v.sample_element)))
+    case r: Record => r.elements.map { case (name, tpe) => name -> new SramMask(tpe) }
   }
 
   /** Used to assert that the SramMask and process its elements */
diff --git a/src/main/scala-2/chisel3/util/Switch.scala b/src/main/scala-2/chisel3/util/Switch.scala
index 05e3454f78a..3240609b8ff 100644
--- a/src/main/scala-2/chisel3/util/Switch.scala
+++ b/src/main/scala-2/chisel3/util/Switch.scala
@@ -32,7 +32,7 @@ object switch {
       tree match {
         // TODO: remove when Chisel compatibility package is removed
         case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
-        case q"chisel3.util.is.apply( ..$params )( ..$body )"     => q"$acc.is( ..$params )( ..$body )"
+        case q"chisel3.util.is.apply( ..$params )( ..$body )" => q"$acc.is( ..$params )( ..$body )"
         case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
       }
     }
diff --git a/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala
index 44a7f15f8dc..3c350d4c757 100644
--- a/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala
+++ b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala
@@ -17,7 +17,7 @@ object scanLeftOr {
   def apply(data: UInt): UInt = {
     val width = data.widthOption match {
       case Some(w) => w
-      case None    => throw new IllegalArgumentException("Cannot call scanLeftOr on data with unknown width.")
+      case None => throw new IllegalArgumentException("Cannot call scanLeftOr on data with unknown width.")
     }
 
     def helper(s: Int, x: UInt): UInt =
@@ -39,7 +39,7 @@ object scanRightOr {
   def apply(data: UInt): UInt = {
     val width = data.widthOption match {
       case Some(w) => w
-      case None    => throw new IllegalArgumentException("Cannot call scanRightOr on data with unknown width.")
+      case None => throw new IllegalArgumentException("Cannot call scanRightOr on data with unknown width.")
     }
     def helper(s: Int, x: UInt): UInt =
       if (s >= width) x else helper(s + s, x | (x >> s))
diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
index 9bd2c085014..a1e5df21c1c 100644
--- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala
+++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala
@@ -232,8 +232,8 @@ object ChiselGeneratorAnnotation extends HasShellOptions {
 
     str match {
       case boolean if boolean.toBooleanOption.isDefined => boolean.toBoolean
-      case integer if integer.toIntOption.isDefined     => integer.toInt
-      case float if float.toDoubleOption.isDefined      => float.toDouble
+      case integer if integer.toIntOption.isDefined => integer.toInt
+      case float if float.toDoubleOption.isDefined => float.toDouble
       case classPattern(a, b) =>
         val constructor = Class.forName(a).getConstructors()(0)
         if (b.isEmpty) {
diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala
index 04045195392..3dc826dd5cf 100644
--- a/src/main/scala/chisel3/stage/package.scala
+++ b/src/main/scala/chisel3/stage/package.scala
@@ -21,18 +21,18 @@ package object stage {
       .foldLeft(new ChiselOptions()) { (c, x) =>
         x match {
           case PrintFullStackTraceAnnotation => c.copy(printFullStackTrace = true)
-          case ThrowOnFirstErrorAnnotation   => c.copy(throwOnFirstError = true)
+          case ThrowOnFirstErrorAnnotation => c.copy(throwOnFirstError = true)
           case WarningsAsErrorsAnnotation =>
             c.copy(warningFilters = c.warningFilters :+ WarningsAsErrorsAnnotation.asFilter)
           case ChiselOutputFileAnnotation(f) => c.copy(outputFile = Some(f))
-          case ChiselCircuitAnnotation(a)    => c.copy(chiselCircuit = Some(a))
-          case SourceRootAnnotation(s)       => c.copy(sourceRoots = c.sourceRoots :+ s)
-          case a: WarningConfigurationAnnotation     => c.copy(warningFilters = c.warningFilters ++ a.filters)
+          case ChiselCircuitAnnotation(a) => c.copy(chiselCircuit = Some(a))
+          case SourceRootAnnotation(s) => c.copy(sourceRoots = c.sourceRoots :+ s)
+          case a: WarningConfigurationAnnotation => c.copy(warningFilters = c.warningFilters ++ a.filters)
           case a: WarningConfigurationFileAnnotation => c.copy(warningFilters = c.warningFilters ++ a.filters)
-          case UseLegacyWidthBehavior         => c.copy(useLegacyWidth = true)
+          case UseLegacyWidthBehavior => c.copy(useLegacyWidth = true)
           case RemapLayer(oldLayer, newLayer) => c.copy(layerMap = c.layerMap + ((oldLayer, newLayer)))
-          case IncludeUtilMetadata            => c.copy(includeUtilMetadata = true)
-          case UseSRAMBlackbox                => c.copy(useSRAMBlackbox = true)
+          case IncludeUtilMetadata => c.copy(includeUtilMetadata = true)
+          case UseSRAMBlackbox => c.copy(useSRAMBlackbox = true)
         }
       }
 
diff --git a/src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala b/src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala
index 6b920284f57..90f7ad63c19 100644
--- a/src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala
+++ b/src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala
@@ -29,10 +29,10 @@ class AddDedupGroupAnnotations extends Phase {
     val skipAnnos = annotations.collect { case x: DedupGroupAnnotation => x.target }.toSet
 
     val annos = circuit.components.filter {
-      case x @ DefBlackBox(id, _, _, _, _)   => !id._isImportedDefinition
+      case x @ DefBlackBox(id, _, _, _, _) => !id._isImportedDefinition
       case DefIntrinsicModule(_, _, _, _, _) => false
-      case DefClass(_, _, _, _)              => false
-      case x                                 => true
+      case DefClass(_, _, _, _) => false
+      case x => true
     }.collect {
       case x if !(skipAnnos.contains(x.id.toTarget)) => DedupGroupAnnotation(x.id.toTarget, x.id._proposedName)
     }
diff --git a/src/main/scala/chisel3/stage/phases/Checks.scala b/src/main/scala/chisel3/stage/phases/Checks.scala
index 568e69554ba..41be0d5bac1 100644
--- a/src/main/scala/chisel3/stage/phases/Checks.scala
+++ b/src/main/scala/chisel3/stage/phases/Checks.scala
@@ -24,24 +24,24 @@ class Checks extends Phase {
     val st, outF, lm = collection.mutable.ListBuffer[Annotation]()
     annotations.foreach {
       case a: PrintFullStackTraceAnnotation.type => a +=: st
-      case a: ChiselOutputFileAnnotation         => a +=: outF
-      case a: RemapLayer                         => a +=: lm
+      case a: ChiselOutputFileAnnotation => a +=: outF
+      case a: RemapLayer => a +=: lm
       case _ =>
     }
 
     if (st.size > 1) {
       throw new OptionsException(
         s"""|At most one PrintFullStackTraceAnnotation can be specified, but found '${st.size}'. Did you duplicate:
-            |    - option or annotation: --full-stacktrace, PrintFullStackTraceAnnotation
-            |""".stripMargin
+          |    - option or annotation: --full-stacktrace, PrintFullStackTraceAnnotation
+          |""".stripMargin
       )
     }
 
     if (outF.size > 1) {
       throw new OptionsException(
         s"""|At most one Chisel output file can be specified but found '${outF.size}'. Did you duplicate:
-            |    - option or annotation: --chisel-output-file, ChiselOutputFileAnnotation
-            |""".stripMargin
+          |    - option or annotation: --chisel-output-file, ChiselOutputFileAnnotation
+          |""".stripMargin
       )
     }
 
@@ -50,7 +50,7 @@ class Checks extends Phase {
       case RemapLayer(oldLayer, newLayer) if lmMap.contains(oldLayer) =>
         throw new OptionsException(
           s"""|The same old layer, '$oldLayer' is renamed multiple times: '${lmMap(oldLayer)}' and '$newLayer'
-              |""".stripMargin
+            |""".stripMargin
         )
       case RemapLayer(oldLayer, newLayer) => lmMap += ((oldLayer, newLayer))
     }
diff --git a/src/main/scala/chisel3/util/BitwiseImpl.scala b/src/main/scala/chisel3/util/BitwiseImpl.scala
index 01dafe7dd37..a6dc1f5829d 100644
--- a/src/main/scala/chisel3/util/BitwiseImpl.scala
+++ b/src/main/scala/chisel3/util/BitwiseImpl.scala
@@ -30,8 +30,8 @@ private[chisel3] trait FillImpl {
   protected def _applyImpl(n: Int, x: UInt)(implicit sourceInfo: SourceInfo): UInt = {
     n match {
       case _ if n < 0 => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
-      case 0          => UInt(0.W)
-      case 1          => x
+      case 0 => UInt(0.W)
+      case 1 => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
         Mux(x.asBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ =>
@@ -49,7 +49,7 @@ private[chisel3] trait ReverseImpl {
 
   private def doit(in: UInt, length: Int)(implicit sourceInfo: SourceInfo): UInt =
     length match {
-      case _ if length < 0  => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
+      case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
       case _ if length <= 1 => in
       case _ if isPow2(length) && length >= 8 && length <= 64 =>
         // This esoterica improves simulation performance
diff --git a/src/main/scala/chisel3/util/Conditional.scala b/src/main/scala/chisel3/util/Conditional.scala
index 7f6bbfaff75..aa9ae3859fc 100644
--- a/src/main/scala/chisel3/util/Conditional.scala
+++ b/src/main/scala/chisel3/util/Conditional.scala
@@ -29,7 +29,7 @@ class SwitchContext[T <: Element](cond: T, whenContext: Option[WhenContext], lit
       def p = v.map(_.asUInt === cond.asUInt).reduce(_ || _)
       whenContext match {
         case Some(w) => new SwitchContext(cond, Some(w.elsewhen(p)(block)), lits ++ newLits)
-        case None    => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
+        case None => new SwitchContext(cond, Some(when(p)(block)), lits ++ newLits)
       }
     } else {
       this
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 99d1f046ac1..cbb1f5f77e1 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -41,7 +41,7 @@ class Counter private (r: Range, oldN: Option[Int] = None) extends AffectsChisel
     */
   def n: Int = oldN match {
     case Some(x) => x
-    case None    =>
+    case None =>
       // Reasonable for typical ranges
       require(
         r.start == 0 && r.step == 1,
diff --git a/src/main/scala/chisel3/util/Math.scala b/src/main/scala/chisel3/util/Math.scala
index aa27d89f761..8e660b50f93 100644
--- a/src/main/scala/chisel3/util/Math.scala
+++ b/src/main/scala/chisel3/util/Math.scala
@@ -130,9 +130,9 @@ object signedBitLength {
     */
   def apply(in: BigInt): Int = {
     in.toInt match {
-      case 0  => 0
+      case 0 => 0
       case -1 => 1
-      case _  => in.bitLength + 1
+      case _ => in.bitLength + 1
     }
 
   }
diff --git a/src/main/scala/chisel3/util/SparseVec.scala b/src/main/scala/chisel3/util/SparseVec.scala
index 67fd0e9f98e..0a1f8979651 100644
--- a/src/main/scala/chisel3/util/SparseVec.scala
+++ b/src/main/scala/chisel3/util/SparseVec.scala
@@ -82,7 +82,7 @@ class SparseVec[A <: Data](
   // twice.
   override final val elements = {
     var nonUniqueIndices: List[Int] = Nil // List is cheap in common case, no allocation
-    val duplicates:       HashSet[Int] = HashSet.empty[Int]
+    val duplicates: HashSet[Int] = HashSet.empty[Int]
     val result = indices.view.map { case index =>
       if (!duplicates.add(index))
         nonUniqueIndices ::= index
@@ -173,7 +173,7 @@ class SparseVec[A <: Data](
         // value needed, then start user data at address zero.  Otherwise, user
         // data starts at address one.
         val baseEncodedAddress = hasDefaultValue match {
-          case true  => 1
+          case true => 1
           case false => 0
         }
 
@@ -213,7 +213,7 @@ class SparseVec[A <: Data](
           bitPats,
           (hasDefaultValue, defaultValue) match {
             case (false, _) | (_, DefaultValueBehavior.Indeterminate) => BitPat.dontCare(encodedSize)
-            case _                                                    => BitPat(d.encoding(0, encodedSize))
+            case _ => BitPat(d.encoding(0, encodedSize))
           }
         )
 
diff --git a/src/main/scala/chisel3/util/circt/DPI.scala b/src/main/scala/chisel3/util/circt/DPI.scala
index 1e6cd2fe79f..a8c182d173e 100644
--- a/src/main/scala/chisel3/util/circt/DPI.scala
+++ b/src/main/scala/chisel3/util/circt/DPI.scala
@@ -107,13 +107,13 @@ object RawClockedVoidFunctionCall {
 // A common trait for DPI functions.
 trait DPIFunctionImport {
   def functionName: String
-  def inputNames:   Option[Seq[String]] = None
+  def inputNames: Option[Seq[String]] = None
 }
 
 // Base trait for a non-void function that returns `T`.
 trait DPINonVoidFunctionImport[T <: Data] extends DPIFunctionImport {
-  def ret:        T
-  def clocked:    Boolean
+  def ret:     T
+  def clocked: Boolean
   def outputName: Option[String] = None
   final def callWithEnable(enable: Bool, data: Data*): T =
     if (clocked) {
diff --git a/src/main/scala/chisel3/util/experimental/BoringUtils.scala b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
index f6eb88d82a5..d274263509c 100644
--- a/src/main/scala/chisel3/util/experimental/BoringUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/BoringUtils.scala
@@ -182,7 +182,7 @@ object BoringUtils {
       throw new BoringUtilsException(s"Sink ID '$name' not found in BoringUtils ID namespace")
     }
     def moduleName = component.toNamed match {
-      case c: ModuleName    => c
+      case c: ModuleName => c
       case c: ComponentName => c.module
       case _ => throw new ChiselException("Can only add a Module or Component sink", null)
     }
@@ -235,15 +235,15 @@ object BoringUtils {
       case Some(pi) =>
         // If the source is already a probe, don't double wrap it in a probe.
         purePortTypeBase.probeInfo match {
-          case Some(_)             => purePortTypeBase
+          case Some(_) => purePortTypeBase
           case None if pi.writable => RWProbe(purePortTypeBase)
-          case None                => Probe(purePortTypeBase)
+          case None => Probe(purePortTypeBase)
         }
       case None => purePortTypeBase
     }
     def isPort(d: Data): Boolean = d.topBindingOpt match {
       case Some(PortBinding(_)) => true
-      case _                    => false
+      case _ => false
     }
     def isDriveDone(d: Data): Boolean = {
       isDrive && isPort(d) && DataMirror.directionOf(d) == ActualDirection.Input
diff --git a/src/main/scala/chisel3/util/experimental/SlangUtils.scala b/src/main/scala/chisel3/util/experimental/SlangUtils.scala
index 837d3227924..b854eec4dc6 100644
--- a/src/main/scala/chisel3/util/experimental/SlangUtils.scala
+++ b/src/main/scala/chisel3/util/experimental/SlangUtils.scala
@@ -50,8 +50,8 @@ object SlangUtils {
                   }
 
                 value.value("direction").str match {
-                  case "In"    => Input(UInt(width.W))
-                  case "Out"   => Output(UInt(width.W))
+                  case "In" => Input(UInt(width.W))
+                  case "Out" => Output(UInt(width.W))
                   case "InOut" => Analog(width.W)
                 }
               }
diff --git a/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala b/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
index 8c85b6d1941..8a1dc49fb42 100644
--- a/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
+++ b/src/main/scala/chisel3/util/experimental/decode/EspressoMinimizer.scala
@@ -34,7 +34,7 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
       }
       val tableType: String = defaultType match {
         case '?' => "fr"
-        case _   => "fd"
+        case _ => "fd"
       }
       val rawTable = table.toString
         .split("\n")
@@ -49,9 +49,9 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
         .map(row => s"${row(0)} ${invert(row(1))}")
         .mkString("\n")
       s""".i ${table.inputWidth}
-         |.o ${table.outputWidth}
-         |.type ${tableType}
-         |""".stripMargin ++ (if (defaultType == '1') invertRawTable else rawTable)
+        |.o ${table.outputWidth}
+        |.type ${tableType}
+        |""".stripMargin ++ (if (defaultType == '1') invertRawTable else rawTable)
     }
 
     def readTable(espressoTable: String) = {
@@ -75,8 +75,8 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
 
     val input = writeTable(table)
     logger.trace(s"""espresso input table:
-                    |$input
-                    |""".stripMargin)
+      |$input
+      |""".stripMargin)
     val output =
       try {
         os.proc("espresso").call(stdin = input).out.chunks.mkString
@@ -85,8 +85,8 @@ object EspressoMinimizer extends Minimizer with LazyLogging {
           throw EspressoNotFoundException
       }
     logger.trace(s"""espresso output table:
-                    |$output
-                    |""".stripMargin)
+      |$output
+      |""".stripMargin)
     TruthTable.fromEspressoOutput(readTable(output), table.default)
   }
 }
diff --git a/src/main/scala/chisel3/util/random/GaloisLFSR.scala b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
index be3d8b98b0b..411a8ffa576 100644
--- a/src/main/scala/chisel3/util/random/GaloisLFSR.scala
+++ b/src/main/scala/chisel3/util/random/GaloisLFSR.scala
@@ -51,7 +51,7 @@ class GaloisLFSR(
     val first = s.head
     (s.tail :+ first).zipWithIndex.map {
       case (a, i) if taps(i + 1) && (i + 1 != s.size) => reduction(a, first)
-      case (a, _)                                     => a
+      case (a, _) => a
     }
   }
 
diff --git a/src/main/scala/chisel3/util/random/LFSR.scala b/src/main/scala/chisel3/util/random/LFSR.scala
index b26cfa5d911..0c7c46551c4 100644
--- a/src/main/scala/chisel3/util/random/LFSR.scala
+++ b/src/main/scala/chisel3/util/random/LFSR.scala
@@ -50,7 +50,7 @@ trait LFSR extends PRNG {
   override protected def resetValue: Vec[Bool] = seed match {
     case Some(s) =>
       reduction match {
-        case XOR  => require(s != 0, "Seed cannot be zero")
+        case XOR => require(s != 0, "Seed cannot be zero")
         case XNOR => require(s != BigInt(2).pow(width) - 1, "Seed cannot be all ones (max value)")
       }
       super.resetValue
@@ -59,7 +59,7 @@ trait LFSR extends PRNG {
       val res = WireDefault(Vec(width, Bool()), DontCare)
 
       reduction match {
-        case XOR  => res(0) := true.B
+        case XOR => res(0) := true.B
         case XNOR => res(0) := false.B
       }
 
diff --git a/src/main/scala/chisel3/util/random/PRNG.scala b/src/main/scala/chisel3/util/random/PRNG.scala
index 2566c8d6978..3e2e79e0efa 100644
--- a/src/main/scala/chisel3/util/random/PRNG.scala
+++ b/src/main/scala/chisel3/util/random/PRNG.scala
@@ -44,7 +44,7 @@ abstract class PRNG(val width: Int, val seed: Option[BigInt], step: Int = 1, upd
   /** Allow implementations to override the reset value, e.g., if some bits should be don't-cares. */
   protected def resetValue: Vec[Bool] = seed match {
     case Some(s) => VecInit(s.U(width.W).asBools)
-    case None    => WireDefault(Vec(width, Bool()), DontCare)
+    case None => WireDefault(Vec(width, Bool()), DontCare)
   }
 
   /** Internal state of the PRNG. If the user sets a seed, this is initialized to the seed. If the user does not set a
diff --git a/src/main/scala/circt/stage/Annotations.scala b/src/main/scala/circt/stage/Annotations.scala
index 9cd9285741c..b3c784c5042 100644
--- a/src/main/scala/circt/stage/Annotations.scala
+++ b/src/main/scala/circt/stage/Annotations.scala
@@ -21,10 +21,10 @@ object PreserveAggregate extends HasShellOptions {
     new ShellOption[String](
       longOption = "preserve-aggregate",
       toAnnotationSeq = _ match {
-        case "none"   => Seq.empty
+        case "none" => Seq.empty
         case "1d-vec" => Seq(PreserveAggregate(PreserveAggregate.OneDimVec))
-        case "vec"    => Seq(PreserveAggregate(PreserveAggregate.Vec))
-        case "all"    => Seq(PreserveAggregate(PreserveAggregate.All))
+        case "vec" => Seq(PreserveAggregate(PreserveAggregate.Vec))
+        case "all" => Seq(PreserveAggregate(PreserveAggregate.All))
       },
       helpText = "Do not lower aggregate types to ground types"
     )
@@ -70,13 +70,13 @@ object CIRCTTargetAnnotation extends HasShellOptions {
     new ShellOption[String](
       longOption = "target",
       toAnnotationSeq = _ match {
-        case "chirrtl"       => Seq(CIRCTTargetAnnotation(CIRCTTarget.CHIRRTL))
-        case "firrtl"        => Seq(CIRCTTargetAnnotation(CIRCTTarget.FIRRTL))
-        case "hw"            => Seq(CIRCTTargetAnnotation(CIRCTTarget.HW))
-        case "verilog"       => Seq(CIRCTTargetAnnotation(CIRCTTarget.Verilog))
+        case "chirrtl" => Seq(CIRCTTargetAnnotation(CIRCTTarget.CHIRRTL))
+        case "firrtl" => Seq(CIRCTTargetAnnotation(CIRCTTarget.FIRRTL))
+        case "hw" => Seq(CIRCTTargetAnnotation(CIRCTTarget.HW))
+        case "verilog" => Seq(CIRCTTargetAnnotation(CIRCTTarget.Verilog))
         case "systemverilog" => Seq(CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog))
-        case "btor2"         => Seq(CIRCTTargetAnnotation(CIRCTTarget.Btor2))
-        case a               => throw new OptionsException(s"Unknown target name '$a'! (Did you misspell it?)")
+        case "btor2" => Seq(CIRCTTargetAnnotation(CIRCTTarget.Btor2))
+        case a => throw new OptionsException(s"Unknown target name '$a'! (Did you misspell it?)")
       },
       helpText = "The CIRCT",
       helpValueName = Some("{chirrtl|firrtl|hw|verilog|systemverilog|btor2}")
diff --git a/src/main/scala/circt/stage/ChiselStage.scala b/src/main/scala/circt/stage/ChiselStage.scala
index 93cdf601ea7..3e2cd5f9b41 100644
--- a/src/main/scala/circt/stage/ChiselStage.scala
+++ b/src/main/scala/circt/stage/ChiselStage.scala
@@ -81,7 +81,7 @@ object ChiselStage {
       case a: ChiselCircuitAnnotation =>
         circuitAnno = Some(CircuitSerializationAnnotation(a.circuit, "", FirrtlFileFormat))
         None
-      case _: Unserializable     => None
+      case _: Unserializable => None
       case _: CustomFileEmission => None
       case a => Some(a)
     }
diff --git a/src/main/scala/circt/stage/package.scala b/src/main/scala/circt/stage/package.scala
index c42fbf7a362..52a82dba015 100644
--- a/src/main/scala/circt/stage/package.scala
+++ b/src/main/scala/circt/stage/package.scala
@@ -16,19 +16,19 @@ package object stage {
 
     def view(annotations: AnnotationSeq): CIRCTOptions =
       annotations.collect {
-        case a: CIRCTOption  => a
+        case a: CIRCTOption => a
         case a: FirrtlOption => a
       }
         .foldLeft(new CIRCTOptions()) { (acc, c) =>
           c match {
-            case OutputFileAnnotation(a)  => acc.copy(outputFile = Some(new File(a)))
+            case OutputFileAnnotation(a) => acc.copy(outputFile = Some(new File(a)))
             case CIRCTTargetAnnotation(a) => acc.copy(target = Some(a))
-            case PreserveAggregate(a)     => acc.copy(preserveAggregate = Some(a))
-            case FirtoolBinaryPath(a)     => acc.copy(firtoolBinaryPath = Some(a))
-            case FirtoolOption(a)         => acc.copy(firtoolOptions = acc.firtoolOptions :+ a)
-            case SplitVerilog             => acc.copy(splitVerilog = true)
-            case DumpFir                  => acc.copy(dumpFir = true)
-            case _                        => acc
+            case PreserveAggregate(a) => acc.copy(preserveAggregate = Some(a))
+            case FirtoolBinaryPath(a) => acc.copy(firtoolBinaryPath = Some(a))
+            case FirtoolOption(a) => acc.copy(firtoolOptions = acc.firtoolOptions :+ a)
+            case SplitVerilog => acc.copy(splitVerilog = true)
+            case DumpFir => acc.copy(dumpFir = true)
+            case _ => acc
           }
         }
 
diff --git a/src/main/scala/circt/stage/phases/CIRCT.scala b/src/main/scala/circt/stage/phases/CIRCT.scala
index b174328ffcd..c1a541acdb0 100644
--- a/src/main/scala/circt/stage/phases/CIRCT.scala
+++ b/src/main/scala/circt/stage/phases/CIRCT.scala
@@ -34,11 +34,11 @@ private object Helpers {
   implicit class LogLevelHelpers(logLevel: LogLevel.Value) {
     def toCIRCTOptions: Seq[String] = logLevel match {
       case LogLevel.Error => Seq.empty
-      case LogLevel.Warn  => Seq.empty
-      case LogLevel.Info  => Seq("-verbose-pass-executions")
+      case LogLevel.Warn => Seq.empty
+      case LogLevel.Info => Seq("-verbose-pass-executions")
       case LogLevel.Debug => Seq("-verbose-pass-executions")
       case LogLevel.Trace => Seq("-verbose-pass-executions", "-mlir-print-ir-after-all")
-      case LogLevel.None  => Seq.empty
+      case LogLevel.None => Seq.empty
     }
   }
 
@@ -63,7 +63,7 @@ private object Helpers {
       .mkString("\n")
     filtered.forall(_.isWhitespace) match {
       case false => JsonProtocol.deserialize(filtered, false)
-      case true  => Seq.empty
+      case true => Seq.empty
     }
   }
 
@@ -85,9 +85,9 @@ private[this] object Exceptions {
     */
   def dramaticError(header: String, body: String): String = {
     s"""|$header
-        |${"-" * 78}
-        |$body
-        |${"-" * 78}""".stripMargin
+      |${"-" * 78}
+      |$body
+      |${"-" * 78}""".stripMargin
   }
 
   def versionAdvice: String =
@@ -121,9 +121,9 @@ private[this] object Exceptions {
         dramaticError(
           header = s"Error resolving firtool",
           body = s"""|Chisel requires firtool, the MLIR-based FIRRTL Compiler (MFC), to generate Verilog.
-                     |Something is wrong with your firtool installation, please see the following logging
-                     |information.
-                     |$msg""".stripMargin
+            |Something is wrong with your firtool installation, please see the following logging
+            |information.
+            |$msg""".stripMargin
         )
       )
       with NoStackTrace
@@ -150,7 +150,7 @@ class CIRCT extends Phase {
     // Early exit (do not run firtool) if the target is "CHIRRTL", i.e., specification FIRRTL.
     circtOptions.target match {
       case Some(CIRCTTarget.CHIRRTL) => return annotations
-      case _                         =>
+      case _ =>
     }
 
     val firrtlOptions = view[FirrtlOptions](annotations)
@@ -190,8 +190,8 @@ class CIRCT extends Phase {
     /* Filter the annotations to only those things which CIRCT should see. */
     val filteredAnnotations = annotationsx.flatMap {
       case _: ChiselCircuitAnnotation => None
-      case _: Unserializable          => None
-      case _: CustomFileEmission      => None
+      case _: Unserializable => None
+      case _: CustomFileEmission => None
       case a => Some(a)
     }
 
@@ -241,21 +241,21 @@ class CIRCT extends Phase {
         /* The following options are on by default, so we disable them if they are false. */
         (circtOptions.preserveAggregate match {
           case Some(PreserveAggregate.OneDimVec) => Seq("-preserve-aggregate=1d-vec")
-          case Some(PreserveAggregate.Vec)       => Seq("-preserve-aggregate=vec")
-          case Some(PreserveAggregate.All)       => Seq("-preserve-aggregate=all")
-          case None                              => None
+          case Some(PreserveAggregate.Vec) => Seq("-preserve-aggregate=vec")
+          case Some(PreserveAggregate.All) => Seq("-preserve-aggregate=all")
+          case None => None
         }) ++
         circtOptions.preserveAggregate.map(_ => "-scalarize-public-modules=0") ++
         includeDirs.flatMap(d => Seq("--include-dir", d.toString)) ++
         /* Convert the target to a firtool-compatible option. */
         ((circtOptions.target, split) match {
-          case (Some(CIRCTTarget.FIRRTL), false)        => Seq("-ir-fir")
-          case (Some(CIRCTTarget.HW), false)            => Seq("-ir-hw")
-          case (Some(CIRCTTarget.Verilog), true)        => Seq("--split-verilog", s"-o=${stageOptions.targetDir}")
-          case (Some(CIRCTTarget.Verilog), false)       => None
-          case (Some(CIRCTTarget.SystemVerilog), true)  => Seq("--split-verilog", s"-o=${stageOptions.targetDir}")
+          case (Some(CIRCTTarget.FIRRTL), false) => Seq("-ir-fir")
+          case (Some(CIRCTTarget.HW), false) => Seq("-ir-hw")
+          case (Some(CIRCTTarget.Verilog), true) => Seq("--split-verilog", s"-o=${stageOptions.targetDir}")
+          case (Some(CIRCTTarget.Verilog), false) => None
+          case (Some(CIRCTTarget.SystemVerilog), true) => Seq("--split-verilog", s"-o=${stageOptions.targetDir}")
           case (Some(CIRCTTarget.SystemVerilog), false) => None
-          case (Some(CIRCTTarget.Btor2), false)         => Seq("--btor2")
+          case (Some(CIRCTTarget.Btor2), false) => Seq("--btor2")
           case (None, _) =>
             throw new Exception(
               "No 'circtOptions.target' specified. This should be impossible if dependencies are satisfied!"
diff --git a/src/main/scala/circt/stage/phases/Checks.scala b/src/main/scala/circt/stage/phases/Checks.scala
index a2822e2d0f8..30af0a41f16 100644
--- a/src/main/scala/circt/stage/phases/Checks.scala
+++ b/src/main/scala/circt/stage/phases/Checks.scala
@@ -22,7 +22,7 @@ class Checks extends Phase {
     annotations.foreach {
       case a: OutputFileAnnotation => outputFile += a
       case a @ SplitVerilog => split += a
-      case a: TargetDirAnnotation   => targetDir += a
+      case a: TargetDirAnnotation => targetDir += a
       case a: CIRCTTargetAnnotation => target += a
       case _ =>
     }
diff --git a/src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala b/src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala
index c1cf81e7480..be1f65405d8 100644
--- a/src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala
+++ b/src/test/scala/chisel3/util/experimental/decode/TruthTableSpec.scala
@@ -22,11 +22,11 @@ class TruthTableSpec extends AnyFlatSpec {
     BitPat("b0")
   )
   val str = """001->?
-              |010->?
-              |100->1
-              |101->1
-              |111->1
-              |0""".stripMargin
+    |010->?
+    |100->1
+    |101->1
+    |111->1
+    |0""".stripMargin
   "TruthTable" should "serialize" in {
     assert(table.toString contains "001->?")
     assert(table.toString contains "010->?")
@@ -118,9 +118,9 @@ class TruthTableSpec extends AnyFlatSpec {
     assert(
       TruthTable.fromEspressoOutput(mapping, BitPat("b?")) ==
         TruthTable.fromString("""110->001
-                                |111->111
-                                |?
-                                |""".stripMargin)
+          |111->111
+          |?
+          |""".stripMargin)
     )
   }
 
diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
index b466bea5dba..f818c9b60fd 100644
--- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
+++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala
@@ -116,11 +116,11 @@ class DiamondTester extends BasicTester {
 class AnnotatingDiamondSpec extends AnyFreeSpec with Matchers {
 
   """|Diamond is an example of a module that has two sub-modules A and B who both instantiate their
-     |own instances of module C.  This highlights the difference between specific and general
-     |annotation scopes""".stripMargin - {
+    |own instances of module C.  This highlights the difference between specific and general
+    |annotation scopes""".stripMargin - {
 
     """|annotations are not resolved at after circuit elaboration,
-       |that happens only after emit has been called on circuit""".stripMargin in {
+      |that happens only after emit has been called on circuit""".stripMargin in {
 
       val annos = (new ChiselStage)
         .execute(
diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala
index 4d46237e9bd..6c9ead407fd 100644
--- a/src/test/scala/chiselTests/BlackBoxImpl.scala
+++ b/src/test/scala/chiselTests/BlackBoxImpl.scala
@@ -23,12 +23,12 @@ class BlackBoxAdd(n: Int) extends HasBlackBoxInline {
   setInline(
     "BlackBoxAdd.v",
     s"""
-       |module BlackBoxAdd(
-       |    input  [15:0] in,
-       |    output [15:0] out
-       |);
-       |  assign out = in + $n;
-       |endmodule
+      |module BlackBoxAdd(
+      |    input  [15:0] in,
+      |    output [15:0] out
+      |);
+      |  assign out = in + $n;
+      |endmodule
     """.stripMargin
   )
 }
diff --git a/src/test/scala/chiselTests/ChiselEnum.scala b/src/test/scala/chiselTests/ChiselEnum.scala
index 861aa1211ab..4effa28270e 100644
--- a/src/test/scala/chiselTests/ChiselEnum.scala
+++ b/src/test/scala/chiselTests/ChiselEnum.scala
@@ -531,8 +531,8 @@ class ChiselEnumSpec extends ChiselFlatSpec with Utils with FileCheck {
     }
     elaborateAndFileCheckOutAndErr(new MyModule)(
       """| CHECK:      [W001] Casting non-literal UInt to [[enum:[a-zA-Z0-9_$.]+]].
-         | CHECK-SAME: You can use [[enum]].safe to cast without this warning.
-         |""".stripMargin
+        | CHECK-SAME: You can use [[enum]].safe to cast without this warning.
+        |""".stripMargin
     )
   }
 
@@ -797,17 +797,17 @@ class ChiselEnumAnnotationSpec extends AnyFreeSpec with Matchers {
     println("Enum definitions:")
     annos.foreach {
       case EnumDefAnnotation(enumTypeName, definition) => println(s"\t$enumTypeName: $definition")
-      case _                                           =>
+      case _ =>
     }
     println("Enum components:")
     annos.foreach {
       case EnumComponentAnnotation(target, enumTypeName) => println(s"\t$target => $enumTypeName")
-      case _                                             =>
+      case _ =>
     }
     println("Enum vecs:")
     annos.foreach {
       case EnumVecAnnotation(target, enumTypeName, fields) => println(s"\t$target[$fields] => $enumTypeName")
-      case _                                               =>
+      case _ =>
     }
   }
 
@@ -821,7 +821,7 @@ class ChiselEnumAnnotationSpec extends AnyFreeSpec with Matchers {
   def isCorrect(anno: EnumComponentAnnotation, correct: CorrectCompAnno): Boolean = {
     (anno.target match {
       case ComponentName(name, _) => name == correct.targetName
-      case _                      => throw new Exception("Unknown target type in EnumComponentAnnotation")
+      case _ => throw new Exception("Unknown target type in EnumComponentAnnotation")
     }) &&
     (anno.enumTypeName == correct.typeName || anno.enumTypeName.endsWith("." + correct.typeName) ||
       anno.enumTypeName.endsWith("$" + correct.typeName))
@@ -830,7 +830,7 @@ class ChiselEnumAnnotationSpec extends AnyFreeSpec with Matchers {
   def isCorrect(anno: EnumVecAnnotation, correct: CorrectVecAnno): Boolean = {
     (anno.target match {
       case ComponentName(name, _) => name == correct.targetName
-      case _                      => throw new Exception("Unknown target type in EnumVecAnnotation")
+      case _ => throw new Exception("Unknown target type in EnumVecAnnotation")
     }) &&
     (anno.typeName == correct.typeName || anno.typeName.endsWith("." + correct.typeName) ||
       anno.typeName.endsWith("$" + correct.typeName)) &&
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 04710e88361..ecf69dd531c 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -218,7 +218,7 @@ trait FileCheck extends BeforeAndAfterEachTestData { this: Suite =>
 
   private val testRunDir: os.Path = os.pwd / os.RelPath(BackendCompilationUtilities.TestDirectory)
   private val suiteDir:   os.Path = testRunDir / sanitize(suiteName)
-  private var checkFile:  Option[os.Path] = None
+  private var checkFile: Option[os.Path] = None
 
   override def beforeEach(testData: TestData): Unit = {
     // TODO check that these are always available
@@ -385,7 +385,7 @@ trait Utils {
   def extractCause[A <: Throwable: ClassTag](thunk: => Any): Unit = {
     def unrollCauses(a: Throwable): Seq[Throwable] = a match {
       case null => Seq.empty
-      case _    => a +: unrollCauses(a.getCause)
+      case _ => a +: unrollCauses(a.getCause)
     }
 
     val exceptions: Seq[_ <: Throwable] =
@@ -400,7 +400,7 @@ trait Utils {
       case Some(a) => throw a
       case None =>
         exceptions match {
-          case Nil    => ()
+          case Nil => ()
           case h :: t => throw h
         }
     }
diff --git a/src/test/scala/chiselTests/DPISpec.scala b/src/test/scala/chiselTests/DPISpec.scala
index 5f1bbbb90f1..f9c4ede9a3a 100644
--- a/src/test/scala/chiselTests/DPISpec.scala
+++ b/src/test/scala/chiselTests/DPISpec.scala
@@ -15,18 +15,18 @@ import svsim._
 private object EmitDPIImplementation {
   def apply() = {
     val dpiImpl = s"""
-                     |#include <stdint.h>
-                     |#include <iostream>
-                     |
-                     |extern "C" void hello()
-                     |{
-                     |    std::cout << "hello from c++\\n";
-                     |}
-                     |
-                     |extern "C" void add(int lhs, int rhs, int* result)
-                     |{
-                     |    *result = lhs + rhs;
-                     |}
+      |#include <stdint.h>
+      |#include <iostream>
+      |
+      |extern "C" void hello()
+      |{
+      |    std::cout << "hello from c++\\n";
+      |}
+      |
+      |extern "C" void add(int lhs, int rhs, int* result)
+      |{
+      |    *result = lhs + rhs;
+      |}
   """.stripMargin
 
     class DummyDPI extends BlackBox with HasBlackBoxInline {
diff --git a/src/test/scala/chiselTests/DecoupledSpec.scala b/src/test/scala/chiselTests/DecoupledSpec.scala
index 434c5c13662..58c9ab8f6a9 100644
--- a/src/test/scala/chiselTests/DecoupledSpec.scala
+++ b/src/test/scala/chiselTests/DecoupledSpec.scala
@@ -24,12 +24,12 @@ class DecoupledSpec extends ChiselFlatSpec with FileCheck {
       val deq = IO(Decoupled(UInt(8.W)))
       deq <> enq.map(_ + 1.U)
     })("""|CHECK: node [[node1:[a-zA-Z0-9_]+]] = add(enq.bits, UInt<1>(0h1))
-          |CHECK: node [[node2:[a-zA-Z0-9_]+]] = tail([[node1]], 1)
-          |CHECK: connect [[result:[a-zA-Z0-9_]+]].bits, [[node2]]
-          |# Check for back-pressure (ready signal is driven in the opposite direction of bits + valid)
-          |CHECK: connect enq.ready, [[result]].ready
-          |CHECK: connect deq, [[result]]
-          |""".stripMargin)
+      |CHECK: node [[node2:[a-zA-Z0-9_]+]] = tail([[node1]], 1)
+      |CHECK: connect [[result:[a-zA-Z0-9_]+]].bits, [[node2]]
+      |# Check for back-pressure (ready signal is driven in the opposite direction of bits + valid)
+      |CHECK: connect enq.ready, [[result]].ready
+      |CHECK: connect deq, [[result]]
+      |""".stripMargin)
   }
 
   "Decoupled.map" should "apply a function to a wrapped Bundle" in {
diff --git a/src/test/scala/chiselTests/ExtModuleImpl.scala b/src/test/scala/chiselTests/ExtModuleImpl.scala
index d7da39a2edc..b079fc566af 100644
--- a/src/test/scala/chiselTests/ExtModuleImpl.scala
+++ b/src/test/scala/chiselTests/ExtModuleImpl.scala
@@ -27,12 +27,12 @@ class ExtModuleAdd(n: Int) extends ExtModule with HasExtModuleInline {
   setInline(
     "ExtModuleAdd.v",
     s"""
-       |module ExtModuleAdd(
-       |    input  [15:0] in,
-       |    output [15:0] out
-       |);
-       |  assign out = in + $n;
-       |endmodule
+      |module ExtModuleAdd(
+      |    input  [15:0] in,
+      |    output [15:0] out
+      |);
+      |  assign out = in + $n;
+      |endmodule
     """.stripMargin
   )
 }
diff --git a/src/test/scala/chiselTests/LayerSpec.scala b/src/test/scala/chiselTests/LayerSpec.scala
index 34fbe431a55..41854d7276b 100644
--- a/src/test/scala/chiselTests/LayerSpec.scala
+++ b/src/test/scala/chiselTests/LayerSpec.scala
@@ -42,15 +42,15 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     info("CHIRRTL emission looks correct")
     generateFirrtlAndFileCheck(new Foo) {
       s"""|CHECK:      layer A, bind, "A" :
-          |CHECK-NEXT:   layer B, bind, "A${sep}B" :
-          |
-          |CHECK:      module Foo :
-          |CHECK:        layerblock A :
-          |CHECK-NEXT:     wire w : UInt<1>
-          |CHECK:          layerblock B :
-          |CHECK-NEXT:       wire x : UInt<1>
-          |CHECK:        wire y : UInt<1>
-          |""".stripMargin
+        |CHECK-NEXT:   layer B, bind, "A${sep}B" :
+        |
+        |CHECK:      module Foo :
+        |CHECK:        layerblock A :
+        |CHECK-NEXT:     wire w : UInt<1>
+        |CHECK:          layerblock B :
+        |CHECK-NEXT:       wire x : UInt<1>
+        |CHECK:        wire y : UInt<1>
+        |""".stripMargin
     }
   }
 
@@ -66,9 +66,9 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     val check =
       generateFirrtlAndFileCheck(new Foo) {
         """|CHECK: layerblock A :
-           |CHECK:   layerblock B :
-           |CHECK:     layerblock C :
-           |""".stripMargin
+          |CHECK:   layerblock B :
+          |CHECK:     layerblock C :
+          |""".stripMargin
       }
   }
 
@@ -83,8 +83,8 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     val check =
       generateFirrtlAndFileCheck(new Foo) {
         """|CHECK:     layerblock A :
-           |CHECK-NOT:   layerblock C :
-           |""".stripMargin
+          |CHECK-NOT:   layerblock C :
+          |""".stripMargin
       }
   }
 
@@ -126,13 +126,13 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     // Layer-under-module-under-layer is rejected by firtool presently.
     generateFirrtlAndFileCheck(new Foo) {
       """|CHECK:      module Bar :
-         |CHECK:        layerblock A :
-         |CHECK-NEXT:     layerblock B :
-         |
-         |CHECK:      module Foo :
-         |CHECK:        layerblock A :
-         |CHECK-NEXT:     inst bar of Bar
-         |""".stripMargin
+        |CHECK:        layerblock A :
+        |CHECK-NEXT:     layerblock B :
+        |
+        |CHECK:      module Foo :
+        |CHECK:        layerblock A :
+        |CHECK-NEXT:     inst bar of Bar
+        |""".stripMargin
     }
   }
 
@@ -155,14 +155,14 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
 
     generateFirrtlAndFileCheck(new Foo) {
       """|CHECK:      module Foo :
-         |CHECK:        define x = probe(a)
-         |CHECK-NEXT:   define y = probe(b)
-         |CHECK-NEXT:   layerblock A :
-         |CHECK-NEXT:     define x = probe(c)
-         |CHECK-NEXT:     define y = probe(d)
-         |CHECK-NEXT:     layerblock B :
-         |CHECK-NEXT:       define y = probe(e)
-         |""".stripMargin
+        |CHECK:        define x = probe(a)
+        |CHECK-NEXT:   define y = probe(b)
+        |CHECK-NEXT:   layerblock A :
+        |CHECK-NEXT:     define x = probe(c)
+        |CHECK-NEXT:     define y = probe(d)
+        |CHECK-NEXT:     layerblock B :
+        |CHECK-NEXT:       define y = probe(e)
+        |""".stripMargin
     }
   }
 
@@ -204,11 +204,11 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
 
     generateFirrtlAndFileCheck(new Foo) {
       """|CHECK:      layer A, bind
-         |CHECK-NEXT:   layer B, bind
-         |CHECK-NEXT: layer C, bind
-         |
-         |CHECK: module Foo enablelayer A.B enablelayer C :
-         |""".stripMargin
+        |CHECK-NEXT:   layer B, bind
+        |CHECK-NEXT: layer C, bind
+        |
+        |CHECK: module Foo enablelayer A.B enablelayer C :
+        |""".stripMargin
     }
 
   }
@@ -278,19 +278,19 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
 
     generateFirrtlAndFileCheck(new Foo) {
       s"""|CHECK:      circuit Foo :
-          |CHECK-NEXT:   layer LayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir${sep}SublayerWithDefaultOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
-          |CHECK-NEXT:   layer LayerWithCustomOutputDir, bind, "myOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "myOutputDir${sep}SublayerWithDefaultOutputDir"
-          |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
-          |CHECK-NEXT:   layer LayerWithNoOutputDir, bind :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "SublayerWithDefaultOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
-          |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
-          |""".stripMargin
+        |CHECK-NEXT:   layer LayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir${sep}SublayerWithDefaultOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
+        |CHECK-NEXT:   layer LayerWithCustomOutputDir, bind, "myOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "myOutputDir${sep}SublayerWithDefaultOutputDir"
+        |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
+        |CHECK-NEXT:   layer LayerWithNoOutputDir, bind :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "SublayerWithDefaultOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithCustomOutputDir, bind, "myOtherOutputDir" :
+        |CHECK-NEXT:     layer SublayerWithNoOutputDir, bind :
+        |""".stripMargin
     }
   }
 
@@ -313,8 +313,8 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
 
     generateFirrtlAndFileCheck(new Foo) {
       """|CHECK:     layer A
-         |CHECK-NOT:   layerblock
-         |""".stripMargin
+        |CHECK-NOT:   layerblock
+        |""".stripMargin
     }
   }
 
@@ -325,10 +325,10 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     info("default layers are emitted")
     fileCheckString(chirrtl) {
       s"""|CHECK:      layer Verification, bind, "verification" :
-          |CHECK-NEXT:   layer Assert, bind, "verification${sep}assert" :
-          |CHECK-NEXT:   layer Assume, bind, "verification${sep}assume" :
-          |CHECK-NEXT:   layer Cover, bind, "verification${sep}cover" :
-          |""".stripMargin
+        |CHECK-NEXT:   layer Assert, bind, "verification${sep}assert" :
+        |CHECK-NEXT:   layer Assume, bind, "verification${sep}assume" :
+        |CHECK-NEXT:   layer Cover, bind, "verification${sep}cover" :
+        |""".stripMargin
     }
 
     info("user-defined layers are not emitted if not used")
@@ -405,9 +405,9 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     info("FIRRTL okay")
     generateFirrtlAndFileCheck(new Foo) {
       """|CHECK:      layer A, bind
-         |CHECK-NEXT:   layer B, inline :
-         |CHECK-NEXT:     layer C, inline :
-         |""".stripMargin
+        |CHECK-NEXT:   layer B, inline :
+        |CHECK-NEXT:     layer C, inline :
+        |""".stripMargin
     }
 
     info("SystemVerilog okay")
@@ -420,17 +420,17 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
     )
     fileCheckString(verilog) {
       """|CHECK:      module Foo(
-         |CHECK-NOT:    assert property
-         |
-         |CHECK:      module Foo_A(
-         |CHECK-NOT:    `ifdef
-         |CHECK:        foo: assert property
-         |CHECK:        `ifdef layer_Foo$A$B
-         |CHECK-NEXT:     bar: assert property
-         |CHECK-NEXT:     `ifdef layer_Foo$A$B$C
-         |CHECK-NEXT:       baz: assert property
-         |CHECK-NEXT:     `endif
-         |CHECK-NEXT:   `endif""".stripMargin
+        |CHECK-NOT:    assert property
+        |
+        |CHECK:      module Foo_A(
+        |CHECK-NOT:    `ifdef
+        |CHECK:        foo: assert property
+        |CHECK:        `ifdef layer_Foo$A$B
+        |CHECK-NEXT:     bar: assert property
+        |CHECK-NEXT:     `ifdef layer_Foo$A$B$C
+        |CHECK-NEXT:       baz: assert property
+        |CHECK-NEXT:     `endif
+        |CHECK-NEXT:   `endif""".stripMargin
     }
   }
 
@@ -476,15 +476,15 @@ class LayerSpec extends ChiselFlatSpec with Utils with FileCheck {
 
     generateFirrtlAndFileCheck(new Foo) {
       s"""|CHECK:      layer LayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir" :
-          |CHECK-NEXT:   layer InlineSublayer, inline :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir${sep}SublayerWithDefaultOutputDir" :
-          |CHECK-NEXT: layer LayerWithCustomOutputDir, bind, "myOutputDir" :
-          |CHECK-NEXT:   layer InlineSublayer, inline :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "myOutputDir${sep}SublayerWithDefaultOutputDir" :
-          |CHECK-NEXT: layer LayerWithNoOutputDir, bind :
-          |CHECK-NEXT:   layer InlineSublayer, inline :
-          |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "SublayerWithDefaultOutputDir" :
-          |""".stripMargin
+        |CHECK-NEXT:   layer InlineSublayer, inline :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "LayerWithDefaultOutputDir${sep}SublayerWithDefaultOutputDir" :
+        |CHECK-NEXT: layer LayerWithCustomOutputDir, bind, "myOutputDir" :
+        |CHECK-NEXT:   layer InlineSublayer, inline :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "myOutputDir${sep}SublayerWithDefaultOutputDir" :
+        |CHECK-NEXT: layer LayerWithNoOutputDir, bind :
+        |CHECK-NEXT:   layer InlineSublayer, inline :
+        |CHECK-NEXT:     layer SublayerWithDefaultOutputDir, bind, "SublayerWithDefaultOutputDir" :
+        |""".stripMargin
     }
   }
 }
diff --git a/src/test/scala/chiselTests/Math.scala b/src/test/scala/chiselTests/Math.scala
index 57c2a8590bd..09396917c78 100644
--- a/src/test/scala/chiselTests/Math.scala
+++ b/src/test/scala/chiselTests/Math.scala
@@ -27,9 +27,9 @@ class Math extends ChiselPropSpec {
           val t = n match {
             case -2 => 2
             case -1 => 1
-            case 0  => 0
-            case 1  => 2
-            case 2  => 3
+            case 0 => 0
+            case 1 => 2
+            case 2 => 3
             case _ =>
               if (n > 0) {
                 if (offset < 0) width else width + 1
diff --git a/src/test/scala/chiselTests/experimental/AutoBlackBoxSpec.scala b/src/test/scala/chiselTests/experimental/AutoBlackBoxSpec.scala
index aa73ae5f748..e9f36641dff 100644
--- a/src/test/scala/chiselTests/experimental/AutoBlackBoxSpec.scala
+++ b/src/test/scala/chiselTests/experimental/AutoBlackBoxSpec.scala
@@ -35,7 +35,7 @@ class AutoBlackBoxSpec extends ChiselFlatSpec {
                 {
                   case "VDD" => false
                   case "VSS" => false
-                  case _     => true
+                  case _ => true
                 }
               )
             )
diff --git a/src/test/scala/chiselTests/experimental/TraceSpec.scala b/src/test/scala/chiselTests/experimental/TraceSpec.scala
index 79d986356d2..c621df6219c 100644
--- a/src/test/scala/chiselTests/experimental/TraceSpec.scala
+++ b/src/test/scala/chiselTests/experimental/TraceSpec.scala
@@ -106,58 +106,58 @@ class TraceSpec extends ChiselFlatSpec with Matchers {
           }.get}"""
       }
       s"""
-         |#include "V${topName}.h"
-         |#include "verilated_vpi.h"
-         |#include <memory>
-         |#include <verilated.h>
-         |
-         |int vpiGetInt(const char name[]) {
-         |  vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8 *)name, NULL);
-         |  if (!vh1)
-         |    vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
-         |  s_vpi_value v;
-         |  v.format = vpiIntVal;
-         |  vpi_get_value(vh1, &v);
-         |  return v.value.integer;
-         |}
-         |
-         |int main(int argc, char **argv) {
-         |  const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-         |  contextp->commandArgs(argc, argv);
-         |  const std::unique_ptr<V$topName> top{new V$topName{contextp.get(), "TOP"}};
-         |  top->reset = 0;
-         |  top->clock = 0;
-         |  int a_b = 1;
-         |  top->i_a_b = a_b;
-         |  bool started = false;
-         |  int ticks = 20;
-         |  while (ticks--) {
-         |    contextp->timeInc(1);
-         |    top->clock = !top->clock;
-         |    if (!top->clock) {
-         |      if (contextp->time() > 1 && contextp->time() < 10) {
-         |        top->reset = 1;
-         |      } else {
-         |        top->reset = 0;
-         |        started = true;
-         |      }
-         |      a_b = a_b ? 0 : 1;
-         |      top->i_a_b = a_b;
-         |    }
-         |    top->eval();
-         |    VerilatedVpi::callValueCbs();
-         |    if (started && !top->clock) {
-         |      const int i = top->i_a_b;
-         |      const int o = vpiGetInt("${vpiNames.head}");
-         |      if (i == o)
-         |        vl_fatal(__FILE__, __LINE__, "sim_main", "${vpiNames.head} should be the old value of Module1.i_a_b");
-         |      printf("${vpiNames.head}=%d Module1.m0.o_a_b=%d\\n", i, o);
-         |    }
-         |  }
-         |  top->final();
-         |  return 0;
-         |}
-         |""".stripMargin
+        |#include "V${topName}.h"
+        |#include "verilated_vpi.h"
+        |#include <memory>
+        |#include <verilated.h>
+        |
+        |int vpiGetInt(const char name[]) {
+        |  vpiHandle vh1 = vpi_handle_by_name((PLI_BYTE8 *)name, NULL);
+        |  if (!vh1)
+        |    vl_fatal(__FILE__, __LINE__, "sim_main", "No handle found");
+        |  s_vpi_value v;
+        |  v.format = vpiIntVal;
+        |  vpi_get_value(vh1, &v);
+        |  return v.value.integer;
+        |}
+        |
+        |int main(int argc, char **argv) {
+        |  const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+        |  contextp->commandArgs(argc, argv);
+        |  const std::unique_ptr<V$topName> top{new V$topName{contextp.get(), "TOP"}};
+        |  top->reset = 0;
+        |  top->clock = 0;
+        |  int a_b = 1;
+        |  top->i_a_b = a_b;
+        |  bool started = false;
+        |  int ticks = 20;
+        |  while (ticks--) {
+        |    contextp->timeInc(1);
+        |    top->clock = !top->clock;
+        |    if (!top->clock) {
+        |      if (contextp->time() > 1 && contextp->time() < 10) {
+        |        top->reset = 1;
+        |      } else {
+        |        top->reset = 0;
+        |        started = true;
+        |      }
+        |      a_b = a_b ? 0 : 1;
+        |      top->i_a_b = a_b;
+        |    }
+        |    top->eval();
+        |    VerilatedVpi::callValueCbs();
+        |    if (started && !top->clock) {
+        |      const int i = top->i_a_b;
+        |      const int o = vpiGetInt("${vpiNames.head}");
+        |      if (i == o)
+        |        vl_fatal(__FILE__, __LINE__, "sim_main", "${vpiNames.head} should be the old value of Module1.i_a_b");
+        |      printf("${vpiNames.head}=%d Module1.m0.o_a_b=%d\\n", i, o);
+        |    }
+        |  }
+        |  top->final();
+        |  return 0;
+        |}
+        |""".stripMargin
     }
 
     val config = os.temp(dir = testDir, contents = generateVerilatorConfigFile(Seq(dut.m0.o.a.b), annos))
diff --git a/src/test/scala/chiselTests/experimental/hierarchy/InstantiateSpec.scala b/src/test/scala/chiselTests/experimental/hierarchy/InstantiateSpec.scala
index 037a5549313..5dbf3e05ed2 100644
--- a/src/test/scala/chiselTests/experimental/hierarchy/InstantiateSpec.scala
+++ b/src/test/scala/chiselTests/experimental/hierarchy/InstantiateSpec.scala
@@ -88,7 +88,7 @@ object InstantiateSpec {
     @public val out = IO(Output(UInt(8.W)))
     val n = arg match {
       case s: String => s.toInt
-      case i: Int    => i
+      case i: Int => i
     }
     out := in + n.U
   }
@@ -96,8 +96,8 @@ object InstantiateSpec {
   // TODO we should provide a better version of this in Chisel
   def dataToString(data: Data): String = data match {
     case elt: Element => elt.toString
-    case vec: Vec[_]  => s"Vec_${vec.size}_${dataToString(vec(0))}"
-    case rec: Record  => rec.toString
+    case vec: Vec[_] => s"Vec_${vec.size}_${dataToString(vec(0))}"
+    case rec: Record => rec.toString
   }
 
   @instantiable
@@ -128,8 +128,8 @@ object InstantiateSpec {
   class ModuleParameterizedByProductTypes(param: MyEnumeration) extends Module {
     override def desiredName = s"${this.getClass.getSimpleName}_$param"
     val gen = param match {
-      case FooEnum     => UInt(8.W)
-      case BarEnum     => SInt(8.W)
+      case FooEnum => UInt(8.W)
+      case BarEnum => SInt(8.W)
       case FizzEnum(n) => Vec(n, UInt(8.W))
       case BuzzEnum(n) => Vec(n, SInt(8.W))
     }
diff --git a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala b/src/test/scala/chiselTests/simulator/SimulatorSpec.scala
index e0d5db4cdb6..b1d73afc3ce 100644
--- a/src/test/scala/chiselTests/simulator/SimulatorSpec.scala
+++ b/src/test/scala/chiselTests/simulator/SimulatorSpec.scala
@@ -103,11 +103,11 @@ class SimulatorSpec extends AnyFunSpec with Matchers {
         setInline(
           "Bar.sv",
           """|module Bar(
-             |  output a
-             |);
-             | assign a = 1'b1;
-             |endmodule
-             |""".stripMargin
+            |  output a
+            |);
+            | assign a = 1'b1;
+            |endmodule
+            |""".stripMargin
         )
       }
 
diff --git a/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala b/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
index 60eee48bffa..b555d58b4dd 100644
--- a/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
+++ b/src/test/scala/chiselTests/stage/WarningConfigurationSpec.scala
@@ -244,8 +244,8 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
       info("For suppressing warnings")
       val file = makeFile("basic_suppressing.conf")(
         """|id=1:s
-           |any:e
-           |""".stripMargin
+          |any:e
+          |""".stripMargin
       )
       val args = Array("--warn-conf-file", file.toString, "--throw-on-first-error")
       ChiselStage.emitCHIRRTL(new ModuleWithWarning, args)
@@ -253,7 +253,7 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
       info("Including source filters")
       val file2 = makeFile("with_source_filter.conf")(
         """|id=1&src=**/WarningConfigurationSpec.scala:s
-           |any:e""".stripMargin
+          |any:e""".stripMargin
       )
       val args2 = Array("--warn-conf-file", file2.toString, "--throw-on-first-error")
       ChiselStage.emitCHIRRTL(new ModuleWithWarning, args2)
@@ -262,10 +262,10 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
     it("should support line comments") {
       val file = makeFile("with_comments.conf")(
         """|# Here is a comment
-           |id=1:s  # And one at the end of a line
-           |  # And another one!
-           |any:e#what about this one?
-           |""".stripMargin
+          |id=1:s  # And one at the end of a line
+          |  # And another one!
+          |any:e#what about this one?
+          |""".stripMargin
       )
       val args = Array("--warn-conf-file", file.toString, "--throw-on-first-error")
       ChiselStage.emitCHIRRTL(new ModuleWithWarning, args)
@@ -277,7 +277,7 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
       val carat = "    ^"
       val badAction = makeFile("bad_action.conf")(
         s"""|$badln
-            |any:e""".stripMargin
+          |any:e""".stripMargin
       )
       checkInvalid(badAction, badln, carat, "Invalid action ':x'")
 
@@ -286,9 +286,9 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
       val carat2 = "     ^"
       val badAction2 = makeFile("bad_action2.conf")(
         s"""|# How about a comment?
-            |id=4&src=**.scala:s
-            |$badln2
-            |any:w""".stripMargin
+          |id=4&src=**.scala:s
+          |$badln2
+          |any:w""".stripMargin
       )
       checkInvalid(badAction2, badln2, carat2, "Cannot have duplicates of the same category")
     }
@@ -296,7 +296,7 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
     it("should support leading whitespace") {
       val file = makeFile("leading_whitespace.conf")(
         """|  id=1&src=**/WarningConfigurationSpec.scala:s
-           |    any:e""".stripMargin
+          |    any:e""".stripMargin
       )
       val args = Array("--warn-conf-file", file.toString, "--throw-on-first-error")
       ChiselStage.emitCHIRRTL(new ModuleWithWarning, args)
@@ -306,7 +306,7 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
       val carat = "       ^"
       val badAction = makeFile("bad_action_leading_whitespace.conf")(
         s"""|$badln
-            |any:e""".stripMargin
+          |any:e""".stripMargin
       )
       checkInvalid(badAction, badln, carat, "Cannot have duplicates of the same category")
     }
@@ -314,11 +314,11 @@ class WarningConfigurationSpec extends AnyFunSpec with Matchers with chiselTests
     it("should work when specified multiple times") {
       val suppressConf = makeFile("supress_all.conf")(
         """|any:s
-           |""".stripMargin
+          |""".stripMargin
       )
       val errorConf = makeFile("error_all.conf")(
         """|any:e
-           |""".stripMargin
+          |""".stripMargin
       )
       val suppress = Array("--warn-conf-file", suppressConf.toString)
       val errorFile = Array("--warn-conf-file", errorConf.toString)
diff --git a/src/test/scala/chiselTests/util/BitSetSpec.scala b/src/test/scala/chiselTests/util/BitSetSpec.scala
index 72f1688c3db..f8169042c49 100644
--- a/src/test/scala/chiselTests/util/BitSetSpec.scala
+++ b/src/test/scala/chiselTests/util/BitSetSpec.scala
@@ -12,8 +12,8 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
   it should "reject unequal width when constructing a BitSet" in {
     intercept[IllegalArgumentException] {
       BitSet.fromString("""b0010
-                          |b00010
-                          |""".stripMargin)
+        |b00010
+        |""".stripMargin)
     }
   }
 
@@ -41,9 +41,9 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "be able to handle complex subtract between BitSet" in {
     val aBitSet = BitSet.fromString("""b?01?0
-                                      |b11111
-                                      |b00000
-                                      |""".stripMargin)
+      |b11111
+      |b00000
+      |""".stripMargin)
     val bBitSet = BitSet.fromString(
       """b?1111
         |b?0000
@@ -56,7 +56,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "support checking equality" in {
     val set = BitSet.fromString("""b100
-                                  |b101""".stripMargin)
+      |b101""".stripMargin)
     val a = BitPat("b10?")
     val a2 = BitPat("b10?")
     val b = BitPat("b1??")
@@ -72,8 +72,8 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "support checking for cover" in {
     val set = BitSet.fromString("""b110
-                                  |b100
-                                  |b101""".stripMargin)
+      |b100
+      |b101""".stripMargin)
     val a = BitPat("b10?")
     val b = BitPat("b1??")
 
@@ -88,7 +88,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "support checking for overlap" in {
     val set = BitSet.fromString("""b01?0
-                                  |b0000""".stripMargin)
+      |b0000""".stripMargin)
     val a = BitPat("b00??")
     val b = BitPat("b01?0")
     val c = BitPat("b0000")
@@ -107,7 +107,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "be generated from BitPat union" in {
     val aBitSet = BitSet.fromString("""b001?0
-                                      |b000??""".stripMargin)
+      |b000??""".stripMargin)
     val aBitPat = BitPat("b000??")
     val bBitPat = BitPat("b001?0")
     val cBitPat = BitPat("b00000")
@@ -119,7 +119,7 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "be generated from BitPat subtraction" in {
     val aBitSet = BitSet.fromString("""b001?0
-                                      |b000??""".stripMargin)
+      |b000??""".stripMargin)
     val aBitPat = BitPat("b00???")
     val bBitPat = BitPat("b001?1")
 
@@ -128,8 +128,8 @@ class BitSetSpec extends AnyFlatSpec with Matchers {
 
   it should "union two BitSet together" in {
     val aBitSet = BitSet.fromString("""b001?0
-                                      |b001?1
-                                      |""".stripMargin)
+      |b001?1
+      |""".stripMargin)
     val bBitSet = BitSet.fromString(
       """b000??
         |b01???
diff --git a/src/test/scala/circtTests/stage/ChiselStageSpec.scala b/src/test/scala/circtTests/stage/ChiselStageSpec.scala
index f57d81dc210..8b4dc89e05d 100644
--- a/src/test/scala/circtTests/stage/ChiselStageSpec.scala
+++ b/src/test/scala/circtTests/stage/ChiselStageSpec.scala
@@ -1201,30 +1201,30 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.Utils {
         firtoolOpts = Array("-enable-layers=Verification,Verification.Assert,Verification.Assume,Verification.Cover")
       )
       btor2 should include("""|1 sort bitvec 1
-                              |2 input 1 reset
-                              |3 sort bitvec 32
-                              |4 state 3 count
-                              |5 constd 1 0
-                              |6 state 1 hbr
-                              |7 init 1 6 5
-                              |8 constd 3 43
-                              |9 constd 3 1
-                              |10 constd 3 42
-                              |11 constd 3 0
-                              |12 eq 1 4 10
-                              |13 add 3 4 9
-                              |14 ite 3 12 11 13
-                              |15 ult 1 4 8
-                              |16 constd 1 -1
-                              |17 or 1 2 6
-                              |18 xor 1 2 16
-                              |19 and 1 6 18
-                              |20 implies 1 19 15
-                              |21 not 1 20
-                              |22 bad 21
-                              |23 ite 3 2 11 14
-                              |24 next 3 4 23
-                              |25 next 1 6 17""".stripMargin)
+        |2 input 1 reset
+        |3 sort bitvec 32
+        |4 state 3 count
+        |5 constd 1 0
+        |6 state 1 hbr
+        |7 init 1 6 5
+        |8 constd 3 43
+        |9 constd 3 1
+        |10 constd 3 42
+        |11 constd 3 0
+        |12 eq 1 4 10
+        |13 add 3 4 9
+        |14 ite 3 12 11 13
+        |15 ult 1 4 8
+        |16 constd 1 -1
+        |17 or 1 2 6
+        |18 xor 1 2 16
+        |19 and 1 6 18
+        |20 implies 1 19 15
+        |21 not 1 20
+        |22 bad 21
+        |23 ite 3 2 11 14
+        |24 next 3 4 23
+        |25 next 1 6 17""".stripMargin)
     }
 
     it("""should error if give a "--target-directory" option""") {
diff --git a/src/test/scala/examples/VendingMachineGenerator.scala b/src/test/scala/examples/VendingMachineGenerator.scala
index b8a016babea..f150f6b8de6 100644
--- a/src/test/scala/examples/VendingMachineGenerator.scala
+++ b/src/test/scala/examples/VendingMachineGenerator.scala
@@ -84,7 +84,7 @@ class ParameterizedVendingMachineTester(mod: => ParameterizedVendingMachine, tes
 
   val inputVec: Vec[UInt] = VecInit(inputs.map {
     case Some(coin) => (1 << dut.io.indexMap(coin.name)).asUInt(coins.size.W)
-    case None       => 0.asUInt(coins.size.W)
+    case None => 0.asUInt(coins.size.W)
   })
   val expectedVec: Vec[Bool] = VecInit(expected.map(_.B))
 
diff --git a/src/test/scala/examples/VendingMachineUtils.scala b/src/test/scala/examples/VendingMachineUtils.scala
index 8d5aea571a5..6847768ab58 100644
--- a/src/test/scala/examples/VendingMachineUtils.scala
+++ b/src/test/scala/examples/VendingMachineUtils.scala
@@ -24,7 +24,7 @@ object VendingMachineUtils {
     for (input <- inputs) {
       val incValue = input match {
         case Some(coin) => coin.value
-        case None       => 0
+        case None => 0
       }
       if (value >= sodaCost) {
         outputs.append(true)
diff --git a/svsim/src/test/scala/BackendSpec.scala b/svsim/src/test/scala/BackendSpec.scala
index 1df97a039b0..16c215774c0 100644
--- a/svsim/src/test/scala/BackendSpec.scala
+++ b/svsim/src/test/scala/BackendSpec.scala
@@ -19,7 +19,7 @@ class VCSSpec extends BackendSpec {
   )
   backend match {
     case Some(backend) => test("vcs", backend)(compilationSettings)
-    case None          => ignore("Svsim backend 'vcs'") {}
+    case None => ignore("Svsim backend 'vcs'") {}
   }
 }