SVSim fails when pokeing and incrementing clock in loop

[HakamAtassi]

Running

class misbehavingSVSim extends AnyFreeSpec with Matchers {

  val parameters = Parameters()
  val addressMap = AddressMap()

  "fails SVSim" in {
      simulate(new myModule(parameters)) { dut =>
          dut.reset.poke(1.B)          
          dut.clock.step()
          dut.reset.poke(0.B)          
          dut.clock.step()

          dut.clock.step()
          dut.clock.step()

          for(i <- 0 until 100){
            dut.io.commit.valid.poke(1.B)
            dut.clock.step()
          }
      }
  }

}

causes

[info] -fails SVSim *** FAILED ***
[info] svsim.Simulation$UnexpectedEndOfMessages$:
[info] at svsim.Simulation$UnexpectedEndOfMessages$.(Simulation.scala:348)

while

class misbehavingSVSim extends AnyFreeSpec with Matchers {

  val parameters = Parameters()
  val addressMap = AddressMap()

  "fails SVSim" in {
      simulate(new myModule(parameters)) { dut =>

          dut.reset.poke(1.B)          
          dut.clock.step()
          dut.reset.poke(0.B)          
          dut.clock.step()

          dut.clock.step()
          dut.clock.step()

          for(i <- 0 until 100){
            dut.io.commit.valid.poke(1.B)
            //dut.clock.step()
          }
      }
  }
}

works, and so does

class misbehavingSVSim extends AnyFreeSpec with Matchers {

  val parameters = Parameters()
  val addressMap = AddressMap()

  "fails SVSim" in {
      simulate(new myModule(parameters)) { dut =>

          dut.reset.poke(1.B)          
          dut.clock.step()
          dut.reset.poke(0.B)          
          dut.clock.step()

          dut.clock.step()
          dut.clock.step()

          for(i <- 0 until 100){
            //dut.io.commit.valid.poke(1.B)
            dut.clock.step()
          }
      }
  }
}

Not exactly sure what is going on. The complete stack trace is

[info] - fails SVSim *** FAILED ***
[info]   svsim.Simulation$UnexpectedEndOfMessages$:
[info]   at svsim.Simulation$UnexpectedEndOfMessages$.<clinit>(Simulation.scala:348)
[info]   at svsim.Simulation$Controller.readNextAvailableMessage(Simulation.scala:140)
[info]   at svsim.Simulation$Controller.processNextMessage(Simulation.scala:214)
[info]   at svsim.Simulation$Port.tick(Simulation.scala:406)
[info]   at chisel3.simulator.PeekPokeAPI$testableClock.step(PeekPokeAPI.scala:41)
[info]   at ChaosCore.brokenSVSim.$anonfun$new$22(rename.scala:275)
[info]   at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:190)
[info]   at ChaosCore.brokenSVSim.$anonfun$new$21(rename.scala:272)
[info]   at ChaosCore.brokenSVSim.$anonfun$new$21$adapted(rename.scala:262)
[info]   at chisel3.simulator.EphemeralSimulator$.$anonfun$simulate$1(EphemeralSimulator.scala:25)

Just found that removing the loop does not help. I tried driving a different input that is not of type Flipped(ValidIO)) and SVSim has no problem. ie:

class misbehavingSVSim extends AnyFreeSpec with Matchers {

  val parameters = Parameters()
  val addressMap = AddressMap()

  "assigns full empty correctly" in {
      simulate(new myModule(parameters)) { dut =>

          dut.reset.poke(1.B)          
          dut.clock.step()
          dut.reset.poke(0.B)          
          dut.clock.step()

          dut.clock.step()
          dut.clock.step()

          dut.io.signal(0).poke(1.B)        // input of type: signal            = Input(Vec(param, Bool()))            (works)
          //dut.io.commit.valid.poke(1.B)   // input of type: signal            = Flipped(ValidIO(new bundle(params)))  (doesnt work)
          dut.clock.step()

      }
  }
}