scala.MatchError when using AttributeAnnotation for a module with several instances

[AlexMontgomerie]

What is the current behavior?

I've come across an issue with AttributeAnnotation where it fails when it is applied to a module with several instances. A scala.MatchError is thrown. This error only occurs if the module is instantiated more than once.

What is the expected behavior?

To generate an annotation for each module instance.

Steps to Reproduce

https://scastie.scala-lang.org/dxQpOW9CS2iAz69fo11wXQ

Your environment

• Chisel Versions: 3.5.1 and 3.5.0
• OS: Ubuntu 18.04.6 LTS

External Information

brought it up on gitter first: https://gitter.im/freechipsproject/chisel3?at=6202b14b3349fe1c71ffe75f

[AlexMontgomerie]

What I've found is that with a single module instance, I get the following Verilog generated:

(*  attr annotation  *)
module Bar(
  input   io_in,
  output  io_out
);
  assign io_out = ~io_in; // @[main.scala 14:13]
endmodule

module Foo(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  wire  m1_io_in; // @[main.scala 41:18]
  wire  m1_io_out; // @[main.scala 41:18]
  Bar m1 ( // @[main.scala 41:18]
    .io_in(m1_io_in),
    .io_out(m1_io_out)
  );
  assign io_out = m1_io_out; // @[main.scala 46:10]
  assign m1_io_in = io_in; // @[main.scala 44:12]
endmodule

When I thought it would give the attribute to the instance, like

module Bar(
  input   io_in,
  output  io_out
);
  assign io_out = ~io_in; // @[main.scala 14:13]
endmodule

module Foo(
  input   clock,
  input   reset,
  input   io_in,
  output  io_out
);
  wire  m1_io_in; // @[main.scala 41:18]
  wire  m1_io_out; // @[main.scala 41:18]
  (*  attr annotation  *) Bar m1 ( // @[main.scala 41:18]
    .io_in(m1_io_in),
    .io_out(m1_io_out)
  );
  assign io_out = m1_io_out; // @[main.scala 46:10]
  assign m1_io_in = io_in; // @[main.scala 44:12]
endmodule