semantics of multi clock memory

[wky17]

When I'm running multi-clock memory in treadle, there are troubles understanding the result, here are the samples:

circuit OuterMemModule : @[:@2.0]
  module OuterMemModule : @[:@13.2]
    input clockr : Clock @[:@14.4]
    input clockw : Clock @[:@14.4]
    input io_Address : UInt<10> @[:@16.4]
    input io_writeData : UInt<32> @[:@16.4]
    output io_readData : UInt<32> @[:@16.4]

    mem billy : @[MemPokeSpec.scala 22:18:@21.4]
      data-type => UInt<32>
      depth => 1024
      read-latency => 1
      write-latency => 1
      reader => _T_6
      writer => _T_4
      read-under-write => undefined

    io_readData <= billy._T_6.data
    billy._T_6.addr <= io_Address @[:@13.2]
    billy._T_6.en <= UInt<1>("h1") @[:@13.2]
    billy._T_6.clk <= clockr @[:@13.2]

    billy._T_4.data <= io_writeData
    billy._T_4.addr <= io_Address @[:@13.2]
    billy._T_4.en <= UInt<1>("h1") @[:@13.2]
    billy._T_4.mask <= UInt<1>("h1")
    billy._T_4.clk <= clockw @[:@13.2]

it's about reader and writer always connect to the same address, but I give them different clock signals.
Case1:
clockr: 0 0 1 0 0 1
clockw: 0 1 0 1 0 1
io_Address: 1 1 1 1 1 1
io_writeData: 95 20 10 38 53 21
output io_readData is 0 0 95 10 10 53
My thought is that, writer.data is connected to 95 at the first clk, after write-latency of 1, at 2nd clk, clockw meets a rising edge, billy has 95 at address 1. Why we get output 95 at 3rd clk is that, reader.data always connect to address 1, count from 2nd clk, after read-latency of 1, at 3rd clk, clockr meets a rising edge, reader get the 2nd clock's value at address 1.
it's similar that at 4th clk, billy should have 10 at address 1. But, there's no rising edge for clockr at 4th and 5th clk. So does that means reader.clk do not work? after the first rising edge, reader doesn't depend on it's clk signal.
then at 6th clk, reader.data get the value 53 which is the 5th input and should be written after 1 write-latency to address 1. Does that mean read-latency count from 5th clk, even the value is't written until 6th clk?

Case2:
Further more, to find out how latency works, I change read-latency to 2, and give the following inputs:
clockr: 0 1 0 0 1 0
clockw: 0 1 0 0 1 0
io_Address: 1 1 1 1 1 1
io_writeData: 95 20 10 38 53 21
output io_readData is 0 0 0 0 38 38
As the 4th input is 38 and read-latency is 2, I can't figure out why 5th output is 38.

I wonder the exact semantics on memory's multi-clock and latency.
Thank you.