{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":617151898,"defaultBranch":"main","name":"riscv-arch-test","ownerLogin":"cmuellner","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2023-03-21T19:56:00.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/92810?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1700036717.0","currentOid":""},"activityList":{"items":[{"before":"a9e8317c0e8f6ee9393363e854eba6f2e4b9fd1e","after":"b3cd00d9184977085f0684edfb27c428663b38e1","ref":"refs/heads/zvk","pushedAt":"2024-07-19T05:27:12.000Z","pushType":"push","commitsCount":199,"pusher":{"login":"UmerShahidengr","name":"Umer Shahid","path":"/UmerShahidengr","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/55623682?s=80&v=4"},"commit":{"message":"Merge branch 'dev' into zvk","shortMessageHtmlLink":"Merge branch 'dev' into zvk"}},{"before":"6288e0d48b31a8d0cd6f9e704e6387eb5037a548","after":"20e08addc44214adc44685ad7e23b38ecc52d8fe","ref":"refs/heads/zfa","pushedAt":"2024-05-03T05:49:57.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"UmerShahidengr","name":"Umer Shahid","path":"/UmerShahidengr","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/55623682?s=80&v=4"},"commit":{"message":"Update CHANGELOG.md\n\nAdded new entry in Changelog and resolved conflicts\n\nSigned-off-by: Umer Shahid ","shortMessageHtmlLink":"Update CHANGELOG.md"}},{"before":"6c62015c164afb2c17f06aec84e08436d5ae87ef","after":"6288e0d48b31a8d0cd6f9e704e6387eb5037a548","ref":"refs/heads/zfa","pushedAt":"2024-05-03T05:48:47.000Z","pushType":"push","commitsCount":21,"pusher":{"login":"UmerShahidengr","name":"Umer Shahid","path":"/UmerShahidengr","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/55623682?s=80&v=4"},"commit":{"message":"Merge branch 'main' into zfa\n\nSigned-off-by: Umer Shahid ","shortMessageHtmlLink":"Merge branch 'main' into zfa"}},{"before":"29be7889875204545383a32cc43fc2abe73dfbcf","after":"6c62015c164afb2c17f06aec84e08436d5ae87ef","ref":"refs/heads/zfa","pushedAt":"2024-04-09T18:31:16.000Z","pushType":"push","commitsCount":13,"pusher":{"login":"allenjbaum","name":"Allen Baum","path":"/allenjbaum","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/31423142?s=80&v=4"},"commit":{"message":"Merge branch 'main' into zfa\n\nSigned-off-by: Allen Baum <31423142+allenjbaum@users.noreply.github.com>","shortMessageHtmlLink":"Merge branch 'main' into zfa"}},{"before":"e7fb08f1c1bd9a65d5f3d27cb7fce7ef0dd21eb8","after":"29be7889875204545383a32cc43fc2abe73dfbcf","ref":"refs/heads/zfa","pushedAt":"2024-04-02T08:18:47.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i}, $FLEN={32,64}), and CFG=$INSN:\n riscv_ctg.py \\\n --cgf sample_cgfs/dataset.cgf \\\n --cgf sample_cgfs/zfa/$CGF \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is ratified and can be found here:\n https://github.com/riscv/riscv-isa-manual/blob/main/src/zfa.adoc\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"e899600de5e1845d60a5496fcbba883301765a72","after":"e7fb08f1c1bd9a65d5f3d27cb7fce7ef0dd21eb8","ref":"refs/heads/zfa","pushedAt":"2024-01-16T23:04:17.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is not frozen at the moment (which is why this\npatch is RFC) and can be found here:\nhttps://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"594d4837681033a1d57a59c098a89f8c662418a7","after":"b8bd7a6e8a06bfe9aeb79313a8d2f8369387dd60","ref":"refs/heads/zicond","pushedAt":"2023-12-01T07:04:59.000Z","pushType":"push","commitsCount":7,"pusher":{"login":"allenjbaum","name":"Allen Baum","path":"/allenjbaum","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/31423142?s=80&v=4"},"commit":{"message":"Merge branch 'main' into zicond\n\nSigned-off-by: Allen Baum <31423142+allenjbaum@users.noreply.github.com>","shortMessageHtmlLink":"Merge branch 'main' into zicond"}},{"before":"2c09dad0ea5e383d4d263a2563731c5722cde61b","after":"e7eea74c4fee1a7255a2a55188e937feae32825c","ref":"refs/heads/ssdtso","pushedAt":"2023-11-30T16:45:39.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)\n\nThe {m,s,h}envcfg CSRs have been defined a long time ago.\nThey contain bits that are defined by a the following ISA extensions:\n Zicbom_Zicboz_Zicsr_Ssdtso_Sstc\n\nThis patch introduces tests which read and write all of the defined\nbitsfields of these registers from M, S, and U mode.\n\nIn case of (expected) valid accesses we toggle the bits twice to test\nif we can set and clear the bits.\nIn case of (expected) illegal accesses we capture the exception state\nin the signature using the default ACT trap handler code.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)"}},{"before":"50643654cc40e30a9be6a8418e285c480427d773","after":"2c09dad0ea5e383d4d263a2563731c5722cde61b","ref":"refs/heads/ssdtso","pushedAt":"2023-11-19T10:35:29.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)\n\nThe {m,s,h}envcfg CSRs have been defined a long time ago.\nThey contain bits that are defined by a the following ISA extensions:\n Zicbom_Zicboz_Zicsr_Ssdtso_Sstc\n\nThis patch introduces tests which read and write all of the defined\nbitsfields of these registers from M, S, and U mode.\n\nIn case of (expected) valid accesses we toggle the bits twice to test\nif we can set and clear the bits.\nIn case of (expected) illegal accesses we capture the exception state\nin the signature using the default ACT trap handler code.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)"}},{"before":"1767703913f90b692112572418bab8d4acc8f049","after":"50643654cc40e30a9be6a8418e285c480427d773","ref":"refs/heads/ssdtso","pushedAt":"2023-11-17T14:01:49.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)\n\nThe {m,s,h}envcfg CSRs have been defined a long time ago.\nThey contain bits that are defined by a the following ISA extensions:\n Zicbom_Zicboz_Zicsr_Ssdtso_Sstc\n\nThis patch introduces a test which attempts to write all of the defined bits\nin menvcfg (similar to #381). After the tests, the original value of\nthe CSR will be restored to avoid side-effects with other tests.\n\nThis commit is incomplete, as it does not test the illegal exceptions\nwhich are triggered on access violations.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)"}},{"before":"8fd3f2b57b2e967edcc26ebc92e6cf02d73c00ec","after":"594d4837681033a1d57a59c098a89f8c662418a7","ref":"refs/heads/zicond","pushedAt":"2023-11-17T09:26:28.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zicond ISA extension\n\nThis patch intoduces a coverage model and the generated\ntest cases using riscv_ctg.\n\nThe tests have been generated using the following command:\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv32i \\\n -d tests/\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv64i \\\n -d tests64/\n\nThe resulting tests have been copied to the target directory:\n cp tests/*S riscv-test-suite/rv32i_m/Zicond/src/\n cp tests64/*S riscv-test-suite/rv64i_m/Zicond/src/\n\nThis PR depends on Zicond support in the riscv-ctg repo:\n https://github.com/riscv-software-src/riscv-ctg/pull/59\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zicond ISA extension"}},{"before":null,"after":"1767703913f90b692112572418bab8d4acc8f049","ref":"refs/heads/ssdtso","pushedAt":"2023-11-15T08:25:17.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)\n\nThe {m,s,h}envcfg CSRs have been defined a long time ago.\nThey contain bits that are defined by a the following ISA extensions:\n Zicbom_Zicboz_Zicsr_Ssdtso_Sstc\n\nThis patch introduces a test which attempts to write all of the defined bits\nin menvcfg (similar to #381). After the tests, the original value of\nthe CSR will be restored to avoid side-effects with other tests.\n\nFuture commits could introduce the following additional tests:\n* write tests for the bits in senvcfg\n* write tests for the bits in henvcfg\n* test that {m,s,h}envcfg CSRs are only accessible in the relevant modes\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)"}},{"before":"3ec98ff0c63caa40ba62a9dc1c2adddf10e95d92","after":"e899600de5e1845d60a5496fcbba883301765a72","ref":"refs/heads/zfa","pushedAt":"2023-05-23T10:01:46.735Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is not frozen at the moment (which is why this\npatch is RFC) and can be found here:\nhttps://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"d310dd73fb36f7e842e9512cb5dc3d934bb5e5ec","after":"3ec98ff0c63caa40ba62a9dc1c2adddf10e95d92","ref":"refs/heads/zfa","pushedAt":"2023-05-23T09:57:38.995Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is not frozen at the moment (which is why this\npatch is RFC) and can be found here:\nhttps://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"9f55fa15eb4836de2bb920ef7809a9e54d4c9e95","after":"d310dd73fb36f7e842e9512cb5dc3d934bb5e5ec","ref":"refs/heads/zfa","pushedAt":"2023-05-10T22:54:13.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is not frozen at the moment (which is why this\npatch is RFC) and can be found here:\nhttps://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"dec272428016ed2381dac17fe34ae0ef48059b69","after":"a9e8317c0e8f6ee9393363e854eba6f2e4b9fd1e","ref":"refs/heads/zvk","pushedAt":"2023-04-12T09:38:04.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for Zvksh\n\nThis patch introduces support for Zvksh\n- vsm3c.vi\n- vsm3me.vv\n\nSupport for RV32 and RV64 is added, but both versions are identical.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for Zvksh"}},{"before":"cc1ece1697fbc81309abdfd9d8a31abff0fc4bc6","after":"dec272428016ed2381dac17fe34ae0ef48059b69","ref":"refs/heads/zvk","pushedAt":"2023-04-09T19:01:15.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for Zvksh\n\nThis patch introduces support for Zvksh\n- vsm3c.vi\n- vsm3me.vv\n\nSupport for RV32 and RV64 is added, but both versions are identical.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for Zvksh"}},{"before":null,"after":"cc1ece1697fbc81309abdfd9d8a31abff0fc4bc6","ref":"refs/heads/zvk","pushedAt":"2023-04-09T18:51:45.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for Zvkb\n\nThis patch introduces support for Zvkb:\n- vandn.[vv,vx]\n- vbrev8.v\n- vclmul.[vv,vx]\n- vclmulh.[vv,vx]\n- vrev8.v\n\nSupport for RV32 and RV64 is added, but both versions are identical.\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for Zvkb"}},{"before":null,"after":"9f55fa15eb4836de2bb920ef7809a9e54d4c9e95","ref":"refs/heads/zfa","pushedAt":"2023-04-06T12:28:30.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zfa ISA extension\n\nThis patch introduces the RISC-V Zfa extension, which introduces\nadditional floating-point extensions:\n* fli (load-immediate) with pre-defined immediates\n* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)\n* fround/froundmx (round to integer)\n* fcvtmod.w.d (Modular Convert-to-Integer)\n* fmv* to access high bits of float register bigger than XLEN\n* Quiet comparison instructions (fleq/fltq)\n\nZfa defines its instructions in combination with the following\nextensions:\n* single-precision floating-point (F)\n* double-precision floating-point (D)\n* quad-precision floating-point (Q)\n* half-precision floating-point (Zfh)\n\nSince the RISC-V architecture test framework does not support\nthe RISC-V quad-precision floating-point ISA extension (Q) and\nthe RISC-V half-precision floating-point ISA extension (Zfh),\nthis patch does not include tests for instructions that depend\non these extensions.\n\nGiven missing infrastructure support, the fli.* instruction tests\nare hand written and not generated.\nAll other test files are generated using riscv-ctg.\n\nThe generated test files have been generated using the following\ncommand (with $BASEISA={rv32i,rv64i} and $FLEN={32,64}):\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n --base-isa $BASEISA \\\n --flen $FLEN \\\n -d tests_$BASEISA_$FLEN/\n\nExceptions are:\n* fcvtmod.w.d.cgf is for FLEN=32 only\n* fmvh.x.d and fmvp.d.x are for BASEISA=rv32i only\n\nThe resulting tests have been copied to the target directory.\n\nThe generation of the Zfa test cases depends on a PR in the riscv-ctg\nrepository:\n https://github.com/riscv-software-src/riscv-ctg/pull/60\n\nThe Zfa specification is not frozen at the moment (which is why this\npatch is RFC) and can be found here:\nhttps://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zfa ISA extension"}},{"before":"27df189e42499e2a7b5a1c9232bfe0ce01e30c32","after":"8fd3f2b57b2e967edcc26ebc92e6cf02d73c00ec","ref":"refs/heads/zicond","pushedAt":"2023-03-21T20:08:18.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zicond ISA extension\n\nThis patch intoduces a coverage model and the generated\ntest cases using riscv_ctg.\n\nThe tests have been generated using the following command:\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv32i \\\n -d tests/\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv64i \\\n -d tests64/\n\nThe resulting tests have been copied to the target directory:\n cp tests/*S riscv-test-suite/rv32i_m/Zicond/src/\n cp tests64/*S riscv-test-suite/rv64i_m/Zicond/src/\n\nThis PR depends on Zicond support in the riscv-ctg repo:\n https://github.com/riscv-software-src/riscv-ctg/pull/59\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zicond ISA extension"}},{"before":null,"after":"27df189e42499e2a7b5a1c9232bfe0ce01e30c32","ref":"refs/heads/zicond","pushedAt":"2023-03-21T19:59:06.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"cmuellner","name":"Christoph Müllner","path":"/cmuellner","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/92810?s=80&v=4"},"commit":{"message":"Add support for the Zicond ISA extension\n\nThis patch intoduces a coverage model and the generated\ntest cases using riscv_ctg.\n\nThe tests have been generated using the following command:\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv32i \\\n -d tests/\n riscv_ctg.py \\\n --cgf coverage/dataset.cgf \\\n --cgf coverage/zicond.cgf \\\n -bi rv64i \\\n -d tests64/\n\nThe resulting tests have been copied to the target directory:\n cp tests/*S riscv-test-suite/rv32i_m/Zicond/src/\n cp tests64/*S riscv-test-suite/rv64i_m/Zicond/src/\n\nThis PR depends on Zicond support in the riscv-ctg repo:\n https://github.com/riscv-software-src/riscv-ctg/pull/59\n\nSigned-off-by: Christoph Müllner ","shortMessageHtmlLink":"Add support for the Zicond ISA extension"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"startCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wNy0xOVQwNToyNzoxMi4wMDAwMDBazwAAAASDkxqM","endCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wMy0yMVQxOTo1OTowNi4wMDAwMDBazwAAAAMIU5W1"}},"title":"Activity · cmuellner/riscv-arch-test"}