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Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc)
The {m,s,h}envcfg CSRs have been defined a long time ago.
They contain bits that are defined by a the following ISA extensions:
Zicbom_Zicboz_Zicsr_Ssdtso_Sstc
This patch introduces a test which attempts to write all of the defined bits
in menvcfg (similar to riscv-non-isa#381). After the tests, the original value of
the CSR will be restored to avoid side-effects with other tests.
This commit is incomplete, as it does not test the illegal exceptions
which are triggered on access violations.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>- Loading branch information
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,96 @@ | ||
| // ----------- | ||
| // Copyright (c) 2023. RISC-V International. All rights reserved. | ||
| // SPDX-License-Identifier: BSD-3-Clause | ||
| // ----------- | ||
| // | ||
| // This assembly file tests the menvcfg CSR access. | ||
| // | ||
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| #include "model_test.h" | ||
| #include "arch_test.h" | ||
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| RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc") | ||
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| # Test code region | ||
| .section .text.init | ||
| .globl rvtest_entry_point | ||
| rvtest_entry_point: | ||
| RVMODEL_BOOT | ||
| RVTEST_CODE_BEGIN | ||
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| RVTEST_SIGBASE(a1,signature_a1_m) | ||
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| #ifdef TEST_CASE_1 | ||
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| RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",senvcfg) | ||
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| inst_M_toggle: | ||
| RVTEST_GOTO_MMODE | ||
| // Toggle all bits | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) | ||
| // Toggle all bits again (restore original value) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) | ||
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||
| inst_S_toggle: | ||
| RVTEST_GOTO_LOWER_MODE Smode | ||
| // Toggle all bits | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) | ||
| // Toggle all bits again (restore original value) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) | ||
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| inst_U_illegal: | ||
| RVTEST_GOTO_LOWER_MODE Umode | ||
| cssr t0, CSR_HENVCFG | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
| csrw CSR_HENVCFG, x0 | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
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| #endif | ||
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| RVTEST_CODE_END | ||
| RVMODEL_HALT | ||
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| RVTEST_DATA_BEGIN | ||
| # Input data section. | ||
| .data | ||
| .align 4 | ||
| RVTEST_DATA_END | ||
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| # Output data section. | ||
| RVMODEL_DATA_BEGIN | ||
| rvtest_sig_begin: | ||
| signature_a1_m: | ||
| .fill 32*(XLEN/32),4,0xdeadbeef | ||
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| sig_begin_canary: | ||
| CANARY; | ||
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| mtrap_sigptr: | ||
| .fill 4, 4, 0xdeadbeef | ||
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| #ifdef rvtest_gpr_save | ||
| gpr_save: | ||
| .fill 32*(XLEN/32), 4, 0xdeadbeef | ||
| #endif | ||
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| sig_end_canary: | ||
| CANARY; | ||
| rvtest_sig_end: | ||
| RVMODEL_DATA_END |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,88 @@ | ||
| // ----------- | ||
| // Copyright (c) 2023. RISC-V International. All rights reserved. | ||
| // SPDX-License-Identifier: BSD-3-Clause | ||
| // ----------- | ||
| // | ||
| // This assembly file tests the menvcfg CSR access. | ||
| // | ||
|
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||
| #include "model_test.h" | ||
| #include "arch_test.h" | ||
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| RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc") | ||
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| # Test code region | ||
| .section .text.init | ||
| .globl rvtest_entry_point | ||
| rvtest_entry_point: | ||
| RVMODEL_BOOT | ||
| RVTEST_CODE_BEGIN | ||
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| RVTEST_SIGBASE(a1,signature_a1_m) | ||
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| #ifdef TEST_CASE_1 | ||
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| RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",menvcfg) | ||
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| inst_M_toggle: | ||
| RVTEST_GOTO_MMODE | ||
| // Toggle all bits | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_DTSO, t1, t0, a1) | ||
| // Toggle all bits again (restore original value) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_FIOM, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBIE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBCFE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBZE, t1, t0, a1) | ||
| RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_DTSO, t1, t0, a1) | ||
|
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| inst_S_illegal: | ||
| RVTEST_GOTO_LOWER_MODE Smode | ||
| cssr t0, CSR_MENVCFG | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
| csrw CSR_MENVCFG, x0 | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
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| inst_U_illegal: | ||
| RVTEST_GOTO_LOWER_MODE Umode | ||
| cssr t0, CSR_MENVCFG | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
| csrw CSR_MENVCFG, x0 | ||
| // TODO: ensure the illegal instruction exception is captured in the signature | ||
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| #endif | ||
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| RVTEST_CODE_END | ||
| RVMODEL_HALT | ||
|
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| RVTEST_DATA_BEGIN | ||
| # Input data section. | ||
| .data | ||
| .align 4 | ||
| RVTEST_DATA_END | ||
|
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| # Output data section. | ||
| RVMODEL_DATA_BEGIN | ||
| rvtest_sig_begin: | ||
| signature_a1_m: | ||
| .fill 32*(XLEN/32),4,0xdeadbeef | ||
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| sig_begin_canary: | ||
| CANARY; | ||
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| mtrap_sigptr: | ||
| .fill 4, 4, 0xdeadbeef | ||
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| #ifdef rvtest_gpr_save | ||
| gpr_save: | ||
| .fill 32*(XLEN/32), 4, 0xdeadbeef | ||
| #endif | ||
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| sig_end_canary: | ||
| CANARY; | ||
| rvtest_sig_end: | ||
| RVMODEL_DATA_END |
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