From 50643654cc40e30a9be6a8418e285c480427d773 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Wed, 15 Nov 2023 09:10:24 +0100 Subject: [PATCH] Add menvcfg support (Zicbom_Zicboz_Zicsr_Ssdtso_Sstc) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The {m,s,h}envcfg CSRs have been defined a long time ago. They contain bits that are defined by a the following ISA extensions: Zicbom_Zicboz_Zicsr_Ssdtso_Sstc This patch introduces a test which attempts to write all of the defined bits in menvcfg (similar to #381). After the tests, the original value of the CSR will be restored to avoid side-effects with other tests. This commit is incomplete, as it does not test the illegal exceptions which are triggered on access violations. Signed-off-by: Christoph Müllner --- riscv-test-suite/env/encoding.h | 46 +++++++++ riscv-test-suite/env/test_macros.h | 27 ++++++ .../rv32i_m/privilege/src/henvcfg.S | 96 +++++++++++++++++++ .../rv32i_m/privilege/src/menvcfg.S | 88 +++++++++++++++++ .../rv32i_m/privilege/src/senvcfg.S | 96 +++++++++++++++++++ 5 files changed, 353 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/privilege/src/henvcfg.S create mode 100644 riscv-test-suite/rv32i_m/privilege/src/menvcfg.S create mode 100644 riscv-test-suite/rv32i_m/privilege/src/senvcfg.S diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h index 1ee1285be..6c889e0b0 100755 --- a/riscv-test-suite/env/encoding.h +++ b/riscv-test-suite/env/encoding.h @@ -131,6 +131,42 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_DTSO 0x00000100 +#define MENVCFG_ADUE 0x2000000000000000 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_ADUE 0x20000000 +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + +#define MSTATEEN0_HENVCFG 0x4000000000000000 +#define MSTATEEN0H_HENVCFG 0x40000000 +#define HENVCFG_FIOM 0x00000001 +#define HENVCFG_CBIE 0x00000030 +#define HENVCFG_CBCFE 0x00000040 +#define HENVCFG_CBZE 0x00000080 +#define HENVCFG_DTSO 0x00000100 +#define HENVCFG_ADUE 0x2000000000000000 +#define HENVCFG_PBMTE 0x4000000000000000 +#define HENVCFG_STCE 0x8000000000000000 + +#define HENVCFGH_ADUE 0x20000000 +#define HENVCFGH_PBMTE 0x40000000 +#define HENVCFGH_STCE 0x80000000 + +#define HSTATEEN0_SENVCFG 0x4000000000000000 +#define HSTATEEN0H_SENVCFG 0x40000000 +#define SENVCFG_FIOM 0x00000001 +#define SENVCFG_CBIE 0x00000030 +#define SENVCFG_CBCFE 0x00000040 +#define SENVCFG_CBZE 0x00000080 +#define SENVCFG_DTSO 0x00000100 + #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 @@ -813,6 +849,7 @@ #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 +#define CSR_SENVCFG 0x10a #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 @@ -820,6 +857,7 @@ #define CSR_SIP 0x144 #define CSR_SATP 0x180 #define CSR_SEDELEG 0x102 +#define CSR_HENVCFG 0x60a #define CSR_MSTATUS 0x300 #define CSR_MSTATUSH 0x310 #define CSR_MISA 0x301 @@ -828,6 +866,7 @@ #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 +#define CSR_MENVCFG 0x30a #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -924,6 +963,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_HENVCFGH 0x61a #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 @@ -956,6 +996,7 @@ #define CSR_HPMCOUNTER29H 0xc9d #define CSR_HPMCOUNTER30H 0xc9e #define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MENVCFGH 0x31a #define CSR_MCYCLEH 0xb80 #define CSR_MINSTRETH 0xb82 #define CSR_MHPMCOUNTER3H 0xb83 @@ -1309,12 +1350,14 @@ DECLARE_CSR(sstatus, CSR_SSTATUS) DECLARE_CSR(sie, CSR_SIE) DECLARE_CSR(stvec, CSR_STVEC) DECLARE_CSR(scounteren, CSR_SCOUNTEREN) +DECLARE_CSR(senvcfg, CSR_SENVCFG) DECLARE_CSR(sscratch, CSR_SSCRATCH) DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(stval, CSR_STVAL) DECLARE_CSR(sip, CSR_SIP) DECLARE_CSR(satp, CSR_SATP) +DECLARE_CSR(henvcfg, CSR_HENVCFG) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(mstatush, CSR_MSTATUSH) DECLARE_CSR(hstatus, CSR_HSTATUS) @@ -1324,6 +1367,7 @@ DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) +DECLARE_CSR(menvcfg, CSR_MENVCFG) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) @@ -1420,6 +1464,7 @@ DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(henvcfgh, CSR_HENVCFGH) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) @@ -1452,6 +1497,7 @@ DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(menvcfgh, CSR_MENVCFGH) DECLARE_CSR(mcycleh, CSR_MCYCLEH) DECLARE_CSR(minstreth, CSR_MINSTRETH) DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 20a31a710..539a40a03 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -275,6 +275,33 @@ SREG _R,offset(_BR) ;\ .set offset,offset+REGWIDTH +/* RVTEST_SIGUPD_CSR(SIG, TMP, CSR) */ +/* This macro reads the provided CSR and stores the value in the */ +/* signature referenced by SIG using the help of the temporary register */ +/* TMP. */ +#define RVTEST_SIGUPD_CSR(_SIG, _TMP, _CSR) ;\ + csrr _TMP, _CSR ;\ + RVTEST_SIGUPD(_SIG, _TMP) + +/* RVTEST_TOOGLE_BITS_IN_CSR(CSR, MASK, TMP1, TMP2) */ +/* This macro is used to toogle the set bits of the provided MASK in */ +/* the given CSR (read-modify-write) with the help of the temporary */ +/* registers TMP1 and TMP2. */ +#define RVTEST_TOGGLE_BITS_IN_CSR(_CSR, _MASK, _TMP1, _TMP2) ;\ + csrr _TMP1, _CSR ;\ + LI(_TMP2, _MASK) ;\ + xor _TMP1, _TMP1, _TMP2 ;\ + csrw _CSR, _TMP1 + +/* RVTEST_CSR_TOGGLE_TEST_CASE(CSR, MASK, TMP1, TMP2, SIG) */ +/* This macro is used to toggle the set bits of the provided MASK in */ +/* the given CSR (read-modify-write) and store the read-back value of */ +/* the CSR in the signature referenced by SIG using the help of the */ +/* temporary registers TMP1 and TMP2. */ +#define RVTEST_CSR_TOGGLE_TEST_CASE(_CSR, _MASK, _TMP1, _TMP2, _SIG) ;\ + TOGGLE_BITS_IN_CSR(_CSR, _MASK, _TMP1, _TMP2) ;\ + RVTEST_SIGUPD_CSR(_CSR, _TMP2, _SIG) + /* RVTEST_SIGUPD_F(basereg, sigreg,flagreg,newoff) */ /* This macro is used to store the signature values of (32 & 64) F and D */ /* teats which use TEST_(FPSR_OP, FPIO_OP, FPRR_OP, FPR4_OP) opcodes */ diff --git a/riscv-test-suite/rv32i_m/privilege/src/henvcfg.S b/riscv-test-suite/rv32i_m/privilege/src/henvcfg.S new file mode 100644 index 000000000..75b770d11 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/henvcfg.S @@ -0,0 +1,96 @@ +// ----------- +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the menvcfg CSR access. +// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE(a1,signature_a1_m) + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",senvcfg) + +inst_M_toggle: +RVTEST_GOTO_MMODE +// Toggle all bits +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) +// Toggle all bits again (restore original value) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) + +inst_S_toggle: +RVTEST_GOTO_LOWER_MODE Smode +// Toggle all bits +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) +// Toggle all bits again (restore original value) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_HENVCFG, HENVCFG_DTSO, t1, t0, a1) + +inst_U_illegal: +RVTEST_GOTO_LOWER_MODE Umode +cssr t0, CSR_HENVCFG +// TODO: ensure the illegal instruction exception is captured in the signature +csrw CSR_HENVCFG, x0 +// TODO: ensure the illegal instruction exception is captured in the signature + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# Input data section. + .data + .align 4 +RVTEST_DATA_END + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +signature_a1_m: + .fill 32*(XLEN/32),4,0xdeadbeef + +sig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S b/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S new file mode 100644 index 000000000..b30341762 --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/menvcfg.S @@ -0,0 +1,88 @@ +// ----------- +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the menvcfg CSR access. +// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE(a1,signature_a1_m) + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",menvcfg) + +inst_M_toggle: +RVTEST_GOTO_MMODE +// Toggle all bits +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_DTSO, t1, t0, a1) +// Toggle all bits again (restore original value) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_MENVCFG, MENVCFG_DTSO, t1, t0, a1) + +inst_S_illegal: +RVTEST_GOTO_LOWER_MODE Smode +cssr t0, CSR_MENVCFG +// TODO: ensure the illegal instruction exception is captured in the signature +csrw CSR_MENVCFG, x0 +// TODO: ensure the illegal instruction exception is captured in the signature + +inst_U_illegal: +RVTEST_GOTO_LOWER_MODE Umode +cssr t0, CSR_MENVCFG +// TODO: ensure the illegal instruction exception is captured in the signature +csrw CSR_MENVCFG, x0 +// TODO: ensure the illegal instruction exception is captured in the signature + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# Input data section. + .data + .align 4 +RVTEST_DATA_END + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +signature_a1_m: + .fill 32*(XLEN/32),4,0xdeadbeef + +sig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/privilege/src/senvcfg.S b/riscv-test-suite/rv32i_m/privilege/src/senvcfg.S new file mode 100644 index 000000000..52c62a08c --- /dev/null +++ b/riscv-test-suite/rv32i_m/privilege/src/senvcfg.S @@ -0,0 +1,96 @@ +// ----------- +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the menvcfg CSR access. +// + +#include "model_test.h" +#include "arch_test.h" + +RVTEST_ISA("RV32I_Zicbom_Zicboz_Zicsr_Ssdtso_Sstc") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +RVTEST_SIGBASE(a1,signature_a1_m) + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zicbom.*Zicboz.*Zicsr.*Ssdtso.*Sstc); def rvtest_mtrap_routine=True; def TEST_CASE_1=True",senvcfg) + +inst_M_toggle: +RVTEST_GOTO_MMODE +// Toggle all bits +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_DTSO, t1, t0, a1) +// Toggle all bits again (restore original value) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_DTSO, t1, t0, a1) + +inst_S_toggle: +RVTEST_GOTO_LOWER_MODE Smode +// Toggle all bits +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_DTSO, t1, t0, a1) +// Toggle all bits again (restore original value) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_FIOM, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBIE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBCFE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_CBZE, t1, t0, a1) +RVTEST_CSR_TOGGLE_TEST_CASE(CSR_SENVCFG, SENVCFG_DTSO, t1, t0, a1) + +inst_U_illegal: +RVTEST_GOTO_LOWER_MODE Umode +cssr t0, CSR_SENVCFG +// TODO: ensure the illegal instruction exception is captured in the signature +csrw CSR_SENVCFG, x0 +// TODO: ensure the illegal instruction exception is captured in the signature + +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +# Input data section. + .data + .align 4 +RVTEST_DATA_END + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +signature_a1_m: + .fill 32*(XLEN/32),4,0xdeadbeef + +sig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END