readyLatency in AvalonSTMonitor not working

[hjmedenblik]

Hi,
I am testing my AvalonST packet device. But my hdl assumes readyLatency=1. I see that the config of readyLatency is defined in the monitors/avalon.py but the implementation is missing.
I suggest to add a shiftregister functionality based on the readyLatency param and applied to self.bus.ready.value. That one can then be used in the def valid()

tnx
Henk

[cmarqu]

See also cocotb/cocotb#577, cocotb/cocotb#864, and cocotb/cocotb#1488.

[gardintrapp]

According to the Avalon specifications for the case where readyAllowance = readyLatency : When readyLatency is not 0, the source must deassert valid on non-ready cycles.
A simple fix may be to only look at valid in def valid() if readyLatency is set to any other value than 0. This fix worked for me.

[imphil]

@gardintrapp would you mind opening a pull request with your enhancement? Thanks!