Regression: Feature 'Enable mixed capitalization' breaks access to hierarchical bus signals

[HoT-1]

Before commit b4196ba it was was possible to use signals names containing a dot to define a bus, e.g.:

class MyAXI4LiteMaster(AXI4LiteMaster):
    _signals = {
        "AWVALID": "from_master.AWVALID",
        "AWREADY": "to_master.AWREADY"
    }

    def __init__(self, entity: SimHandleBase, name: str, clock: SimHandleBase, **kwargs):
        super().__init__(entity, name, clock, bus_separator="_", **kwargs)

After the commit the bus signals name cannot be resolved any more because the commit introduces a new argument case_insensitive which defaults to True and uses a different algorithm to resolve the signal name. But this algorithm does not support hierarchical signals. A workaround is to set case_insensitive=False.

[HoT-1]

A workaround is to set case_insensitive=False.

Matching of the signal names is case insensitive anyway in my setup (Quasta with VHDL top-level).

[elgorwi]

@HoT-1 @imphil Noticed the same issue using systemverilog interfaces. Setting 'case_insensitive' to False fixed the issue.

Any chance of changing the default value of the 'case_insensitive' parameter to False, to maintain compatibility with existing code?
Thanks

[alexforencich]

I never even considered that you could do that. That is a very neat hack, tbh. We should definitely adjust the case-insensitive lookup to handle this case appropriately; presumably we just need to split on the dots and recurse.

And if a simulator is internally case-insensitive, then the case-insensitive lookup could certainly be bypassed when running under that simulator.