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Case-sensitivity problem #45
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I've added to the Bus class following method:
then in line 72 I've replaced "if hasattr(entity, signame):" to "if self._caseInsensHasattr(entity, signame):" |
Presumably this was fixed with b4196ba |
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cocotb==1.6.2
cocotbext-axi==0.1.16
Questa Sim-64 Version 10.7f
Hello,
I published this problem in cocotbext-axi: alexforencich/cocotbext-axi#40
But I've tracked it to the Bus class.
My SystemVerilog Interface's instance contains all signals from AXI4-Stream spec (all uppercase as in spec), i.e.
TDATA,
TLAST,
TKEEP,
TUSER,
TVALID,
TREADY
Let's launch remote_pdb and see at Bus constructor in cocotb_bus/bus.py file. (I'll omit line's numbers because they shifted because of "breakpoints")
See in this loop "for attr_name, sig_name in _build_sig_attr_dict(optional_signals).items():" where "optional signals" must be founded.
Here are some Pdb logs:
(Pdb) p dir(entity)
['ACLK', 'ARESETn', 'TDATA', 'TID', 'TKEEP', 'TLAST', 'TREADY', 'TUSER', 'TVALID', '_HierarchyObject__get_sub_handle_by_name', 'class', 'delattr', 'dict', 'dir', 'doc', 'eq', 'format', 'ge', 'getattr', 'getattribute', 'gt', 'hash', 'init', 'init_subclass', 'iter', 'le', 'len', 'lt', 'module', 'ne', 'new', 'reduce', 'reduce_ex', 'repr', 'setattr', 'sizeof', 'str', 'subclasshook', 'weakref', '_child_path', '_compat_mapping', '_def_file', '_def_name', '_discover_all', '_discovered', '_fullname', '_handle', '_id', '_invalid_sub_handles', '_len', '_log', '_name', '_path', '_sub_handle_key', '_sub_handles', '_type', 'get_definition_file', 'get_definition_name']
(Pdb) p signame
'tvalid'
(Pdb) !hasattr(entity, signame)
False
(Pdb) !hasattr(entity,'tvalid')
False
(Pdb) !hasattr(entity,'TVALID')
True
Comparing to previous loop which finds "main" signals, this has hasattr() function which checks if "optional signal" is exist. And it's case-sensitive. So this is where "case-sensitivity" option loses its functionality.
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