From b3b0a8cc2c2cf94040c0571c2d03e049f914af18 Mon Sep 17 00:00:00 2001 From: Nils Larsen Date: Tue, 2 Jul 2024 17:02:48 +0200 Subject: [PATCH] drivers: gpio: imx rt11xx: fix wrong gpio pull disable mask A wrong bit mask (wrong: IOMUXC_SW_PAD_CTL_PAD_PUS_MASK = 0x8) was used. That bit mask is for PUE/PUS-type gpio registers, but this is the section for registers with alternative PULL (PDRV) type layout. Right bit mask: IOMUXC_SW_PAD_CTL_PAD_PULL_MASK (cherry picked from commit dcfc3e7872542038abc51da7d6a468ac76e71613) Original-Fixes: #75390 Original-Signed-off-by: Nils Larsen GitOrigin-RevId: dcfc3e7872542038abc51da7d6a468ac76e71613 Change-Id: Ic734626340fb5953c3f263d4225f50c487cbd58a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5682733 Tested-by: ChromeOS Prod (Robot) Commit-Queue: Yuval Peress Reviewed-by: Yuval Peress Tested-by: Yuval Peress --- drivers/gpio/gpio_mcux_igpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index 91ed22b4422..a6ce542175f 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -124,7 +124,7 @@ static int mcux_igpio_configure(const struct device *dev, } } else { /* Set pin to no pull */ - reg |= IOMUXC_SW_PAD_CTL_PAD_PUS_MASK; + reg |= IOMUXC_SW_PAD_CTL_PAD_PULL_MASK; } /* PDRV/SNVS/LPSR reg have different ODE bits */ if (config->pin_muxes[cfg_idx].pdrv_mux) {