From eef8bf750af48017fd89c35ce4081aa8909cc021 Mon Sep 17 00:00:00 2001 From: Andrzej Kaczmarek Date: Wed, 22 May 2024 11:18:54 +0200 Subject: [PATCH] drivers: clock_control: smartbond: Update CMAC sleep clock The CMAC uses lp_clk as a sleep clock so it has to be updated if frequency of lp_clk has changed. This happens either after XTAL32K settling or RCX calibration. (cherry picked from commit 5ead91d0991bc26b3b95a3bb3b924f76a82716b4) Original-Signed-off-by: Andrzej Kaczmarek GitOrigin-RevId: 5ead91d0991bc26b3b95a3bb3b924f76a82716b4 Change-Id: Id8e6a51ba24344b2a094fa06606f1d3f0e86ef97 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5570400 Tested-by: ChromeOS Prod (Robot) Commit-Queue: Fabio Baltieri Reviewed-by: Fabio Baltieri --- .../clock_control/clock_control_smartbond.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clock_control/clock_control_smartbond.c b/drivers/clock_control/clock_control_smartbond.c index 6da9c88b9a5..30f9820f2b0 100644 --- a/drivers/clock_control/clock_control_smartbond.c +++ b/drivers/clock_control/clock_control_smartbond.c @@ -13,6 +13,9 @@ #include #include #include +#if defined(CONFIG_BT_DA1469X) +#include +#endif LOG_MODULE_REGISTER(clock_control, CONFIG_CLOCK_CONTROL_LOG_LEVEL); @@ -53,6 +56,14 @@ static void calibration_work_cb(struct k_work *work) lpc_clock_state.rcx_freq = da1469x_clock_lp_rcx_freq_get(); LOG_DBG("RCX calibration done, RCX freq: %d", (int)lpc_clock_state.rcx_freq); + +#if defined(CONFIG_BT_DA1469X) + /* Update CMAC sleep clock with calculated frequency if RCX is set as lp_clk */ + if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) == + (1 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos)) { + cmac_request_lp_clock_freq_set(lpc_clock_state.rcx_freq); + } +#endif } if (lpc_clock_state.rc32k_started) { da1469x_clock_lp_rc32k_calibrate(); @@ -82,6 +93,14 @@ static void xtal32k_settle_work_cb(struct k_work *work) if (lpc_clock_state.xtal32k_started && !lpc_clock_state.xtal32k_ready) { LOG_DBG("XTAL32K settled."); lpc_clock_state.xtal32k_ready = true; + +#if defined(CONFIG_BT_DA1469X) + /* Update CMAC sleep clock if XTAL32K is set as lp_clk */ + if ((CRG_TOP->CLK_CTRL_REG & CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk) == + (2 << CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos)) { + cmac_request_lp_clock_freq_set(32768); + } +#endif } }