From f53315aeaa5112e99cb79b2a302cb80e1dd5fa1d Mon Sep 17 00:00:00 2001 From: Martin Kiepfer Date: Mon, 11 Sep 2023 21:09:25 +0200 Subject: [PATCH] boards: m5stack_core2: Increase i2c bitrate on i2c0 All periphals connected on i2c0 support 400kbit. The default speed has been increased to improve responsiveness. (cherry picked from commit 555baf719716f97bb8ce881df00a49a4c22546dc) Original-Signed-off-by: Martin Kiepfer GitOrigin-RevId: 555baf719716f97bb8ce881df00a49a4c22546dc Change-Id: Ie7502781b5c73335d1643100768e2792e0c80fb8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5407197 Reviewed-by: Fabio Baltieri Commit-Queue: Fabio Baltieri Tested-by: ChromeOS Prod (Robot) --- boards/xtensa/m5stack_core2/m5stack_core2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts index 2e70e5b6405..f90a19c3981 100644 --- a/boards/xtensa/m5stack_core2/m5stack_core2.dts +++ b/boards/xtensa/m5stack_core2/m5stack_core2.dts @@ -85,7 +85,7 @@ &i2c0 { status = "okay"; - clock-frequency = ; + clock-frequency = ; sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; pinctrl-0 = <&i2c0_default>;