From faabf0ec3b7706a14dab8bef9d94ec7330b745bd Mon Sep 17 00:00:00 2001 From: Alex Fabre Date: Tue, 25 Jun 2024 11:34:39 +0200 Subject: [PATCH] doc: st: fix `nucleo_h533re` documentation 1. Changing default ADC sens line for ch0 on PA0 - `adc1` was documented to be sensing ch14 on PB1. - This seems impossible because of a conflict between ch14 and UART2. - `adc1` node is not defined in the board's DTS. 2. Set SPI1 NSS pin to PA4 - hardware NSS signal was documented to output on PC9. - PC9 cannot be assigned as HW NSS for SPI1. - HW NSS on SPI1 is by default on PA4, and remapeable to PA15. 3. Update number of UART lines available - There are a total of 7 U(S)ARTs available on this board. (cherry picked from commit 12bb4057830b026a55c296ab948355fc1c41a9ba) Original-Signed-off-by: Alex Fabre GitOrigin-RevId: 12bb4057830b026a55c296ab948355fc1c41a9ba Change-Id: I8684703c41e8b6a0a51b857e9ddda6ce7440066b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5666208 Reviewed-by: Ting Shen Commit-Queue: Ting Shen Tested-by: ChromeOS Prod (Robot) Tested-by: Ting Shen --- boards/st/nucleo_h533re/doc/index.rst | 8 +++++--- boards/st/nucleo_h533re/nucleo_h533re.yaml | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/boards/st/nucleo_h533re/doc/index.rst b/boards/st/nucleo_h533re/doc/index.rst index b2ddb225e13..7a8e5ff560f 100644 --- a/boards/st/nucleo_h533re/doc/index.rst +++ b/boards/st/nucleo_h533re/doc/index.rst @@ -170,6 +170,8 @@ The Zephyr nucleo_h533re board configuration supports the following hardware fea +-----------+------------+-------------------------------------+ | WATCHDOG | on-chip | independent watchdog | +-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. @@ -205,9 +207,9 @@ For more details please refer to `STM32H5 Nucleo-64 board User Manual`_. Default Zephyr Peripheral Mapping: ---------------------------------- -- ADC1 channel 14 input: PB1 +- ADC1 channel 0 input: PA0 - USART1 TX/RX : PB14/PB15 (Arduino USART1) -- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9 +- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PA4 - UART2 TX/RX : PA2/PA3 (VCP) - USER_PB : PC13 @@ -221,7 +223,7 @@ as well as main PLL clock. By default System clock is driven by PLL clock at Serial Port ----------- -Nucleo H533RE board has up to 6 U(S)ARTs. The Zephyr console output is assigned +Nucleo H533RE board has up to 4 USARTs, 2 UARTs, and one LPUART. The Zephyr console output is assigned to USART2. Default settings are 115200 8N1. Programming and Debugging diff --git a/boards/st/nucleo_h533re/nucleo_h533re.yaml b/boards/st/nucleo_h533re/nucleo_h533re.yaml index 8262b95a843..5810046d688 100644 --- a/boards/st/nucleo_h533re/nucleo_h533re.yaml +++ b/boards/st/nucleo_h533re/nucleo_h533re.yaml @@ -14,4 +14,5 @@ supported: - watchdog - pwm - rtc + - adc vendor: st