Wanted: Cannon Lake, Ice Lake, Tiger Lake, Comet Lake, Rocket Lake, Alder Lake and Raptor Lake

[cyring]

I miss testings reports from all processors, post Coffee lake generation.

Signatures are installed into CoreFreq with the assumption they are using the same KBL, CFL registers.

Thanks for any contribution.

[cyring]

[svmlegacy]

See my outputs here of a Cannon Lake 8121U

If you want any specifics, please let me know and I can accomodate.

[cyring]

Great.
To compare with references:

• TDP of 15W according to:
  https://ark.intel.com/content/www/us/en/ark/products/136863/intel-core-i3-8121u-processor-4m-cache-up-to-3-20-ghz.html
• Vcore: no reference found

Intel provides only Power registers for whole Cores and Package.

Package C-states PC02 up to PC10 are not showing up. I will check source code.

[cyring]

See my outputs here of a Cannon Lake 8121U

If you want any specifics, please let me know and I can accomodate.

Hello,
I'm back to this i3-8121U issue: Memory Controller output is empty. Need the device DID of RAM controller or similar.
But after googling for CNL and this NUC , no registers datasheet, especially vol 2, seems publicly available.
Some @ Intel community forum pretend to use the Comet Lake specification.
We could try to plug the Comet Lake IMC decoder to your i3-8121U using DID returned by lspci -nn

[svmlegacy]

Hello,
I'm back to this i3-8121U issue: Memory Controller output is empty. Need the device DID of RAM controller or similar.
But after googling for CNL and this NUC , no registers datasheet, especially vol 2, seems publicly available.
Some @ Intel community forum pretend to use the Comet Lake specification.
We could try to plug the Comet Lake IMC decoder to your i3-8121U using DID returned by lspci -nn

Happy holidays! Getting back to it now.

lspci dumped here

[cyring]

Hello

For your information issue #309 has been created to collect testing report of your i3-8121U
Branch develop contains your PCI identifiers to trigger the memory controller decoder.

Thank you

[cyring]

Hello,
I'm back to this i3-8121U issue: Memory Controller output is empty. Need the device DID of RAM controller or similar...
lspci dumped here

develop branch contains your PCI IDs for IMC decoding.
Can you plz give a try ?
See #309

[svmlegacy]

Core i7-10510U (Comet Lake-U) outputs added to wiki.

[cyring]

Awesome.
First report from a Lenovo + CFL processor.
Looks like fully implemented despite it was paper programmed.
I still have to study each item of this report, bit after bit ...

Do you have any Tremont processor ?

[cyring]

Core i7-10510U (Comet Lake-U) outputs added to wiki.

Hello,

For the i7-10510U, can you please post the output of:

lspci -nn

This is to try to decode the Memory Controller information.

[svmlegacy]

00:00.0 Host bridge [0600]: Intel Corporation Comet Lake-U v1 4c Host Bridge/DRAM Controller [8086:9b61] (rev 0c)
00:02.0 VGA compatible controller [0300]: Intel Corporation CometLake-U GT2 [UHD Graphics] [8086:9b41] (rev 02)
00:04.0 Signal processing controller [1180]: Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem [8086:1903] (rev 0c)
00:08.0 System peripheral [0880]: Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th/8th Gen Core Processor Gaussian Mixture Model [8086:1911]
00:12.0 Signal processing controller [1180]: Intel Corporation Comet Lake Thermal Subsytem [8086:02f9]
00:14.0 USB controller [0c03]: Intel Corporation Comet Lake PCH-LP USB 3.1 xHCI Host Controller [8086:02ed]
00:14.2 RAM memory [0500]: Intel Corporation Comet Lake PCH-LP Shared SRAM [8086:02ef]
00:14.3 Network controller [0280]: Intel Corporation Comet Lake PCH-LP CNVi WiFi [8086:02f0]
00:16.0 Communication controller [0780]: Intel Corporation Comet Lake Management Engine Interface [8086:02e0]
00:1c.0 PCI bridge [0604]: Intel Corporation Comet Lake PCI Express Root Port #1 [8086:02b8] (rev f0)
00:1c.4 PCI bridge [0604]: Intel Corporation Comet Lake PCI Express Root Port #5 [8086:02bc] (rev f0)
00:1d.0 PCI bridge [0604]: Intel Corporation Comet Lake PCI Express Root Port #9 [8086:02b0] (rev f0)
00:1d.4 PCI bridge [0604]: Intel Corporation Comet Lake PCI Express Root Port #13 [8086:02b4] (rev f0)
00:1f.0 ISA bridge [0601]: Intel Corporation Comet Lake PCH-LP LPC Premium Controller/eSPI Controller [8086:0284]
00:1f.3 Audio device [0403]: Intel Corporation Comet Lake PCH-LP cAVS [8086:02c8]
00:1f.4 SMBus [0c05]: Intel Corporation Comet Lake PCH-LP SMBus Host Controller [8086:02a3]
00:1f.5 Serial bus controller [0c80]: Intel Corporation Comet Lake SPI (flash) Controller [8086:02a4]
00:1f.6 Ethernet controller [0200]: Intel Corporation Ethernet Connection (10) I219-V [8086:0d4f]
02:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. RTS522A PCI Express Card Reader [10ec:522a] (rev 01)
03:00.0 PCI bridge [0604]: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] [8086:15c0] (rev 01)
04:00.0 PCI bridge [0604]: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] [8086:15c0] (rev 01)
04:01.0 PCI bridge [0604]: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] [8086:15c0] (rev 01)
04:02.0 PCI bridge [0604]: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] [8086:15c0] (rev 01)
05:00.0 System peripheral [0880]: Intel Corporation JHL6240 Thunderbolt 3 NHI (Low Power) [Alpine Ridge LP 2016] [8086:15bf] (rev 01)
2b:00.0 USB controller [0c03]: Intel Corporation JHL6240 Thunderbolt 3 USB 3.1 Controller (Low Power) [Alpine Ridge LP 2016] [8086:15c1] (rev 01)
2d:00.0 3D controller [0302]: NVIDIA Corporation GP108GLM [Quadro P520] [10de:1d34] (rev a1)
2e:00.0 Non-Volatile memory controller [0108]: Toshiba Corporation XG6 NVMe SSD Controller [1179:011a]

[cyring]

Intel 400 Series Chipset

• Volume 1

[cyring]

@svmlegacy : Hello
develop branch contains entries to query the IMC of your Cometlake/U
Can you please give a try and show the output of IMC ?
Thank you

[cyring]

Thanks for your test but can you try again with latest develop ?
Because the device id and chipset name are missing in your output.

[svmlegacy]

Thanks for your test but can you try again with latest develop ?
Because the device id and chipset name are missing in your output.

Haha, the code formatting made the first line disappear. Here's the real result. All is well.

                         400 Series-Prem-U  [ 284]                         
Controller #0                                               Single Channel 
 Bus Rate  4000 MT/s      Bus Speed 4008 MT/s          DRAM Speed 2667 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    10   10   10   28    5  234    0    6   23   20    0    8  1T  5054
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     4    4    6    7         8    8    9   10        19   16    6    6
      sgWW dgWW drWW ddWW                                         CKE   ECC
  #0     4    4    7    7                                           4    0 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    1    131072         0           8192                    

[cyring]

Sorry, I just push another commit which may fix the columns count.
Can you plz pull, rebuild all and try again ?

May also fix previous Celeron case.

DIMM size is computed like this:

(8 x Bank x Rank x Row x Col) / (1024 x 1024) = MemSize (MB)

[svmlegacy]

Never a problem!
I'll be able to test the Celeron machine later this week. Currently on the test bed is a CPU which is also rather interesting... an AMD PRO A6-8570. Unfortunately I don't have any Tremont CPU though.

                         400 Series-Prem-U  [ 284]                         
Controller #0                                               Single Channel 
 Bus Rate  4000 MT/s      Bus Speed 4007 MT/s          DRAM Speed 2667 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS  RRD  RFC   WR RTPr WTPr  FAW  B2B  CWL CMD  REFI
  #0    10   10   10   28    5  234    0    6   23   20    0    8  1T  5054
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     4    4    6    7         8    8    9   10        19   16    6    6
      sgWW dgWW drWW ddWW                                         CKE   ECC
  #0     4    4    7    7                                           4    0 
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    1    131072       512           8192                    

[cyring]

Thanks to your tests, I have been able to deduce that unspecified 512 columns.
Thanks +1000

Sure I would like a test with A6-8570.
But save your files, first time it is tested.
I jumped indeed from K8 to Ryzen and except one Bulldozer case, I have no report from previous AMD architectures.

[cyring]

@svmlegacy
In datasheet of 10th generation:

• U processors have a size unit of 512
  

• Others have a size unit of 1024
  

Surprisingly my error has been to compute your Comet Lake-U with a 1024MB size and it gives the right size (when comparing with the Kernel accounting)

[cyring]

So here are the first impacts:

Changes happened with the introduction of the 10th generation, but Comet Lake has two cases U and Non-U

[cyring]

I have received various reports from those processor families which are presented into the Wiki/CPU Support

Thank you very much to all CoreFreq contributors.

They are still many bits to improve and fix to get a complete support of latest Intel architectures.
The develop version is available for your testings.

[cyring]

• Saving MC registers of Processor 11th Gen Intel(R) Core(TM) i7-1165G7 @ 2.80GHz for debug purposes

CoreFreq(1:5): Processor [ 06_8C] Architecture [Tiger Lake/U] SMT [8/8]
MADCH=0
MADC0=0 / MADC1=0
MADD0=0 / MADD1=0

[cyring]

Other impact found in 11th Generation Intel® Core™Processor

MCHBAR in bits [38-16], rather than [38-15] of previous Skylake(s)

[cyring]

What a mess in those specs: 11th Gen of UP3 Plateform

[cyring]

Adding i7-1165G7 of Tiger Lake/U
IMC unsolved yet
Edit: go to issue #269

[cyring]

To followers:

Per hour, renting bare-metal servers, gifted with EPYC and Xeon, is the only solution I found to speed up CoreFreq development with quality and reliability.

Case of hybrid processors is not solved yet as I have not found providers yet. In addition to that ADL Alder Lake datasheets, especially Memory Controller registers, is still a quest.

[svmlegacy]

Lakefield Hybrid CPU Intel Core i5-L16G7 dumped here.

4x Tremont + 1x Sunny Cove. Onboard 8 GB LPDDR4x (Foveros packaging, part of the CPU)
Samsung Galaxy Book S

lspci -nn at very bottom. Will skim through the results later on this week.

[cyring]

Awesome. Thank U

This answers question about APIC IDs among Tremont and Sunny Cove are distincts.

Presuming CPU #4 belongs to Sunny Cove; starting the driver with an affinity to that CPU could show other decoding among these:

Processor                             [Intel(R) Core(TM) i5-L16G7 CPU @ 1.40GHz]
|- Architecture                                              [Tremont/Lakefield]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x00000027]
|- Signature                                                           [  06_8A]
|- Stepping                                                            [      1]
|- Online CPU                                                          [  5/  5]
|- Base Clock                                                          [ 98.742]
|- Frequency            (MHz)                      Ratio                        
                 Min    789.94                    <   8 >                       
                 Max   1382.39                    <  14 >                       

To bind the Service Processor Thread to CPU 4:

insmod corefreqk.ko ServiceProcessor=4

[svmlegacy]

-s does not appear much different to my eye... same CPUID and signatures here.
Gist Here.

[cyring]

The only differences I'm finding are the HWP ratios and the L1 HW, L2 HW Prefetchers state.
Those are dynamic thus it depends on usage and/or BIOS setup.
So on Hybrid, all features read on CPUID, whatever the Core is, are reported the same.

[cyring]

EDIT: found a bug in L1/L2 HW Prefetchers. I'll provide a fix to reset their state.

[cyring]

Very interesting ADL info found at https://openbenchmarking.org/system/2111089-TJ-BUILDLINU44/intel-i5-12600k-pl1pl2@125W-6x-pcore-4x-ecore/cpuinfo

• CPUID reports same model and brand for all 16 CPUs
• Whereas APIC ID are listeded in this set:
  [0, 1, 8, 9, 16, 17, 24, 25, 32, 33, 40, 41, 56, 58, 60, 62]

Looking at those numbers, I now feel confident that CoreFreq will succeed to map the Alder Lake Cores topology.

[cyring]

Apparently two sequences:

P-Cores: APIC_k = ( (k SHR 1) SHL 3 ) + (k AND 1)
E-Cores: APIC_k = ( (k SHR 1) SHL 2 ) + 32 + ( (k AND 1) SHL 1 )

[cyring]

Intel 10th & 11th generations : pull the develop branch which attempts to better compute the DIMM rows.

As a remainder, DIMM size is equal to:

Size(MB) = 8 x banks x ranks x rows x cols / (1024 x 1024)

Please post your IMC outputs, whatever the results is, I'll check myself for coherency.

[cyring]

I can only test 12th gen on my Z690 motherboard.

user@localhost:~/bin/CoreFreq> ./corefreq-cli -M
                             Intel B660  [7AB8]                            
Controller #0                                                Dual Channel  
 Bus Rate  3600 MHz       Bus Speed 3609 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    18   22   22   42    4    9   40   24   12   46   18   7   2T     1
  #1     0    0    0    0    0    0    0    0    0    0    0   0   1T     1
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     7    4   12   12                    14055  630  648   11    4    0
  #1     0    0    0    0                        0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                                                                  
                                                                           
Controller #1                                                Dual Channel  
 Bus Rate  3600 MHz       Bus Speed 3609 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    18   22   22   42    4    9   40   24   12   46   18   7   2T     1
  #1     0    0    0    0    0    0    0    0    0    0    0   0   1T     1
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     7    4   12   12                    14055  630  648   11    4    0
  #1     0    0    0    0                        0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                                                               

Hello,

Could you please give a try to latest develop branch and post the output of the Memory Controller ?

[BugReporterZ]

i7-12700K on MSI PRO Z690-A DDR4 WIFI here, with 4x16GB DDR4-3600 modules:

user@localhost:~/bin/CoreFreq> ./corefreq-cli -M
                             Intel Z690  [7A84]                            
Controller #0                                                Dual Channel  
 Bus Rate  3600 MHz       Bus Speed 3609 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    18   22   22   42    4    9   40   24   12   46   18   7   2T     1
  #1     0    0    0    0    0    0    0    0    0    0    0   0   1T     1
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     7    4   12   12                    14055  630  648   11    4    0
  #1     0    0    0    0                        0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                                                                  
                                                                           
Controller #1                                                Dual Channel  
 Bus Rate  3600 MHz       Bus Speed 3609 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    18   22   22   42    4    9   40   24   12   46   18   7   2T     1
  #1     0    0    0    0    0    0    0    0    0    0    0   0   1T     1
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     0    0    0    0         0    0    0    0         0    0    0    0
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     7    4   12   12                    14055  630  648   11    4    0
  #1     0    0    0    0                        0    0    0    0    0    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                  

I should be on the develop branch:

[cyring]

Thank you for the output.

Now you can export tRCD_R and tRCD_W. It works with my Matisse 3950X but I would like your JSON output part of timings (channel zero which has data will be enough).
Indeed, Alder Lake, Raptor Lake datasheets don't say much if tRCD_W is DDR5 only or is provided with DDR4 also ?

[BugReporterZ]

Here's the data after pulling the latest changes.
data.zip

[cyring]

Now we know tRCD_W is not available with DDR4 on Alder Lake.

Thank you.

[cyring]

There's an IMC change pending in the development branch for Intel starting 11th generation.

Can your guys with CML, RKL, TGL, ADL, RPL of any segment (desktop or mobile) post the output of

corefreq-cli -M

[BugReporterZ]

Unfortunately at the moment I don't have a Linux installation on my Intel 12th system, so I cannot test it.

[cyring]

Unfortunately at the moment I don't have a Linux installation on my Intel 12th system, so I cannot test it.

Ok, just let me know if I can provide an updated ISO image ?

[BugReporterZ]

It was just a matter of installing a Linux distribution on a secondary SSD, which I should have done anyway at some point. However, at the moment my daily activities are on Windows.

This is the output from a fresh build from the develop branch:

> ./corefreq-cli -M
                             Intel Z690  [7A84]                            
Controller #0                                                Dual Channel  
 Bus Rate  4600 MHz       Bus Speed 4612 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL RCDr RCDw   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL  CKE  CMD
  #0    18   22   22   22   42    4    9   40   24   12   46   18    7   2T
  #1     5    8    8    8   28    4    4   16   14    6   24    6    4   1T
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     4    4    4    4         4    4    4    4         4    4    4    4
      sgWW dgWW drWW ddWW                REFI  RFC  XS   XP CPDED GEAR  ECC
  #0     7    4   12   12               14055  630  648   11    4    1    0
  #1     4    4    4    4                4100  180    0    4    1    1    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                                                                  
                                                                           
Controller #1                                                Dual Channel  
 Bus Rate  4600 MHz       Bus Speed 4612 MHz           DDR4 Speed 3609 MHz 
                                                                           
 Cha    CL RCDr RCDw   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL  CKE  CMD
  #0    18   22   22   22   42    4    9   40   24   12   46   18    7   2T
  #1     5    8    8    8   28    4    4   16   14    6   24    6    4   1T
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     7    4   12   12        14   15   15   16        36   29    7    7
  #1     4    4    4    4         4    4    4    4         4    4    4    4
      sgWW dgWW drWW ddWW                REFI  RFC  XS   XP CPDED GEAR  ECC
  #0     7    4   12   12               14055  630  648   11    4    1    0
  #1     4    4    4    4                4100  180    0    4    1    1    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384  CMK32GX4M2D3600C18
       #1    16    2     65536      1024          16384  CMK32GX4M2D3600C18
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0                                                                  
       #1                                

[cyring]

I want to program an universal IMC decoder for ADL Desktop and Mobile, DDR4 and DDR5

i7-12700H with DDR5 shows more consistency among timings.
In your case, I don't get why timings of second channel look garbage: tCL of 5 for instance!