From 9b65e1fdb45503a4740d8c931f016cbbaf418b91 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 6 Mar 2024 14:11:08 +0800 Subject: [PATCH 01/40] riscv: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- arch/riscv/Kconfig.socs | 5 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 7 + .../riscv/boot/dts/sophgo/mango-2sockets.dtsi | 700 ++++++++++ .../boot/dts/sophgo/mango-clock-socket0.dtsi | 124 ++ .../boot/dts/sophgo/mango-clock-socket1.dtsi | 124 ++ .../boot/dts/sophgo/mango-cpus-socket0.dtsi | 1148 ++++++++++++++++ .../boot/dts/sophgo/mango-cpus-socket1.dtsi | 1149 +++++++++++++++++ .../boot/dts/sophgo/mango-milkv-pioneer.dts | 163 +++ .../riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi | 81 ++ .../dts/sophgo/mango-pcie-3rc-capricorn.dtsi | 116 ++ .../boot/dts/sophgo/mango-pcie-3rc-v2.dtsi | 115 ++ .../riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi | 112 ++ .../boot/dts/sophgo/mango-pcie-4rc-v2.dtsi | 155 +++ .../riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi | 151 +++ arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi | 434 +++++++ .../dts/sophgo/mango-sophgo-capricorn.dts | 57 + .../boot/dts/sophgo/mango-sophgo-pisces.dts | 58 + .../boot/dts/sophgo/mango-sophgo-x4evb.dts | 137 ++ .../boot/dts/sophgo/mango-sophgo-x8evb.dts | 165 +++ .../boot/dts/sophgo/mango-top-intc2.dtsi | 62 + .../boot/dts/sophgo/mango-yixin-s2110.dts | 63 + arch/riscv/boot/dts/sophgo/mango.dtsi | 941 ++++++++++++++ 23 files changed, 6068 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-top-intc2.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango.dtsi diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 30fd6a5128285..e08e91c49abec 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,11 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. +config ARCH_SOPHGO + bool "Sophgo SoCs" + help + This enables support for Sophgo SoC platform hardware. + config ARCH_STARFIVE def_bool SOC_STARFIVE diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f60a280abb157..72030fd727af6 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y += canaan subdir-y += microchip subdir-y += renesas subdir-y += sifive +subdir-y += sophgo subdir-y += starfive subdir-y += thead diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile new file mode 100644 index 0000000000000..6e7c7763b0a9b --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-x4evb.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-x8evb.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-pisces.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-capricorn.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-milkv-pioneer.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-yixin-s2110.dtb diff --git a/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi new file mode 100644 index 0000000000000..97de3fdcad388 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi @@ -0,0 +1,700 @@ +#define NR_CPUS 128 + +#include "mango.dtsi" +#if NR_CPUS > 64 +#include "mango-cpus-socket1.dtsi" +#endif +#include "mango-clock-socket1.dtsi" + +/ { + /delete-node/ distance-map; + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, //chip0 + <0 1 15>, + <0 2 25>, + <0 3 30>, + <0 4 110>, + <0 5 115>, + <0 6 125>, + <0 7 130>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <1 4 115>, + <1 5 110>, + <1 6 130>, + <1 7 125>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <2 4 125>, + <2 5 130>, + <2 6 110>, + <2 7 115>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>, + <3 4 130>, + <3 5 125>, + <3 6 115>, + <3 7 110>, + <4 0 110>, //chip1 + <4 1 115>, + <4 2 125>, + <4 3 130>, + <4 4 10>, + <4 5 15>, + <4 6 25>, + <4 7 30>, + <5 0 115>, + <5 1 110>, + <5 2 130>, + <5 3 125>, + <5 4 15>, + <5 5 10>, + <5 6 30>, + <5 7 25>, + <6 0 125>, + <6 1 130>, + <6 2 110>, + <6 3 115>, + <6 4 25>, + <6 5 30>, + <6 6 10>, + <6 7 15>, + <7 0 130>, + <7 1 125>, + <7 2 115>, + <7 3 110>, + <7 4 30>, + <7 5 25>, + <7 6 15>, + <7 7 10>; + }; + + soc { +#if NR_CPUS > 64 + /delete-node/ clint-mswi@7094000000; + clint_mswi: clint-mswi@7094000000 { + compatible = "thead,c900-clint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = < + &cpu0_intc 3 + &cpu1_intc 3 + &cpu2_intc 3 + &cpu3_intc 3 + &cpu4_intc 3 + &cpu5_intc 3 + &cpu6_intc 3 + &cpu7_intc 3 + &cpu8_intc 3 + &cpu9_intc 3 + &cpu10_intc 3 + &cpu11_intc 3 + &cpu12_intc 3 + &cpu13_intc 3 + &cpu14_intc 3 + &cpu15_intc 3 + &cpu16_intc 3 + &cpu17_intc 3 + &cpu18_intc 3 + &cpu19_intc 3 + &cpu20_intc 3 + &cpu21_intc 3 + &cpu22_intc 3 + &cpu23_intc 3 + &cpu24_intc 3 + &cpu25_intc 3 + &cpu26_intc 3 + &cpu27_intc 3 + &cpu28_intc 3 + &cpu29_intc 3 + &cpu30_intc 3 + &cpu31_intc 3 + &cpu32_intc 3 + &cpu33_intc 3 + &cpu34_intc 3 + &cpu35_intc 3 + &cpu36_intc 3 + &cpu37_intc 3 + &cpu38_intc 3 + &cpu39_intc 3 + &cpu40_intc 3 + &cpu41_intc 3 + &cpu42_intc 3 + &cpu43_intc 3 + &cpu44_intc 3 + &cpu45_intc 3 + &cpu46_intc 3 + &cpu47_intc 3 + &cpu48_intc 3 + &cpu49_intc 3 + &cpu50_intc 3 + &cpu51_intc 3 + &cpu52_intc 3 + &cpu53_intc 3 + &cpu54_intc 3 + &cpu55_intc 3 + &cpu56_intc 3 + &cpu57_intc 3 + &cpu58_intc 3 + &cpu59_intc 3 + &cpu60_intc 3 + &cpu61_intc 3 + &cpu62_intc 3 + &cpu63_intc 3 + + // chip 1 + &cpu64_intc 3 + &cpu65_intc 3 + &cpu66_intc 3 + &cpu67_intc 3 + &cpu68_intc 3 + &cpu69_intc 3 + &cpu70_intc 3 + &cpu71_intc 3 + &cpu72_intc 3 + &cpu73_intc 3 + &cpu74_intc 3 + &cpu75_intc 3 + &cpu76_intc 3 + &cpu77_intc 3 + &cpu78_intc 3 + &cpu79_intc 3 + &cpu80_intc 3 + &cpu81_intc 3 + &cpu82_intc 3 + &cpu83_intc 3 + &cpu84_intc 3 + &cpu85_intc 3 + &cpu86_intc 3 + &cpu87_intc 3 + &cpu88_intc 3 + &cpu89_intc 3 + &cpu90_intc 3 + &cpu91_intc 3 + &cpu92_intc 3 + &cpu93_intc 3 + &cpu94_intc 3 + &cpu95_intc 3 + &cpu96_intc 3 + &cpu97_intc 3 + &cpu98_intc 3 + &cpu99_intc 3 + &cpu100_intc 3 + &cpu101_intc 3 + &cpu102_intc 3 + &cpu103_intc 3 + &cpu104_intc 3 + &cpu105_intc 3 + &cpu106_intc 3 + &cpu107_intc 3 + &cpu108_intc 3 + &cpu109_intc 3 + &cpu110_intc 3 + &cpu111_intc 3 + &cpu112_intc 3 + &cpu113_intc 3 + &cpu114_intc 3 + &cpu115_intc 3 + &cpu116_intc 3 + &cpu117_intc 3 + &cpu118_intc 3 + &cpu119_intc 3 + &cpu120_intc 3 + &cpu121_intc 3 + &cpu122_intc 3 + &cpu123_intc 3 + &cpu124_intc 3 + &cpu125_intc 3 + &cpu126_intc 3 + &cpu127_intc 3 + >; + }; + + clint_mtimer16: clint-mtimer@70ac100000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac100000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu64_intc 7 + &cpu65_intc 7 + &cpu66_intc 7 + &cpu67_intc 7 + >; + }; + + clint_mtimer17: clint-mtimer@70ac110000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac110000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu68_intc 7 + &cpu69_intc 7 + &cpu70_intc 7 + &cpu71_intc 7 + >; + }; + + clint_mtimer18: clint-mtimer@70ac120000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac120000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu72_intc 7 + &cpu73_intc 7 + &cpu74_intc 7 + &cpu75_intc 7 + >; + }; + + clint_mtimer19: clint-mtimer@70ac130000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac130000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu76_intc 7 + &cpu77_intc 7 + &cpu78_intc 7 + &cpu79_intc 7 + >; + }; + + clint_mtimer20: clint-mtimer@70ac140000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac140000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu80_intc 7 + &cpu81_intc 7 + &cpu82_intc 7 + &cpu83_intc 7 + >; + }; + + clint_mtimer21: clint-mtimer@70ac150000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac150000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu84_intc 7 + &cpu85_intc 7 + &cpu86_intc 7 + &cpu87_intc 7 + >; + }; + + clint_mtimer22: clint-mtimer@70ac160000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac160000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu88_intc 7 + &cpu89_intc 7 + &cpu90_intc 7 + &cpu91_intc 7 + >; + }; + + clint_mtimer23: clint-mtimer@70ac170000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac170000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu92_intc 7 + &cpu93_intc 7 + &cpu94_intc 7 + &cpu95_intc 7 + >; + }; + + clint_mtimer24: clint-mtimer@70ac180000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac180000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu96_intc 7 + &cpu97_intc 7 + &cpu98_intc 7 + &cpu99_intc 7 + >; + }; + + clint_mtimer25: clint-mtimer@70ac190000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac190000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu100_intc 7 + &cpu101_intc 7 + &cpu102_intc 7 + &cpu103_intc 7 + >; + }; + + clint_mtimer26: clint-mtimer@70ac1a0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1a0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu104_intc 7 + &cpu105_intc 7 + &cpu106_intc 7 + &cpu107_intc 7 + >; + }; + + clint_mtimer27: clint-mtimer@70ac1b0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1b0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu108_intc 7 + &cpu109_intc 7 + &cpu110_intc 7 + &cpu111_intc 7 + >; + }; + + clint_mtimer28: clint-mtimer@70ac1c0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1c0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu112_intc 7 + &cpu113_intc 7 + &cpu114_intc 7 + &cpu115_intc 7 + >; + }; + + clint_mtimer29: clint-mtimer@70ac1d0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1d0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu116_intc 7 + &cpu117_intc 7 + &cpu118_intc 7 + &cpu119_intc 7 + >; + }; + + clint_mtimer30: clint-mtimer@70ac1e0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1e0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu120_intc 7 + &cpu121_intc 7 + &cpu122_intc 7 + &cpu123_intc 7 + >; + }; + + clint_mtimer31: clint-mtimer@70ac1f0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac1f0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu124_intc 7 + &cpu125_intc 7 + &cpu126_intc 7 + &cpu127_intc 7 + >; + }; +#endif + + /delete-node/ interrupt-controller@7090000000; + intc: interrupt-controller@7090000000 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "thead,c900-plic"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9 + &cpu5_intc 11 &cpu5_intc 9 + &cpu6_intc 11 &cpu6_intc 9 + &cpu7_intc 11 &cpu7_intc 9 + &cpu8_intc 11 &cpu8_intc 9 + &cpu9_intc 11 &cpu9_intc 9 + &cpu10_intc 11 &cpu10_intc 9 + &cpu11_intc 11 &cpu11_intc 9 + &cpu12_intc 11 &cpu12_intc 9 + &cpu13_intc 11 &cpu13_intc 9 + &cpu14_intc 11 &cpu14_intc 9 + &cpu15_intc 11 &cpu15_intc 9 + &cpu16_intc 11 &cpu16_intc 9 + &cpu17_intc 11 &cpu17_intc 9 + &cpu18_intc 11 &cpu18_intc 9 + &cpu19_intc 11 &cpu19_intc 9 + &cpu20_intc 11 &cpu20_intc 9 + &cpu21_intc 11 &cpu21_intc 9 + &cpu22_intc 11 &cpu22_intc 9 + &cpu23_intc 11 &cpu23_intc 9 + &cpu24_intc 11 &cpu24_intc 9 + &cpu25_intc 11 &cpu25_intc 9 + &cpu26_intc 11 &cpu26_intc 9 + &cpu27_intc 11 &cpu27_intc 9 + &cpu28_intc 11 &cpu28_intc 9 + &cpu29_intc 11 &cpu29_intc 9 + &cpu30_intc 11 &cpu30_intc 9 + &cpu31_intc 11 &cpu31_intc 9 + &cpu32_intc 11 &cpu32_intc 9 + &cpu33_intc 11 &cpu33_intc 9 + &cpu34_intc 11 &cpu34_intc 9 + &cpu35_intc 11 &cpu35_intc 9 + &cpu36_intc 11 &cpu36_intc 9 + &cpu37_intc 11 &cpu37_intc 9 + &cpu38_intc 11 &cpu38_intc 9 + &cpu39_intc 11 &cpu39_intc 9 + &cpu40_intc 11 &cpu40_intc 9 + &cpu41_intc 11 &cpu41_intc 9 + &cpu42_intc 11 &cpu42_intc 9 + &cpu43_intc 11 &cpu43_intc 9 + &cpu44_intc 11 &cpu44_intc 9 + &cpu45_intc 11 &cpu45_intc 9 + &cpu46_intc 11 &cpu46_intc 9 + &cpu47_intc 11 &cpu47_intc 9 + &cpu48_intc 11 &cpu48_intc 9 + &cpu49_intc 11 &cpu49_intc 9 + &cpu50_intc 11 &cpu50_intc 9 + &cpu51_intc 11 &cpu51_intc 9 + &cpu52_intc 11 &cpu52_intc 9 + &cpu53_intc 11 &cpu53_intc 9 + &cpu54_intc 11 &cpu54_intc 9 + &cpu55_intc 11 &cpu55_intc 9 + &cpu56_intc 11 &cpu56_intc 9 + &cpu57_intc 11 &cpu57_intc 9 + &cpu58_intc 11 &cpu58_intc 9 + &cpu59_intc 11 &cpu59_intc 9 + &cpu60_intc 11 &cpu60_intc 9 + &cpu61_intc 11 &cpu61_intc 9 + &cpu62_intc 11 &cpu62_intc 9 + &cpu63_intc 11 &cpu63_intc 9 + +#if NR_CPUS > 64 + //chip 1 + &cpu64_intc 11 &cpu64_intc 9 + &cpu65_intc 11 &cpu65_intc 9 + &cpu66_intc 11 &cpu66_intc 9 + &cpu67_intc 11 &cpu67_intc 9 + &cpu68_intc 11 &cpu68_intc 9 + &cpu69_intc 11 &cpu69_intc 9 + &cpu70_intc 11 &cpu70_intc 9 + &cpu71_intc 11 &cpu71_intc 9 + &cpu72_intc 11 &cpu72_intc 9 + &cpu73_intc 11 &cpu73_intc 9 + &cpu74_intc 11 &cpu74_intc 9 + &cpu75_intc 11 &cpu75_intc 9 + &cpu76_intc 11 &cpu76_intc 9 + &cpu77_intc 11 &cpu77_intc 9 + &cpu78_intc 11 &cpu78_intc 9 + &cpu79_intc 11 &cpu79_intc 9 + &cpu80_intc 11 &cpu80_intc 9 + &cpu81_intc 11 &cpu81_intc 9 + &cpu82_intc 11 &cpu82_intc 9 + &cpu83_intc 11 &cpu83_intc 9 + &cpu84_intc 11 &cpu84_intc 9 + &cpu85_intc 11 &cpu85_intc 9 + &cpu86_intc 11 &cpu86_intc 9 + &cpu87_intc 11 &cpu87_intc 9 + &cpu88_intc 11 &cpu88_intc 9 + &cpu89_intc 11 &cpu89_intc 9 + &cpu90_intc 11 &cpu90_intc 9 + &cpu91_intc 11 &cpu91_intc 9 + &cpu92_intc 11 &cpu92_intc 9 + &cpu93_intc 11 &cpu93_intc 9 + &cpu94_intc 11 &cpu94_intc 9 + &cpu95_intc 11 &cpu95_intc 9 + &cpu96_intc 11 &cpu96_intc 9 + &cpu97_intc 11 &cpu97_intc 9 + &cpu98_intc 11 &cpu98_intc 9 + &cpu99_intc 11 &cpu99_intc 9 + &cpu100_intc 11 &cpu100_intc 9 + &cpu101_intc 11 &cpu101_intc 9 + &cpu102_intc 11 &cpu102_intc 9 + &cpu103_intc 11 &cpu103_intc 9 + &cpu104_intc 11 &cpu104_intc 9 + &cpu105_intc 11 &cpu105_intc 9 + &cpu106_intc 11 &cpu106_intc 9 + &cpu107_intc 11 &cpu107_intc 9 + &cpu108_intc 11 &cpu108_intc 9 + &cpu109_intc 11 &cpu109_intc 9 + &cpu110_intc 11 &cpu110_intc 9 + &cpu111_intc 11 &cpu111_intc 9 + &cpu112_intc 11 &cpu112_intc 9 + &cpu113_intc 11 &cpu113_intc 9 + &cpu114_intc 11 &cpu114_intc 9 + &cpu115_intc 11 &cpu115_intc 9 + &cpu116_intc 11 &cpu116_intc 9 + &cpu117_intc 11 &cpu117_intc 9 + &cpu118_intc 11 &cpu118_intc 9 + &cpu119_intc 11 &cpu119_intc 9 + &cpu120_intc 11 &cpu120_intc 9 + &cpu121_intc 11 &cpu121_intc 9 + &cpu122_intc 11 &cpu122_intc 9 + &cpu123_intc 11 &cpu123_intc 9 + &cpu124_intc 11 &cpu124_intc 9 + &cpu125_intc 11 &cpu125_intc 9 + &cpu126_intc 11 &cpu126_intc 9 + &cpu127_intc 11 &cpu127_intc 9 +#endif + >; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <448>; + }; + + top1_misc: top_misc_ctrl@f030010000 { + compatible = "syscon"; + reg = <0xf0 0x30010000 0x0 0x8000>; + }; + + rst1: reset1-controller { + #reset-cells = <1>; + compatible = "bitmain,reset"; + subctrl-syscon = <&top1_misc>; + top_rst_offset = <0x3000>; + nr_resets = ; + }; + + gpio3: gpio@f030009000 { + compatible = "snps,dw-apb-gpio"; + reg = <0xf0 0x30009000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&s1_div_clk GATE_CLK_APB_GPIO>, + <&s1_div_clk GATE_CLK_APB_GPIO_INTR>, + <&s1_div_clk GATE_CLK_GPIO_DB>; + clock-names = "base_clk", "intr_clk", "db_clk"; + + port3a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "port0a"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = ; + }; + }; + + ethernet1: ethernet@f040026000 { + compatible = "bitmain,ethernet"; + reg = <0xf0 0x40026000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "clk_tx", "gate_clk_tx", "stmmaceth", "ptp_ref", "gate_clk_ref"; + clocks = <&s1_div_clk DIV_CLK_FPLL_TX_ETH0>, + <&s1_div_clk GATE_CLK_TX_ETH0>, + <&s1_div_clk GATE_CLK_AXI_ETH0>, + <&s1_div_clk GATE_CLK_PTP_REF_I_ETH0>, + <&s1_div_clk GATE_CLK_REF_ETH0>; + + /* no hash filter and perfect filter support */ + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,aal; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + phy-mode = "rgmii-txid"; + phy-reset-gpios = <&port3a 27 0>; + phy-handle = <&phy1>; + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x0>; + }; + }; + }; + + emmc1: bm-emmc@f04002A000 { + compatible = "bitmain,bm-emmc"; + reg = <0xf0 0x4002A000 0x0 0x1000>; + reg-names = "core_mem"; + interrupt-parent = <&intc>; + interrupts = ; + bus-width = <4>; + non-removable; + no-sdio; + no-sd; + resets = <&rst1 RST_EMMC>; + reset-names = "emmc"; + clocks = + <&s1_div_clk GATE_CLK_EMMC_100M>, + <&s1_div_clk GATE_CLK_AXI_EMMC>, + <&s1_div_clk GATE_CLK_100K_EMMC>; + clock-names = + "clk_gate_emmc", + "clk_gate_axi_emmc", + "clk_gate_100k_emmc"; + }; + + sd1: bm-sd@f04002B000 { + compatible = "bitmain,bm-sd"; + reg = <0xf0 0x4002B000 0x0 0x1000>; + reg-names = "core_mem"; + interrupt-parent = <&intc>; + interrupts = ; + bus-width = <4>; + no-sdio; + no-mmc; + resets = <&rst1 RST_SD>; + reset-names = "sdio"; + clocks = + <&s1_div_clk GATE_CLK_SD_100M>, + <&s1_div_clk GATE_CLK_AXI_SD>, + <&s1_div_clk GATE_CLK_100K_SD>; + clock-names = + "clk_gate_sd", + "clk_gate_axi_sd", + "clk_gate_100k_sd"; + }; + }; + + spifmc2: flash-controller@f000180000 { + compatible = "sophgo,spifmc"; + reg = <0xf0 0x00180000 0x0 0x1000000>; + reg-names = "memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000000>; + clocks = <&s1_div_clk GATE_CLK_AHB_SF>; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + }; + + spifmc3: flash-controller@f002180000 { + compatible = "sophgo,spifmc"; + reg = <0xf0 0x02180000 0x0 0x1000000>; + reg-names = "memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000000>; + clocks = <&s1_div_clk GATE_CLK_AHB_SF>; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + }; + + aliases { + serial0 = &uart0; + ethernet0 = ðernet0; + ethernet1 = ðernet1; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi b/arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi new file mode 100644 index 0000000000000..af3380412f1d8 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi @@ -0,0 +1,124 @@ +/ { + socket0-clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cgi: ctrystal { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "cgi"; + #clock-cells = <0>; + }; + + /* pll clock */ + mpll: mpll { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top_misc>; + clocks = <&cgi>; + clock-output-names = "mpll_clock"; + }; + + fpll: fpll { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top_misc>; + clocks = <&cgi>; + clock-output-names = "fpll_clock"; + }; + + dpll0: dpll0 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top_misc>; + clocks = <&cgi>; + clock-output-names = "dpll0_clock"; + }; + + dpll1: dpll1 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + mode = ; + subctrl-syscon = <&top_misc>; + clocks = <&cgi>; + id = ; + clock-output-names = "dpll1_clock"; + }; + + div_clk: div_clk { + compatible = "mango, pll-child-clock"; + #clock-cells = <1>; + id = ; + subctrl-syscon = <&top_misc>; + }; + + mux_clk: mux_clk { + compatible = "mango, pll-mux-clock"; + #clock-cells = <1>; + id = ; + subctrl-syscon = <&top_misc>; + }; + + socket0_default_rates { + compatible = "mango, clk-default-rates"; + #clock-cells = <1>; + subctrl-syscon = <&top_misc>; + clocks = \ + <&mpll>, <&fpll>, + + <&div_clk DIV_CLK_FPLL_RP_CPU_NORMAL_1>, + <&div_clk DIV_CLK_FPLL_50M_A53>, + <&div_clk DIV_CLK_FPLL_TOP_RP_CMN_DIV2>, + <&div_clk DIV_CLK_FPLL_UART_500M>, + <&div_clk DIV_CLK_FPLL_AHB_LPC>, + <&div_clk DIV_CLK_FPLL_EFUSE>, + <&div_clk DIV_CLK_FPLL_TX_ETH0>, + <&div_clk DIV_CLK_FPLL_PTP_REF_I_ETH0>, + <&div_clk DIV_CLK_FPLL_REF_ETH0>, + <&div_clk DIV_CLK_FPLL_EMMC>, + <&div_clk DIV_CLK_FPLL_SD>, + <&div_clk DIV_CLK_FPLL_TOP_AXI0>, + <&div_clk DIV_CLK_FPLL_TOP_AXI_HSPERI>, + <&div_clk DIV_CLK_FPLL_AXI_DDR_1>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER1>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER2>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER3>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER4>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER5>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER6>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER7>, + <&div_clk DIV_CLK_FPLL_DIV_TIMER8>, + <&div_clk DIV_CLK_FPLL_100K_EMMC>, + <&div_clk DIV_CLK_FPLL_100K_SD>, + <&div_clk DIV_CLK_FPLL_GPIO_DB>, + + <&div_clk DIV_CLK_MPLL_RP_CPU_NORMAL_0>, + <&div_clk DIV_CLK_MPLL_AXI_DDR_0>; + + clock-rates = \ + <2000000000>, <1000000000>, + + <2000000000>, <50000000>, + <1000000000>, <500000000>, + <200000000>, <25000000>, + <125000000>, <50000000>, + <25000000>, <100000000>, + <100000000>, <100000000>, + <250000000>, <1000000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <100000>, <100000>, <100000>, + + <2000000001>, <1000000001>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi b/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi new file mode 100644 index 0000000000000..cfe34495e4fd6 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi @@ -0,0 +1,124 @@ +/ { + socket1-clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cgi1: ctrystal1 { + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "s1_cgi"; + #clock-cells = <0>; + }; + + /* pll clock */ + mpll1: mpll1 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top1_misc>; + clocks = <&cgi1>; + clock-output-names = "s1_mpll_clock"; + }; + + fpll1: fpll1 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top1_misc>; + clocks = <&cgi1>; + clock-output-names = "s1_fpll_clock"; + }; + + dpll01: dpll01 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + id = ; + mode = ; + subctrl-syscon = <&top1_misc>; + clocks = <&cgi1>; + clock-output-names = "s1_dpll0_clock"; + }; + + dpll11: dpll11 { + compatible = "mango, pll-clock"; + #clock-cells = <0>; + mode = ; + subctrl-syscon = <&top1_misc>; + clocks = <&cgi1>; + id = ; + clock-output-names = "s1_dpll1_clock"; + }; + + s1_div_clk: s1_div_clk { + compatible = "mango, pll-child-clock"; + #clock-cells = <1>; + id = ; + subctrl-syscon = <&top1_misc>; + }; + + s1_mux_clk: s1_mux_clk { + compatible = "mango, pll-mux-clock"; + #clock-cells = <1>; + id = ; + subctrl-syscon = <&top1_misc>; + }; + + socket1_default_rates { + compatible = "mango, clk-default-rates"; + #clock-cells = <1>; + subctrl-syscon = <&top1_misc>; + clocks = \ + <&mpll1>, <&fpll1>, + + <&s1_div_clk DIV_CLK_FPLL_RP_CPU_NORMAL_1>, + <&s1_div_clk DIV_CLK_FPLL_50M_A53>, + <&s1_div_clk DIV_CLK_FPLL_TOP_RP_CMN_DIV2>, + <&s1_div_clk DIV_CLK_FPLL_UART_500M>, + <&s1_div_clk DIV_CLK_FPLL_AHB_LPC>, + <&s1_div_clk DIV_CLK_FPLL_EFUSE>, + <&s1_div_clk DIV_CLK_FPLL_TX_ETH0>, + <&s1_div_clk DIV_CLK_FPLL_PTP_REF_I_ETH0>, + <&s1_div_clk DIV_CLK_FPLL_REF_ETH0>, + <&s1_div_clk DIV_CLK_FPLL_EMMC>, + <&s1_div_clk DIV_CLK_FPLL_SD>, + <&s1_div_clk DIV_CLK_FPLL_TOP_AXI0>, + <&s1_div_clk DIV_CLK_FPLL_TOP_AXI_HSPERI>, + <&s1_div_clk DIV_CLK_FPLL_AXI_DDR_1>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER1>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER2>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER3>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER4>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER5>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER6>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER7>, + <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER8>, + <&s1_div_clk DIV_CLK_FPLL_100K_EMMC>, + <&s1_div_clk DIV_CLK_FPLL_100K_SD>, + <&s1_div_clk DIV_CLK_FPLL_GPIO_DB>, + + <&s1_div_clk DIV_CLK_MPLL_RP_CPU_NORMAL_0>, + <&s1_div_clk DIV_CLK_MPLL_AXI_DDR_0>; + + clock-rates = \ + <2000000000>, <1000000000>, + + <2000000000>, <50000000>, + <1000000000>, <500000000>, + <200000000>, <25000000>, + <125000000>, <50000000>, + <25000000>, <100000000>, + <100000000>, <100000000>, + <250000000>, <1000000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <100000>, <100000>, <100000>, + + <2000000001>, <1000000001>; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi b/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi new file mode 100644 index 0000000000000..7efc9741f3e7f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi @@ -0,0 +1,1148 @@ +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu-map { + socket0 { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu16>; + }; + core1 { + cpu = <&cpu17>; + }; + core2 { + cpu = <&cpu18>; + }; + core3 { + cpu = <&cpu19>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu20>; + }; + core1 { + cpu = <&cpu21>; + }; + core2 { + cpu = <&cpu22>; + }; + core3 { + cpu = <&cpu23>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu8>; + }; + core1 { + cpu = <&cpu9>; + }; + core2 { + cpu = <&cpu10>; + }; + core3 { + cpu = <&cpu11>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu12>; + }; + core1 { + cpu = <&cpu13>; + }; + core2 { + cpu = <&cpu14>; + }; + core3 { + cpu = <&cpu15>; + }; + }; + + cluster6 { + core0 { + cpu = <&cpu24>; + }; + core1 { + cpu = <&cpu25>; + }; + core2 { + cpu = <&cpu26>; + }; + core3 { + cpu = <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu = <&cpu28>; + }; + core1 { + cpu = <&cpu29>; + }; + core2 { + cpu = <&cpu30>; + }; + core3 { + cpu = <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu = <&cpu32>; + }; + core1 { + cpu = <&cpu33>; + }; + core2 { + cpu = <&cpu34>; + }; + core3 { + cpu = <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu = <&cpu36>; + }; + core1 { + cpu = <&cpu37>; + }; + core2 { + cpu = <&cpu38>; + }; + core3 { + cpu = <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu = <&cpu48>; + }; + core1 { + cpu = <&cpu49>; + }; + core2 { + cpu = <&cpu50>; + }; + core3 { + cpu = <&cpu51>; + }; + }; + + cluster11 { + core0 { + cpu = <&cpu52>; + }; + core1 { + cpu = <&cpu53>; + }; + core2 { + cpu = <&cpu54>; + }; + core3 { + cpu = <&cpu55>; + }; + }; + + cluster12 { + core0 { + cpu = <&cpu40>; + }; + core1 { + cpu = <&cpu41>; + }; + core2 { + cpu = <&cpu42>; + }; + core3 { + cpu = <&cpu43>; + }; + }; + + cluster13 { + core0 { + cpu = <&cpu44>; + }; + core1 { + cpu = <&cpu45>; + }; + core2 { + cpu = <&cpu46>; + }; + core3 { + cpu = <&cpu47>; + }; + }; + + cluster14 { + core0 { + cpu = <&cpu56>; + }; + core1 { + cpu = <&cpu57>; + }; + core2 { + cpu = <&cpu58>; + }; + core3 { + cpu = <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu = <&cpu60>; + }; + core1 { + cpu = <&cpu61>; + }; + core2 { + cpu = <&cpu62>; + }; + core3 { + cpu = <&cpu63>; + }; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + device_type = "cpu"; + reg = <1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + device_type = "cpu"; + reg = <2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + device_type = "cpu"; + reg = <3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + device_type = "cpu"; + reg = <4>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu5: cpu@5 { + device_type = "cpu"; + reg = <5>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu5_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu6: cpu@6 { + device_type = "cpu"; + reg = <6>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu6_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu7: cpu@7 { + device_type = "cpu"; + reg = <7>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu7_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu8: cpu@8 { + device_type = "cpu"; + reg = <8>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu8_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu9: cpu@9 { + device_type = "cpu"; + reg = <9>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu9_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu10: cpu@10 { + device_type = "cpu"; + reg = <10>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu10_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu11: cpu@11 { + device_type = "cpu"; + reg = <11>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu11_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu12: cpu@12 { + device_type = "cpu"; + reg = <12>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu12_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu13: cpu@13 { + device_type = "cpu"; + reg = <13>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu13_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu14: cpu@14 { + device_type = "cpu"; + reg = <14>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu14_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu15: cpu@15 { + device_type = "cpu"; + reg = <15>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu15_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu16: cpu@16 { + device_type = "cpu"; + reg = <16>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu16_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu17: cpu@17 { + device_type = "cpu"; + reg = <17>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu17_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu18: cpu@18 { + device_type = "cpu"; + reg = <18>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu18_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu19: cpu@19 { + device_type = "cpu"; + reg = <19>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu19_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu20: cpu@20 { + device_type = "cpu"; + reg = <20>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu20_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu21: cpu@21 { + device_type = "cpu"; + reg = <21>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu21_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu22: cpu@22 { + device_type = "cpu"; + reg = <22>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu22_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu23: cpu@23 { + device_type = "cpu"; + reg = <23>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu23_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu24: cpu@24 { + device_type = "cpu"; + reg = <24>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu24_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu25: cpu@25 { + device_type = "cpu"; + reg = <25>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu25_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu26: cpu@26 { + device_type = "cpu"; + reg = <26>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu26_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu27: cpu@27 { + device_type = "cpu"; + reg = <27>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu27_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu28: cpu@28 { + device_type = "cpu"; + reg = <28>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu28_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu29: cpu@29 { + device_type = "cpu"; + reg = <29>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu29_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu30: cpu@30 { + device_type = "cpu"; + reg = <30>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu30_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu31: cpu@31 { + device_type = "cpu"; + reg = <31>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu31_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu32: cpu@32 { + device_type = "cpu"; + reg = <32>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu32_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu33: cpu@33 { + device_type = "cpu"; + reg = <33>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu33_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu34: cpu@34 { + device_type = "cpu"; + reg = <34>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu34_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu35: cpu@35 { + device_type = "cpu"; + reg = <35>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu35_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu36: cpu@36 { + device_type = "cpu"; + reg = <36>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu36_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu37: cpu@37 { + device_type = "cpu"; + reg = <37>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu37_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu38: cpu@38 { + device_type = "cpu"; + reg = <38>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu38_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu39: cpu@39 { + device_type = "cpu"; + reg = <39>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu39_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu40: cpu@40 { + device_type = "cpu"; + reg = <40>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu40_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu41: cpu@41 { + device_type = "cpu"; + reg = <41>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu41_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu42: cpu@42 { + device_type = "cpu"; + reg = <42>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu42_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu43: cpu@43 { + device_type = "cpu"; + reg = <43>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu43_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu44: cpu@44 { + device_type = "cpu"; + reg = <44>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu44_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu45: cpu@45 { + device_type = "cpu"; + reg = <45>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu45_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu46: cpu@46 { + device_type = "cpu"; + reg = <46>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu46_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu47: cpu@47 { + device_type = "cpu"; + reg = <47>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu47_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu48: cpu@48 { + device_type = "cpu"; + reg = <48>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu48_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu49: cpu@49 { + device_type = "cpu"; + reg = <49>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu49_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu50: cpu@50 { + device_type = "cpu"; + reg = <50>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu50_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu51: cpu@51 { + device_type = "cpu"; + reg = <51>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu51_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu52: cpu@52 { + device_type = "cpu"; + reg = <52>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu52_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu53: cpu@53 { + device_type = "cpu"; + reg = <53>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu53_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu54: cpu@54 { + device_type = "cpu"; + reg = <54>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu54_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu55: cpu@55 { + device_type = "cpu"; + reg = <55>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu55_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu56: cpu@56 { + device_type = "cpu"; + reg = <56>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu56_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu57: cpu@57 { + device_type = "cpu"; + reg = <57>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu57_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu58: cpu@58 { + device_type = "cpu"; + reg = <58>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu58_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu59: cpu@59 { + device_type = "cpu"; + reg = <59>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu59_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu60: cpu@60 { + device_type = "cpu"; + reg = <60>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu60_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu61: cpu@61 { + device_type = "cpu"; + reg = <61>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu61_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu62: cpu@62 { + device_type = "cpu"; + reg = <62>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu62_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu63: cpu@63 { + device_type = "cpu"; + reg = <63>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu63_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi b/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi new file mode 100644 index 0000000000000..255306410f40c --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi @@ -0,0 +1,1149 @@ +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <50000000>; + + cpu-map { + socket1 { + cluster0 { + core0 { + cpu = <&cpu64>; + }; + core1 { + cpu = <&cpu65>; + }; + core2 { + cpu = <&cpu66>; + }; + core3 { + cpu = <&cpu67>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu68>; + }; + core1 { + cpu = <&cpu69>; + }; + core2 { + cpu = <&cpu70>; + }; + core3 { + cpu = <&cpu71>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu80>; + }; + core1 { + cpu = <&cpu81>; + }; + core2 { + cpu = <&cpu82>; + }; + core3 { + cpu = <&cpu83>; + }; + }; + + cluster3 { + core0 { + cpu = <&cpu84>; + }; + core1 { + cpu = <&cpu85>; + }; + core2 { + cpu = <&cpu86>; + }; + core3 { + cpu = <&cpu87>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu72>; + }; + core1 { + cpu = <&cpu73>; + }; + core2 { + cpu = <&cpu74>; + }; + core3 { + cpu = <&cpu75>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu76>; + }; + core1 { + cpu = <&cpu77>; + }; + core2 { + cpu = <&cpu78>; + }; + core3 { + cpu = <&cpu79>; + }; + }; + + cluster6 { + core0 { + cpu = <&cpu88>; + }; + core1 { + cpu = <&cpu89>; + }; + core2 { + cpu = <&cpu90>; + }; + core3 { + cpu = <&cpu91>; + }; + }; + + cluster7 { + core0 { + cpu = <&cpu92>; + }; + core1 { + cpu = <&cpu93>; + }; + core2 { + cpu = <&cpu94>; + }; + core3 { + cpu = <&cpu95>; + }; + }; + + cluster8 { + core0 { + cpu = <&cpu96>; + }; + core1 { + cpu = <&cpu97>; + }; + core2 { + cpu = <&cpu98>; + }; + core3 { + cpu = <&cpu99>; + }; + }; + + cluster9 { + core0 { + cpu = <&cpu100>; + }; + core1 { + cpu = <&cpu101>; + }; + core2 { + cpu = <&cpu102>; + }; + core3 { + cpu = <&cpu103>; + }; + }; + + cluster10 { + core0 { + cpu = <&cpu112>; + }; + core1 { + cpu = <&cpu113>; + }; + core2 { + cpu = <&cpu114>; + }; + core3 { + cpu = <&cpu115>; + }; + }; + + cluster11 { + core0 { + cpu = <&cpu116>; + }; + core1 { + cpu = <&cpu117>; + }; + core2 { + cpu = <&cpu118>; + }; + core3 { + cpu = <&cpu119>; + }; + }; + + cluster12 { + core0 { + cpu = <&cpu104>; + }; + core1 { + cpu = <&cpu105>; + }; + core2 { + cpu = <&cpu106>; + }; + core3 { + cpu = <&cpu107>; + }; + }; + + cluster13 { + core0 { + cpu = <&cpu108>; + }; + core1 { + cpu = <&cpu109>; + }; + core2 { + cpu = <&cpu110>; + }; + core3 { + cpu = <&cpu111>; + }; + }; + + cluster14 { + core0 { + cpu = <&cpu120>; + }; + core1 { + cpu = <&cpu121>; + }; + core2 { + cpu = <&cpu122>; + }; + core3 { + cpu = <&cpu123>; + }; + }; + + cluster15 { + core0 { + cpu = <&cpu124>; + }; + core1 { + cpu = <&cpu125>; + }; + core2 { + cpu = <&cpu126>; + }; + core3 { + cpu = <&cpu127>; + }; + }; + }; + }; + + + cpu64: cpu@64 { + device_type = "cpu"; + reg = <64>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu64_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu65: cpu@65 { + device_type = "cpu"; + reg = <65>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu65_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu66: cpu@66 { + device_type = "cpu"; + reg = <66>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu66_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu67: cpu@67 { + device_type = "cpu"; + reg = <67>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu67_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu68: cpu@68 { + device_type = "cpu"; + reg = <68>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu68_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu69: cpu@69 { + device_type = "cpu"; + reg = <69>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu69_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu70: cpu@70 { + device_type = "cpu"; + reg = <70>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu70_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu71: cpu@71 { + device_type = "cpu"; + reg = <71>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu71_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu72: cpu@72 { + device_type = "cpu"; + reg = <72>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu72_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu73: cpu@73 { + device_type = "cpu"; + reg = <73>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu73_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu74: cpu@74 { + device_type = "cpu"; + reg = <74>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu74_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu75: cpu@75 { + device_type = "cpu"; + reg = <75>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu75_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu76: cpu@76 { + device_type = "cpu"; + reg = <76>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu76_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu77: cpu@77 { + device_type = "cpu"; + reg = <77>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu77_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu78: cpu@78 { + device_type = "cpu"; + reg = <78>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu78_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu79: cpu@79 { + device_type = "cpu"; + reg = <79>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu79_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu80: cpu@80 { + device_type = "cpu"; + reg = <80>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu80_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu81: cpu@81 { + device_type = "cpu"; + reg = <81>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu81_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu82: cpu@82 { + device_type = "cpu"; + reg = <82>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu82_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu83: cpu@83 { + device_type = "cpu"; + reg = <83>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu83_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu84: cpu@84 { + device_type = "cpu"; + reg = <84>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu84_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu85: cpu@85 { + device_type = "cpu"; + reg = <85>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu85_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu86: cpu@86 { + device_type = "cpu"; + reg = <86>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu86_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu87: cpu@87 { + device_type = "cpu"; + reg = <87>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <4>; + cpu87_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu88: cpu@88 { + device_type = "cpu"; + reg = <88>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu88_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu89: cpu@89 { + device_type = "cpu"; + reg = <89>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu89_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu90: cpu@90 { + device_type = "cpu"; + reg = <90>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu90_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu91: cpu@91 { + device_type = "cpu"; + reg = <91>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu91_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu92: cpu@92 { + device_type = "cpu"; + reg = <92>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu92_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu93: cpu@93 { + device_type = "cpu"; + reg = <93>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu93_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu94: cpu@94 { + device_type = "cpu"; + reg = <94>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu94_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu95: cpu@95 { + device_type = "cpu"; + reg = <95>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <5>; + cpu95_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu96: cpu@96 { + device_type = "cpu"; + reg = <96>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu96_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu97: cpu@97 { + device_type = "cpu"; + reg = <97>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu97_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu98: cpu@98 { + device_type = "cpu"; + reg = <98>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu98_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu99: cpu@99 { + device_type = "cpu"; + reg = <99>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu99_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu100: cpu@100 { + device_type = "cpu"; + reg = <100>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu100_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu101: cpu@101 { + device_type = "cpu"; + reg = <101>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu101_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu102: cpu@102 { + device_type = "cpu"; + reg = <102>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu102_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu103: cpu@103 { + device_type = "cpu"; + reg = <103>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu103_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu104: cpu@104 { + device_type = "cpu"; + reg = <104>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu104_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu105: cpu@105 { + device_type = "cpu"; + reg = <105>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu105_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu106: cpu@106 { + device_type = "cpu"; + reg = <106>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu106_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu107: cpu@107 { + device_type = "cpu"; + reg = <107>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu107_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu108: cpu@108 { + device_type = "cpu"; + reg = <108>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu108_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu109: cpu@109 { + device_type = "cpu"; + reg = <109>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu109_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu110: cpu@110 { + device_type = "cpu"; + reg = <110>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu110_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu111: cpu@111 { + device_type = "cpu"; + reg = <111>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu111_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu112: cpu@112 { + device_type = "cpu"; + reg = <112>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu112_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu113: cpu@113 { + device_type = "cpu"; + reg = <113>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu113_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu114: cpu@114 { + device_type = "cpu"; + reg = <114>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu114_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu115: cpu@115 { + device_type = "cpu"; + reg = <115>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu115_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu116: cpu@116 { + device_type = "cpu"; + reg = <116>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu116_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu117: cpu@117 { + device_type = "cpu"; + reg = <117>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu117_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu118: cpu@118 { + device_type = "cpu"; + reg = <118>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu118_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu119: cpu@119 { + device_type = "cpu"; + reg = <119>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <6>; + cpu119_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu120: cpu@120 { + device_type = "cpu"; + reg = <120>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu120_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu121: cpu@121 { + device_type = "cpu"; + reg = <121>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu121_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu122: cpu@122 { + device_type = "cpu"; + reg = <122>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu122_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu123: cpu@123 { + device_type = "cpu"; + reg = <123>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu123_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu124: cpu@124 { + device_type = "cpu"; + reg = <124>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu124_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu125: cpu@125 { + device_type = "cpu"; + reg = <125>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu125_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu126: cpu@126 { + device_type = "cpu"; + reg = <126>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu126_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu127: cpu@127 { + device_type = "cpu"; + reg = <127>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <7>; + cpu127_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts new file mode 100644 index 0000000000000..00f2d5e2c6743 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts @@ -0,0 +1,163 @@ +#include "mango.dtsi" +#include "mango-pcie-4rc.dtsi" + +/ { + info { + file-name = "mango-milkv-pioneer.dts"; + }; +}; + +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; + + mango_srst: mango-reset@17 { + compatible = "mango,reset"; + reg = <0x17>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_acquire>; +}; + +&soc { + /delete-node/ ethernet@7040026000; + gpio-poweroff { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + label = "GPIO Key Power"; + linux,code = ; + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; + + gpio-restart { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&restart_key>; + + restart { + label = "GPIO Key Restart"; + linux,code = ; + gpios = <&port0a 23 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; +}; + +&tach0 { + pinctrl-names = "default"; + pinctrl-0 = <&fan0_acquire>; +}; + +&tach1 { + pinctrl-names = "default"; + pinctrl-0 = <&fan1_acquire>; +}; + +/ { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 40000>, <&pwm 1 40000>; // period_ns + pwm-names = "pwm0","pwm1"; + pwm_inuse = "pwm0"; + #cooling-cells = <2>; + cooling-levels = <1 1 1 1 1>; //total 255 + }; + + thermal_zones: thermal-zones { + soc { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 0>; + + trips { + soc_pwmfan_trip1: soc_pwmfan_trip@1 { + temperature = <30000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip2: soc_pwmfan_trip@2 { + temperature = <40000>; /* millicelsius */ + hysteresis = <12000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip3: soc_pwmfan_trip@3 { + temperature = <50000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip4: soc_pwmfan_trip@4 { + temperature = <60000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_pwmfan_trip1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_pwmfan_trip2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_pwmfan_trip3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_pwmfan_trip4>; + cooling-device = <&pwmfan 3 4>; + }; + }; + + }; + + board { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 1>; + + trips { + board_pwmfan_trip1: board_pwmfan_trip@1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_pwmfan_trip1>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; + +}; + +&chosen { + bootargs = "console=ttyS0,115200 console=tty1 earlycon maxcpus=1"; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi new file mode 100644 index 0000000000000..e39b3a80bf06e --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi @@ -0,0 +1,81 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <1>; + interrupt-parent = <&intc1>; + //interrupts = ; + //interrupt-names = "msi"; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@f060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xff>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <1>; + msix-supported = <0>; + interrupt-parent = <&intc2>; + //interrupts = ; + //interrupt-names = "msi"; + reg = <0xf0 0x60000000 0x0 0x02000000>, + <0xc0 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0800000 0xc0 0xc0800000 0x0 0x00800000>, + <0x42000000 0x0 0xd0000000 0xc0 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0xc0 0xe0000000 0x0 0x20000000>, + <0x43000000 0xc2 0x00000000 0xc2 0x00000000 0x2 0x00000000>, + <0x03000000 0xc1 0x00000000 0xc1 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi new file mode 100644 index 0000000000000..776889585272d --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi @@ -0,0 +1,116 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x0 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; + + pcie@7060800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x40 0x7f>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <0>; + top-intc-id = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x44 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x02000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; + + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xff>; + linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi new file mode 100644 index 0000000000000..9c4c9641e1c04 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi @@ -0,0 +1,115 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x0 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + top-intc-id = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@7060800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x40 0x7f>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + //interrupts = ; + //interrupt-names = "msi"; + reg = <0x44 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x02000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xff>; + linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi new file mode 100644 index 0000000000000..63fb41b438092 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi @@ -0,0 +1,112 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x0 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@7060800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x40 0x7f>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x44 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xff>; + linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x03000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi new file mode 100644 index 0000000000000..efbcc5c047405 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi @@ -0,0 +1,155 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + /* + * IO, check IO_SPACE_LIMIT + * 32bit prefetchable memory + * 32bit non-prefetchable memory + * 64bit prefetchable memory + * 64bit non-prefetchable memory + */ + ranges = <0x01000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@7062800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x40 0x7f>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + /* + * IO, check IO_SPACE_LIMIT + * 32bit prefetchable memory + * 32bit non-prefetchable memory + * 64bit prefetchable memory + * 64bit non-prefetchable memory + */ + ranges = <0x01000000 0x0 0xc0000000 0x4c 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x4c 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x4c 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@f060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xbf>; + linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <1>; + msix-supported = <0>; + interrupt-parent = <&intc2>; + reg = <0xf0 0x60000000 0x0 0x02000000>, + <0xc0 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + /* + * IO, check IO_SPACE_LIMIT + * 32bit prefetchable memory + * 32bit non-prefetchable memory + * 64bit prefetchable memory + * 64bit non-prefetchable memory + */ + ranges = <0x01000000 0x0 0xc0000000 0xc0 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0xc0 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0xc0 0xe0000000 0x0 0x20000000>, + <0x43000000 0xc2 0x00000000 0xc2 0x00000000 0x2 0x00000000>, + <0x03000000 0xc1 0x00000000 0xc1 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; + + pcie@f068000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0xc0 0xff>; + linux,pci-domain = <3>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <1>; + msix-supported = <0>; + interrupt-parent = <&intc2>; + reg = <0xc4 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + /* + * IO, check IO_SPACE_LIMIT + * 32bit prefetchable memory + * 32bit non-prefetchable memory + * 64bit prefetchable memory + * 64bit non-prefetchable memory + */ + ranges = <0x01000000 0x0 0xc0000000 0xc4 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0xc4 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0xc4 0xe0000000 0x0 0x20000000>, + <0x43000000 0xc6 0x00000000 0xc6 0x00000000 0x2 0x00000000>, + <0x03000000 0xc5 0x00000000 0xc5 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi new file mode 100644 index 0000000000000..22bc466757bf3 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi @@ -0,0 +1,151 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + pcie@7060000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x0 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <1>; + interrupt-parent = <&intc1>; + //top-intc-used = <0>; + //interrupt-parent = <&intc>; + //interrupts = ; + //interrupt-names = "msi"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +#if 0 + pcie@7060800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x40 0x7f>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x44 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +#endif + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x80 0xbf>; + linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x0>; + top-intc-used = <0>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "msi"; + reg = <0x70 0x62000000 0x0 0x02000000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + + status = "okay"; + }; + + pcie@7062800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0xc0 0xff>; + linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x1>; + link-id = /bits/ 16 <0x1>; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; + reg = <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "cfg"; + + // IO, check IO_SPACE_LIMIT + // 32bit prefetchable memory + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi b/arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi new file mode 100644 index 0000000000000..f3fb2e39af266 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi @@ -0,0 +1,434 @@ +/ { + bmpctrl: pinctrl@50010400 { + compatible = "sophgo, pinctrl-mango"; + subctrl-syscon = <&top_misc>; + top_pinctl_offset = <0x1000>; + + lpc_acquire: lpc_acquire { + mux { + groups = "lpc_grp"; + function = "lpc_a"; + }; + }; + + lpc_release: lpc_release{ + mux { + groups = "lpc_grp"; + function = "lpc_r"; + }; + }; + + pcie_acquire: pcie_acquire { + mux { + groups = "pcie_grp"; + function = "pcie_a"; + }; + }; + + pcie_release: pcie_release{ + mux { + groups = "pcie_grp"; + function = "pcie_r"; + }; + }; + + spif_acquire: spif_acquire { + mux { + groups = "spif_grp"; + function = "spif_a"; + }; + }; + + spif_release: spif_release{ + mux { + groups = "spif_grp"; + function = "spif_r"; + }; + }; + + emmc_acquire: emmc_acquire { + mux { + groups = "emmc_grp"; + function = "emmc_a"; + }; + }; + + emmc_release: emmc_release{ + mux { + groups = "emmc_grp"; + function = "emmc_r"; + }; + }; + + sdio_acquire: sdio_acquire { + mux { + groups = "sdio_grp"; + function = "sdio_a"; + }; + }; + + sdio_release: sdio_release{ + mux { + groups = "sdio_grp"; + function = "sdio_r"; + }; + }; + + eth0_acquire: eth0_acquire { + mux { + groups = "eth0_grp"; + function = "eth0_a"; + }; + }; + + eth0_release: eth0_release{ + mux { + groups = "eth0_grp"; + function = "eth0_r"; + }; + }; + + pwm0_acquire: pwm0_acquire { + mux { + groups = "pwm0_grp"; + function = "pwm0_a"; + }; + }; + + pwm0_release: pwm0_release{ + mux { + groups = "pwm0_grp"; + function = "pwm0_r"; + }; + }; + + pwm1_acquire: pwm1_acquire { + mux { + groups = "pwm1_grp"; + function = "pwm1_a"; + }; + }; + + pwm1_release: pwm1_release{ + mux { + groups = "pwm1_grp"; + function = "pwm1_r"; + }; + }; + + pwm2_acquire: pwm2_acquire { + mux { + groups = "pwm2_grp"; + function = "pwm2_a"; + }; + }; + + pwm2_release: pwm2_release{ + mux { + groups = "pwm2_grp"; + function = "pwm2_r"; + }; + }; + + pwm3_acquire: pwm3_acquire { + mux { + groups = "pwm3_grp"; + function = "pwm3_a"; + }; + }; + + pwm3_release: pwm3_release{ + mux { + groups = "pwm3_grp"; + function = "pwm3_r"; + }; + }; + + fan0_acquire: fan0_acquire { + mux { + groups = "fan0_grp"; + function = "fan0_a"; + }; + }; + + fan0_release: fan0_release{ + mux { + groups = "fan0_grp"; + function = "fan0_r"; + }; + }; + + fan1_acquire: fan1_acquire { + mux { + groups = "fan1_grp"; + function = "fan1_a"; + }; + }; + + fan1_release: fan1_release{ + mux { + groups = "fan1_grp"; + function = "fan1_r"; + }; + }; + + fan2_acquire: fan2_acquire { + mux { + groups = "fan2_grp"; + function = "fan2_a"; + }; + }; + + fan2_release: fan2_release{ + mux { + roups = "fan2_grp"; + function = "fan2_r"; + }; + }; + + fan3_acquire: fan3_acquire { + mux { + groups = "fan3_grp"; + function = "fan3_a"; + }; + }; + + fan3_release: fan3_release{ + mux { + groups = "fan3_grp"; + function = "fan3_r"; + }; + }; + + i2c0_acquire: i2c0_acquire { + mux { + groups = "i2c0_grp"; + function = "i2c0_a"; + }; + }; + + i2c0_release: i2c0_release{ + mux { + groups = "i2c0_grp"; + function = "i2c0_r"; + }; + }; + + i2c1_acquire: i2c1_acquire { + mux { + groups = "i2c1_grp"; + function = "i2c1_a"; + }; + }; + + i2c1_release: i2c1_release{ + mux { + groups = "i2c1_grp"; + function = "i2c1_r"; + }; + }; + + i2c2_acquire: i2c2_acquire { + mux { + groups = "i2c2_grp"; + function = "i2c2_a"; + }; + }; + + i2c2_release: i2c2_release{ + mux { + groups = "i2c2_grp"; + function = "i2c2_r"; + }; + }; + + i2c3_acquire: i2c3_acquire { + mux { + groups = "i2c3_grp"; + function = "i2c3_a"; + }; + }; + + i2c3_release: i2c3_release{ + mux { + groups = "i2c3_grp"; + function = "i2c3_r"; + }; + }; + + uart0_acquire: uart0_acquire { + mux { + groups = "uart0_grp"; + function = "uart0_a"; + }; + }; + + uart0_release: uart0_release{ + mux { + groups = "uart0_grp"; + function = "uart0_r"; + }; + }; + + uart1_acquire: uart1_acquire { + mux { + groups = "uart1_grp"; + function = "uart1_a"; + }; + }; + + uart1_release: uart1_release{ + mux { + groups = "uart1_grp"; + function = "uart1_r"; + }; + }; + + uart2_acquire: uart2_acquire { + mux { + groups = "uart2_grp"; + function = "uart2_a"; + }; + }; + + uart2_release: uart2_release{ + mux { + groups = "uart2_grp"; + function = "uart2_r"; + }; + }; + + uart3_acquire: uart3_acquire { + mux { + groups = "uart3_grp"; + function = "uart3_a"; + }; + }; + + uart3_release: uart3_release{ + mux { + groups = "uart3_grp"; + function = "uart3_r"; + }; + }; + + spi0_acquire: spi0_acquire { + mux { + groups = "spi0_grp"; + function = "spi0_a"; + }; + }; + + spi0_release: spi0_release{ + mux { + groups = "spi0_grp"; + function = "spi0_r"; + }; + }; + + spi1_acquire: spi1_acquire { + mux { + groups = "spi1_grp"; + function = "spi1_a"; + }; + }; + + spi1_release: spi1_release{ + mux { + groups = "spi1_grp"; + function = "spi1_r"; + }; + }; + + jtag0_acquire: jtag0_acquire { + mux { + groups = "jtag0_grp"; + function = "jtag0_a"; + }; + }; + + jtag0_release: jtag0_release{ + mux { + groups = "jtag0_grp"; + function = "jtag0_r"; + }; + }; + + jtag1_acquire: jtag1_acquire { + mux { + groups = "jtag1_grp"; + function = "jtag1_a"; + }; + }; + + jtag1_release: jtag1_release{ + mux { + groups = "jtag1_grp"; + function = "jtag1_r"; + }; + }; + + jtag2_acquire: jtag2_acquire { + mux { + groups = "jtag2_grp"; + function = "jtag2_a"; + }; + }; + + jtag2_release: jtag2_release{ + mux { + groups = "jtag2_grp"; + function = "jtag2_r"; + }; + }; + + gpio2_acquire: gpio2_acquire { + mux { + pins = <127>; + function = "gpio0_a"; + }; + }; + + gpio3_release: gpio3_release { + mux { + pins = <128>; + function = "gpio0_r"; + }; + }; + + gpio5_release: gpio5_release { + mux { + pins = <130>; + function = "gpio0_r"; + }; + }; + + pwr_key: pwr-key { + mux { + pins = <147>; + function = "gpio0_a"; + }; + }; + + restart_key: restart-key { + mux { + pins = <148>; + function = "gpio0_a"; + }; + }; + + dbgi2c_acquire: dbgi2c_acquire { + mux { + groups = "dbgi2c_grp"; + function = "dbgi2c_a"; + }; + }; + + dbgi2c_release: dbgi2c_release{ + mux { + groups = "dbgi2c_grp"; + function = "dbgi2c_r"; + }; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts new file mode 100644 index 0000000000000..94892b74467f8 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts @@ -0,0 +1,57 @@ +#include "mango.dtsi" +#include "mango-pcie-3rc-capricorn.dtsi" + +/ { + info { + file-name = "mango-sophgo-capricorn.dts"; + }; +}; + +ðernet0 { + max-speed = <1000>; + eth-sophgo-config { + autoneg = "enable"; + }; +}; + +&soc { + gpio-poweroff { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_acquire>; + + power { + label = "GPIO Key Power"; + linux,code = ; + gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; +}; + +&port0a { + compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; + + cpld_poweroff: cpld-poweroff { + compatible = "mango,cpld-poweroff"; + gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; + }; + + cpld_reboot: cpld-reboot { + compatible = "mango,cpld-reboot"; + gpios = <&port0a 5 GPIO_ACTIVE_HIGH>; + }; +}; + +/ { + board-info { + /* compatible MUST be sophgo,board-info */ + compatible = "sophgo,board-info"; + /* valid values are: full-function, xmr */ + chip-package = "full-function"; + /* valid values are: x4, x8 */ + ddr-pcb-type = "x4"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts new file mode 100644 index 0000000000000..98761cbf42e8d --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts @@ -0,0 +1,58 @@ +#include "mango-2sockets.dtsi" +#include "mango-top-intc2.dtsi" +#include "mango-pcie-2rc.dtsi" + +/ { + info { + file-name = "mango-sophgo-pisces.dts"; + }; +}; + +ðernet0 { + max-speed = <1000>; + eth-sophgo-config { + autoneg = "enable"; + }; +}; + +&soc { + gpio-poweroff { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_acquire>; + + power { + label = "GPIO Key Power"; + linux,code = ; + gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; +}; + +&port0a { + compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; + + cpld_poweroff: cpld-poweroff { + compatible = "mango,cpld-poweroff"; + gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; + }; + + cpld_reboot: cpld-reboot { + compatible = "mango,cpld-reboot"; + gpios = <&port0a 5 GPIO_ACTIVE_HIGH>; + }; +}; + +/ { + board-info { + /* compatible MUST be sophgo,board-info */ + compatible = "sophgo,board-info"; + /* valid values are: full-function, xmr */ + chip-package = "full-function"; + /* valid values are: x4, x8 */ + ddr-pcb-type = "x4"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts new file mode 100644 index 0000000000000..78495159bbb41 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts @@ -0,0 +1,137 @@ +#include "mango.dtsi" +#include "mango-pcie-3rc-v2.dtsi" + +/ { + info { + file-name = "mango-sophgo-x4evb.dts"; + }; +}; + +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; + + mango_srst: mango-reset@17 { + compatible = "mango,reset"; + reg = <0x17>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_acquire>; +}; + +&tach0 { + pinctrl-names = "default"; + pinctrl-0 = <&fan0_acquire>; +}; + +&tach1 { + pinctrl-names = "default"; + pinctrl-0 = <&fan1_acquire>; +}; + +ðernet0 { + max-speed = <1000>; + eth-sophgo-config { + autoneg = "enable"; + }; +}; + +&soc { + /delete-node/ flash-controller@7000180000; +}; + +/ { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 40000>, <&pwm 1 40000>; // period_ns + pwm-names = "pwm0","pwm1"; + pwm_inuse = "pwm0"; + #cooling-cells = <2>; + cooling-levels = <102 127 178 229 254>; //total 255 + }; + + thermal_zones: thermal-zones { + soc { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 0>; + + trips { + soc_pwmfan_trip1: soc_pwmfan_trip@1 { + temperature = <40000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip2: soc_pwmfan_trip@2 { + temperature = <58000>; /* millicelsius */ + hysteresis = <12000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip3: soc_pwmfan_trip@3 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip4: soc_pwmfan_trip@4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_pwmfan_trip1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_pwmfan_trip2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_pwmfan_trip3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_pwmfan_trip4>; + cooling-device = <&pwmfan 3 4>; + }; + }; + + }; + + board { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 1>; + + trips { + board_pwmfan_trip1: board_pwmfan_trip@1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_pwmfan_trip1>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; + +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts new file mode 100644 index 0000000000000..83e4f1411f2ee --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts @@ -0,0 +1,165 @@ +#include "mango.dtsi" +#include "mango-pcie-3rc.dtsi" + +/ { + info { + file-name = "mango-sophgo-x8evb.dts"; + }; +}; + +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; + reg = <0x17>; + #thermal-sensor-cells = <1>; + }; + + mango_srst: mango-reset@17 { + compatible = "mango,reset"; + reg = <0x17>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_acquire>; +}; + +&soc { + gpio-poweroff { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + label = "GPIO Key Power"; + linux,code = ; + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; + + gpio-restart { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&restart_key>; + + restart { + label = "GPIO Key Restart"; + linux,code = ; + gpios = <&port0a 23 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; +}; + +&tach0 { + pinctrl-names = "default"; + pinctrl-0 = <&fan0_acquire>; +}; + +&tach1 { + pinctrl-names = "default"; + pinctrl-0 = <&fan1_acquire>; +}; + +ðernet0 { + max-speed = <1000>; + eth-sophgo-config { + autoneg = "enable"; + }; +}; + +/ { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm 0 40000>, <&pwm 1 40000>; // period_ns + pwm-names = "pwm0","pwm1"; + pwm_inuse = "pwm0"; + #cooling-cells = <2>; + cooling-levels = <153 128 77 26 1>; //total 255 + }; + + thermal_zones: thermal-zones { + soc { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 0>; + + trips { + soc_pwmfan_trip1: soc_pwmfan_trip@1 { + temperature = <40000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip2: soc_pwmfan_trip@2 { + temperature = <58000>; /* millicelsius */ + hysteresis = <12000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip3: soc_pwmfan_trip@3 { + temperature = <70000>; /* millicelsius */ + hysteresis = <10000>; /* millicelsius */ + type = "active"; + }; + + soc_pwmfan_trip4: soc_pwmfan_trip@4 { + temperature = <85000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_pwmfan_trip1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_pwmfan_trip2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_pwmfan_trip3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_pwmfan_trip4>; + cooling-device = <&pwmfan 3 4>; + }; + }; + + }; + + board { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&mcu 1>; + + trips { + board_pwmfan_trip1: board_pwmfan_trip@1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <8000>; /* millicelsius */ + type = "active"; + }; + }; + + cooling-maps { + map4 { + trip = <&board_pwmfan_trip1>; + cooling-device = <&pwmfan 3 4>; + }; + }; + }; + }; + +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-top-intc2.dtsi b/arch/riscv/boot/dts/sophgo/mango-top-intc2.dtsi new file mode 100644 index 0000000000000..6d364cf6b3c56 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-top-intc2.dtsi @@ -0,0 +1,62 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + intc2: top_intc@f030010300 { + compatible = "sophgo,top-intc"; + reg = <0xf0 0x300102E0 0x0 0x4>, + <0xf0 0x30010300 0x0 0x4>, + <0xf0 0x30010304 0x0 0x4>; + reg-names = "sta", "set", "clr"; + reg-bitwidth = <32>; + top-intc-id = <1>; + interrupt-controller; + #interrupt-cells = <0x1>; // only applies to child node + for-msi; + + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "msi16", "msi17", "msi18", "msi19", + "msi20", "msi21", "msi22", "msi23", + "msi24", "msi25", "msi26", "msi27", + "msi28", "msi29", "msi30", "msi31"; + + }; + +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts b/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts new file mode 100644 index 0000000000000..172421ffc1960 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts @@ -0,0 +1,63 @@ +#include "mango-2sockets.dtsi" +#include "mango-top-intc2.dtsi" +#include "mango-pcie-4rc-v2.dtsi" + +/ { + info { + file-name = "mango-yixin-s2110.dts"; + }; +}; + +ðernet0 { + max-speed = <1000>; + eth-sophgo-config { + autoneg = "enable"; + }; +}; + +&soc { + gpio-poweroff { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_acquire>; + + power { + label = "GPIO Key Power"; + linux,code = ; + gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; + linux,input-type = <1>; + debounce-interval = <100>; + }; + }; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&dbgi2c_release>; +}; + +&port0a { + compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; + + cpld_poweroff: cpld-poweroff { + compatible = "mango,cpld-poweroff"; + gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; + }; + + cpld_reboot: cpld-reboot { + compatible = "mango,cpld-reboot"; + gpios = <&port0a 29 GPIO_ACTIVE_HIGH>; + }; +}; + +/ { + board-info { + /* compatible MUST be sophgo,board-info */ + compatible = "sophgo,board-info"; + /* valid values are: full-function, xmr */ + chip-package = "full-function"; + /* valid values are: x4, x8 */ + ddr-pcb-type = "x8"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango.dtsi b/arch/riscv/boot/dts/sophgo/mango.dtsi new file mode 100644 index 0000000000000..8c1ba532531ca --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango.dtsi @@ -0,0 +1,941 @@ +/dts-v1/; +#include +#include +#include +#include +#include +#include + +#include "mango-cpus-socket0.dtsi" +#include "mango-clock-socket0.dtsi" +#include "mango-pinctrl.dtsi" + +#define SOC_PERIPHERAL_IRQ(nr) (nr) + +/ { + model = "Sophgo Mango"; + compatible = "sophgo,mango"; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + distance-map { + compatible = "numa-distance-map-v1"; + distance-matrix = <0 0 10>, + <0 1 15>, + <0 2 25>, + <0 3 30>, + <1 0 15>, + <1 1 10>, + <1 2 30>, + <1 3 25>, + <2 0 25>, + <2 1 30>, + <2 2 10>, + <2 3 15>, + <3 0 30>, + <3 1 25>, + <3 2 15>, + <3 3 10>; + }; + + pmu { + compatible = "riscv,pmu"; + riscv,event-to-mhpmevent = + <0x00003 0x00000000 0x00000010>, + <0x00004 0x00000000 0x00000011>, + <0x00005 0x00000000 0x00000007>, + <0x00006 0x00000000 0x00000006>, + <0x00008 0x00000000 0x00000027>, + <0x00009 0x00000000 0x00000028>, + <0x10000 0x00000000 0x0000000c>, + <0x10001 0x00000000 0x0000000d>, + <0x10002 0x00000000 0x0000000e>, + <0x10003 0x00000000 0x0000000f>, + <0x10008 0x00000000 0x00000001>, + <0x10009 0x00000000 0x00000002>, + <0x10010 0x00000000 0x00000010>, + <0x10011 0x00000000 0x00000011>, + <0x10012 0x00000000 0x00000012>, + <0x10013 0x00000000 0x00000013>, + <0x10019 0x00000000 0x00000004>, + <0x10021 0x00000000 0x00000003>, + <0x10030 0x00000000 0x0000001c>, + <0x10031 0x00000000 0x0000001b>; + riscv,event-to-mhpmcounters = + <0x00003 0x00003 0xfffffff8>, + <0x00004 0x00004 0xfffffff8>, + <0x00005 0x00005 0xfffffff8>, + <0x00006 0x00006 0xfffffff8>, + <0x00007 0x00007 0xfffffff8>, + <0x00008 0x00008 0xfffffff8>, + <0x00009 0x00009 0xfffffff8>, + <0x0000a 0x0000a 0xfffffff8>, + <0x10000 0x10000 0xfffffff8>, + <0x10001 0x10001 0xfffffff8>, + <0x10002 0x10002 0xfffffff8>, + <0x10003 0x10003 0xfffffff8>, + <0x10008 0x10008 0xfffffff8>, + <0x10009 0x10009 0xfffffff8>, + <0x10010 0x10010 0xfffffff8>, + <0x10011 0x10011 0xfffffff8>, + <0x10012 0x10012 0xfffffff8>, + <0x10013 0x10013 0xfffffff8>, + <0x10019 0x10019 0xfffffff8>, + <0x10021 0x10021 0xfffffff8>, + <0x10030 0x10030 0xfffffff8>, + <0x10031 0x10031 0xfffffff8>; + riscv,raw-event-to-mhpmcounters = + <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>, + <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x1f 0x0>; + + clint_mswi: clint-mswi@7094000000 { + compatible = "thead,c900-clint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = < + &cpu0_intc 3 + &cpu1_intc 3 + &cpu2_intc 3 + &cpu3_intc 3 + &cpu4_intc 3 + &cpu5_intc 3 + &cpu6_intc 3 + &cpu7_intc 3 + &cpu8_intc 3 + &cpu9_intc 3 + &cpu10_intc 3 + &cpu11_intc 3 + &cpu12_intc 3 + &cpu13_intc 3 + &cpu14_intc 3 + &cpu15_intc 3 + &cpu16_intc 3 + &cpu17_intc 3 + &cpu18_intc 3 + &cpu19_intc 3 + &cpu20_intc 3 + &cpu21_intc 3 + &cpu22_intc 3 + &cpu23_intc 3 + &cpu24_intc 3 + &cpu25_intc 3 + &cpu26_intc 3 + &cpu27_intc 3 + &cpu28_intc 3 + &cpu29_intc 3 + &cpu30_intc 3 + &cpu31_intc 3 + &cpu32_intc 3 + &cpu33_intc 3 + &cpu34_intc 3 + &cpu35_intc 3 + &cpu36_intc 3 + &cpu37_intc 3 + &cpu38_intc 3 + &cpu39_intc 3 + &cpu40_intc 3 + &cpu41_intc 3 + &cpu42_intc 3 + &cpu43_intc 3 + &cpu44_intc 3 + &cpu45_intc 3 + &cpu46_intc 3 + &cpu47_intc 3 + &cpu48_intc 3 + &cpu49_intc 3 + &cpu50_intc 3 + &cpu51_intc 3 + &cpu52_intc 3 + &cpu53_intc 3 + &cpu54_intc 3 + &cpu55_intc 3 + &cpu56_intc 3 + &cpu57_intc 3 + &cpu58_intc 3 + &cpu59_intc 3 + &cpu60_intc 3 + &cpu61_intc 3 + &cpu62_intc 3 + &cpu63_intc 3 + >; + }; + + clint_mtimer0: clint-mtimer@70ac000000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu0_intc 7 + &cpu1_intc 7 + &cpu2_intc 7 + &cpu3_intc 7 + >; + }; + + clint_mtimer1: clint-mtimer@70ac010000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu4_intc 7 + &cpu5_intc 7 + &cpu6_intc 7 + &cpu7_intc 7 + >; + }; + + clint_mtimer2: clint-mtimer@70ac020000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu8_intc 7 + &cpu9_intc 7 + &cpu10_intc 7 + &cpu11_intc 7 + >; + }; + + clint_mtimer3: clint-mtimer@70ac030000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu12_intc 7 + &cpu13_intc 7 + &cpu14_intc 7 + &cpu15_intc 7 + >; + }; + + clint_mtimer4: clint-mtimer@70ac040000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu16_intc 7 + &cpu17_intc 7 + &cpu18_intc 7 + &cpu19_intc 7 + >; + }; + + clint_mtimer5: clint-mtimer@70ac050000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu20_intc 7 + &cpu21_intc 7 + &cpu22_intc 7 + &cpu23_intc 7 + >; + }; + + clint_mtimer6: clint-mtimer@70ac060000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu24_intc 7 + &cpu25_intc 7 + &cpu26_intc 7 + &cpu27_intc 7 + >; + }; + + clint_mtimer7: clint-mtimer@70ac070000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu28_intc 7 + &cpu29_intc 7 + &cpu30_intc 7 + &cpu31_intc 7 + >; + }; + + clint_mtimer8: clint-mtimer@70ac080000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu32_intc 7 + &cpu33_intc 7 + &cpu34_intc 7 + &cpu35_intc 7 + >; + }; + + clint_mtimer9: clint-mtimer@70ac090000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu36_intc 7 + &cpu37_intc 7 + &cpu38_intc 7 + &cpu39_intc 7 + >; + }; + + clint_mtimer10: clint-mtimer@70ac0a0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu40_intc 7 + &cpu41_intc 7 + &cpu42_intc 7 + &cpu43_intc 7 + >; + }; + + clint_mtimer11: clint-mtimer@70ac0b0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu44_intc 7 + &cpu45_intc 7 + &cpu46_intc 7 + &cpu47_intc 7 + >; + }; + + clint_mtimer12: clint-mtimer@70ac0c0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu48_intc 7 + &cpu49_intc 7 + &cpu50_intc 7 + &cpu51_intc 7 + >; + }; + + clint_mtimer13: clint-mtimer@70ac0d0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu52_intc 7 + &cpu53_intc 7 + &cpu54_intc 7 + &cpu55_intc 7 + >; + }; + + clint_mtimer14: clint-mtimer@70ac0e0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu56_intc 7 + &cpu57_intc 7 + &cpu58_intc 7 + &cpu59_intc 7 + >; + }; + + clint_mtimer15: clint-mtimer@70ac0f0000 { + compatible = "thead,c900-clint-mtimer"; + reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; + interrupts-extended = < + &cpu60_intc 7 + &cpu61_intc 7 + &cpu62_intc 7 + &cpu63_intc 7 + >; + }; + + intc: interrupt-controller@7090000000 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "thead,c900-plic"; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 11 &cpu0_intc 9 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9 + &cpu5_intc 11 &cpu5_intc 9 + &cpu6_intc 11 &cpu6_intc 9 + &cpu7_intc 11 &cpu7_intc 9 + &cpu8_intc 11 &cpu8_intc 9 + &cpu9_intc 11 &cpu9_intc 9 + &cpu10_intc 11 &cpu10_intc 9 + &cpu11_intc 11 &cpu11_intc 9 + &cpu12_intc 11 &cpu12_intc 9 + &cpu13_intc 11 &cpu13_intc 9 + &cpu14_intc 11 &cpu14_intc 9 + &cpu15_intc 11 &cpu15_intc 9 + &cpu16_intc 11 &cpu16_intc 9 + &cpu17_intc 11 &cpu17_intc 9 + &cpu18_intc 11 &cpu18_intc 9 + &cpu19_intc 11 &cpu19_intc 9 + &cpu20_intc 11 &cpu20_intc 9 + &cpu21_intc 11 &cpu21_intc 9 + &cpu22_intc 11 &cpu22_intc 9 + &cpu23_intc 11 &cpu23_intc 9 + &cpu24_intc 11 &cpu24_intc 9 + &cpu25_intc 11 &cpu25_intc 9 + &cpu26_intc 11 &cpu26_intc 9 + &cpu27_intc 11 &cpu27_intc 9 + &cpu28_intc 11 &cpu28_intc 9 + &cpu29_intc 11 &cpu29_intc 9 + &cpu30_intc 11 &cpu30_intc 9 + &cpu31_intc 11 &cpu31_intc 9 + &cpu32_intc 11 &cpu32_intc 9 + &cpu33_intc 11 &cpu33_intc 9 + &cpu34_intc 11 &cpu34_intc 9 + &cpu35_intc 11 &cpu35_intc 9 + &cpu36_intc 11 &cpu36_intc 9 + &cpu37_intc 11 &cpu37_intc 9 + &cpu38_intc 11 &cpu38_intc 9 + &cpu39_intc 11 &cpu39_intc 9 + &cpu40_intc 11 &cpu40_intc 9 + &cpu41_intc 11 &cpu41_intc 9 + &cpu42_intc 11 &cpu42_intc 9 + &cpu43_intc 11 &cpu43_intc 9 + &cpu44_intc 11 &cpu44_intc 9 + &cpu45_intc 11 &cpu45_intc 9 + &cpu46_intc 11 &cpu46_intc 9 + &cpu47_intc 11 &cpu47_intc 9 + &cpu48_intc 11 &cpu48_intc 9 + &cpu49_intc 11 &cpu49_intc 9 + &cpu50_intc 11 &cpu50_intc 9 + &cpu51_intc 11 &cpu51_intc 9 + &cpu52_intc 11 &cpu52_intc 9 + &cpu53_intc 11 &cpu53_intc 9 + &cpu54_intc 11 &cpu54_intc 9 + &cpu55_intc 11 &cpu55_intc 9 + &cpu56_intc 11 &cpu56_intc 9 + &cpu57_intc 11 &cpu57_intc 9 + &cpu58_intc 11 &cpu58_intc 9 + &cpu59_intc 11 &cpu59_intc 9 + &cpu60_intc 11 &cpu60_intc 9 + &cpu61_intc 11 &cpu61_intc 9 + &cpu62_intc 11 &cpu62_intc 9 + &cpu63_intc 11 &cpu63_intc 9 + >; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <224>; + }; + + timer0: dw-apb-timer0@7030003000 { + compatible = "snps,dw-apb-timer"; + interrupt-parent = <&intc>; + interrupts = ; + reg = <0x70 0x30003000 0x0 0x14>; + clocks = <&div_clk GATE_CLK_TIMER1>, + <&div_clk GATE_CLK_APB_TIMER>; + clock-names = "timer", "pclk"; + clk-drv-rating = <300>; + }; + + timer1: dw-apb-timer1@7030003014 { + compatible = "snps,dw-apb-timer"; + interrupt-parent = <&intc>; + interrupts = ; + reg = <0x70 0x30003014 0x0 0x10>; + clocks = <&div_clk GATE_CLK_TIMER2>, + <&div_clk GATE_CLK_APB_TIMER>; + clock-names = "timer", "pclk"; + clk-drv-rating = <300>; + }; + + top_misc: top_misc_ctrl@7030010000 { + compatible = "syscon"; + reg = <0x70 0x30010000 0x0 0x8000>; + }; + + rst: reset-controller { + #reset-cells = <1>; + compatible = "bitmain,reset"; + subctrl-syscon = <&top_misc>; + top_rst_offset = <0x3000>; + nr_resets = ; + }; + + i2c0: i2c@7030005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + clocks = <&div_clk GATE_CLK_APB_I2C>; + clock-names = "clk_gate_apb_i2c"; + reg = <0x70 0x30005000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000>; + resets = <&rst RST_I2C0>; + reset-names = "i2c0"; + }; + + i2c1: i2c@7030006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + clocks = <&div_clk GATE_CLK_APB_I2C>; + clock-names = "clk_gate_apb_i2c"; + reg = <0x70 0x30006000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000>; + resets = <&rst RST_I2C1>; + reset-names = "i2c1"; + }; + + i2c2: i2c@7030007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + clocks = <&div_clk GATE_CLK_APB_I2C>; + clock-names = "clk_gate_apb_i2c"; + reg = <0x70 0x30007000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000>; + resets = <&rst RST_I2C2>; + reset-names = "i2c2"; + }; + + i2c3: i2c@7030008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + clocks = <&div_clk GATE_CLK_APB_I2C>; + clock-names = "clk_gate_apb_i2c"; + reg = <0x70 0x30008000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000>; + resets = <&rst RST_I2C3>; + reset-names = "i2c3"; + }; + + gpio0: gpio@7030009000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x30009000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, + <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; + clock-names = "base_clk", "intr_clk", "db_clk"; + + port0a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "port0a"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = ; + }; + }; + + gpio1: gpio@703000a000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x3000a000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, + <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; + clock-names = "base_clk", "intr_clk", "db_clk"; + + port1a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "port0a"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = ; + }; + }; + + gpio2: gpio@703000b000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x70 0x3000b000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, + <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; + clock-names = "base_clk", "intr_clk", "db_clk"; + + port2a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + bank-name = "port0a"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = ; + }; + }; + + pwm: pwm@703000C000 { + compatible = "sophgo,sophgo-pwm"; + reg = <0x70 0x3000C000 0x0 0x20>; + clocks = <&div_clk GATE_CLK_APB_PWM>; + clock-names = "clk_gate_apb_pwm"; + #pwm-cells = <2>; + pwm-num = <2>; + no-polarity; + }; + + tach0: tach@703000C020 { + compatible = "sophgo,sophgo-tach"; + reg = <0x70 0x3000C020 0x0 0x8>; + }; + + tach1: tach@703000C028 { + compatible = "sophgo,sophgo-tach"; + reg = <0x70 0x3000C028 0x0 0x8>; + }; + + uart0: serial@7040000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&div_clk GATE_CLK_UART_500M>, + <&div_clk GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: serial@7040001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40001000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&div_clk GATE_CLK_UART_500M>, + <&div_clk GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart2: serial@7040002000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40002000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&div_clk GATE_CLK_UART_500M>, + <&div_clk GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart3: serial@7040003000 { + compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40003000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <500000000>; + clocks = <&div_clk GATE_CLK_UART_500M>, + <&div_clk GATE_CLK_APB_UART>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + }; + + emmc: bm-emmc@704002A000 { + compatible = "bitmain,bm-emmc"; + reg = <0x70 0x4002A000 0x0 0x1000>; + reg-names = "core_mem"; + interrupt-parent = <&intc>; + interrupts = ; + bus-width = <4>; + non-removable; + no-sdio; + no-sd; + resets = <&rst RST_EMMC>; + reset-names = "emmc"; + clocks = + <&div_clk GATE_CLK_EMMC_100M>, + <&div_clk GATE_CLK_AXI_EMMC>, + <&div_clk GATE_CLK_100K_EMMC>; + clock-names = + "clk_gate_emmc", + "clk_gate_axi_emmc", + "clk_gate_100k_emmc"; + }; + + sd: bm-sd@704002B000 { + compatible = "bitmain,bm-sd"; + reg = <0x70 0x4002B000 0x0 0x1000>; + reg-names = "core_mem"; + interrupt-parent = <&intc>; + interrupts = ; + bus-width = <4>; + no-sdio; + no-mmc; + resets = <&rst RST_SD>; + reset-names = "sdio"; + clocks = + <&div_clk GATE_CLK_SD_100M>, + <&div_clk GATE_CLK_AXI_SD>, + <&div_clk GATE_CLK_100K_SD>; + clock-names = + "clk_gate_sd", + "clk_gate_axi_sd", + "clk_gate_100k_sd"; + }; + + spifmc0: flash-controller@7000180000 { + compatible = "sophgo,spifmc"; + reg = <0x70 0x00180000 0x0 0x1000000>; + reg-names = "memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000000>; + clocks = <&div_clk GATE_CLK_AHB_SF>; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + }; + + spifmc1: flash-controller@7002180000 { + compatible = "sophgo,spifmc"; + reg = <0x70 0x02180000 0x0 0x1000000>; + reg-names = "memory"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&intc>; + interrupts = ; + clock-frequency = <100000000>; + clocks = <&div_clk GATE_CLK_AHB_SF>; + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + }; + }; + + spi0: spi@7040004000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70 0x40004000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&div_clk GATE_CLK_APB_SPI>, + <&div_clk GATE_CLK_SYSDMA_AXI>; + clock-frequency = <250000000>; + resets = <&rst RST_SPI0>; + reset-names = "spi0"; + num-cs = <2>; + status = "okay"; + }; + + spi1: spi@7040005000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70 0x40005000 0x0 0x1000>; + interrupt-parent = <&intc>; + interrupts = ; + clocks = <&div_clk GATE_CLK_APB_SPI>, + <&div_clk GATE_CLK_SYSDMA_AXI>; + clock-frequency = <250000000>; + resets = <&rst RST_SPI1>; + reset-names = "spi1"; + num-cs = <2>; + status = "okay"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + snps,blen = <4 8 16 0 0 0 0>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + ethernet0: ethernet@7040026000 { + compatible = "bitmain,ethernet"; + reg = <0x70 0x40026000 0x0 0x4000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "clk_tx", "gate_clk_tx", "stmmaceth", "ptp_ref", "gate_clk_ref"; + clocks = <&div_clk DIV_CLK_FPLL_TX_ETH0>, + <&div_clk GATE_CLK_TX_ETH0>, + <&div_clk GATE_CLK_AXI_ETH0>, + <&div_clk GATE_CLK_PTP_REF_I_ETH0>, + <&div_clk GATE_CLK_REF_ETH0>; + + /* no hash filter and perfect filter support */ + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,aal; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + phy-mode = "rgmii-txid"; + phy-reset-gpios = <&port0a 27 0>; + phy-handle = <&phy0>; + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + compatible = "snps,dwmac-mdio"; + phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + device_type = "ethernet-phy"; + reg = <0x0>; + }; + }; + }; + }; + + intc1: top_intc@7030010300 { + compatible = "sophgo,top-intc"; + reg = <0x70 0x300102E0 0x0 0x4>, + <0x70 0x30010300 0x0 0x4>, + <0x70 0x30010304 0x0 0x4>; + reg-names = "sta", "set", "clr"; + reg-bitwidth = <32>; + top_intc_id = <0>; + interrupt-controller; + #interrupt-cells = <0x1>; // only applies to child node + for-msi; + + interrupt-parent = <&intc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", + "msi12", "msi13", "msi14", "msi15", + "msi16", "msi17", "msi18", "msi19", + "msi20", "msi21", "msi22", "msi23", + "msi24", "msi25", "msi26", "msi27", + "msi28", "msi29", "msi30", "msi31"; + + }; + + aliases { + serial0 = &uart0; + }; + + chosen: chosen { + bootargs = "console=ttyS0,115200 earlycon maxcpus=1"; + stdout-path = "serial0"; + }; +}; From 7b48c3df12299fe790fc44d6319e1825d63cee1d Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Mon, 22 Jan 2024 10:31:30 +0800 Subject: [PATCH 02/40] riscv: errata: Replace thead cache clean with flush Signed-off-by: Xiaoguang Xing --- arch/riscv/include/asm/errata_list.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index d3f3c237adad7..d8a2d56279ec6 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -128,7 +128,7 @@ asm volatile(ALTERNATIVE( \ * 0000000 11001 00000 000 00000 0001011 */ #define THEAD_inval_A0 ".long 0x0265000b" -#define THEAD_clean_A0 ".long 0x0255000b" +#define THEAD_clean_A0 ".long 0x0275000b" #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" From 27e63d8223f30484da2363e579f26b0bd68877b5 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 4 Jan 2023 15:41:44 +0800 Subject: [PATCH 03/40] riscv: errata: cmo: add CMO macro variant with both VA and PA The standardized Zicbom extension supports only VA, however there's some vendor extensions (e.g. XtheadCmo) that can handle cache management operations on PA directly, bypassing the TLB lookup. Add a CMO alternatives macro variant that come with both VA and PA supplied, and the code can be patched to use either the VA or the PA at runtime. In this case the codepath is now patched to use VA for Zicbom and PA for XtheadCmo. Signed-off-by: Icenowy Zheng Reviewed-by: Guo Ren --- arch/riscv/include/asm/errata_list.h | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index d8a2d56279ec6..a29b67dd3c564 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -131,6 +131,9 @@ asm volatile(ALTERNATIVE( \ #define THEAD_clean_A0 ".long 0x0275000b" #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" +#define THEAD_inval_PA_A0 ".long 0x02a5000b" +#define THEAD_clean_PA_A0 ".long 0x0295000b" +#define THEAD_flush_PA_A0 ".long 0x02b5000b" #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ asm volatile(ALTERNATIVE_2( \ @@ -157,6 +160,33 @@ asm volatile(ALTERNATIVE_2( \ "r"((unsigned long)(_start) + (_size)) \ : "a0") +#define ALT_CMO_OP_VPA(_op, _vaddr, _paddr, _size, _cachesize) \ +asm volatile(ALTERNATIVE_2( \ + __nops(6), \ + "mv a0, %1\n\t" \ + "j 2f\n\t" \ + "3:\n\t" \ + "cbo." __stringify(_op) " (a0)\n\t" \ + "add a0, a0, %0\n\t" \ + "2:\n\t" \ + "bltu a0, %2, 3b\n\t" \ + "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "mv a0, %3\n\t" \ + "j 2f\n\t" \ + "3:\n\t" \ + THEAD_##_op##_PA_A0 "\n\t" \ + "add a0, a0, %0\n\t" \ + "2:\n\t" \ + "bltu a0, %4, 3b\n\t" \ + THEAD_SYNC_S, THEAD_VENDOR_ID, \ + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ + : : "r"(_cachesize), \ + "r"((unsigned long)(_vaddr) & ~((_cachesize) - 1UL)), \ + "r"((unsigned long)(_vaddr) + (_size)), \ + "r"((unsigned long)(_paddr) & ~((_cachesize) - 1UL)), \ + "r"((unsigned long)(_paddr) + (_size)) \ + : "a0") + #define THEAD_C9XX_RV_IRQ_PMU 17 #define THEAD_C9XX_CSR_SCOUNTEROF 0x5c5 From ac02e2f7af7399d810a004998d755b7682a271de Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 4 Jan 2023 15:41:45 +0800 Subject: [PATCH 04/40] riscv: use VA+PA variant of CMO macros for DMA synchorization DMA synchorization is done on PA and the VA is calculated from the PA. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren Signed-off-by: Icenowy Zheng Reviewed-by: Guo Ren --- arch/riscv/mm/dma-noncoherent.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index 341bd6706b4c5..22de7f222637f 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -25,7 +25,7 @@ static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) return; } #endif - ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP_VPA(clean, vaddr, paddr, size, riscv_cbom_block_size); } static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) @@ -39,7 +39,7 @@ static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) } #endif - ALT_CMO_OP(inval, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP_VPA(inval, vaddr, paddr, size, riscv_cbom_block_size); } static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) @@ -53,7 +53,7 @@ static inline void arch_dma_cache_wback_inv(phys_addr_t paddr, size_t size) } #endif - ALT_CMO_OP(flush, vaddr, size, riscv_cbom_block_size); + ALT_CMO_OP_VPA(flush, vaddr, paddr, size, riscv_cbom_block_size); } static inline bool arch_sync_dma_clean_before_fromdevice(void) From a635dc847123cce01be72e7b37dd2e04fa68cd50 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Wed, 4 Jan 2023 15:41:46 +0800 Subject: [PATCH 05/40] riscv: use VA+PA variant of CMO macros for DMA page preparation When doing DMA page preparation, both the VA and the PA are easily accessible from struct page. Use the alternative macro variant that takes both VA and PA as parameters, thus in case the ISA extension used support PA directly, the overhead for re-converting VA to PA can be omitted. Suggested-by: Guo Ren Signed-off-by: Icenowy Zheng --- arch/riscv/mm/dma-noncoherent.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c index 22de7f222637f..8932a93ec50cd 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -117,6 +117,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, void arch_dma_prep_coherent(struct page *page, size_t size) { void *flush_addr = page_address(page); + phys_addr_t paddr = PFN_PHYS(page_to_pfn(page)); #ifdef CONFIG_RISCV_NONSTANDARD_CACHE_OPS if (unlikely(noncoherent_cache_ops.wback_inv)) { @@ -125,7 +126,7 @@ void arch_dma_prep_coherent(struct page *page, size_t size) } #endif - ALT_CMO_OP(flush, flush_addr, size, riscv_cbom_block_size); + ALT_CMO_OP_VPA(flush, flush_addr, paddr, size, riscv_cbom_block_size); } void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, From b62c4ef905302282fddea045181d497f1ce6b7a0 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Thu, 19 Oct 2023 17:55:11 +0800 Subject: [PATCH 06/40] riscv: errata: thead: Make cache clean to flush Signed-off-by: Xiaoguang Xing --- arch/riscv/include/asm/errata_list.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index a29b67dd3c564..d415c50f22e84 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -132,7 +132,7 @@ asm volatile(ALTERNATIVE( \ #define THEAD_flush_A0 ".long 0x0275000b" #define THEAD_SYNC_S ".long 0x0190000b" #define THEAD_inval_PA_A0 ".long 0x02a5000b" -#define THEAD_clean_PA_A0 ".long 0x0295000b" +#define THEAD_clean_PA_A0 ".long 0x02b5000b" #define THEAD_flush_PA_A0 ".long 0x02b5000b" #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ From 5286ea8366d14a2a1c1362dde013da110b563308 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 24 Feb 2023 17:22:38 +0800 Subject: [PATCH 07/40] riscv: changing T-Head PBMT attributes Originall the T-Head PBMT implementation in the kernel is intended for D1, thus the Sharable bit is not set. In addition, the Bufferable bit is not set for writecombine situation. Set these bits in the T-Head PBMT attributes definition. Signed-off-by: Icenowy Zheng --- arch/riscv/include/asm/pgtable-64.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 7a5097202e157..96b09048c68aa 100644 --- a/arch/riscv/include/asm/pgtable-64.h +++ b/arch/riscv/include/asm/pgtable-64.h @@ -127,13 +127,13 @@ enum napot_cont_order { /* * [63:59] T-Head Memory Type definitions: * - * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable + * 00010 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable - * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable + * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable */ #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60)) -#define _PAGE_NOCACHE_THEAD 0UL -#define _PAGE_IO_THEAD (1UL << 63) +#define _PAGE_NOCACHE_THEAD ((1UL << 61) | (1UL << 60)) +#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60)) #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) static inline u64 riscv_page_mtmask(void) From 28e0bb337c3efec4b07751cc59ffcddf3a98add1 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Mon, 29 Jan 2024 16:00:34 +0800 Subject: [PATCH 08/40] riscv: add ioremap_wc for gpu Signed-off-by: Xiaoguang Xing --- arch/riscv/include/asm/io.h | 4 ++++ arch/riscv/include/asm/pgtable.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 42497d487a174..bbdc3c7ed6cad 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -140,4 +140,8 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) #endif +#undef ioremap_wc +#define ioremap_wc(addr, size) \ + ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) + #endif /* _ASM_RISCV_IO_H */ diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index 719c3041ae1c2..9ebb064892356 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -205,7 +205,8 @@ extern struct pt_alloc_ops pt_ops __initdata; #define PAGE_TABLE __pgprot(_PAGE_TABLE) -#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) +#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) +#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) extern pgd_t swapper_pg_dir[]; From 3628e0896a7d7f87ce77466fdcaebae366377420 Mon Sep 17 00:00:00 2001 From: "xiaoguang.xing" Date: Thu, 25 May 2023 18:38:27 +0800 Subject: [PATCH 09/40] riscv: add smp_cond_load_acquire() Fix qspinlock issue that loops to call cpu_relax and not exit. The call trace is: queued_spin_lock_slowpath->arch_mcs_spin_lock_contended ->smp_cond_load_acquire. RISCV has not defined smp_cond_load_acquire, so it uses generic funtion that defined in include/asm-generic/barrier.h. The generic smp_cond_load_acquire calls smp_cond_load_relaxed that loops to call READ_ONCE and cpu_relax. The READ_ONCE need barrier after it to get the new value. --- arch/riscv/include/asm/barrier.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 110752594228e..2dc4083cbc88d 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -44,6 +44,18 @@ do { \ ___p1; \ }) +#define smp_cond_load_acquire(ptr, cond_expr) ({ \ + typeof(ptr) __PTR = (ptr); \ + __unqual_scalar_typeof(*ptr) VAL; \ + for (;;) { \ + VAL = __smp_load_acquire(__PTR); \ + if (cond_expr) \ + break; \ + cpu_relax(); \ + } \ + (typeof(*ptr))VAL; \ +}) + /* * This is a very specific barrier: it's currently only used in two places in * the kernel, both in the scheduler. See include/linux/spinlock.h for the two From a22e0ed95fde1e8ef287dcad86d94e991e2ba33e Mon Sep 17 00:00:00 2001 From: "haijiao.liu" Date: Sat, 21 Oct 2023 18:45:33 +0800 Subject: [PATCH 10/40] riscv: spinlock: Fix deadlock issue Fix T-Head C9xx store merge buffer delay problem Signed-off-by: haijiao.liu --- arch/riscv/include/asm/barrier.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h index 2dc4083cbc88d..2b1f98b7e9bf3 100644 --- a/arch/riscv/include/asm/barrier.h +++ b/arch/riscv/include/asm/barrier.h @@ -29,12 +29,22 @@ #define __smp_rmb() RISCV_FENCE(r,r) #define __smp_wmb() RISCV_FENCE(w,w) +#ifdef CONFIG_ARCH_SOPHGO #define __smp_store_release(p, v) \ do { \ compiletime_assert_atomic_type(*p); \ RISCV_FENCE(rw,w); \ WRITE_ONCE(*p, v); \ + RISCV_FENCE(w,rw); \ } while (0) +#else +#define __smp_store_release(p, v) \ +do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ +} while (0) +#endif #define __smp_load_acquire(p) \ ({ \ From 8638ab15cccd4184811694bcceffe89565680911 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 10:31:03 +0800 Subject: [PATCH 11/40] driver: clk: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/clk/Makefile | 1 + drivers/clk/sophgo/Makefile | 3 + drivers/clk/sophgo/clk-dummy.c | 600 +++++++++++ drivers/clk/sophgo/clk-mango.c | 977 ++++++++++++++++++ drivers/clk/sophgo/clk.c | 883 ++++++++++++++++ drivers/clk/sophgo/clk.h | 152 +++ .../dt-bindings/clock/sophgo-mango-clock.h | 165 +++ include/dt-bindings/clock/sophgo.h | 15 + 8 files changed, 2796 insertions(+) create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-dummy.c create mode 100644 drivers/clk/sophgo/clk-mango.c create mode 100644 drivers/clk/sophgo/clk.c create mode 100644 drivers/clk/sophgo/clk.h create mode 100644 include/dt-bindings/clock/sophgo-mango-clock.h create mode 100644 include/dt-bindings/clock/sophgo.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 18969cbd4bb1e..9ba81342d0119 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -124,6 +124,7 @@ obj-$(CONFIG_ARCH_STM32) += stm32/ obj-y += starfive/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-y += sunxi-ng/ +obj-$(CONFIG_ARCH_SOPHGO) += sophgo/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ diff --git a/drivers/clk/sophgo/Makefile b/drivers/clk/sophgo/Makefile new file mode 100644 index 0000000000000..55997fc07b5b7 --- /dev/null +++ b/drivers/clk/sophgo/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_SOPHGO) += clk-dummy.o +obj-$(CONFIG_ARCH_SOPHGO) += clk.o +obj-$(CONFIG_ARCH_SOPHGO) += clk-mango.o diff --git a/drivers/clk/sophgo/clk-dummy.c b/drivers/clk/sophgo/clk-dummy.c new file mode 100644 index 0000000000000..99af0e6dae6ad --- /dev/null +++ b/drivers/clk/sophgo/clk-dummy.c @@ -0,0 +1,600 @@ +/* + * Copyright (c) 2022 SOPHGO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/* + * @hw: handle between common and hardware-specific interfaces + * @reg: register containing divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @initial_val:initial value of the divider + * @table: the div table that the divider supports + * @lock: register lock + */ +struct mango_clk_divider { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + u32 initial_val; + const struct clk_div_table *table; + spinlock_t *lock; +}; + +static unsigned long mango_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct device_node *node; + struct of_phandle_args clkspec; + int rc, index = 0; + u32 rate; + struct property *prop; + const __be32 *cur; + struct clk *clk; + + node = of_find_node_by_name(NULL, "default_rates"); + + of_property_for_each_u32 (node, "clock-rates", prop, cur, rate) { + if (rate) { + rc = of_parse_phandle_with_args(node, "clocks", + "#clock-cells", index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return rc; + } + + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) + return PTR_ERR(clk); + if (!strcmp(clk_hw_get_name(hw), __clk_get_name(clk))) + return rate; + } + index++; + } + return 0; +} + +static long mango_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return rate; +} + +static int mango_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +/* + * @hw: ccf use to hook get mango_pll_clock + * @parent_rate: parent rate + * + * The is function will be called through clk_get_rate + * and return current rate after decoding reg value + */ +static unsigned long mango_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct device_node *node; + struct of_phandle_args clkspec; + int rc, index = 0; + u32 rate; + struct property *prop; + const __be32 *cur; + + node = of_find_node_by_name(NULL, "default_rates"); + + of_property_for_each_u32 (node, "clock-rates", prop, cur, rate) { + if (rate) { + rc = of_parse_phandle_with_args(node, "clocks", + "#clock-cells", index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return rc; + } + + if (!strncmp(clk_hw_get_name(hw), clkspec.np->name, 4)) + return rate; + } + index++; + } + return 0; +} + +static long mango_clk_pll_round_rate(struct clk_hw *hw, + unsigned long req_rate, unsigned long *prate) +{ + return req_rate; +} + +static int mango_clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + req->rate = mango_clk_pll_round_rate(hw, min(req->rate, req->max_rate), + &req->best_parent_rate); + return 0; +} + +static int mango_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +const struct clk_ops dm_mango_clk_divider_ops = { + .recalc_rate = mango_clk_divider_recalc_rate, + .round_rate = mango_clk_divider_round_rate, + .set_rate = mango_clk_divider_set_rate, +}; + +const struct clk_ops dm_mango_clk_divider_ro_ops = { + .recalc_rate = mango_clk_divider_recalc_rate, + .round_rate = mango_clk_divider_round_rate, +}; + +const struct clk_ops dm_mango_clk_pll_ops = { + .recalc_rate = mango_clk_pll_recalc_rate, + .round_rate = mango_clk_pll_round_rate, + .determine_rate = mango_clk_pll_determine_rate, + .set_rate = mango_clk_pll_set_rate, +}; + +const struct clk_ops dm_mango_clk_pll_ro_ops = { + .recalc_rate = mango_clk_pll_recalc_rate, + .round_rate = mango_clk_pll_round_rate, +}; + +struct mux_cb_clk_name { + const char *name; + struct list_head node; +}; + +static struct list_head mux_cb_clk_name_list = + LIST_HEAD_INIT(mux_cb_clk_name_list); +static int mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + int ret = 0; + static unsigned char mux_id = 1; + struct clk_notifier_data *ndata = data; + struct clk_hw *hw = __clk_get_hw(ndata->clk); + const struct clk_ops *ops = &clk_mux_ops; + struct mux_cb_clk_name *cb_lsit; + + if (event == PRE_RATE_CHANGE) { + struct clk_hw *hw_p = clk_hw_get_parent(hw); + + cb_lsit = kmalloc(sizeof(*cb_lsit), GFP_KERNEL); + if (cb_lsit) { + INIT_LIST_HEAD(&cb_lsit->node); + list_add_tail(&cb_lsit->node, &mux_cb_clk_name_list); + } else { + pr_err("mux cb kmalloc mem fail\n"); + goto out; + } + + cb_lsit->name = clk_hw_get_name(hw_p); + mux_id = ops->get_parent(hw); + if (mux_id > 1) { + ret = 1; + goto out; + } + ops->set_parent(hw, !mux_id); + } else if (event == POST_RATE_CHANGE) { + struct clk_hw *hw_p = clk_hw_get_parent(hw); + + cb_lsit = list_first_entry_or_null(&mux_cb_clk_name_list, + typeof(*cb_lsit), node); + if (cb_lsit) { + const char *pre_name = cb_lsit->name; + + list_del_init(&cb_lsit->node); + kfree(cb_lsit); + if (strcmp(clk_hw_get_name(hw_p), pre_name)) + goto out; + } + + ops->set_parent(hw, mux_id); + } + +out: + return notifier_from_errno(ret); +} + +int dm_set_default_clk_rates(struct device_node *node) +{ + struct of_phandle_args clkspec; + struct property *prop; + const __be32 *cur; + int rc, index = 0; + struct clk *clk; + u32 rate; + + of_property_for_each_u32 (node, "clock-rates", prop, cur, rate) { + if (rate) { + rc = of_parse_phandle_with_args(node, "clocks", + "#clock-cells", index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return rc; + } + + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) { + pr_warn("clk: couldn't get clock %d for %s\n", + index, node->full_name); + return PTR_ERR(clk); + } + + rc = clk_set_rate(clk, rate); + if (rc < 0) + pr_err("clk: couldn't set %s clk rate to %d (%d), current rate: %ld\n", + __clk_get_name(clk), rate, rc, + clk_get_rate(clk)); + clk_put(clk); + } + index++; + } + + return 0; +} + +static struct clk *__register_divider_clks(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 initial_val, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct mango_clk_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the divider */ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops = &dm_mango_clk_divider_ro_ops; + else + init.ops = &dm_mango_clk_divider_ops; + init.flags = flags; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + /* struct mango_clk_divider assignments */ + div->reg = reg; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + div->initial_val = initial_val; + + /* register the clock */ + hw = &div->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(div); + hw = ERR_PTR(ret); + return ERR_PTR(-EBUSY); + } + + return hw->clk; +} + +static inline int register_provider_clks +(struct device_node *node, struct mango_clk_data *clk_data, int clk_num) +{ + return of_clk_add_provider(node, of_clk_src_onecell_get, + &clk_data->clk_data); +} + +static int register_gate_clks(struct device *dev, struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_gate_clock *gate_clks = table->gate_clks; + void __iomem *base = clk_data->base; + int clk_num = table->gate_clks_num; + int i; + + for (i = 0; i < clk_num; i++) { + clk = clk_register_gate( + dev, gate_clks[i].name, gate_clks[i].parent_name, + gate_clks[i].flags | CLK_IS_CRITICAL, base + gate_clks[i].offset, + gate_clks[i].bit_idx, gate_clks[i].gate_flags, + &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + gate_clks[i].name); + goto err; + } + + if (gate_clks[i].alias) + clk_register_clkdev(clk, gate_clks[i].alias, NULL); + + clk_data->clk_data.clks[gate_clks[i].id] = clk; + } + + return 0; + +err: + while (i--) + clk_unregister_gate(clk_data->clk_data.clks[gate_clks[i].id]); + + return PTR_ERR(clk); +} + +static int register_divider_clks(struct device *dev, + struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_divider_clock *div_clks = table->div_clks; + void __iomem *base = clk_data->base; + int clk_num = table->div_clks_num; + int i, val; + + for (i = 0; i < clk_num; i++) { + clk = __register_divider_clks( + NULL, div_clks[i].name, div_clks[i].parent_name, + div_clks[i].flags, base + div_clks[i].offset, + div_clks[i].shift, div_clks[i].width, + div_clks[i].initial_val, + (div_clks[i].initial_sel & MANGO_CLK_USE_INIT_VAL) ? + div_clks[i].div_flags | CLK_DIVIDER_READ_ONLY : + div_clks[i].div_flags, + div_clks[i].table, &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + div_clks[i].name); + goto err; + } + + clk_data->clk_data.clks[div_clks[i].id] = clk; + + if (div_clks[i].initial_sel == MANGO_CLK_USE_REG_VAL) { + regmap_read(clk_data->syscon_top, div_clks[i].offset, + &val); + + /* + * set a default divider factor, + * clk driver should not select divider clock as the + * clock source, before set the divider by right process + * (assert div, set div factor, de assert div). + */ + if (div_clks[i].initial_val > 0) + val |= (div_clks[i].initial_val << 16 | 1 << 3); + else { + /* + * the div register is config to use divider factor, don't change divider + */ + if (!(val >> 3 & 0x1)) + val |= 1 << 16; + } + + regmap_write(clk_data->syscon_top, div_clks[i].offset, + val); + } + } + + return 0; + +err: + while (i--) + clk_unregister_divider(clk_data->clk_data.clks[div_clks[i].id]); + + return PTR_ERR(clk); +} + +static int register_mux_clks(struct device *dev, struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_mux_clock *mux_clks = table->mux_clks; + void __iomem *base = clk_data->base; + int clk_num = table->mux_clks_num; + int i; + + for (i = 0; i < clk_num; i++) { + u32 mask = BIT(mux_clks[i].width) - 1; + + clk = clk_register_mux_table( + dev, mux_clks[i].name, mux_clks[i].parent_names, + mux_clks[i].num_parents, mux_clks[i].flags, + base + mux_clks[i].offset, mux_clks[i].shift, mask, + mux_clks[i].mux_flags, mux_clks[i].table, + &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + mux_clks[i].name); + goto err; + } + + clk_data->clk_data.clks[mux_clks[i].id] = clk; + + if (!(mux_clks[i].flags & CLK_MUX_READ_ONLY)) { + struct clk *parent; + struct notifier_block *clk_nb; + + /* set mux clock default parent here, it's parent index + * value is read from the mux clock reg. dts can override + * setting the mux clock parent later. + */ + parent = clk_get_parent(clk); + clk_set_parent(clk, parent); + + /* add a notify callback function */ + clk_nb = kzalloc(sizeof(*clk_nb), GFP_KERNEL); + if (!clk_nb) + goto err; + clk_nb->notifier_call = mux_notifier_cb; + if (clk_notifier_register(clk, clk_nb)) + pr_err("%s: failed to register clock notifier for %s\n", + __func__, mux_clks[i].name); + } + } + + return 0; + +err: + while (i--) + clk_unregister_mux(clk_data->clk_data.clks[mux_clks[i].id]); + + return PTR_ERR(clk); +} + +/* pll clock init */ +int dm_mango_register_pll_clks(struct device_node *node, + struct mango_clk_data *clk_data, const char *clk_name) +{ + struct clk *clk = NULL; + struct mango_pll_clock *pll_clks; + int i, ret = 0; + const struct clk_ops *local_ops; + + pll_clks = (struct mango_pll_clock *)clk_data->table->pll_clks; + for (i = 0; i < clk_data->table->pll_clks_num; i++) { + if (!strcmp(clk_name, pll_clks[i].name)) { + /* have to assigne pll_clks.syscon_top first + * since clk_register_composite will need it + * to calculate current rate. + */ + pll_clks[i].syscon_top = clk_data->syscon_top; + pll_clks[i].lock = &clk_data->lock; + if (pll_clks[i].ini_flags & MANGO_CLK_RO) + local_ops = &dm_mango_clk_pll_ro_ops; + else + local_ops = &dm_mango_clk_pll_ops; + clk = clk_register_composite( + NULL, pll_clks[i].name, &pll_clks[i].parent_name, + 1, NULL, NULL, &pll_clks[i].hw, local_ops, + NULL, NULL, pll_clks[i].flags); + + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + pll_clks[i].name); + ret = -EINVAL; + goto out; + } + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + clk_unregister(clk); + } else { + continue; + } + } + +out: + return ret; +} + +/* mux clk init */ +int dm_mango_register_mux_clks(struct device_node *node, struct mango_clk_data *clk_data) +{ + int ret; + int count; + struct clk **clk_table; + + count = clk_data->table->mux_clks_num + clk_data->table->gate_clks_num; + clk_table = kcalloc(count, sizeof(*clk_table), GFP_KERNEL); + if (!clk_table) + return -ENOMEM; + + clk_data->clk_data.clks = clk_table; + clk_data->clk_data.clk_num = count; + + ret = register_mux_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_gate_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_provider_clks(node, clk_data, count); + if (ret) + goto err; + + return 0; +err: + kfree(clk_table); + return ret; +} + +/* pll divider init */ +int dm_mango_register_div_clks(struct device_node *node, struct mango_clk_data *clk_data) +{ + int ret; + int count; + + struct clk **clk_table; + + count = clk_data->table->div_clks_num + clk_data->table->gate_clks_num; + clk_table = kcalloc(count, sizeof(*clk_table), GFP_KERNEL); + if (!clk_table) + return -ENOMEM; + + clk_data->clk_data.clks = clk_table; + clk_data->clk_data.clk_num = count; + + ret = register_divider_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_gate_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_provider_clks(node, clk_data, count); + if (ret) + goto err; + + + return 0; +err: + kfree(clk_table); + pr_err("%s error %d\n", __func__, ret); + return ret; +} diff --git a/drivers/clk/sophgo/clk-mango.c b/drivers/clk/sophgo/clk-mango.c new file mode 100644 index 0000000000000..70e17f65c6fb4 --- /dev/null +++ b/drivers/clk/sophgo/clk-mango.c @@ -0,0 +1,977 @@ +/* + * Copyright (c) 2022 SOPHGO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include + +#include "clk.h" + +/* fixed clocks */ +struct mango_pll_clock mango_root_pll_clks[] = { + { + .id = FPLL_CLK, + .name = "fpll_clock", + .parent_name = "cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + }, { + .id = DPLL0_CLK, + .name = "dpll0_clock", + .parent_name = "cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + .status_offset = 0xc0, + .enable_offset = 0xc4, + }, { + .id = DPLL1_CLK, + .name = "dpll1_clock", + .parent_name = "cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + .status_offset = 0xc0, + .enable_offset = 0xc4, + }, { + .id = MPLL_CLK, + .name = "mpll_clock", + .parent_name = "cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .status_offset = 0xc0, + .enable_offset = 0xc4, + },{ + .id = FPLL_CLK, + .name = "s1_fpll_clock", + .parent_name = "s1_cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + }, { + .id = DPLL0_CLK, + .name = "s1_dpll0_clock", + .parent_name = "s1_cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + .status_offset = 0xc0, + .enable_offset = 0xc4, + }, { + .id = DPLL1_CLK, + .name = "s1_dpll1_clock", + .parent_name = "s1_cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .ini_flags = MANGO_CLK_RO, + .status_offset = 0xc0, + .enable_offset = 0xc4, + }, { + .id = MPLL_CLK, + .name = "s1_mpll_clock", + .parent_name = "s1_cgi", + .flags = CLK_GET_RATE_NOCACHE | CLK_GET_ACCURACY_NOCACHE, + .status_offset = 0xc0, + .enable_offset = 0xc4, + } +}; + +/* divider clocks */ +static const struct mango_divider_clock s0_div_clks[] = { + { DIV_CLK_MPLL_RP_CPU_NORMAL_0, "clk_div_rp_cpu_normal_0", "clk_gate_rp_cpu_normal_div0", + 0, 0x2044, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_MPLL_AXI_DDR_0, "clk_div_axi_ddr_0", "clk_gate_axi_ddr_div0", + 0, 0x20a8, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, 5}, + { DIV_CLK_FPLL_DDR01_1, "clk_div_ddr01_1", "clk_gate_ddr01_div1", + 0, 0x20b0, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_FPLL_DDR23_1, "clk_div_ddr23_1", "clk_gate_ddr23_div1", + 0, 0x20b8, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_FPLL_RP_CPU_NORMAL_1, "clk_div_rp_cpu_normal_1", "clk_gate_rp_cpu_normal_div1", + 0, 0x2040, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_50M_A53, "clk_div_50m_a53", "fpll_clock", + 0, 0x2048, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_RP_CMN_DIV2, "clk_div_top_rp_cmn_div2", "clk_mux_rp_cpu_normal", + 0, 0x204c, 16, 16, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_UART_500M, "clk_div_uart_500m", "fpll_clock", + 0, 0x2050, 16, 7, CLK_DIVIDER_READ_ONLY, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_AHB_LPC, "clk_div_ahb_lpc", "fpll_clock", + 0, 0x2054, 16, 16, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_EFUSE, "clk_div_efuse", "fpll_clock", + 0, 0x2078, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TX_ETH0, "clk_div_tx_eth0", "fpll_clock", + 0, 0x2080, 16, 11, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_PTP_REF_I_ETH0, "clk_div_ptp_ref_i_eth0", "fpll_clock", + 0, 0x2084, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_REF_ETH0, "clk_div_ref_eth0", "fpll_clock", + 0, 0x2088, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_EMMC, "clk_div_emmc", "fpll_clock", + 0, 0x208c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_SD, "clk_div_sd", "fpll_clock", + 0, 0x2094, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_AXI0, "clk_div_top_axi0", "fpll_clock", + 0, 0x209c, 16, 5, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_AXI_HSPERI, "clk_div_top_axi_hsperi", "fpll_clock", + 0, 0x20a0, 16, 5, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_AXI_DDR_1, "clk_div_axi_ddr_1", "clk_gate_axi_ddr_div1", + 0, 0x20a4, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, 5}, + { DIV_CLK_FPLL_DIV_TIMER1, "clk_div_timer1", "clk_div_50m_a53", + 0, 0x2058, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER2, "clk_div_timer2", "clk_div_50m_a53", + 0, 0x205c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER3, "clk_div_timer3", "clk_div_50m_a53", + 0, 0x2060, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER4, "clk_div_timer4", "clk_div_50m_a53", + 0, 0x2064, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER5, "clk_div_timer5", "clk_div_50m_a53", + 0, 0x2068, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER6, "clk_div_timer6", "clk_div_50m_a53", + 0, 0x206c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER7, "clk_div_timer7", "clk_div_50m_a53", + 0, 0x2070, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER8, "clk_div_timer8", "clk_div_50m_a53", + 0, 0x2074, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_100K_EMMC, "clk_div_100k_emmc", "clk_div_top_axi0", + 0, 0x2090, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_100K_SD, "clk_div_100k_sd", "clk_div_top_axi0", + 0, 0x2098, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_GPIO_DB, "clk_div_gpio_db", "clk_div_top_axi0", + 0, 0x207c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_DPLL0_DDR01_0, "clk_div_ddr01_0", "clk_gate_ddr01_div0", + 0, 0x20ac, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_DPLL1_DDR23_0, "clk_div_ddr23_0", "clk_gate_ddr23_div0", + 0, 0x20b4, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, +}; + +/* gate clocks */ +static const struct mango_gate_clock s0_gate_clks[] = { + { GATE_CLK_RP_CPU_NORMAL_DIV0, "clk_gate_rp_cpu_normal_div1", "mpll_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR_DIV0, "clk_gate_axi_ddr_div1", "mpll_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_DDR01_DIV0, "clk_gate_ddr01_div0", "fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 14, 0 }, + { GATE_CLK_DDR23_DIV0, "clk_gate_ddr23_div0", "fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 15, 0 }, + { GATE_CLK_RP_CPU_NORMAL_DIV1, "clk_gate_rp_cpu_normal_div0", "fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR_DIV1, "clk_gate_axi_ddr_div0", "fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_DDR01_DIV1, "clk_gate_ddr01_div1", "dpll0_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 14, 0 }, + { GATE_CLK_DDR23_DIV1, "clk_gate_ddr23_div1", "dpll1_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 15, 0 }, + { GATE_CLK_A53_50M, "clk_gate_a53_50m", "clk_div_50m_a53", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 1, 0 }, + { GATE_CLK_TOP_RP_CMN_DIV2, "clk_gate_top_rp_cmn_div2", "clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 2, 0 }, + { GATE_CLK_AXI_PCIE0, "clk_gate_axi_pcie0", "clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 8, 0 }, + { GATE_CLK_AXI_PCIE1, "clk_gate_axi_pcie1", "clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 9, 0 }, + { GATE_CLK_HSDMA, "clk_gate_hsdma", "clk_gate_top_rp_cmn_div2", + CLK_SET_RATE_PARENT, 0x2004, 10, 0 }, + { GATE_CLK_EMMC_100M, "clk_gate_emmc", "clk_div_emmc", + CLK_SET_RATE_PARENT, 0x2004, 3, 0 }, + { GATE_CLK_SD_100M, "clk_gate_sd", "clk_div_sd", + CLK_SET_RATE_PARENT, 0x2004, 6, 0 }, + { GATE_CLK_TX_ETH0, "clk_gate_tx_eth0", "clk_div_tx_eth0", + CLK_SET_RATE_PARENT, 0x2000, 30, 0 }, + { GATE_CLK_PTP_REF_I_ETH0, "clk_gate_ptp_ref_i_eth0", "clk_div_ptp_ref_i_eth0", + CLK_SET_RATE_PARENT, 0x2004, 0, 0 }, + { GATE_CLK_REF_ETH0, "clk_gate_ref_eth0", "clk_div_ref_eth0", + CLK_SET_RATE_PARENT, 0x2004, 1, 0 }, + { GATE_CLK_UART_500M, "clk_gate_uart_500m", "clk_div_uart_500m", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 4, 0 }, + { GATE_CLK_AHB_LPC, "clk_gate_ahb_lpc", "clk_div_ahb_lpc", + CLK_SET_RATE_PARENT, 0x2000, 7, 0 }, + { GATE_CLK_EFUSE, "clk_gate_efuse", "clk_div_efuse", + CLK_SET_RATE_PARENT, 0x2000, 20, 0}, + { GATE_CLK_TOP_AXI0, "clk_gate_top_axi0", "clk_div_top_axi0", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 11, 0 }, + { GATE_CLK_TOP_AXI_HSPERI, "clk_gate_top_axi_hsperi", "clk_div_top_axi_hsperi", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 12, 0 }, + { GATE_CLK_AHB_ROM, "clk_gate_ahb_rom", "clk_gate_top_axi0", + 0, 0x2000, 8, 0 }, + { GATE_CLK_AHB_SF, "clk_gate_ahb_sf", "clk_gate_top_axi0", + 0, 0x2000, 9, 0 }, + { GATE_CLK_AXI_SRAM, "clk_gate_axi_sram", "clk_gate_top_axi0", + CLK_IGNORE_UNUSED, 0x2000, 10, 0 }, + { GATE_CLK_APB_TIMER, "clk_gate_apb_timer", "clk_gate_top_axi0", + CLK_IGNORE_UNUSED, 0x2000, 11, 0 }, + { GATE_CLK_APB_EFUSE, "clk_gate_apb_efuse", "clk_gate_top_axi0", + 0, 0x2000, 21, 0 }, + { GATE_CLK_APB_GPIO, "clk_gate_apb_gpio", "clk_gate_top_axi0", + 0, 0x2000, 22, 0 }, + { GATE_CLK_APB_GPIO_INTR, "clk_gate_apb_gpio_intr", "clk_gate_top_axi0", + 0, 0x2000, 23, 0 }, + { GATE_CLK_APB_I2C, "clk_gate_apb_i2c", "clk_gate_top_axi0", + 0, 0x2000, 26, 0 }, + { GATE_CLK_APB_WDT, "clk_gate_apb_wdt", "clk_gate_top_axi0", + 0, 0x2000, 27, 0 }, + { GATE_CLK_APB_PWM, "clk_gate_apb_pwm", "clk_gate_top_axi0", + 0, 0x2000, 28, 0 }, + { GATE_CLK_APB_RTC, "clk_gate_apb_rtc", "clk_gate_top_axi0", + 0, 0x2000, 29, 0 }, + { GATE_CLK_SYSDMA_AXI, "clk_gate_sysdma_axi", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 3, 0 }, + { GATE_CLK_APB_UART, "clk_gate_apb_uart", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 5, 0 }, + { GATE_CLK_AXI_DBG_I2C, "clk_gate_axi_dbg_i2c", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 6, 0 }, + { GATE_CLK_APB_SPI, "clk_gate_apb_spi", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 25, 0 }, + { GATE_CLK_AXI_ETH0, "clk_gate_axi_eth0", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 31, 0 }, + { GATE_CLK_AXI_EMMC, "clk_gate_axi_emmc", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 2, 0 }, + { GATE_CLK_AXI_SD, "clk_gate_axi_sd", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 5, 0 }, + { GATE_CLK_TIMER1, "clk_gate_timer1", "clk_div_timer1", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 }, + { GATE_CLK_TIMER2, "clk_gate_timer2", "clk_div_timer2", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 }, + { GATE_CLK_TIMER3, "clk_gate_timer3", "clk_div_timer3", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 }, + { GATE_CLK_TIMER4, "clk_gate_timer4", "clk_div_timer4", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 }, + { GATE_CLK_TIMER5, "clk_gate_timer5", "clk_div_timer5", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 }, + { GATE_CLK_TIMER6, "clk_gate_timer6", "clk_div_timer6", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 }, + { GATE_CLK_TIMER7, "clk_gate_timer7", "clk_div_timer7", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 }, + { GATE_CLK_TIMER8, "clk_gate_timer8", "clk_div_timer8", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 }, + { GATE_CLK_100K_EMMC, "clk_gate_100k_emmc", "clk_div_100k_emmc", + CLK_SET_RATE_PARENT, 0x2004, 4, 0 }, + { GATE_CLK_100K_SD, "clk_gate_100k_sd", "clk_div_100k_sd", + CLK_SET_RATE_PARENT, 0x2004, 7, 0 }, + { GATE_CLK_GPIO_DB, "clk_gate_gpio_db", "clk_div_gpio_db", + CLK_SET_RATE_PARENT, 0x2000, 24, 0 }, + { GATE_CLK_DDR01, "clk_gate_ddr01", "clk_mux_ddr01", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 14, 0 }, + { GATE_CLK_DDR23, "clk_gate_ddr23", "clk_mux_ddr23", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 15, 0 }, + { GATE_CLK_RP_CPU_NORMAL, "clk_gate_rp_cpu_normal", "clk_mux_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR, "clk_gate_axi_ddr", "clk_mux_axi_ddr", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_RXU0, "clk_gate_rxu0", "clk_gate_rp_cpu_normal", + 0, 0x368, 0, 0 }, + { GATE_CLK_RXU1, "clk_gate_rxu1", "clk_gate_rp_cpu_normal", + 0, 0x368, 1, 0 }, + { GATE_CLK_RXU2, "clk_gate_rxu2", "clk_gate_rp_cpu_normal", + 0, 0x368, 2, 0 }, + { GATE_CLK_RXU3, "clk_gate_rxu3", "clk_gate_rp_cpu_normal", + 0, 0x368, 3, 0 }, + { GATE_CLK_RXU4, "clk_gate_rxu4", "clk_gate_rp_cpu_normal", + 0, 0x368, 4, 0 }, + { GATE_CLK_RXU5, "clk_gate_rxu5", "clk_gate_rp_cpu_normal", + 0, 0x368, 5, 0 }, + { GATE_CLK_RXU6, "clk_gate_rxu6", "clk_gate_rp_cpu_normal", + 0, 0x368, 6, 0 }, + { GATE_CLK_RXU7, "clk_gate_rxu7", "clk_gate_rp_cpu_normal", + 0, 0x368, 7, 0 }, + { GATE_CLK_RXU8, "clk_gate_rxu8", "clk_gate_rp_cpu_normal", + 0, 0x368, 8, 0 }, + { GATE_CLK_RXU9, "clk_gate_rxu9", "clk_gate_rp_cpu_normal", + 0, 0x368, 9, 0 }, + { GATE_CLK_RXU10, "clk_gate_rxu10", "clk_gate_rp_cpu_normal", + 0, 0x368, 10, 0 }, + { GATE_CLK_RXU11, "clk_gate_rxu11", "clk_gate_rp_cpu_normal", + 0, 0x368, 11, 0 }, + { GATE_CLK_RXU12, "clk_gate_rxu12", "clk_gate_rp_cpu_normal", + 0, 0x368, 12, 0 }, + { GATE_CLK_RXU13, "clk_gate_rxu13", "clk_gate_rp_cpu_normal", + 0, 0x368, 13, 0 }, + { GATE_CLK_RXU14, "clk_gate_rxu14", "clk_gate_rp_cpu_normal", + 0, 0x368, 14, 0 }, + { GATE_CLK_RXU15, "clk_gate_rxu15", "clk_gate_rp_cpu_normal", + 0, 0x368, 15, 0 }, + { GATE_CLK_RXU16, "clk_gate_rxu16", "clk_gate_rp_cpu_normal", + 0, 0x368, 16, 0 }, + { GATE_CLK_RXU17, "clk_gate_rxu17", "clk_gate_rp_cpu_normal", + 0, 0x368, 17, 0 }, + { GATE_CLK_RXU18, "clk_gate_rxu18", "clk_gate_rp_cpu_normal", + 0, 0x368, 18, 0 }, + { GATE_CLK_RXU19, "clk_gate_rxu19", "clk_gate_rp_cpu_normal", + 0, 0x368, 19, 0 }, + { GATE_CLK_RXU20, "clk_gate_rxu20", "clk_gate_rp_cpu_normal", + 0, 0x368, 20, 0 }, + { GATE_CLK_RXU21, "clk_gate_rxu21", "clk_gate_rp_cpu_normal", + 0, 0x368, 21, 0 }, + { GATE_CLK_RXU22, "clk_gate_rxu22", "clk_gate_rp_cpu_normal", + 0, 0x368, 22, 0 }, + { GATE_CLK_RXU23, "clk_gate_rxu23", "clk_gate_rp_cpu_normal", + 0, 0x368, 23, 0 }, + { GATE_CLK_RXU24, "clk_gate_rxu24", "clk_gate_rp_cpu_normal", + 0, 0x368, 24, 0 }, + { GATE_CLK_RXU25, "clk_gate_rxu25", "clk_gate_rp_cpu_normal", + 0, 0x368, 25, 0 }, + { GATE_CLK_RXU26, "clk_gate_rxu26", "clk_gate_rp_cpu_normal", + 0, 0x368, 26, 0 }, + { GATE_CLK_RXU27, "clk_gate_rxu27", "clk_gate_rp_cpu_normal", + 0, 0x368, 27, 0 }, + { GATE_CLK_RXU28, "clk_gate_rxu28", "clk_gate_rp_cpu_normal", + 0, 0x368, 28, 0 }, + { GATE_CLK_RXU29, "clk_gate_rxu29", "clk_gate_rp_cpu_normal", + 0, 0x368, 29, 0 }, + { GATE_CLK_RXU30, "clk_gate_rxu30", "clk_gate_rp_cpu_normal", + 0, 0x368, 30, 0 }, + { GATE_CLK_RXU31, "clk_gate_rxu31", "clk_gate_rp_cpu_normal", + 0, 0x368, 31, 0 }, + { GATE_CLK_MP0, "clk_gate_mp0", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x384, 0, 0 }, + { GATE_CLK_MP1, "clk_gate_mp1", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x38c, 0, 0 }, + { GATE_CLK_MP2, "clk_gate_mp2", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x394, 0, 0 }, + { GATE_CLK_MP3, "clk_gate_mp3", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x39c, 0, 0 }, + { GATE_CLK_MP4, "clk_gate_mp4", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3a4, 0, 0 }, + { GATE_CLK_MP5, "clk_gate_mp5", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3ac, 0, 0 }, + { GATE_CLK_MP6, "clk_gate_mp6", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3b4, 0, 0 }, + { GATE_CLK_MP7, "clk_gate_mp7", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3bc, 0, 0 }, + { GATE_CLK_MP8, "clk_gate_mp8", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3c4, 0, 0 }, + { GATE_CLK_MP9, "clk_gate_mp9", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3cc, 0, 0 }, + { GATE_CLK_MP10, "clk_gate_mp10", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3d4, 0, 0 }, + { GATE_CLK_MP11, "clk_gate_mp11", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3dc, 0, 0 }, + { GATE_CLK_MP12, "clk_gate_mp12", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3e4, 0, 0 }, + { GATE_CLK_MP13, "clk_gate_mp13", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3ec, 0, 0 }, + { GATE_CLK_MP14, "clk_gate_mp14", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3f4, 0, 0 }, + { GATE_CLK_MP15, "clk_gate_mp15", "clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3fc, 0, 0 }, +}; + +static const struct mango_divider_clock s1_div_clks[] = { + { DIV_CLK_MPLL_RP_CPU_NORMAL_0, "s1_clk_div_rp_cpu_normal_0", "s1_clk_gate_rp_cpu_normal_div0", + 0, 0x2044, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_MPLL_AXI_DDR_0, "s1_clk_div_axi_ddr_0", "s1_clk_gate_axi_ddr_div0", + 0, 0x20a8, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, 5}, + { DIV_CLK_FPLL_DDR01_1, "s1_clk_div_ddr01_1", "s1_clk_gate_ddr01_div1", + 0, 0x20b0, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_FPLL_DDR23_1, "s1_clk_div_ddr23_1", "s1_clk_gate_ddr23_div1", + 0, 0x20b8, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_FPLL_RP_CPU_NORMAL_1, "s1_clk_div_rp_cpu_normal_1", "s1_clk_gate_rp_cpu_normal_div1", + 0, 0x2040, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_50M_A53, "s1_clk_div_50m_a53", "s1_fpll_clock", + 0, 0x2048, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_RP_CMN_DIV2, "s1_clk_div_top_rp_cmn_div2", "s1_clk_mux_rp_cpu_normal", + 0, 0x204c, 16, 16, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_UART_500M, "s1_clk_div_uart_500m", "s1_fpll_clock", + 0, 0x2050, 16, 7, CLK_DIVIDER_READ_ONLY, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_AHB_LPC, "s1_clk_div_ahb_lpc", "s1_fpll_clock", + 0, 0x2054, 16, 16, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_EFUSE, "s1_clk_div_efuse", "s1_fpll_clock", + 0, 0x2078, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TX_ETH0, "s1_clk_div_tx_eth0", "s1_fpll_clock", + 0, 0x2080, 16, 11, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_PTP_REF_I_ETH0, "s1_clk_div_ptp_ref_i_eth0", "s1_fpll_clock", + 0, 0x2084, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_REF_ETH0, "s1_clk_div_ref_eth0", "s1_fpll_clock", + 0, 0x2088, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_EMMC, "s1_clk_div_emmc", "s1_fpll_clock", + 0, 0x208c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_SD, "s1_clk_div_sd", "s1_fpll_clock", + 0, 0x2094, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_AXI0, "s1_clk_div_top_axi0", "s1_fpll_clock", + 0, 0x209c, 16, 5, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_TOP_AXI_HSPERI, "s1_clk_div_top_axi_hsperi", "s1_fpll_clock", + 0, 0x20a0, 16, 5, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_AXI_DDR_1, "s1_clk_div_axi_ddr_1", "s1_clk_gate_axi_ddr_div1", + 0, 0x20a4, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, 5}, + { DIV_CLK_FPLL_DIV_TIMER1, "s1_clk_div_timer1", "s1_clk_div_50m_a53", + 0, 0x2058, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER2, "s1_clk_div_timer2", "s1_clk_div_50m_a53", + 0, 0x205c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER3, "s1_clk_div_timer3", "s1_clk_div_50m_a53", + 0, 0x2060, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER4, "s1_clk_div_timer4", "s1_clk_div_50m_a53", + 0, 0x2064, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER5, "s1_clk_div_timer5", "s1_clk_div_50m_a53", + 0, 0x2068, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER6, "s1_clk_div_timer6", "s1_clk_div_50m_a53", + 0, 0x206c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER7, "s1_clk_div_timer7", "s1_clk_div_50m_a53", + 0, 0x2070, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_DIV_TIMER8, "s1_clk_div_timer8", "s1_clk_div_50m_a53", + 0, 0x2074, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_100K_EMMC, "s1_clk_div_100k_emmc", "s1_clk_div_top_axi0", + 0, 0x2090, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_100K_SD, "s1_clk_div_100k_sd", "s1_clk_div_top_axi0", + 0, 0x2098, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_FPLL_GPIO_DB, "s1_clk_div_gpio_db", "s1_clk_div_top_axi0", + 0, 0x207c, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_REG_VAL, }, + { DIV_CLK_DPLL0_DDR01_0, "s1_clk_div_ddr01_0", "s1_clk_gate_ddr01_div0", + 0, 0x20ac, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, + { DIV_CLK_DPLL1_DDR23_0, "s1_clk_div_ddr23_0", "s1_clk_gate_ddr23_div0", + 0, 0x20b4, 16, 8, CLK_DIVIDER_ONE_BASED | + CLK_DIVIDER_ALLOW_ZERO, MANGO_CLK_USE_INIT_VAL, }, +}; + +static const struct mango_gate_clock s1_gate_clks[] = { + { GATE_CLK_RP_CPU_NORMAL_DIV0, "s1_clk_gate_rp_cpu_normal_div1", "s1_mpll_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR_DIV0, "s1_clk_gate_axi_ddr_div1", "s1_mpll_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_DDR01_DIV0, "s1_clk_gate_ddr01_div0", "s1_fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 14, 0 }, + { GATE_CLK_DDR23_DIV0, "s1_clk_gate_ddr23_div0", "s1_fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 15, 0 }, + { GATE_CLK_RP_CPU_NORMAL_DIV1, "s1_clk_gate_rp_cpu_normal_div0", "s1_fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR_DIV1, "s1_clk_gate_axi_ddr_div0", "s1_fpll_clock", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_DDR01_DIV1, "s1_clk_gate_ddr01_div1", "s1_dpll0_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 14, 0 }, + { GATE_CLK_DDR23_DIV1, "s1_clk_gate_ddr23_div1", "s1_dpll1_clock", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 15, 0 }, + { GATE_CLK_A53_50M, "s1_clk_gate_a53_50m", "s1_clk_div_50m_a53", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 1, 0 }, + { GATE_CLK_TOP_RP_CMN_DIV2, "s1_clk_gate_top_rp_cmn_div2", "s1_clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 2, 0 }, + { GATE_CLK_AXI_PCIE0, "s1_clk_gate_axi_pcie0", "s1_clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 8, 0 }, + { GATE_CLK_AXI_PCIE1, "s1_clk_gate_axi_pcie1", "s1_clk_gate_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2004, 9, 0 }, + { GATE_CLK_HSDMA, "s1_clk_gate_hsdma", "s1_clk_gate_top_rp_cmn_div2", + CLK_SET_RATE_PARENT, 0x2004, 10, 0 }, + { GATE_CLK_EMMC_100M, "s1_clk_gate_emmc", "s1_clk_div_emmc", + CLK_SET_RATE_PARENT, 0x2004, 3, 0 }, + { GATE_CLK_SD_100M, "s1_clk_gate_sd", "s1_clk_div_sd", + CLK_SET_RATE_PARENT, 0x2004, 6, 0 }, + { GATE_CLK_TX_ETH0, "s1_clk_gate_tx_eth0", "s1_clk_div_tx_eth0", + CLK_SET_RATE_PARENT, 0x2000, 30, 0 }, + { GATE_CLK_PTP_REF_I_ETH0, "s1_clk_gate_ptp_ref_i_eth0", "s1_clk_div_ptp_ref_i_eth0", + CLK_SET_RATE_PARENT, 0x2004, 0, 0 }, + { GATE_CLK_REF_ETH0, "s1_clk_gate_ref_eth0", "s1_clk_div_ref_eth0", + CLK_SET_RATE_PARENT, 0x2004, 1, 0 }, + { GATE_CLK_UART_500M, "s1_clk_gate_uart_500m", "s1_clk_div_uart_500m", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 4, 0 }, + { GATE_CLK_AHB_LPC, "s1_clk_gate_ahb_lpc", "s1_clk_div_ahb_lpc", + CLK_SET_RATE_PARENT, 0x2000, 7, 0 }, + { GATE_CLK_EFUSE, "s1_clk_gate_efuse", "s1_clk_div_efuse", + CLK_SET_RATE_PARENT, 0x2000, 20, 0}, + { GATE_CLK_TOP_AXI0, "s1_clk_gate_top_axi0", "s1_clk_div_top_axi0", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 11, 0 }, + { GATE_CLK_TOP_AXI_HSPERI, "s1_clk_gate_top_axi_hsperi", "s1_clk_div_top_axi_hsperi", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 12, 0 }, + { GATE_CLK_AHB_ROM, "s1_clk_gate_ahb_rom", "s1_clk_gate_top_axi0", + 0, 0x2000, 8, 0 }, + { GATE_CLK_AHB_SF, "s1_clk_gate_ahb_sf", "s1_clk_gate_top_axi0", + 0, 0x2000, 9, 0 }, + { GATE_CLK_AXI_SRAM, "s1_clk_gate_axi_sram", "s1_clk_gate_top_axi0", + CLK_IGNORE_UNUSED, 0x2000, 10, 0 }, + { GATE_CLK_APB_TIMER, "s1_clk_gate_apb_timer", "s1_clk_gate_top_axi0", + CLK_IGNORE_UNUSED, 0x2000, 11, 0 }, + { GATE_CLK_APB_EFUSE, "s1_clk_gate_apb_efuse", "s1_clk_gate_top_axi0", + 0, 0x2000, 21, 0 }, + { GATE_CLK_APB_GPIO, "s1_clk_gate_apb_gpio", "s1_clk_gate_top_axi0", + 0, 0x2000, 22, 0 }, + { GATE_CLK_APB_GPIO_INTR, "s1_clk_gate_apb_gpio_intr", "s1_clk_gate_top_axi0", + 0, 0x2000, 23, 0 }, + { GATE_CLK_APB_I2C, "s1_clk_gate_apb_i2c", "s1_clk_gate_top_axi0", + 0, 0x2000, 26, 0 }, + { GATE_CLK_APB_WDT, "s1_clk_gate_apb_wdt", "s1_clk_gate_top_axi0", + 0, 0x2000, 27, 0 }, + { GATE_CLK_APB_PWM, "s1_clk_gate_apb_pwm", "s1_clk_gate_top_axi0", + 0, 0x2000, 28, 0 }, + { GATE_CLK_APB_RTC, "s1_clk_gate_apb_rtc", "s1_clk_gate_top_axi0", + 0, 0x2000, 29, 0 }, + { GATE_CLK_SYSDMA_AXI, "s1_clk_gate_sysdma_axi", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 3, 0 }, + { GATE_CLK_APB_UART, "s1_clk_gate_apb_uart", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 5, 0 }, + { GATE_CLK_AXI_DBG_I2C, "s1_clk_gate_axi_dbg_i2c", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 6, 0 }, + { GATE_CLK_APB_SPI, "s1_clk_gate_apb_spi", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 25, 0 }, + { GATE_CLK_AXI_ETH0, "s1_clk_gate_axi_eth0", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2000, 31, 0 }, + { GATE_CLK_AXI_EMMC, "s1_clk_gate_axi_emmc", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 2, 0 }, + { GATE_CLK_AXI_SD, "s1_clk_gate_axi_sd", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 5, 0 }, + { GATE_CLK_TIMER1, "s1_clk_gate_timer1", "s1_clk_div_timer1", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 }, + { GATE_CLK_TIMER2, "s1_clk_gate_timer2", "s1_clk_div_timer2", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 }, + { GATE_CLK_TIMER3, "s1_clk_gate_timer3", "s1_clk_div_timer3", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 }, + { GATE_CLK_TIMER4, "s1_clk_gate_timer4", "s1_clk_div_timer4", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 }, + { GATE_CLK_TIMER5, "s1_clk_gate_timer5", "s1_clk_div_timer5", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 }, + { GATE_CLK_TIMER6, "s1_clk_gate_timer6", "s1_clk_div_timer6", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 }, + { GATE_CLK_TIMER7, "s1_clk_gate_timer7", "s1_clk_div_timer7", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 }, + { GATE_CLK_TIMER8, "s1_clk_gate_timer8", "s1_clk_div_timer8", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 }, + { GATE_CLK_100K_EMMC, "s1_clk_gate_100k_emmc", "s1_clk_div_100k_emmc", + CLK_SET_RATE_PARENT, 0x2004, 4, 0 }, + { GATE_CLK_100K_SD, "s1_clk_gate_100k_sd", "s1_clk_div_100k_sd", + CLK_SET_RATE_PARENT, 0x2004, 7, 0 }, + { GATE_CLK_GPIO_DB, "s1_clk_gate_gpio_db", "s1_clk_div_gpio_db", + CLK_SET_RATE_PARENT, 0x2000, 24, 0 }, + { GATE_CLK_DDR01, "s1_clk_gate_ddr01", "s1_clk_mux_ddr01", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 14, 0 }, + { GATE_CLK_DDR23, "s1_clk_gate_ddr23", "s1_clk_mux_ddr23", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 15, 0 }, + { GATE_CLK_RP_CPU_NORMAL, "s1_clk_gate_rp_cpu_normal", "s1_clk_mux_rp_cpu_normal", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2000, 0, 0 }, + { GATE_CLK_AXI_DDR, "s1_clk_gate_axi_ddr", "s1_clk_mux_axi_ddr", + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x2004, 13, 0 }, + { GATE_CLK_RXU0, "s1_clk_gate_rxu0", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 0, 0 }, + { GATE_CLK_RXU1, "s1_clk_gate_rxu1", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 1, 0 }, + { GATE_CLK_RXU2, "s1_clk_gate_rxu2", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 2, 0 }, + { GATE_CLK_RXU3, "s1_clk_gate_rxu3", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 3, 0 }, + { GATE_CLK_RXU4, "s1_clk_gate_rxu4", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 4, 0 }, + { GATE_CLK_RXU5, "s1_clk_gate_rxu5", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 5, 0 }, + { GATE_CLK_RXU6, "s1_clk_gate_rxu6", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 6, 0 }, + { GATE_CLK_RXU7, "s1_clk_gate_rxu7", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 7, 0 }, + { GATE_CLK_RXU8, "s1_clk_gate_rxu8", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 8, 0 }, + { GATE_CLK_RXU9, "s1_clk_gate_rxu9", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 9, 0 }, + { GATE_CLK_RXU10, "s1_clk_gate_rxu10", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 10, 0 }, + { GATE_CLK_RXU11, "s1_clk_gate_rxu11", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 11, 0 }, + { GATE_CLK_RXU12, "s1_clk_gate_rxu12", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 12, 0 }, + { GATE_CLK_RXU13, "s1_clk_gate_rxu13", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 13, 0 }, + { GATE_CLK_RXU14, "s1_clk_gate_rxu14", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 14, 0 }, + { GATE_CLK_RXU15, "s1_clk_gate_rxu15", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 15, 0 }, + { GATE_CLK_RXU16, "s1_clk_gate_rxu16", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 16, 0 }, + { GATE_CLK_RXU17, "s1_clk_gate_rxu17", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 17, 0 }, + { GATE_CLK_RXU18, "s1_clk_gate_rxu18", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 18, 0 }, + { GATE_CLK_RXU19, "s1_clk_gate_rxu19", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 19, 0 }, + { GATE_CLK_RXU20, "s1_clk_gate_rxu20", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 20, 0 }, + { GATE_CLK_RXU21, "s1_clk_gate_rxu21", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 21, 0 }, + { GATE_CLK_RXU22, "s1_clk_gate_rxu22", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 22, 0 }, + { GATE_CLK_RXU23, "s1_clk_gate_rxu23", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 23, 0 }, + { GATE_CLK_RXU24, "s1_clk_gate_rxu24", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 24, 0 }, + { GATE_CLK_RXU25, "s1_clk_gate_rxu25", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 25, 0 }, + { GATE_CLK_RXU26, "s1_clk_gate_rxu26", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 26, 0 }, + { GATE_CLK_RXU27, "s1_clk_gate_rxu27", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 27, 0 }, + { GATE_CLK_RXU28, "s1_clk_gate_rxu28", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 28, 0 }, + { GATE_CLK_RXU29, "s1_clk_gate_rxu29", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 29, 0 }, + { GATE_CLK_RXU30, "s1_clk_gate_rxu30", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 30, 0 }, + { GATE_CLK_RXU31, "s1_clk_gate_rxu31", "s1_clk_gate_rp_cpu_normal", + 0, 0x368, 31, 0 }, + { GATE_CLK_MP0, "s1_clk_gate_mp0", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x384, 0, 0 }, + { GATE_CLK_MP1, "s1_clk_gate_mp1", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x38c, 0, 0 }, + { GATE_CLK_MP2, "s1_clk_gate_mp2", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x394, 0, 0 }, + { GATE_CLK_MP3, "s1_clk_gate_mp3", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x39c, 0, 0 }, + { GATE_CLK_MP4, "s1_clk_gate_mp4", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3a4, 0, 0 }, + { GATE_CLK_MP5, "s1_clk_gate_mp5", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3ac, 0, 0 }, + { GATE_CLK_MP6, "s1_clk_gate_mp6", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3b4, 0, 0 }, + { GATE_CLK_MP7, "s1_clk_gate_mp7", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3bc, 0, 0 }, + { GATE_CLK_MP8, "s1_clk_gate_mp8", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3c4, 0, 0 }, + { GATE_CLK_MP9, "s1_clk_gate_mp9", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3cc, 0, 0 }, + { GATE_CLK_MP10, "s1_clk_gate_mp10", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3d4, 0, 0 }, + { GATE_CLK_MP11, "s1_clk_gate_mp11", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3dc, 0, 0 }, + { GATE_CLK_MP12, "s1_clk_gate_mp12", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3e4, 0, 0 }, + { GATE_CLK_MP13, "s1_clk_gate_mp13", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3ec, 0, 0 }, + { GATE_CLK_MP14, "s1_clk_gate_mp14", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3f4, 0, 0 }, + { GATE_CLK_MP15, "s1_clk_gate_mp15", "s1_clk_gate_rp_cpu_normal", + CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0x3fc, 0, 0 }, +}; + +/* socket0 mux clocks */ +static const char *const clk_mux_ddr01_p[] = { + "clk_div_ddr01_0", "clk_div_ddr01_1"}; +static const char *const clk_mux_ddr23_p[] = { + "clk_div_ddr23_0", "clk_div_ddr23_1"}; +static const char *const clk_mux_rp_cpu_normal_p[] = { + "clk_div_rp_cpu_normal_0", "clk_div_rp_cpu_normal_1"}; +static const char *const clk_mux_axi_ddr_p[] = { + "clk_div_axi_ddr_0", "clk_div_axi_ddr_1"}; + +struct mango_mux_clock s0_mux_clks[] = { + { + MUX_CLK_DDR01, "clk_mux_ddr01", clk_mux_ddr01_p, + ARRAY_SIZE(clk_mux_ddr01_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | + CLK_MUX_READ_ONLY, + 0x2020, 2, 1, 0, + }, + { + MUX_CLK_DDR23, "clk_mux_ddr23", clk_mux_ddr23_p, + ARRAY_SIZE(clk_mux_ddr23_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | + CLK_MUX_READ_ONLY, + 0x2020, 3, 1, 0, + }, + { + MUX_CLK_RP_CPU_NORMAL, "clk_mux_rp_cpu_normal", clk_mux_rp_cpu_normal_p, + ARRAY_SIZE(clk_mux_rp_cpu_normal_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x2020, 0, 1, 0, + }, + { + MUX_CLK_AXI_DDR, "clk_mux_axi_ddr", clk_mux_axi_ddr_p, + ARRAY_SIZE(clk_mux_axi_ddr_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x2020, 1, 1, 0, + }, +}; + +/* socket1 mux clocks */ +static const char *const s1_clk_mux_ddr01_p[] = { + "s1_clk_div_ddr01_0", "s1_clk_div_ddr01_1"}; +static const char *const s1_clk_mux_ddr23_p[] = { + "s1_clk_div_ddr23_0", "s1_clk_div_ddr23_1"}; +static const char *const s1_clk_mux_rp_cpu_normal_p[] = { + "s1_clk_div_rp_cpu_normal_0", "s1_clk_div_rp_cpu_normal_1"}; +static const char *const s1_clk_mux_axi_ddr_p[] = { + "s1_clk_div_axi_ddr_0", "s1_clk_div_axi_ddr_1"}; + +struct mango_mux_clock s1_mux_clks[] = { + { + MUX_CLK_DDR01, "s1_clk_mux_ddr01", s1_clk_mux_ddr01_p, + ARRAY_SIZE(s1_clk_mux_ddr01_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | + CLK_MUX_READ_ONLY, + 0x2020, 2, 1, 0, + }, + { + MUX_CLK_DDR23, "s1_clk_mux_ddr23", s1_clk_mux_ddr23_p, + ARRAY_SIZE(s1_clk_mux_ddr23_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT | + CLK_MUX_READ_ONLY, + 0x2020, 3, 1, 0, + }, + { + MUX_CLK_RP_CPU_NORMAL, "s1_clk_mux_rp_cpu_normal", s1_clk_mux_rp_cpu_normal_p, + ARRAY_SIZE(s1_clk_mux_rp_cpu_normal_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x2020, 0, 1, 0, + }, + { + MUX_CLK_AXI_DDR, "s1_clk_mux_axi_ddr", s1_clk_mux_axi_ddr_p, + ARRAY_SIZE(s1_clk_mux_axi_ddr_p), + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + 0x2020, 1, 1, 0, + }, +}; + +struct mango_clk_table pll_clk_tables = { + .pll_clks_num = ARRAY_SIZE(mango_root_pll_clks), + .pll_clks = mango_root_pll_clks, +}; + +struct mango_clk_table div_clk_tables[] = { + { + .id = S0_DIV_CLK_TABLE, + .div_clks_num = ARRAY_SIZE(s0_div_clks), + .div_clks = s0_div_clks, + .gate_clks_num = ARRAY_SIZE(s0_gate_clks), + .gate_clks = s0_gate_clks, + },{ + .id = S1_DIV_CLK_TABLE, + .div_clks_num = ARRAY_SIZE(s1_div_clks), + .div_clks = s1_div_clks, + .gate_clks_num = ARRAY_SIZE(s1_gate_clks), + .gate_clks = s1_gate_clks, + }, +}; + +struct mango_clk_table mux_clk_tables[] = { + { + .id = S0_MUX_CLK_TABLE, + .mux_clks_num = ARRAY_SIZE(s0_mux_clks), + .mux_clks = s0_mux_clks, + },{ + .id = S1_MUX_CLK_TABLE, + .mux_clks_num = ARRAY_SIZE(s1_mux_clks), + .mux_clks = s1_mux_clks, + }, +}; + +static const struct of_device_id mango_clk_match_ids_tables[] = { + { + .compatible = "mango, pll-clock", + .data = &pll_clk_tables, + }, + { + .compatible = "mango, pll-child-clock", + .data = div_clk_tables, + }, + { + .compatible = "mango, pll-mux-clock", + .data = mux_clk_tables, + }, + { + .compatible = "mango, clk-default-rates", + }, + { + .compatible = "mango, dm-pll-clock", + .data = &pll_clk_tables, + }, + { + .compatible = "mango, dm-pll-child-clock", + .data = div_clk_tables, + }, + { + .compatible = "mango, dm-pll-mux-clock", + .data = mux_clk_tables, + }, + { + .compatible = "mango, dm-clk-default-rates", + }, + {} +}; + +static void __init mango_clk_init(struct device_node *node) +{ + struct device_node *np_top; + struct mango_clk_data *clk_data = NULL; + const struct mango_clk_table *dev_data; + struct regmap *syscon; + void __iomem *base; + int i, ret = 0; + unsigned int id; + const char *clk_name; + const struct of_device_id *match = NULL; + + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) { + ret = -ENOMEM; + goto out; + } + match = of_match_node(mango_clk_match_ids_tables, node); + if (match) { + dev_data = (struct mango_clk_table *)match->data; + } else { + pr_err("%s did't match node data\n", __func__); + ret = -ENODEV; + goto no_match_data; + } + + np_top = of_parse_phandle(node, "subctrl-syscon", 0); + if (!np_top) { + pr_err("%s can't get subctrl-syscon node\n", + __func__); + ret = -EINVAL; + goto no_match_data; + } + + syscon = device_node_to_regmap(np_top); + if (IS_ERR_OR_NULL(syscon)) { + pr_err("%s cannot get regmap %ld\n", __func__, PTR_ERR(syscon)); + ret = -ENODEV; + goto no_match_data; + } + base = of_iomap(np_top, 0); + + spin_lock_init(&clk_data->lock); + if (of_device_is_compatible(node, "mango, pll-clock") || + of_device_is_compatible(node, "mango, dm-pll-clock")) { + if (!dev_data->pll_clks_num) { + ret = -EINVAL; + goto no_match_data; + } + + clk_data->table = dev_data; + clk_data->base = base; + clk_data->syscon_top = syscon; + + if (of_property_read_string(node, "clock-output-names", &clk_name)) { + pr_err("%s cannot get pll name for %s\n", + __func__, node->full_name); + ret = -ENODEV; + goto no_match_data; + } + if (of_device_is_compatible(node, "mango, pll-clock")) + ret = mango_register_pll_clks(node, clk_data, clk_name); + else + ret = dm_mango_register_pll_clks(node, clk_data, clk_name); + } + + if (of_device_is_compatible(node, "mango, pll-child-clock") || + of_device_is_compatible(node, "mango, dm-pll-child-clock")) { + ret = of_property_read_u32(node, "id", &id); + if (ret) { + pr_err("not assigned id for %s\n", node->full_name); + ret = -ENODEV; + goto no_match_data; + } + + /* Below brute-force to check dts property "id" + * whether match id of array + */ + for (i = 0; i < ARRAY_SIZE(div_clk_tables); i++) { + if (id == dev_data[i].id) + break; /* found */ + } + clk_data->table = &dev_data[i]; + clk_data->base = base; + clk_data->syscon_top = syscon; + if (of_device_is_compatible(node, "mango, pll-child-clock")) + ret = mango_register_div_clks(node, clk_data); + else + ret = dm_mango_register_div_clks(node, clk_data); + } + + if (of_device_is_compatible(node, "mango, pll-mux-clock") || + of_device_is_compatible(node, "mango, dm-pll-mux-clock")) { + ret = of_property_read_u32(node, "id", &id); + if (ret) { + pr_err("not assigned id for %s\n", node->full_name); + ret = -ENODEV; + goto no_match_data; + } + + /* Below brute-force to check dts property "id" + * whether match id of array + */ + for (i = 0; i < ARRAY_SIZE(mux_clk_tables); i++) { + if (id == dev_data[i].id) + break; /* found */ + } + clk_data->table = &dev_data[i]; + clk_data->base = base; + clk_data->syscon_top = syscon; + if (of_device_is_compatible(node, "mango, pll-mux-clock")) + ret = mango_register_mux_clks(node, clk_data); + else + ret = dm_mango_register_mux_clks(node, clk_data); + } + + if (of_device_is_compatible(node, "mango, clk-default-rates")) + ret = set_default_clk_rates(node); + + if (of_device_is_compatible(node, "mango, dm-clk-default-rates")) + ret = dm_set_default_clk_rates(node); + + if (!ret) + return; + +no_match_data: + kfree(clk_data); + +out: + pr_err("%s failed error number %d\n", __func__, ret); +} + +CLK_OF_DECLARE(mango_clk_pll, "mango, pll-clock", mango_clk_init); +CLK_OF_DECLARE(mango_clk_pll_child, "mango, pll-child-clock", mango_clk_init); +CLK_OF_DECLARE(mango_clk_pll_mux, "mango, pll-mux-clock", mango_clk_init); +CLK_OF_DECLARE(mango_clk_default_rate, "mango, clk-default-rates", mango_clk_init); +CLK_OF_DECLARE(dm_mango_clk_pll, "mango, dm-pll-clock", mango_clk_init); +CLK_OF_DECLARE(dm_mango_clk_pll_child, "mango, dm-pll-child-clock", mango_clk_init); +CLK_OF_DECLARE(dm_mango_clk_pll_mux, "mango, dm-pll-mux-clock", mango_clk_init); +CLK_OF_DECLARE(dm_mango_clk_default_rate, "mango, dm-clk-default-rates", mango_clk_init); diff --git a/drivers/clk/sophgo/clk.c b/drivers/clk/sophgo/clk.c new file mode 100644 index 0000000000000..4d3893ace2b95 --- /dev/null +++ b/drivers/clk/sophgo/clk.c @@ -0,0 +1,883 @@ +/* + * Copyright (c) 2022 SOPHGO + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/* + * @hw: handle between common and hardware-specific interfaces + * @reg: register containing divider + * @shift: shift to the divider bit field + * @width: width of the divider bit field + * @initial_val:initial value of the divider + * @table: the div table that the divider supports + * @lock: register lock + */ +struct mango_clk_divider { + struct clk_hw hw; + void __iomem *reg; + u8 shift; + u8 width; + u8 flags; + u32 initial_val; + const struct clk_div_table *table; + spinlock_t *lock; +}; + +static inline int mango_pll_enable(struct regmap *map, + struct mango_pll_clock *pll, bool en) +{ + unsigned int value; + unsigned long enter; + unsigned int id = pll->id; + + if (en) { + /* wait pll lock */ + enter = jiffies; + regmap_read(map, pll->status_offset, &value); + while (!((value >> (PLL_STAT_LOCK_OFFSET + id)) & 0x1)) { + regmap_read(map, pll->status_offset, &value); + if (time_after(jiffies, enter + HZ / 10)) + pr_warn("%s not locked\n", pll->name); + } + /* wait pll updating */ + enter = jiffies; + regmap_read(map, pll->status_offset, &value); + while (((value >> id) & 0x1)) { + regmap_read(map, pll->status_offset, &value); + if (time_after(jiffies, enter + HZ / 10)) + pr_warn("%s still updating\n", pll->name); + } + /* enable pll */ + regmap_read(map, pll->enable_offset, &value); + regmap_write(map, pll->enable_offset, value | (1 << id)); + } else { + /* disable pll */ + regmap_read(map, pll->enable_offset, &value); + regmap_write(map, pll->enable_offset, value & (~(1 << id))); + } + + return 0; +} + +static inline int mango_pll_write(struct regmap *map, int id, int value) +{ + return regmap_write(map, PLL_CTRL_OFFSET + (id << 2), value); +} + +static inline int mango_pll_read(struct regmap *map, int id, unsigned int *pvalue) +{ + return regmap_read(map, PLL_CTRL_OFFSET + (id << 2), pvalue); +} + +static unsigned int _get_table_div(const struct clk_div_table *table, + unsigned int val) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->val == val) + return clkt->div; + return 0; +} + +static unsigned int _get_div(const struct clk_div_table *table, + unsigned int val, unsigned long flags, u8 width) +{ + if (flags & CLK_DIVIDER_ONE_BASED) + return val; + if (flags & CLK_DIVIDER_POWER_OF_TWO) + return 1 << val; + if (flags & CLK_DIVIDER_MAX_AT_ZERO) + return val ? val : div_mask(width) + 1; + if (table) + return _get_table_div(table, val); + return val + 1; +} + +static unsigned long mango_clk_divider_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mango_clk_divider *divider = to_mango_clk_divider(hw); + unsigned int val; + + val = readl(divider->reg) >> divider->shift; + val &= div_mask(divider->width); + +#ifdef CONFIG_ARCH_BM1880 + /* if select divide factor from initial value */ + if (!(readl(divider->reg) & BIT(3))) + val = divider->initial_val; +#endif + + return divider_recalc_rate(hw, parent_rate, val, divider->table, + divider->flags, divider->width); +} + +static long mango_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + int bestdiv; + struct mango_clk_divider *divider = to_mango_clk_divider(hw); + + /* if read only, just return current value */ + if (divider->flags & CLK_DIVIDER_READ_ONLY) { + bestdiv = readl(divider->reg) >> divider->shift; + bestdiv &= div_mask(divider->width); + bestdiv = _get_div(divider->table, bestdiv, divider->flags, + divider->width); + return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); + } + + return divider_round_rate(hw, rate, prate, divider->table, + divider->width, divider->flags); +} + +static int mango_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + unsigned int value; + unsigned int val; + unsigned long flags = 0; + struct mango_clk_divider *divider = to_mango_clk_divider(hw); + + value = divider_get_val(rate, parent_rate, divider->table, + divider->width, divider->flags); + + if (divider->lock) + spin_lock_irqsave(divider->lock, flags); + else + __acquire(divider->lock); + + /* div assert */ + val = readl(divider->reg); + val &= ~0x1; + writel(val, divider->reg); + + if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { + val = div_mask(divider->width) << (divider->shift + 16); + } else { + val = readl(divider->reg); + val &= ~(div_mask(divider->width) << divider->shift); + } + + val |= value << divider->shift; + writel(val, divider->reg); + + if (!(divider->flags & CLK_DIVIDER_READ_ONLY)) + val |= 1 << 3; + + /* de-assert */ + val |= 1; + writel(val, divider->reg); + if (divider->lock) + spin_unlock_irqrestore(divider->lock, flags); + else + __release(divider->lock); + + return 0; +} + +/* Below array is the total combination lists of POSTDIV1 and POSTDIV2 + * for example: + * postdiv1_2[0] = {1, 1, 1} + * ==> div1 = 1, div2 = 1 , div1 * div2 = 1 + * postdiv1_2[22] = {6, 7, 42} + * ==> div1 = 6, div2 = 7 , div1 * div2 = 42 + * + * And POSTDIV_RESULT_INDEX point to 3rd element in the array + */ +#define POSTDIV_RESULT_INDEX 2 +int postdiv1_2[][3] = { + {2, 4, 8}, {3, 3, 9}, {2, 5, 10}, {2, 6, 12}, + {2, 7, 14}, {3, 5, 15}, {4, 4, 16}, {3, 6, 18}, + {4, 5, 20}, {3, 7, 21}, {4, 6, 24}, {5, 5, 25}, + {4, 7, 28}, {5, 6, 30}, {5, 7, 35}, {6, 6, 36}, + {6, 7, 42}, {7, 7, 49} +}; + +/* + * @reg_value: current register value + * @parent_rate: parent frequency + * + * This function is used to calculate below "rate" in equation + * rate = (parent_rate/REFDIV) x FBDIV/POSTDIV1/POSTDIV2 + * = (parent_rate x FBDIV) / (REFDIV x POSTDIV1 x POSTDIV2) + */ +static unsigned long __pll_recalc_rate(unsigned int reg_value, + unsigned long parent_rate) +{ + unsigned int fbdiv, refdiv; + unsigned int postdiv1, postdiv2; + u64 rate, numerator, denominator; + + fbdiv = (reg_value >> 16) & 0xfff; + refdiv = reg_value & 0x3f; + postdiv1 = (reg_value >> 8) & 0x7; + postdiv2 = (reg_value >> 12) & 0x7; + + numerator = parent_rate * fbdiv; + denominator = refdiv * postdiv1 * postdiv2; + do_div(numerator, denominator); + rate = numerator; + + return rate; +} + +/* + * @reg_value: current register value + * @rate: request rate + * @prate: parent rate + * @pctrl_table: use to save div1/div2/fbdiv/refdiv + * + * We use below equation to get POSTDIV1 and POSTDIV2 + * POSTDIV = (parent_rate/REFDIV) x FBDIV/input_rate + * above POSTDIV = POSTDIV1*POSTDIV2 + */ +static int __pll_get_postdiv_1_2(unsigned long rate, unsigned long prate, + unsigned int fbdiv, unsigned int refdiv, unsigned int *postdiv1, + unsigned int *postdiv2) +{ + int index = 0; + int ret = 0; + u64 tmp0; + + /* calculate (parent_rate/refdiv) + * and result save to prate + */ + tmp0 = prate; + do_div(tmp0, refdiv); + + /* calcuate ((parent_rate/REFDIV) x FBDIV) + * and result save to prate + */ + tmp0 *= fbdiv; + + /* calcuate (((parent_rate/REFDIV) x FBDIV)/input_rate) + * and result save to prate + * here *prate is (POSTDIV1*POSTDIV2) + */ + do_div(tmp0, rate); + + /* calculate div1 and div2 value */ + if (tmp0 <= 7) { + /* (div1 * div2) <= 7, no need to use array search */ + *postdiv1 = tmp0; + *postdiv2 = 1; + } else { + /* (div1 * div2) > 7, use array search */ + for (index = 0; index < ARRAY_SIZE(postdiv1_2); index++) { + if (tmp0 > postdiv1_2[index][POSTDIV_RESULT_INDEX]) { + continue; + } else { + /* found it */ + break; + } + } + if (index < ARRAY_SIZE(postdiv1_2)) { + *postdiv1 = postdiv1_2[index][1]; + *postdiv2 = postdiv1_2[index][0]; + } else { + pr_debug("%s out of postdiv array range!\n", __func__); + ret = -ESPIPE; + } + } + + return ret; +} + +static int __get_pll_ctl_setting(struct mango_pll_ctrl *best, + unsigned long req_rate, unsigned long parent_rate) +{ + int ret; + unsigned int fbdiv, refdiv, fref, postdiv1, postdiv2; + unsigned long tmp = 0, foutvco; + + fref = parent_rate; + + for (refdiv = REFDIV_MIN; refdiv < REFDIV_MAX + 1; refdiv++) { + for (fbdiv = FBDIV_MIN; fbdiv < FBDIV_MAX + 1; fbdiv++) { + foutvco = fref * fbdiv / refdiv; + /* check fpostdiv pfd */ + if (foutvco < PLL_FREQ_MIN || foutvco > PLL_FREQ_MAX + || (fref / refdiv) < 10) + continue; + + ret = __pll_get_postdiv_1_2(req_rate, fref, fbdiv, + refdiv, &postdiv1, &postdiv2); + if (ret) + continue; + + tmp = foutvco / (postdiv1 * postdiv2); + if (abs_diff(tmp, req_rate) < abs_diff(best->freq, req_rate)) { + best->freq = tmp; + best->refdiv = refdiv; + best->fbdiv = fbdiv; + best->postdiv1 = postdiv1; + best->postdiv2 = postdiv2; + if (tmp == req_rate) + return 0; + } + continue; + } + } + + return 0; +} + +/* + * @hw: ccf use to hook get mango_pll_clock + * @parent_rate: parent rate + * + * The is function will be called through clk_get_rate + * and return current rate after decoding reg value + */ +static unsigned long mango_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int value; + unsigned long rate; + struct mango_pll_clock *mango_pll = to_mango_pll_clk(hw); + + mango_pll_read(mango_pll->syscon_top, mango_pll->id, &value); + rate = __pll_recalc_rate(value, parent_rate); + return rate; +} + +static long mango_clk_pll_round_rate(struct clk_hw *hw, + unsigned long req_rate, unsigned long *prate) +{ + unsigned int value; + struct mango_pll_ctrl pctrl_table; + struct mango_pll_clock *mango_pll = to_mango_pll_clk(hw); + long proper_rate; + + memset(&pctrl_table, 0, sizeof(struct mango_pll_ctrl)); + + /* use current setting to get fbdiv, refdiv + * then combine with prate, and req_rate to + * get postdiv1 and postdiv2 + */ + mango_pll_read(mango_pll->syscon_top, mango_pll->id, &value); + __get_pll_ctl_setting(&pctrl_table, req_rate, *prate); + if (!pctrl_table.freq) { + proper_rate = 0; + goto out; + } + + value = TOP_PLL_CTRL(pctrl_table.fbdiv, pctrl_table.postdiv1, + pctrl_table.postdiv2, pctrl_table.refdiv); + proper_rate = (long)__pll_recalc_rate(value, *prate); + +out: + return proper_rate; +} + +static int mango_clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + req->rate = mango_clk_pll_round_rate(hw, min(req->rate, req->max_rate), + &req->best_parent_rate); + return 0; +} + +static int mango_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + unsigned long flags; + unsigned int value; + int ret = 0; + struct mango_pll_ctrl pctrl_table; + struct mango_pll_clock *mango_pll = to_mango_pll_clk(hw); + + memset(&pctrl_table, 0, sizeof(struct mango_pll_ctrl)); + spin_lock_irqsave(mango_pll->lock, flags); + if (mango_pll_enable(mango_pll->syscon_top, mango_pll, 0)) { + pr_warn("Can't disable pll(%s), status error\n", mango_pll->name); + goto out; + } + mango_pll_read(mango_pll->syscon_top, mango_pll->id, &value); + __get_pll_ctl_setting(&pctrl_table, rate, parent_rate); + if (!pctrl_table.freq) { + pr_warn("%s: Can't find a proper pll setting\n", mango_pll->name); + goto out; + } + + value = TOP_PLL_CTRL(pctrl_table.fbdiv, pctrl_table.postdiv1, + pctrl_table.postdiv2, pctrl_table.refdiv); + + /* write the value to top register */ + mango_pll_write(mango_pll->syscon_top, mango_pll->id, value); + mango_pll_enable(mango_pll->syscon_top, mango_pll, 1); +out: + spin_unlock_irqrestore(mango_pll->lock, flags); + return ret; +} + +const struct clk_ops mango_clk_divider_ops = { + .recalc_rate = mango_clk_divider_recalc_rate, + .round_rate = mango_clk_divider_round_rate, + .set_rate = mango_clk_divider_set_rate, +}; + +const struct clk_ops mango_clk_divider_ro_ops = { + .recalc_rate = mango_clk_divider_recalc_rate, + .round_rate = mango_clk_divider_round_rate, +}; + +const struct clk_ops mango_clk_pll_ops = { + .recalc_rate = mango_clk_pll_recalc_rate, + .round_rate = mango_clk_pll_round_rate, + .determine_rate = mango_clk_pll_determine_rate, + .set_rate = mango_clk_pll_set_rate, +}; + +const struct clk_ops mango_clk_pll_ro_ops = { + .recalc_rate = mango_clk_pll_recalc_rate, + .round_rate = mango_clk_pll_round_rate, +}; + +struct mux_cb_clk_name { + const char *name; + struct list_head node; +}; + +static struct list_head mux_cb_clk_name_list = + LIST_HEAD_INIT(mux_cb_clk_name_list); +static int mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *data) +{ + int ret = 0; + static unsigned char mux_id = 1; + struct clk_notifier_data *ndata = data; + struct clk_hw *hw = __clk_get_hw(ndata->clk); + const struct clk_ops *ops = &clk_mux_ops; + struct mux_cb_clk_name *cb_lsit; + + if (event == PRE_RATE_CHANGE) { + struct clk_hw *hw_p = clk_hw_get_parent(hw); + + cb_lsit = kmalloc(sizeof(*cb_lsit), GFP_KERNEL); + if (cb_lsit) { + INIT_LIST_HEAD(&cb_lsit->node); + list_add_tail(&cb_lsit->node, &mux_cb_clk_name_list); + } else { + pr_err("mux cb kmalloc mem fail\n"); + goto out; + } + + cb_lsit->name = clk_hw_get_name(hw_p); + mux_id = ops->get_parent(hw); + if (mux_id > 1) { + ret = 1; + goto out; + } + ops->set_parent(hw, !mux_id); + } else if (event == POST_RATE_CHANGE) { + struct clk_hw *hw_p = clk_hw_get_parent(hw); + + cb_lsit = list_first_entry_or_null(&mux_cb_clk_name_list, + typeof(*cb_lsit), node); + if (cb_lsit) { + const char *pre_name = cb_lsit->name; + + list_del_init(&cb_lsit->node); + kfree(cb_lsit); + if (strcmp(clk_hw_get_name(hw_p), pre_name)) + goto out; + } + + ops->set_parent(hw, mux_id); + } + +out: + return notifier_from_errno(ret); +} + +int set_default_clk_rates(struct device_node *node) +{ + struct of_phandle_args clkspec; + struct property *prop; + const __be32 *cur; + int rc, index = 0; + struct clk *clk; + u32 rate; + + of_property_for_each_u32 (node, "clock-rates", prop, cur, rate) { + if (rate) { + rc = of_parse_phandle_with_args(node, "clocks", + "#clock-cells", index, &clkspec); + if (rc < 0) { + /* skip empty (null) phandles */ + if (rc == -ENOENT) + continue; + else + return rc; + } + + clk = of_clk_get_from_provider(&clkspec); + if (IS_ERR(clk)) { + pr_warn("clk: couldn't get clock %d for %s\n", + index, node->full_name); + return PTR_ERR(clk); + } + + rc = clk_set_rate(clk, rate); + if (rc < 0) + pr_err("clk: couldn't set %s clk rate to %d (%d), current rate: %ld\n", + __clk_get_name(clk), rate, rc, + clk_get_rate(clk)); + clk_put(clk); + } + index++; + } + + return 0; +} + +static struct clk *__register_divider_clks(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 initial_val, + u8 clk_divider_flags, + const struct clk_div_table *table, + spinlock_t *lock) +{ + struct mango_clk_divider *div; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) { + if (width + shift > 16) { + pr_warn("divider value exceeds LOWORD field\n"); + return ERR_PTR(-EINVAL); + } + } + + /* allocate the divider */ + div = kzalloc(sizeof(*div), GFP_KERNEL); + if (!div) + return ERR_PTR(-ENOMEM); + + init.name = name; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops = &mango_clk_divider_ro_ops; + else + init.ops = &mango_clk_divider_ops; + init.flags = flags; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + /* struct mango_clk_divider assignments */ + div->reg = reg; + div->shift = shift; + div->width = width; + div->flags = clk_divider_flags; + div->lock = lock; + div->hw.init = &init; + div->table = table; + div->initial_val = initial_val; + + /* register the clock */ + hw = &div->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(div); + hw = ERR_PTR(ret); + return ERR_PTR(-EBUSY); + } + + return hw->clk; +} + +static inline int register_provider_clks +(struct device_node *node, struct mango_clk_data *clk_data, int clk_num) +{ + return of_clk_add_provider(node, of_clk_src_onecell_get, + &clk_data->clk_data); +} + +static int register_gate_clks(struct device *dev, struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_gate_clock *gate_clks = table->gate_clks; + void __iomem *base = clk_data->base; + int clk_num = table->gate_clks_num; + int i; + + for (i = 0; i < clk_num; i++) { + clk = clk_register_gate( + dev, gate_clks[i].name, gate_clks[i].parent_name, + gate_clks[i].flags, base + gate_clks[i].offset, + gate_clks[i].bit_idx, gate_clks[i].gate_flags, + &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + gate_clks[i].name); + goto err; + } + + if (gate_clks[i].alias) + clk_register_clkdev(clk, gate_clks[i].alias, NULL); + + clk_data->clk_data.clks[gate_clks[i].id] = clk; + } + + return 0; + +err: + while (i--) + clk_unregister_gate(clk_data->clk_data.clks[gate_clks[i].id]); + + return PTR_ERR(clk); +} + +static int register_divider_clks(struct device *dev, + struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_divider_clock *div_clks = table->div_clks; + void __iomem *base = clk_data->base; + int clk_num = table->div_clks_num; + int i, val; + + for (i = 0; i < clk_num; i++) { + clk = __register_divider_clks( + NULL, div_clks[i].name, div_clks[i].parent_name, + div_clks[i].flags, base + div_clks[i].offset, + div_clks[i].shift, div_clks[i].width, + div_clks[i].initial_val, + (div_clks[i].initial_sel & MANGO_CLK_USE_INIT_VAL) ? + div_clks[i].div_flags | CLK_DIVIDER_READ_ONLY : + div_clks[i].div_flags, + div_clks[i].table, &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + div_clks[i].name); + goto err; + } + + clk_data->clk_data.clks[div_clks[i].id] = clk; + + if (div_clks[i].initial_sel == MANGO_CLK_USE_REG_VAL) { + regmap_read(clk_data->syscon_top, div_clks[i].offset, + &val); + + /* + * set a default divider factor, + * clk driver should not select divider clock as the + * clock source, before set the divider by right process + * (assert div, set div factor, de assert div). + */ + if (div_clks[i].initial_val > 0) + val |= (div_clks[i].initial_val << 16 | 1 << 3); + else { + /* + * the div register is config to use divider factor, don't change divider + */ + if (!(val >> 3 & 0x1)) + val |= 1 << 16; + } + + regmap_write(clk_data->syscon_top, div_clks[i].offset, + val); + } + } + + return 0; + +err: + while (i--) + clk_unregister_divider(clk_data->clk_data.clks[div_clks[i].id]); + + return PTR_ERR(clk); +} + +static int register_mux_clks(struct device *dev, struct mango_clk_data *clk_data) +{ + struct clk *clk; + const struct mango_clk_table *table = clk_data->table; + const struct mango_mux_clock *mux_clks = table->mux_clks; + void __iomem *base = clk_data->base; + int clk_num = table->mux_clks_num; + int i; + + for (i = 0; i < clk_num; i++) { + u32 mask = BIT(mux_clks[i].width) - 1; + + clk = clk_register_mux_table( + dev, mux_clks[i].name, mux_clks[i].parent_names, + mux_clks[i].num_parents, mux_clks[i].flags, + base + mux_clks[i].offset, mux_clks[i].shift, mask, + mux_clks[i].mux_flags, mux_clks[i].table, + &clk_data->lock); + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + mux_clks[i].name); + goto err; + } + + clk_data->clk_data.clks[mux_clks[i].id] = clk; + + if (!(mux_clks[i].flags & CLK_MUX_READ_ONLY)) { + struct clk *parent; + struct notifier_block *clk_nb; + + /* set mux clock default parent here, it's parent index + * value is read from the mux clock reg. dts can override + * setting the mux clock parent later. + */ + parent = clk_get_parent(clk); + clk_set_parent(clk, parent); + + /* add a notify callback function */ + clk_nb = kzalloc(sizeof(*clk_nb), GFP_KERNEL); + if (!clk_nb) + goto err; + clk_nb->notifier_call = mux_notifier_cb; + if (clk_notifier_register(clk, clk_nb)) + pr_err("%s: failed to register clock notifier for %s\n", + __func__, mux_clks[i].name); + } + } + + return 0; + +err: + while (i--) + clk_unregister_mux(clk_data->clk_data.clks[mux_clks[i].id]); + + return PTR_ERR(clk); +} + +/* pll clock init */ +int mango_register_pll_clks(struct device_node *node, + struct mango_clk_data *clk_data, const char *clk_name) +{ + struct clk *clk = NULL; + struct mango_pll_clock *pll_clks; + int i, ret = 0; + const struct clk_ops *local_ops; + + pll_clks = (struct mango_pll_clock *)clk_data->table->pll_clks; + for (i = 0; i < clk_data->table->pll_clks_num; i++) { + if (!strcmp(clk_name, pll_clks[i].name)) { + /* have to assigne pll_clks.syscon_top first + * since clk_register_composite will need it + * to calculate current rate. + */ + pll_clks[i].syscon_top = clk_data->syscon_top; + pll_clks[i].lock = &clk_data->lock; + if (pll_clks[i].ini_flags & MANGO_CLK_RO) + local_ops = &mango_clk_pll_ro_ops; + else + local_ops = &mango_clk_pll_ops; + clk = clk_register_composite( + NULL, pll_clks[i].name, &pll_clks[i].parent_name, + 1, NULL, NULL, &pll_clks[i].hw, local_ops, + NULL, NULL, pll_clks[i].flags); + + if (IS_ERR(clk)) { + pr_err("%s: failed to register clock %s\n", __func__, + pll_clks[i].name); + ret = -EINVAL; + goto out; + } + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + clk_unregister(clk); + } else { + continue; + } + } + +out: + return ret; +} + +/* mux clk init */ +int mango_register_mux_clks(struct device_node *node, struct mango_clk_data *clk_data) +{ + int ret; + int count; + struct clk **clk_table; + + count = clk_data->table->mux_clks_num + clk_data->table->gate_clks_num; + clk_table = kcalloc(count, sizeof(*clk_table), GFP_KERNEL); + if (!clk_table) + return -ENOMEM; + + clk_data->clk_data.clks = clk_table; + clk_data->clk_data.clk_num = count; + + ret = register_mux_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_gate_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_provider_clks(node, clk_data, count); + if (ret) + goto err; + + return 0; +err: + kfree(clk_table); + return ret; +} + +/* pll divider init */ +int mango_register_div_clks(struct device_node *node, struct mango_clk_data *clk_data) +{ + int ret; + int count; + + struct clk **clk_table; + + count = clk_data->table->div_clks_num + clk_data->table->gate_clks_num; + clk_table = kcalloc(count, sizeof(*clk_table), GFP_KERNEL); + if (!clk_table) + return -ENOMEM; + + clk_data->clk_data.clks = clk_table; + clk_data->clk_data.clk_num = count; + + ret = register_divider_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_gate_clks(NULL, clk_data); + if (ret) + goto err; + + ret = register_provider_clks(node, clk_data, count); + if (ret) + goto err; + + + return 0; +err: + kfree(clk_table); + pr_err("%s error %d\n", __func__, ret); + return ret; +} diff --git a/drivers/clk/sophgo/clk.h b/drivers/clk/sophgo/clk.h new file mode 100644 index 0000000000000..81e9f9eb1b200 --- /dev/null +++ b/drivers/clk/sophgo/clk.h @@ -0,0 +1,152 @@ +#ifndef __SOPHGO_CLOCK__ +#define __SOPHGO_CLOCK__ + +#include +#include +#include +#include +#include +#include + +#include + +#define KHZ 1000L +#define MHZ (KHZ * KHZ) + +#define MANGO_CLK_USE_INIT_VAL BIT(0) /* use default value */ +#define MANGO_CLK_USE_REG_VAL BIT(1) /* use reg divider value */ +#define MANGO_CLK_RO BIT(2) /* use reg divider value */ + +#define CLK_PLL BIT(0) +#define CLK_MUX BIT(1) + +#define PLL_CTRL_OFFSET 0xE8 +#define PLL_STAT_LOCK_OFFSET 0x8 +#define CLK_MODE 0x4 +#define CLK_MODE_MASK 0x3 + +#define REFDIV_MIN 1 +#define REFDIV_MAX 64 +#define FBDIV_MIN 16 +#define FBDIV_MAX 321 + +#define PLL_FREQ_MIN (16 * MHZ) +#define PLL_FREQ_MAX (3200 * MHZ) + +#define div_mask(width) ((1 << (width)) - 1) +#define TOP_PLL_CTRL(fbdiv, p1, p2, refdiv) \ + (((fbdiv & 0xfff) << 16) | ((p2 & 0x7) << 12) | ((p1 & 0x7) << 8) | (refdiv & 0x3f)) + +struct mango_pll_ctrl { + unsigned int mode; + unsigned long freq; + + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int postdiv2; + unsigned int refdiv; +}; + +struct mango_pll_clock { + unsigned int id; + char *name; + const char *parent_name; + unsigned long flags; + struct clk_hw hw; + struct regmap *syscon_top; + + /* Below lock used to protect PLL top register during write */ + spinlock_t *lock; + u32 ini_flags; + + u32 status_offset; + u32 enable_offset; + + struct mango_pll_ctrl pctrl_table[4]; +}; + +#define to_mango_pll_clk(_hw) container_of(_hw, struct mango_pll_clock, hw) + +#define to_mango_clk_divider(_hw) \ + container_of(_hw, struct mango_clk_divider, hw) + +#define to_mango_clk_mux(nb) \ + container_of(nb, struct mango_mux_clock, clk_nb) + +struct mango_divider_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 div_flags; + u32 initial_sel; + u32 initial_val; + struct clk_div_table *table; +}; + +struct mango_mux_clock { + unsigned int id; + const char *name; + const char *const *parent_names; + u8 num_parents; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 mux_flags; + u32 *table; + + struct notifier_block clk_nb; +}; + +struct mango_gate_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 bit_idx; + u8 gate_flags; + const char *alias; +}; + +struct mango_clk_table { + u32 id; + u32 pll_clks_num; + u32 div_clks_num; + u32 gate_clks_num; + u32 mux_clks_num; + + const struct mango_pll_clock *pll_clks; + const struct mango_divider_clock *div_clks; + const struct mango_gate_clock *gate_clks; + const struct mango_mux_clock *mux_clks; +}; + +struct mango_clk_data { + void __iomem *base; + spinlock_t lock; + struct regmap *syscon_top; + struct clk_onecell_data clk_data; + const struct mango_clk_table *table; +}; + +int mango_register_mux_clks +(struct device_node *node, struct mango_clk_data *clk_data); +int mango_register_div_clks +(struct device_node *node, struct mango_clk_data *clk_data); +int mango_register_pll_clks +(struct device_node *node, struct mango_clk_data *clk_data, const char *clk_name); +int set_default_clk_rates(struct device_node *node); + +int dm_mango_register_mux_clks +(struct device_node *node, struct mango_clk_data *clk_data); +int dm_mango_register_div_clks +(struct device_node *node, struct mango_clk_data *clk_data); +int dm_mango_register_pll_clks +(struct device_node *node, struct mango_clk_data *clk_data, const char *name); +int dm_set_default_clk_rates(struct device_node *node); +#endif diff --git a/include/dt-bindings/clock/sophgo-mango-clock.h b/include/dt-bindings/clock/sophgo-mango-clock.h new file mode 100644 index 0000000000000..aaed4ad27dc1e --- /dev/null +++ b/include/dt-bindings/clock/sophgo-mango-clock.h @@ -0,0 +1,165 @@ +#ifndef __SOPHGO_MANGO_CLOCK__ +#define __SOPHGO_MANGO_CLOCK__ + +#include + +/*div clock*/ +#define DIV_CLK_MPLL_RP_CPU_NORMAL_0 0 +#define DIV_CLK_MPLL_AXI_DDR_0 1 +#define DIV_CLK_FPLL_DDR01_1 2 +#define DIV_CLK_FPLL_DDR23_1 3 +#define DIV_CLK_FPLL_RP_CPU_NORMAL_1 4 +#define DIV_CLK_FPLL_50M_A53 5 +#define DIV_CLK_FPLL_TOP_RP_CMN_DIV2 6 +#define DIV_CLK_FPLL_UART_500M 7 +#define DIV_CLK_FPLL_AHB_LPC 8 +#define DIV_CLK_FPLL_EFUSE 9 +#define DIV_CLK_FPLL_TX_ETH0 10 +#define DIV_CLK_FPLL_PTP_REF_I_ETH0 11 +#define DIV_CLK_FPLL_REF_ETH0 12 +#define DIV_CLK_FPLL_EMMC 13 +#define DIV_CLK_FPLL_SD 14 +#define DIV_CLK_FPLL_TOP_AXI0 15 +#define DIV_CLK_FPLL_TOP_AXI_HSPERI 16 +#define DIV_CLK_FPLL_AXI_DDR_1 17 +#define DIV_CLK_FPLL_DIV_TIMER1 18 +#define DIV_CLK_FPLL_DIV_TIMER2 19 +#define DIV_CLK_FPLL_DIV_TIMER3 20 +#define DIV_CLK_FPLL_DIV_TIMER4 21 +#define DIV_CLK_FPLL_DIV_TIMER5 22 +#define DIV_CLK_FPLL_DIV_TIMER6 23 +#define DIV_CLK_FPLL_DIV_TIMER7 24 +#define DIV_CLK_FPLL_DIV_TIMER8 25 +#define DIV_CLK_FPLL_100K_EMMC 26 +#define DIV_CLK_FPLL_100K_SD 27 +#define DIV_CLK_FPLL_GPIO_DB 28 +#define DIV_CLK_DPLL0_DDR01_0 29 +#define DIV_CLK_DPLL1_DDR23_0 30 + +/* MPLL */ +#define GATE_CLK_RP_CPU_NORMAL_DIV0 31 +#define GATE_CLK_AXI_DDR_DIV0 32 + +/* FPLL */ +#define GATE_CLK_RP_CPU_NORMAL_DIV1 33 +#define GATE_CLK_A53_50M 34 +#define GATE_CLK_TOP_RP_CMN_DIV2 35 +#define GATE_CLK_HSDMA 36 +#define GATE_CLK_EMMC_100M 37 +#define GATE_CLK_SD_100M 38 +#define GATE_CLK_TX_ETH0 39 +#define GATE_CLK_PTP_REF_I_ETH0 40 +#define GATE_CLK_REF_ETH0 41 +#define GATE_CLK_UART_500M 42 +#define GATE_CLK_EFUSE 43 + +#define GATE_CLK_AHB_LPC 44 +#define GATE_CLK_AHB_ROM 45 +#define GATE_CLK_AHB_SF 46 + +#define GATE_CLK_APB_UART 47 +#define GATE_CLK_APB_TIMER 48 +#define GATE_CLK_APB_EFUSE 49 +#define GATE_CLK_APB_GPIO 50 +#define GATE_CLK_APB_GPIO_INTR 51 +#define GATE_CLK_APB_SPI 52 +#define GATE_CLK_APB_I2C 53 +#define GATE_CLK_APB_WDT 54 +#define GATE_CLK_APB_PWM 55 +#define GATE_CLK_APB_RTC 56 + +#define GATE_CLK_AXI_PCIE0 57 +#define GATE_CLK_AXI_PCIE1 58 +#define GATE_CLK_SYSDMA_AXI 59 +#define GATE_CLK_AXI_DBG_I2C 60 +#define GATE_CLK_AXI_SRAM 61 +#define GATE_CLK_AXI_ETH0 62 +#define GATE_CLK_AXI_EMMC 63 +#define GATE_CLK_AXI_SD 64 +#define GATE_CLK_TOP_AXI0 65 +#define GATE_CLK_TOP_AXI_HSPERI 66 + +#define GATE_CLK_TIMER1 67 +#define GATE_CLK_TIMER2 68 +#define GATE_CLK_TIMER3 69 +#define GATE_CLK_TIMER4 70 +#define GATE_CLK_TIMER5 71 +#define GATE_CLK_TIMER6 72 +#define GATE_CLK_TIMER7 73 +#define GATE_CLK_TIMER8 74 +#define GATE_CLK_100K_EMMC 75 +#define GATE_CLK_100K_SD 76 +#define GATE_CLK_GPIO_DB 77 + +#define GATE_CLK_AXI_DDR_DIV1 78 +#define GATE_CLK_DDR01_DIV1 79 +#define GATE_CLK_DDR23_DIV1 80 +/* DPLL0 */ +#define GATE_CLK_DDR01_DIV0 81 +/* DPLL1 */ +#define GATE_CLK_DDR23_DIV0 82 + +#define GATE_CLK_DDR01 83 +#define GATE_CLK_DDR23 84 +#define GATE_CLK_RP_CPU_NORMAL 85 +#define GATE_CLK_AXI_DDR 86 +#define GATE_CLK_RXU0 87 +#define GATE_CLK_RXU1 88 +#define GATE_CLK_RXU2 89 +#define GATE_CLK_RXU3 90 +#define GATE_CLK_RXU4 91 +#define GATE_CLK_RXU5 92 +#define GATE_CLK_RXU6 93 +#define GATE_CLK_RXU7 94 +#define GATE_CLK_RXU8 95 +#define GATE_CLK_RXU9 96 +#define GATE_CLK_RXU10 97 +#define GATE_CLK_RXU11 98 +#define GATE_CLK_RXU12 99 +#define GATE_CLK_RXU13 100 +#define GATE_CLK_RXU14 101 +#define GATE_CLK_RXU15 102 +#define GATE_CLK_RXU16 103 +#define GATE_CLK_RXU17 104 +#define GATE_CLK_RXU18 105 +#define GATE_CLK_RXU19 106 +#define GATE_CLK_RXU20 107 +#define GATE_CLK_RXU21 108 +#define GATE_CLK_RXU22 109 +#define GATE_CLK_RXU23 110 +#define GATE_CLK_RXU24 111 +#define GATE_CLK_RXU25 112 +#define GATE_CLK_RXU26 113 +#define GATE_CLK_RXU27 114 +#define GATE_CLK_RXU28 115 +#define GATE_CLK_RXU29 116 +#define GATE_CLK_RXU30 117 +#define GATE_CLK_RXU31 118 +#define GATE_CLK_MP0 119 +#define GATE_CLK_MP1 120 +#define GATE_CLK_MP2 121 +#define GATE_CLK_MP3 122 +#define GATE_CLK_MP4 123 +#define GATE_CLK_MP5 124 +#define GATE_CLK_MP6 125 +#define GATE_CLK_MP7 126 +#define GATE_CLK_MP8 127 +#define GATE_CLK_MP9 128 +#define GATE_CLK_MP10 129 +#define GATE_CLK_MP11 130 +#define GATE_CLK_MP12 131 +#define GATE_CLK_MP13 132 +#define GATE_CLK_MP14 133 +#define GATE_CLK_MP15 134 + +/* MUX */ +#define MUX_CLK_DDR01 0 +#define MUX_CLK_DDR23 1 +#define MUX_CLK_RP_CPU_NORMAL 2 +#define MUX_CLK_AXI_DDR 3 + +#define S0_DIV_CLK_TABLE 0 +#define S1_DIV_CLK_TABLE 1 +#define S0_MUX_CLK_TABLE 2 +#define S1_MUX_CLK_TABLE 3 +#endif diff --git a/include/dt-bindings/clock/sophgo.h b/include/dt-bindings/clock/sophgo.h new file mode 100644 index 0000000000000..5584243f9135b --- /dev/null +++ b/include/dt-bindings/clock/sophgo.h @@ -0,0 +1,15 @@ +#ifndef __SOPHGO_CLK__ +#define __SOPHGO_CLK__ + +//PLL ID +#define MPLL_CLK 0 +#define FPLL_CLK 3 +#define DPLL0_CLK 4 +#define DPLL1_CLK 5 + +//clock mode +#define NORMAL_MODE 0 +#define FAST_MODE 1 +#define SAFE_MODE 2 +#define BYPASS_MODE 3 +#endif From d2cfc74410b8f3d35249ae40ee1d7f7f66ccdc2d Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 10:45:09 +0800 Subject: [PATCH 12/40] driver: pinctrl: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/Makefile | 1 + drivers/pinctrl/sophgo/Makefile | 2 + drivers/pinctrl/sophgo/pinctrl-mango.c | 453 ++++++++++++++++++++++++ drivers/pinctrl/sophgo/pinctrl-sophgo.c | 292 +++++++++++++++ drivers/pinctrl/sophgo/pinctrl-sophgo.h | 70 ++++ 6 files changed, 819 insertions(+), 1 deletion(-) create mode 100644 drivers/pinctrl/sophgo/Makefile create mode 100644 drivers/pinctrl/sophgo/pinctrl-mango.c create mode 100644 drivers/pinctrl/sophgo/pinctrl-sophgo.c create mode 100644 drivers/pinctrl/sophgo/pinctrl-sophgo.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 79753411b778c..7a71b34732128 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -22,7 +22,7 @@ config PINCONF bool "Support pin configuration controllers" if COMPILE_TEST config GENERIC_PINCONF - bool + bool "GENERIC_PINCONF" select PINCONF config DEBUG_PINCTRL diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4275eca92488e..f3f990a61229f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_SOC_STARFIVE) += starfive/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_ARCH_SOPHGO) += sophgo/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ diff --git a/drivers/pinctrl/sophgo/Makefile b/drivers/pinctrl/sophgo/Makefile new file mode 100644 index 0000000000000..2f2cd0d5a99d1 --- /dev/null +++ b/drivers/pinctrl/sophgo/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARCH_SOPHGO) += pinctrl-sophgo.o +obj-$(CONFIG_ARCH_SOPHGO) += pinctrl-mango.o diff --git a/drivers/pinctrl/sophgo/pinctrl-mango.c b/drivers/pinctrl/sophgo/pinctrl-mango.c new file mode 100644 index 0000000000000..8e7bd08a73db2 --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-mango.c @@ -0,0 +1,453 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pinctrl-utils.h" +#include "pinctrl-sophgo.h" + +#define DRV_PINCTRL_NAME "mango_pinctrl" +#define DRV_PINMUX_NAME "mango_pinmux" + +#define FUNCTION(fname, gname, fmode) \ + { \ + .name = #fname, \ + .groups = gname##_group, \ + .num_groups = ARRAY_SIZE(gname##_group), \ + .mode = fmode, \ + } + +#define PIN_GROUP(gname) \ + { \ + .name = #gname "_grp", \ + .pins = gname##_pins, \ + .num_pins = ARRAY_SIZE(gname##_pins), \ + } + +static const struct pinctrl_pin_desc mango_pins[] = { + PINCTRL_PIN(0, "MIO0"), + PINCTRL_PIN(1, "MIO1"), + PINCTRL_PIN(2, "MIO2"), + PINCTRL_PIN(3, "MIO3"), + PINCTRL_PIN(4, "MIO4"), + PINCTRL_PIN(5, "MIO5"), + PINCTRL_PIN(6, "MIO6"), + PINCTRL_PIN(7, "MIO7"), + PINCTRL_PIN(8, "MIO8"), + PINCTRL_PIN(9, "MIO9"), + PINCTRL_PIN(10, "MIO10"), + PINCTRL_PIN(11, "MIO11"), + PINCTRL_PIN(12, "MIO12"), + PINCTRL_PIN(13, "MIO13"), + PINCTRL_PIN(14, "MIO14"), + PINCTRL_PIN(15, "MIO15"), + PINCTRL_PIN(16, "MIO16"), + PINCTRL_PIN(17, "MIO17"), + PINCTRL_PIN(18, "MIO18"), + PINCTRL_PIN(19, "MIO19"), + PINCTRL_PIN(20, "MIO20"), + PINCTRL_PIN(21, "MIO21"), + PINCTRL_PIN(22, "MIO22"), + PINCTRL_PIN(23, "MIO23"), + PINCTRL_PIN(24, "MIO24"), + PINCTRL_PIN(25, "MIO25"), + PINCTRL_PIN(26, "MIO26"), + PINCTRL_PIN(27, "MIO27"), + PINCTRL_PIN(28, "MIO28"), + PINCTRL_PIN(29, "MIO29"), + PINCTRL_PIN(30, "MIO30"), + PINCTRL_PIN(31, "MIO31"), + PINCTRL_PIN(32, "MIO32"), + PINCTRL_PIN(33, "MIO33"), + PINCTRL_PIN(34, "MIO34"), + PINCTRL_PIN(35, "MIO35"), + PINCTRL_PIN(36, "MIO36"), + PINCTRL_PIN(37, "MIO37"), + PINCTRL_PIN(38, "MIO38"), + PINCTRL_PIN(39, "MIO39"), + PINCTRL_PIN(40, "MIO40"), + PINCTRL_PIN(41, "MIO41"), + PINCTRL_PIN(42, "MIO42"), + PINCTRL_PIN(43, "MIO43"), + PINCTRL_PIN(44, "MIO44"), + PINCTRL_PIN(45, "MIO45"), + PINCTRL_PIN(46, "MIO46"), + PINCTRL_PIN(47, "MIO47"), + PINCTRL_PIN(48, "MIO48"), + PINCTRL_PIN(49, "MIO49"), + PINCTRL_PIN(50, "MIO50"), + PINCTRL_PIN(51, "MIO51"), + PINCTRL_PIN(52, "MIO52"), + PINCTRL_PIN(53, "MIO53"), + PINCTRL_PIN(54, "MIO54"), + PINCTRL_PIN(55, "MIO55"), + PINCTRL_PIN(56, "MIO56"), + PINCTRL_PIN(57, "MIO57"), + PINCTRL_PIN(58, "MIO58"), + PINCTRL_PIN(59, "MIO59"), + PINCTRL_PIN(60, "MIO60"), + PINCTRL_PIN(61, "MIO61"), + PINCTRL_PIN(62, "MIO62"), + PINCTRL_PIN(63, "MIO63"), + PINCTRL_PIN(64, "MIO64"), + PINCTRL_PIN(65, "MIO65"), + PINCTRL_PIN(66, "MIO66"), + PINCTRL_PIN(67, "MIO67"), + PINCTRL_PIN(68, "MIO68"), + PINCTRL_PIN(69, "MIO69"), + PINCTRL_PIN(70, "MIO70"), + PINCTRL_PIN(71, "MIO71"), + PINCTRL_PIN(72, "MIO72"), + PINCTRL_PIN(73, "MIO73"), + PINCTRL_PIN(74, "MIO74"), + PINCTRL_PIN(75, "MIO75"), + PINCTRL_PIN(76, "MIO76"), + PINCTRL_PIN(77, "MIO77"), + PINCTRL_PIN(78, "MIO78"), + PINCTRL_PIN(79, "MIO79"), + PINCTRL_PIN(80, "MIO80"), + PINCTRL_PIN(81, "MIO81"), + PINCTRL_PIN(82, "MIO82"), + PINCTRL_PIN(83, "MIO83"), + PINCTRL_PIN(84, "MIO84"), + PINCTRL_PIN(85, "MIO85"), + PINCTRL_PIN(86, "MIO86"), + PINCTRL_PIN(87, "MIO87"), + PINCTRL_PIN(88, "MIO88"), + PINCTRL_PIN(89, "MIO89"), + PINCTRL_PIN(90, "MIO90"), + PINCTRL_PIN(91, "MIO91"), + PINCTRL_PIN(92, "MIO92"), + PINCTRL_PIN(93, "MIO93"), + PINCTRL_PIN(94, "MIO94"), + PINCTRL_PIN(95, "MIO95"), + PINCTRL_PIN(96, "MIO96"), + PINCTRL_PIN(97, "MIO97"), + PINCTRL_PIN(98, "MIO98"), + PINCTRL_PIN(99, "MIO99"), + PINCTRL_PIN(100, "MIO100"), + PINCTRL_PIN(101, "MIO101"), + PINCTRL_PIN(102, "MIO102"), + PINCTRL_PIN(103, "MIO103"), + PINCTRL_PIN(104, "MIO104"), + PINCTRL_PIN(105, "MIO105"), + PINCTRL_PIN(106, "MIO106"), + PINCTRL_PIN(107, "MIO107"), + PINCTRL_PIN(108, "MIO108"), + PINCTRL_PIN(109, "MIO109"), + PINCTRL_PIN(110, "MIO110"), + PINCTRL_PIN(111, "MIO111"), + PINCTRL_PIN(112, "MIO112"), + PINCTRL_PIN(113, "MIO113"), + PINCTRL_PIN(114, "MIO114"), + PINCTRL_PIN(115, "MIO115"), + PINCTRL_PIN(116, "MIO116"), + PINCTRL_PIN(117, "MIO117"), + PINCTRL_PIN(118, "MIO118"), + PINCTRL_PIN(119, "MIO119"), + PINCTRL_PIN(120, "MIO120"), + PINCTRL_PIN(121, "MIO121"), + PINCTRL_PIN(122, "MIO122"), + PINCTRL_PIN(123, "MIO123"), + PINCTRL_PIN(124, "MIO124"), + PINCTRL_PIN(125, "MIO125"), + PINCTRL_PIN(126, "MIO126"), + PINCTRL_PIN(127, "MIO127"), + PINCTRL_PIN(128, "MIO128"), + PINCTRL_PIN(129, "MIO129"), + PINCTRL_PIN(130, "MIO130"), + PINCTRL_PIN(131, "MIO131"), + PINCTRL_PIN(132, "MIO132"), + PINCTRL_PIN(133, "MIO133"), + PINCTRL_PIN(134, "MIO134"), + PINCTRL_PIN(135, "MIO135"), + PINCTRL_PIN(136, "MIO136"), + PINCTRL_PIN(137, "MIO137"), + PINCTRL_PIN(138, "MIO138"), + PINCTRL_PIN(139, "MIO139"), + PINCTRL_PIN(140, "MIO140"), + PINCTRL_PIN(141, "MIO141"), + PINCTRL_PIN(142, "MIO142"), + PINCTRL_PIN(143, "MIO143"), + PINCTRL_PIN(144, "MIO144"), + PINCTRL_PIN(145, "MIO145"), + PINCTRL_PIN(146, "MIO146"), + PINCTRL_PIN(147, "MIO147"), + PINCTRL_PIN(148, "MIO148"), + PINCTRL_PIN(149, "MIO149"), + PINCTRL_PIN(150, "MIO150"), + PINCTRL_PIN(151, "MIO151"), + PINCTRL_PIN(152, "MIO152"), + PINCTRL_PIN(153, "MIO153"), + PINCTRL_PIN(154, "MIO154"), + PINCTRL_PIN(155, "MIO155"), + PINCTRL_PIN(156, "MIO156"), +}; + +static const unsigned int lpc_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}; +static const unsigned int pcie_pins[] = {13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24}; +static const unsigned int spif_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40}; +static const unsigned int emmc_pins[] = {41, 42, 43, 44}; +static const unsigned int sdio_pins[] = {45, 46, 47, 48}; +static const unsigned int eth0_pins[] = {49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64}; +static const unsigned int pwm0_pins[] = {65}; +static const unsigned int pwm1_pins[] = {66}; +static const unsigned int pwm2_pins[] = {67}; +static const unsigned int pwm3_pins[] = {68}; +static const unsigned int fan0_pins[] = {69}; +static const unsigned int fan1_pins[] = {70}; +static const unsigned int fan2_pins[] = {71}; +static const unsigned int fan3_pins[] = {72}; +static const unsigned int i2c0_pins[] = {73, 74}; +static const unsigned int i2c1_pins[] = {75, 76}; +static const unsigned int i2c2_pins[] = {77, 78}; +static const unsigned int i2c3_pins[] = {79, 80}; +static const unsigned int uart0_pins[] = {81, 82, 83, 84}; +static const unsigned int uart1_pins[] = {85, 86, 87, 88}; +static const unsigned int uart2_pins[] = {89, 90, 91, 92}; +static const unsigned int uart3_pins[] = {93, 94, 95, 96}; +static const unsigned int spi0_pins[] = {97, 98, 99, 100, 101}; +static const unsigned int spi1_pins[] = {102, 103, 104, 105, 106}; +static const unsigned int jtag0_pins[] = {107, 108, 109, 110, 111, 112}; +static const unsigned int jtag1_pins[] = {113, 114, 115, 116, 117, 118}; +static const unsigned int jtag2_pins[] = {119, 120, 121, 122, 123, 124}; +static const unsigned int gpio0_pins[] = {125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,\ + 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150,\ + 151, 152, 153}; +static const unsigned int dbgi2c_pins[] = {154, 155, 156}; + +static const char * const lpc_group[] = {"lpc_grp"}; +static const char * const pcie_group[] = {"pcie_grp"}; +static const char * const spif_group[] = {"spif_grp"}; +static const char * const emmc_group[] = {"emmc_grp"}; +static const char * const sdio_group[] = {"sdio_grp"}; +static const char * const eth0_group[] = {"eth0_grp"}; +static const char * const pwm0_group[] = {"pwm0_grp"}; +static const char * const pwm1_group[] = {"pwm1_grp"}; +static const char * const pwm2_group[] = {"pwm2_grp"}; +static const char * const pwm3_group[] = {"pwm3_grp"}; +static const char * const fan0_group[] = {"fan0_grp"}; +static const char * const fan1_group[] = {"fan1_grp"}; +static const char * const fan2_group[] = {"fan2_grp"}; +static const char * const fan3_group[] = {"fan3_grp"}; +static const char * const i2c0_group[] = {"i2c0_grp"}; +static const char * const i2c1_group[] = {"i2c1_grp"}; +static const char * const i2c2_group[] = {"i2c2_grp"}; +static const char * const i2c3_group[] = {"i2c3_grp"}; +static const char * const uart0_group[] = {"uart0_grp"}; +static const char * const uart1_group[] = {"uart1_grp"}; +static const char * const uart2_group[] = {"uart2_grp"}; +static const char * const uart3_group[] = {"uart3_grp"}; +static const char * const spi0_group[] = {"spi0_grp"}; +static const char * const spi1_group[] = {"spi1_grp"}; +static const char * const jtag0_group[] = {"jtag0_grp"}; +static const char * const jtag1_group[] = {"jtag1_grp"}; +static const char * const jtag2_group[] = {"jtag2_grp"}; +static const char * const gpio0_group[] = {"gpio0_grp"}; +static const char * const dbgi2c_group[] = {"dbgi2c_grp"}; + +static struct mango_group mango_groups[] = { + PIN_GROUP(lpc), + PIN_GROUP(pcie), + PIN_GROUP(spif), + PIN_GROUP(emmc), + PIN_GROUP(sdio), + PIN_GROUP(eth0), + PIN_GROUP(pwm0), + PIN_GROUP(pwm1), + PIN_GROUP(pwm2), + PIN_GROUP(pwm3), + PIN_GROUP(fan0), + PIN_GROUP(fan1), + PIN_GROUP(fan2), + PIN_GROUP(fan3), + PIN_GROUP(i2c0), + PIN_GROUP(i2c1), + PIN_GROUP(i2c2), + PIN_GROUP(i2c3), + PIN_GROUP(uart0), + PIN_GROUP(uart1), + PIN_GROUP(uart2), + PIN_GROUP(uart3), + PIN_GROUP(spi0), + PIN_GROUP(spi1), + PIN_GROUP(jtag0), + PIN_GROUP(jtag1), + PIN_GROUP(jtag2), + PIN_GROUP(gpio0), + PIN_GROUP(dbgi2c), +}; + +static const struct mango_pmx_func mango_funcs[] = { + FUNCTION(lpc_a, lpc, FUNC_MODE0), + FUNCTION(lpc_r, lpc, FUNC_MODE1), + FUNCTION(pcie_a, pcie, FUNC_MODE0), + FUNCTION(pcie_r, pcie, FUNC_MODE1), + FUNCTION(spif_a, spif, FUNC_MODE0), + FUNCTION(spif_r, spif, FUNC_MODE1), + FUNCTION(emmc_a, emmc, FUNC_MODE0), + FUNCTION(emmc_r, emmc, FUNC_MODE1), + FUNCTION(sdio_a, sdio, FUNC_MODE0), + FUNCTION(sdio_r, sdio, FUNC_MODE1), + FUNCTION(eth0_a, eth0, FUNC_MODE1), + FUNCTION(eth0_r, eth0, FUNC_MODE0), + FUNCTION(pwm0_a, pwm0, FUNC_MODE0), + FUNCTION(pwm0_r, pwm0, FUNC_MODE1), + FUNCTION(pwm1_a, pwm1, FUNC_MODE0), + FUNCTION(pwm1_r, pwm1, FUNC_MODE1), + FUNCTION(pwm2_a, pwm2, FUNC_MODE0), + FUNCTION(pwm2_r, pwm2, FUNC_MODE1), + FUNCTION(pwm3_a, pwm3, FUNC_MODE0), + FUNCTION(pwm3_r, pwm3, FUNC_MODE1), + FUNCTION(fan0_a, fan0, FUNC_MODE1), + FUNCTION(fan0_r, fan0, FUNC_MODE0), + FUNCTION(fan1_a, fan1, FUNC_MODE1), + FUNCTION(fan1_r, fan1, FUNC_MODE0), + FUNCTION(fan2_a, fan2, FUNC_MODE1), + FUNCTION(fan2_r, fan2, FUNC_MODE0), + FUNCTION(fan3_a, fan3, FUNC_MODE1), + FUNCTION(fan3_r, fan3, FUNC_MODE0), + FUNCTION(i2c0_a, i2c0, FUNC_MODE0), + FUNCTION(i2c0_r, i2c0, FUNC_MODE1), + FUNCTION(i2c1_a, i2c1, FUNC_MODE0), + FUNCTION(i2c1_r, i2c1, FUNC_MODE1), + FUNCTION(i2c2_a, i2c2, FUNC_MODE1), + FUNCTION(i2c2_r, i2c2, FUNC_MODE0), + FUNCTION(i2c3_a, i2c3, FUNC_MODE1), + FUNCTION(i2c3_r, i2c3, FUNC_MODE0), + FUNCTION(uart0_a, uart0, FUNC_MODE0), + FUNCTION(uart0_r, uart0, FUNC_MODE1), + FUNCTION(uart1_a, uart1, FUNC_MODE0), + FUNCTION(uart1_r, uart1, FUNC_MODE1), + FUNCTION(uart2_a, uart2, FUNC_MODE1), + FUNCTION(uart2_r, uart2, FUNC_MODE0), + FUNCTION(uart3_a, uart3, FUNC_MODE1), + FUNCTION(uart3_r, uart3, FUNC_MODE0), + FUNCTION(spi0_a, spi0, FUNC_MODE1), + FUNCTION(spi0_r, spi0, FUNC_MODE0), + FUNCTION(spi1_a, spi1, FUNC_MODE0), + FUNCTION(spi1_r, spi1, FUNC_MODE1), + FUNCTION(jtag0_a, jtag0, FUNC_MODE0), + FUNCTION(jtag0_r, jtag0, FUNC_MODE1), + FUNCTION(jtag1_a, jtag1, FUNC_MODE1), + FUNCTION(jtag1_r, jtag1, FUNC_MODE0), + FUNCTION(jtag2_a, jtag2, FUNC_MODE1), + FUNCTION(jtag2_r, jtag2, FUNC_MODE0), + FUNCTION(gpio0_a, gpio0, FUNC_MODE1), + FUNCTION(gpio0_r, gpio0, FUNC_MODE0), + FUNCTION(dbgi2c_a, dbgi2c, FUNC_MODE0), + FUNCTION(dbgi2c_r, dbgi2c, FUNC_MODE1), +}; + +static struct device_attribute lpc_attr = __ATTR(lpc, 0664, pinmux_show, pinmux_store); +static struct device_attribute pcie_attr = __ATTR(pcie, 0664, pinmux_show, pinmux_store); +static struct device_attribute spif_attr = __ATTR(spif, 0664, pinmux_show, pinmux_store); +static struct device_attribute emmc_attr = __ATTR(emmc, 0664, pinmux_show, pinmux_store); +static struct device_attribute sdio_attr = __ATTR(sdio, 0664, pinmux_show, pinmux_store); +static struct device_attribute eth0_attr = __ATTR(eth0, 0664, pinmux_show, pinmux_store); +static struct device_attribute pwm0_attr = __ATTR(pwm0, 0664, pinmux_show, pinmux_store); +static struct device_attribute pwm1_attr = __ATTR(pwm1, 0664, pinmux_show, pinmux_store); +static struct device_attribute pwm2_attr = __ATTR(pwm2, 0664, pinmux_show, pinmux_store); +static struct device_attribute pwm3_attr = __ATTR(pwm3, 0664, pinmux_show, pinmux_store); +static struct device_attribute fan0_attr = __ATTR(fan0, 0664, pinmux_show, pinmux_store); +static struct device_attribute fan1_attr = __ATTR(fan1, 0664, pinmux_show, pinmux_store); +static struct device_attribute fan2_attr = __ATTR(fan2, 0664, pinmux_show, pinmux_store); +static struct device_attribute fan3_attr = __ATTR(fan3, 0664, pinmux_show, pinmux_store); +static struct device_attribute i2c0_attr = __ATTR(i2c0, 0664, pinmux_show, pinmux_store); +static struct device_attribute i2c1_attr = __ATTR(i2c1, 0664, pinmux_show, pinmux_store); +static struct device_attribute i2c2_attr = __ATTR(i2c2, 0664, pinmux_show, pinmux_store); +static struct device_attribute i2c3_attr = __ATTR(i2c3, 0664, pinmux_show, pinmux_store); +static struct device_attribute uart0_attr = __ATTR(uart0, 0664, pinmux_show, pinmux_store); +static struct device_attribute uart1_attr = __ATTR(uart1, 0664, pinmux_show, pinmux_store); +static struct device_attribute uart2_attr = __ATTR(uart2, 0664, pinmux_show, pinmux_store); +static struct device_attribute uart3_attr = __ATTR(uart3, 0664, pinmux_show, pinmux_store); +static struct device_attribute spi0_attr = __ATTR(spi0, 0664, pinmux_show, pinmux_store); +static struct device_attribute spi1_attr = __ATTR(spi1, 0664, pinmux_show, pinmux_store); +static struct device_attribute jtag0_attr = __ATTR(jtag0, 0664, pinmux_show, pinmux_store); +static struct device_attribute jtag1_attr = __ATTR(jtag1, 0664, pinmux_show, pinmux_store); +static struct device_attribute jtag2_attr = __ATTR(jtag2, 0664, pinmux_show, pinmux_store); +static struct device_attribute gpio0_attr = __ATTR(gpio0, 0664, pinmux_show, pinmux_store); +static struct device_attribute dbgi2c_attr = __ATTR(dbgi2c, 0664, pinmux_show, pinmux_store); + + +static struct attribute *pinmux_attrs[] = { + &lpc_attr.attr, + &pcie_attr.attr, + &spif_attr.attr, + &emmc_attr.attr, + &sdio_attr.attr, + ð0_attr.attr, + &pwm0_attr.attr, + &pwm1_attr.attr, + &pwm2_attr.attr, + &pwm3_attr.attr, + &fan0_attr.attr, + &fan1_attr.attr, + &fan2_attr.attr, + &fan3_attr.attr, + &i2c0_attr.attr, + &i2c1_attr.attr, + &i2c2_attr.attr, + &i2c3_attr.attr, + &uart0_attr.attr, + &uart1_attr.attr, + &uart2_attr.attr, + &uart3_attr.attr, + &spi0_attr.attr, + &spi1_attr.attr, + &jtag0_attr.attr, + &jtag1_attr.attr, + &jtag2_attr.attr, + &gpio0_attr.attr, + &dbgi2c_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(pinmux); + +static struct class pinmux_class = { + .name = "pinmux", + .dev_groups = pinmux_groups, +}; + +static struct mango_soc_pinctrl_data mango_pinctrl_data = { + .pins = mango_pins, + .npins = ARRAY_SIZE(mango_pins), + .groups = mango_groups, + .groups_count = ARRAY_SIZE(mango_groups), + .functions = mango_funcs, + .functions_count = ARRAY_SIZE(mango_funcs), + .p_class = &pinmux_class, +}; + +static const struct of_device_id mango_pinctrl_of_table[] = { + { + .compatible = "sophgo, pinctrl-mango", + .data = &mango_pinctrl_data, + }, + {} +}; + +static int mango_pinctrl_probe(struct platform_device *pdev) +{ + return sophgo_pinctrl_probe(pdev); +} + +static struct platform_driver mango_pinctrl_driver = { + .probe = mango_pinctrl_probe, + .driver = { + .name = DRV_PINCTRL_NAME, + .of_match_table = of_match_ptr(mango_pinctrl_of_table), + }, +}; + +static int __init mango_pinctrl_init(void) +{ + return platform_driver_register(&mango_pinctrl_driver); +} +postcore_initcall(mango_pinctrl_init); diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo.c b/drivers/pinctrl/sophgo/pinctrl-sophgo.c new file mode 100644 index 0000000000000..0862177d4144a --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo.c @@ -0,0 +1,292 @@ +#include +#include +#include +#include +#include +#include + +#include "pinctrl-sophgo.h" + + +static int mango_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned int * const num_groups); + +static struct mango_soc_pinctrl_data *get_pinmux_data(struct pinctrl_dev *pctldev) +{ + struct mango_pinctrl *mangopctrl = pinctrl_dev_get_drvdata(pctldev); + + return mangopctrl->data; +} + +static int mango_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + return data->functions_count; +} + +static const char *mango_get_fname(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + return data->functions[selector].name; +} + +static int mango_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + int p; + unsigned int pidx; + u32 offset, regval, mux_offset; + struct mango_pinctrl *ctrl = pinctrl_dev_get_drvdata(pctldev); + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + data->groups[group].cur_func_idx = data->functions[selector].mode; + for (p = 0; p < data->groups[group].num_pins; p++) { + pidx = data->groups[group].pins[p]; + offset = (pidx >> 1) << 2; + regmap_read(ctrl->syscon_pinctl, + ctrl->top_pinctl_offset + offset, ®val); + mux_offset = ((!((pidx + 1) & 1) << 4) + 4); + + regval = regval & ~(3 << mux_offset); + regval |= data->functions[selector].mode << mux_offset; + regmap_write(ctrl->syscon_pinctl, + ctrl->top_pinctl_offset + offset, regval); + regmap_read(ctrl->syscon_pinctl, + ctrl->top_pinctl_offset + offset, ®val); + dev_dbg(ctrl->dev, "%s : check new reg=0x%x val=0x%x\n", + data->groups[group].name, + ctrl->top_pinctl_offset + offset, regval); + } + + return 0; +} + +static const struct pinmux_ops mango_pinmux_ops = { + .get_functions_count = mango_get_functions_count, + .get_function_name = mango_get_fname, + .get_function_groups = mango_get_groups, + .set_mux = mango_set_mux, + .strict = true, +}; + +static int mango_pinconf_cfg_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + return 0; +} + +static int mango_pinconf_cfg_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + return 0; +} + +static int mango_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned long *configs, unsigned int num_configs) +{ + return 0; +} + +static const struct pinconf_ops mango_pinconf_ops = { + .is_generic = true, + .pin_config_get = mango_pinconf_cfg_get, + .pin_config_set = mango_pinconf_cfg_set, + .pin_config_group_set = mango_pinconf_group_set, +}; + +static int mango_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + *groups = data->functions[selector].groups; + *num_groups = data->functions[selector].num_groups; + + return 0; +} + +static int mango_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + return data->groups_count; +} + +static const char *mango_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + return data->groups[selector].name; +} + +static int mango_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct mango_soc_pinctrl_data *data = get_pinmux_data(pctldev); + + *pins = data->groups[selector].pins; + *num_pins = data->groups[selector].num_pins; + + return 0; +} + +static void mango_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ +} + +static const struct pinctrl_ops mango_pctrl_ops = { + .get_groups_count = mango_get_groups_count, + .get_group_name = mango_get_group_name, + .get_group_pins = mango_get_group_pins, + .pin_dbg_show = mango_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc mango_desc = { + .name = "mango_pinctrl", + .pctlops = &mango_pctrl_ops, + .pmxops = &mango_pinmux_ops, + .confops = &mango_pinconf_ops, + .owner = THIS_MODULE, +}; + +ssize_t pinmux_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mango_pinctrl *mangopctrl; + int p, ret, group, selector = -1; + struct mango_soc_pinctrl_data *data; + + mangopctrl = dev_get_drvdata(dev); + data = (struct mango_soc_pinctrl_data *)mangopctrl->data; + + for (p = 0; p < data->functions_count; p++) { + if (!strncmp(attr->attr.name, data->functions[p].name, + strlen(attr->attr.name))) { + selector = p; + break; + } + } + if (selector < 0) + return -ENXIO; + + group = selector/2; + ret = snprintf(buf, 128, "%d\n", data->groups[group].cur_func_idx); + if (ret <= 0 || ret > 128) { + dev_err(dev, "snprintf failed %d\n", ret); + return -EFAULT; + } + return ret; +} + +ssize_t pinmux_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct mango_pinctrl *mangopctrl; + int p, ret, group, selector = -1; + unsigned long user_data; + struct mango_soc_pinctrl_data *data; + + ret = kstrtoul(buf, 0, &user_data); + if (ret) + return -EINVAL; + + if (user_data != 0 && user_data != 1) + return -EINVAL; + + mangopctrl = dev_get_drvdata(dev); + data = (struct mango_soc_pinctrl_data *)mangopctrl->data; + + for (p = 0; p < data->functions_count; p++) { + if (!strncmp(attr->attr.name, data->functions[p].name, + strlen(attr->attr.name)) && + (user_data == data->functions[p].mode)) { + selector = p; + break; + } + } + if (selector < 0) + return -ENXIO; + + group = selector/2; + mango_set_mux(mangopctrl->pctl, selector, group); + + dev_info(dev, "pinmux store set %s to func %d\n", + attr->attr.name, data->functions[selector].mode); + return size; +} + + +int sophgo_pinctrl_probe(struct platform_device *pdev) +{ + struct mango_pinctrl *mangopctrl; + struct pinctrl_desc *desc; + struct mango_soc_pinctrl_data *data; + struct device *dev = &pdev->dev; + struct device *pin_dev = NULL; + struct device_node *np = dev->of_node, *np_top; + static struct regmap *syscon; + int ret; + + data = (struct mango_soc_pinctrl_data *)of_device_get_match_data(&pdev->dev); + if (!data) + return -EINVAL; + mangopctrl = devm_kzalloc(&pdev->dev, sizeof(*mangopctrl), GFP_KERNEL); + if (!mangopctrl) + return -ENOMEM; + + mangopctrl->dev = &pdev->dev; + + np_top = of_parse_phandle(np, "subctrl-syscon", 0); + if (!np_top) { + dev_err(dev, "%s can't get subctrl-syscon node\n", __func__); + return -EINVAL; + } + syscon = syscon_node_to_regmap(np_top); + if (IS_ERR(syscon)) { + dev_err(dev, "cannot get regmap\n"); + return PTR_ERR(syscon); + } + mangopctrl->syscon_pinctl = syscon; + + ret = device_property_read_u32(&pdev->dev, + "top_pinctl_offset", &mangopctrl->top_pinctl_offset); + if (ret < 0) { + dev_err(dev, "cannot get top_pinctl_offset\n"); + return ret; + } + + desc = &mango_desc; + desc->pins = data->pins; + desc->npins = data->npins; + + mangopctrl->data = (void *)data; + mangopctrl->pctl = devm_pinctrl_register(&pdev->dev, desc, mangopctrl); + if (IS_ERR(mangopctrl->pctl)) { + dev_err(&pdev->dev, "could not register Sophgo pin ctrl driver\n"); + return PTR_ERR(mangopctrl->pctl); + } + + platform_set_drvdata(pdev, mangopctrl); + + ret = class_register(data->p_class); + if (ret < 0) { + dev_err(dev, "cannot register pinmux class\n"); + return ret; + } + pin_dev = device_create(data->p_class, &pdev->dev, MKDEV(0, 0), mangopctrl, "mango_pinmux"); + if (IS_ERR(pin_dev)) + return PTR_ERR(pin_dev); + + return 0; +} diff --git a/drivers/pinctrl/sophgo/pinctrl-sophgo.h b/drivers/pinctrl/sophgo/pinctrl-sophgo.h new file mode 100644 index 0000000000000..f3a30f0275b1b --- /dev/null +++ b/drivers/pinctrl/sophgo/pinctrl-sophgo.h @@ -0,0 +1,70 @@ +#ifndef __mango_PINCTRL_CORE_H__ +#define __mango_PINCTRL_CORE_H__ + +#include +#include +#include +#include +#include "../pinctrl-utils.h" +#include "../core.h" + +enum FUNC_MODE { + FUNC_MODE0, + FUNC_MODE1, + FUNC_MODE2, + FUNC_MODE3, + FUNC_MASK, +}; + +struct mango_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + u32 top_pinctl_offset; + struct regmap *syscon_pinctl; + void *data; +}; + +struct mango_group { + const char *name; + const unsigned int *pins; + const unsigned int num_pins; + int cur_func_idx; + struct mango_pmx_func *funcs; +}; + +struct mango_pmx_func { + const char *name; + const char * const *groups; + unsigned int num_groups; + enum FUNC_MODE mode; +}; + +struct mango_soc_pinmux_info { + const char name[16]; + const char name_a[16]; + const char name_r[16]; + struct pinctrl_state *pinctrl_a; + struct pinctrl_state *pinctrl_r; + const unsigned int def_state; /* default state */ + int (*set)(struct device *dev, unsigned int data); +}; + +struct mango_soc_pinctrl_data { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + struct mango_group *groups; + int groups_count; + const struct mango_pmx_func *functions; + int functions_count; + struct class *p_class; +}; + +int sophgo_pinctrl_probe(struct platform_device *pdev); +int mango_pmux_probe(struct platform_device *pdev); + +ssize_t pinmux_show(struct device *dev, + struct device_attribute *attr, char *buf); + +ssize_t pinmux_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size); +#endif From de346810afd6fab3777053df95e55657a6a57821 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 10:46:00 +0800 Subject: [PATCH 13/40] driver: reset: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/reset/Makefile | 1 + drivers/reset/reset-sophgo.c | 163 ++++++++++++++++++ .../dt-bindings/reset/sophgo-mango-resets.h | 96 +++++++++++ 3 files changed, 260 insertions(+) create mode 100644 drivers/reset/reset-sophgo.c create mode 100644 include/dt-bindings/reset/sophgo-mango-resets.h diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8270da8a4baa6..89df585549e09 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o +obj-$(CONFIG_ARCH_SOPHGO) += reset-sophgo.o obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o diff --git a/drivers/reset/reset-sophgo.c b/drivers/reset/reset-sophgo.c new file mode 100644 index 0000000000000..3c46a43e24ba8 --- /dev/null +++ b/drivers/reset/reset-sophgo.c @@ -0,0 +1,163 @@ +/* + * Sophgo SoCs Reset Controller driver + * + * Copyright (c) 2018 Bitmain Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BITS_PER_REG 32 + +struct bm_reset_data { + spinlock_t lock; + void __iomem *membase; + struct reset_controller_dev rcdev; + struct regmap *syscon_rst; + u32 top_rst_offset; +}; + +static int bm_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct bm_reset_data *data = container_of(rcdev, + struct bm_reset_data, + rcdev); + int bank = id / BITS_PER_REG; + int offset = id % BITS_PER_REG; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + regmap_read(data->syscon_rst, data->top_rst_offset + (bank * 4), + ®); + regmap_write(data->syscon_rst, data->top_rst_offset + (bank * 4), + reg & ~BIT(offset)); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int bm_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct bm_reset_data *data = container_of(rcdev, + struct bm_reset_data, + rcdev); + int bank = id / BITS_PER_REG; + int offset = id % BITS_PER_REG; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + regmap_read(data->syscon_rst, data->top_rst_offset + (bank * 4), + ®); + regmap_write(data->syscon_rst, data->top_rst_offset + (bank * 4), + reg | BIT(offset)); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static const struct reset_control_ops bm_reset_ops = { + .assert = bm_reset_assert, + .deassert = bm_reset_deassert, +}; + +static const struct of_device_id bm_reset_dt_ids[] = { + { .compatible = "bitmain,reset", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, bm_reset_dt_ids); + +static int bm_reset_probe(struct platform_device *pdev) +{ + struct bm_reset_data *data; + int ret = 0; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node, *np_top; + static struct regmap *syscon; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + np_top = of_parse_phandle(np, "subctrl-syscon", 0); + if (!np_top) { + dev_err(dev, "%s can't get subctrl-syscon node\n", __func__); + goto out_free_devm; + } + + syscon = syscon_node_to_regmap(np_top); + if (IS_ERR(syscon)) { + dev_err(dev, "cannot get regmap\n"); + goto out_free_devm; + } + + data->syscon_rst = syscon; + ret = device_property_read_u32(&pdev->dev, "top_rst_offset", + &data->top_rst_offset); + if (ret < 0) { + dev_err(dev, "cannot get top_rst_offset\n"); + goto out_free_devm; + } + + ret = device_property_read_u32(&pdev->dev, "nr_resets", + &data->rcdev.nr_resets); + if (ret < 0) { + dev_err(dev, "cannot get nr_resets\n"); + goto out_free_devm; + } + + spin_lock_init(&data->lock); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.ops = &bm_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + ret = devm_reset_controller_register(&pdev->dev, &data->rcdev); + if (!ret) + return 0; + +out_free_devm: + devm_kfree(&pdev->dev, data); + return ret; +} + +static struct platform_driver bm_reset_driver = { + .probe = bm_reset_probe, + .driver = { + .name = "bm-reset", + .of_match_table = bm_reset_dt_ids, + }, +}; + +static int __init bm_reset_init(void) +{ + return platform_driver_register(&bm_reset_driver); +} +postcore_initcall(bm_reset_init); + +MODULE_AUTHOR("Wei Huang"); +MODULE_DESCRIPTION("Bitmain SoC Reset Controoler Driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/reset/sophgo-mango-resets.h b/include/dt-bindings/reset/sophgo-mango-resets.h new file mode 100644 index 0000000000000..9ff8ca4c3d67a --- /dev/null +++ b/include/dt-bindings/reset/sophgo-mango-resets.h @@ -0,0 +1,96 @@ +/* + * Sophgo SoCs Reset definitions + * + * Copyright (c) 2018 Bitmain Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _DT_BINDINGS_RST_MANGO_H_ +#define _DT_BINDINGS_RST_MANGO_H_ + +#define RST_MAIN_AP 0 +#define RST_RISCV_CPU 1 +#define RST_RISCV_LOW_SPEED_LOGIC 2 +#define RST_RISCV_CMN 3 +#define RST_HSDMA 4 +#define RST_SYSDMA 5 +#define RST_EFUSE0 6 +#define RST_EFUSE1 7 +#define RST_RTC 8 +#define RST_TIMER 9 +#define RST_WDT 10 +#define RST_AHB_ROM0 11 +#define RST_AHB_ROM1 12 +#define RST_I2C0 13 +#define RST_I2C1 14 +#define RST_I2C2 15 +#define RST_I2C3 16 +#define RST_GPIO0 17 +#define RST_GPIO1 18 +#define RST_GPIO2 19 +#define RST_PWM 20 +#define RST_AXI_SRAM0 21 +#define RST_AXI_SRAM1 22 +#define RST_SF0 23 +#define RST_SF1 24 +#define RST_LPC 25 +#define RST_ETH0 26 +#define RST_EMMC 27 +#define RST_SD 28 +#define RST_UART0 29 +#define RST_UART1 30 +#define RST_UART2 31 + +#define RST_UART3 32 +#define RST_SPI0 33 +#define RST_SPI1 34 +#define RST_DBG_I2C 35 +#define RST_PCIE0 36 +#define RST_PCIE1 37 +#define RST_DDR0 38 +#define RST_DDR1 39 +#define RST_DDR2 40 +#define RST_DDR3 41 +#define RST_FAU0 42 +#define RST_FAU1 43 +#define RST_FAU2 44 +#define RST_RXU0 45 +#define RST_RXU1 46 +#define RST_RXU2 47 +#define RST_RXU3 48 +#define RST_RXU4 49 +#define RST_RXU5 50 +#define RST_RXU6 51 +#define RST_RXU7 52 +#define RST_RXU8 53 +#define RST_RXU9 54 +#define RST_RXU10 55 +#define RST_RXU11 56 +#define RST_RXU12 57 +#define RST_RXU13 58 +#define RST_RXU14 59 +#define RST_RXU15 60 +#define RST_RXU16 61 +#define RST_RXU17 62 +#define RST_RXU18 63 +#define RST_RXU19 64 +#define RST_RXU20 65 +#define RST_RXU21 66 +#define RST_RXU22 67 +#define RST_RXU23 68 +#define RST_RXU24 69 +#define RST_RXU25 70 +#define RST_RXU26 71 +#define RST_RXU27 72 +#define RST_RXU28 73 +#define RST_RXU29 74 +#define RST_RXU30 75 +#define RST_RXU31 76 + +#define RST_MAX_NUM (RST_RXU31+1) + +#endif From dfc7cc79572c66e83f1e5ebb932f928de74fe0d5 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Thu, 21 Mar 2024 13:54:28 +0800 Subject: [PATCH 14/40] driver: mmc: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/mmc/host/Kconfig | 14 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sophgo.c | 619 ++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-sophgo.h | 121 +++++++ drivers/mmc/host/sdhci.c | 9 + drivers/mmc/host/sdhci.h | 3 + 6 files changed, 767 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sophgo.c create mode 100644 drivers/mmc/host/sdhci-sophgo.h diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index a33cddf20d68b..80106c94cf273 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -654,6 +654,20 @@ config MMC_SDHCI_SPRD If unsure, say N. +config MMC_SDHCI_SOPHGO + tristate "Sophgo/BitMain SDIO host Controller" + depends on MMC_SDHCI_PLTFM + help + This selects the SDIO Host Controller in Sophgo/BitMain + SoCs. + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called sdhci-sophgo. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 87bfbbe6d6c5c..fdefab90781ea 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -98,6 +98,7 @@ obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o +obj-$(CONFIG_MMC_SDHCI_SOPHGO) += sdhci-sophgo.o obj-$(CONFIG_MMC_SUNPLUS) += sunplus-mmc.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o cqhci-y += cqhci-core.o diff --git a/drivers/mmc/host/sdhci-sophgo.c b/drivers/mmc/host/sdhci-sophgo.c new file mode 100644 index 0000000000000..8200ccaa68f67 --- /dev/null +++ b/drivers/mmc/host/sdhci-sophgo.c @@ -0,0 +1,619 @@ +/* + * Sophgo SDHCI Platform driver + * + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include "sdhci-pltfm.h" +#include "sdhci-sophgo.h" + +#define DRIVER_NAME "bm" + +#define BM_SDHCI_VENDOR_OFFSET 0x500 +#define BM_SDHCI_VENDOR_MSHC_CTRL_R (BM_SDHCI_VENDOR_OFFSET + 0x8) +#define BM_SDHCI_VENDOR_A_CTRL_R (BM_SDHCI_VENDOR_OFFSET + 0x40) +#define BM_SDHCI_VENDOR_A_STAT_R (BM_SDHCI_VENDOR_OFFSET + 0x44) + +static void bm_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) +{ + sdhci_writel(host, 0x0, BM_SDHCI_VENDOR_MSHC_CTRL_R); + sdhci_writel(host, 0x18, BM_SDHCI_VENDOR_A_CTRL_R); + sdhci_writel(host, tap, BM_SDHCI_VENDOR_A_STAT_R); +} + +static int sdhci_bm_execute_software_tuning(struct sdhci_host *host, u32 opcode) +{ + unsigned int maxwidth = 0; + unsigned int tuntap; + struct { + unsigned int start; + unsigned int end; + unsigned int width; + } tunlist[4]; + unsigned int listcount; + unsigned int listsel; + + unsigned int tun = 0; + unsigned int max = 256; + int i; + + listcount = 0; + for (i = 0; i < ARRAY_SIZE(tunlist); i++) { + while (tun < max) { + bm_sdhci_set_tap(host, tun); + if (!mmc_send_tuning(host->mmc, opcode, NULL)) + break; + tun++; + } + tunlist[i].start = tun; + tun++; + while (tun < max) { + bm_sdhci_set_tap(host, tun); + if (mmc_send_tuning(host->mmc, opcode, NULL)) + break; + tun++; + } + tunlist[i].end = tun-1; + tunlist[i].width = tunlist[i].end - tunlist[i].start; + listcount++; + tun++; + pr_info("%s id:%d start:%d end:%d width:%d\n", mmc_hostname(host->mmc), + i, tunlist[i].start, tunlist[i].end, tunlist[i].width); + if (tun >= max) + break; + } + + //find maxwidth + listsel = 0; + for (i = 0; i < listcount; i++) { + if (tunlist[i].width > maxwidth) { + maxwidth = tunlist[i].width; + listsel = i; + } + } + tuntap = tunlist[listsel].start + (tunlist[listsel].width/2); + + /* The TRM states the ideal tap value is at 75% in the passing range. */ + bm_sdhci_set_tap(host, tuntap); + pr_info("%s listsel:%d tuntap:%d\n", + mmc_hostname(host->mmc), listsel, tuntap); + + return mmc_send_tuning(host->mmc, opcode, NULL); +} + +static int sdhci_bm_select_drive_strength(struct mmc_card *card, + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type) +{ + struct sdhci_host *host = mmc_priv(card->host); + struct mmc_host *mmc = host->mmc; + uint32_t reg; + int driver_type; + + pr_info("%s max_dtr %d, host_drv %d, card_drv %d, drv_type %d\n", + mmc_hostname(mmc), + max_dtr, host_drv, card_drv, *drv_type); + + driver_type = MMC_SET_DRIVER_TYPE_C; + *drv_type = MMC_SET_DRIVER_TYPE_C; + + reg = (1 << PHY_CNFG_PHY_PWRGOOD) | (0xe << PHY_CNFG_PAD_SP) | + (0xe << PHY_CNFG_PAD_SN) | (1 << PHY_CNFG_PHY_RSTN); + sdhci_writel(host, reg, SDHCI_P_PHY_CNFG); + + return driver_type; +} + +static void sdhci_bm_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) +{ + struct mmc_host *mmc = host->mmc; + u16 ctrl_2; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (uhs) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + } + + /* + * When clock frequency is less than 100MHz, the feedback clock must be + * provided and DLL must not be used so that tuning can be skipped. To + * provide feedback clock, the mode selection can be any value less + * than 3'b011 in bits [2:0] of HOST CONTROL2 register. + */ + if (host->clock <= 100000000 && + (uhs == MMC_TIMING_MMC_HS400 || + uhs == MMC_TIMING_MMC_HS200 || + uhs == MMC_TIMING_UHS_SDR104)) + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + + dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n", + mmc_hostname(host->mmc), host->clock, uhs, ctrl_2); + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static unsigned int bm_sdhci_get_min_clock(struct sdhci_host *host) +{ + return 200 * 1000; +} + +static unsigned int bm_sdhci_get_max_clock(struct sdhci_host *host) +{ + return 50 * 1000 * 1000; +} + +#if 0 // FIXME, SD card not working after this. +static void bm_sdhci_hw_reset(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_bm_host *bm_host; + struct mmc_host *mmc = host->mmc; + + pltfm_host = sdhci_priv(host); + bm_host = sdhci_pltfm_priv(pltfm_host); + + pr_info("%s hardware reset\n", mmc_hostname(mmc)); + reset_control_assert(bm_host->reset); + udelay(10); + reset_control_deassert(bm_host->reset); +} +#endif + +void bm_sdhci_reset(struct sdhci_host *host, u8 mask) +{ +#if 0 // FIXME, SD card not working after this. + bm_sdhci_hw_reset(host); +#endif + sdhci_reset(host, mask); + + if (mask & SDHCI_RESET_ALL) + bm_sdhci_phy_init(host); +} + +int bm_sdhci_phy_init(struct sdhci_host *host) +{ + // Asset reset of phy + sdhci_writel(host, sdhci_readl(host, SDHCI_P_PHY_CNFG) & ~(1 << PHY_CNFG_PHY_RSTN), SDHCI_P_PHY_CNFG); + + // Set PAD_SN PAD_SP + sdhci_writel(host, + (1 << PHY_CNFG_PHY_PWRGOOD) | (0x9 << PHY_CNFG_PAD_SP) | (0x8 << PHY_CNFG_PAD_SN), + SDHCI_P_PHY_CNFG); + + // Set CMDPAD + sdhci_writew(host, (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N), SDHCI_P_CMDPAD_CNFG); + + // Set DATAPAD + sdhci_writew(host, (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N), SDHCI_P_DATPAD_CNFG); + + // Set CLKPAD + sdhci_writew(host, + (0x2 << PAD_CNFG_RXSEL) | (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N), + SDHCI_P_CLKPAD_CNFG); + + // Set STB_PAD + sdhci_writew(host, (0x2 << PAD_CNFG_RXSEL) | (0x2 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N), SDHCI_P_STBPAD_CNFG); + + // Set RSTPAD + sdhci_writew(host, (0x2 << PAD_CNFG_RXSEL) | (1 << PAD_CNFG_WEAKPULL_EN) | + (0x3 << PAD_CNFG_TXSLEW_CTRL_P) | (0x2 << PAD_CNFG_TXSLEW_CTRL_N), SDHCI_P_RSTNPAD_CNFG); + + // Set SDCLKDL_CNFG, EXTDLY_EN = 1, fix delay + sdhci_writeb(host, (1 << SDCLKDL_CNFG_EXTDLY_EN), SDHCI_P_SDCLKDL_CNFG); + + // Add 10 * 70ps = 0.7ns for output delay + sdhci_writeb(host, 10, SDHCI_P_SDCLKDL_DC); + + //if (host->index == 1) { + // Set SMPLDL_CNFG, Bypass + sdhci_writeb(host, (1 << SMPLDL_CNFG_BYPASS_EN), SDHCI_P_SMPLDL_CNFG); + //} + //else { + // Set SMPLDL_CNFG, INPSEL_CNFG = 0x2 + //sdhci_writeb(host, (0x2 << SMPLDL_CNFG_INPSEL_CNFG), SDHCI_P_SMPLDL_CNFG); + //} + + // Set ATDL_CNFG, tuning clk not use for init + sdhci_writeb(host, (2 << ATDL_CNFG_INPSEL_CNFG), SDHCI_P_ATDL_CNFG); + + // deasset reset of phy + sdhci_writel(host, sdhci_readl(host, SDHCI_P_PHY_CNFG) | (1 << PHY_CNFG_PHY_RSTN), SDHCI_P_PHY_CNFG); + + return 0; +} + +void bm_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + sdhci_set_clock(host, clock); + + if (clock == 0) + // forward tx + sdhci_writeb(host, 0x0, SDHCI_P_SDCLKDL_DC); + else + // revert tx + sdhci_writeb(host, 0x10, SDHCI_P_SDCLKDL_DC); +} + +/* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. + */ +#define BOUNDARY_OK(addr, len) \ + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) + +static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, + dma_addr_t addr, int len, unsigned int cmd) +{ + int tmplen, offset; + + if (likely(!len || BOUNDARY_OK(addr, len))) { + sdhci_adma_write_desc(host, desc, addr, len, cmd); + return; + } + + offset = addr & (SZ_128M - 1); + tmplen = SZ_128M - offset; + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); + + addr += tmplen; + len -= tmplen; + sdhci_adma_write_desc(host, desc, addr, len, cmd); +} + + +/* ------------- bm palludium sdcard --------------- */ +static const struct sdhci_ops sdhci_bm_pldm_sd_ops = { + .reset = bm_sdhci_reset, + .set_clock = bm_sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = sdhci_bm_set_uhs_signaling, + .get_max_clock = bm_sdhci_get_max_clock, + .get_min_clock = bm_sdhci_get_min_clock, + .adma_write_desc = dwcmshc_adma_write_desc, +}; + +static const struct sdhci_pltfm_data sdhci_bm_pldm_sd_pdata = { + .ops = &sdhci_bm_pldm_sd_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 = SDHCI_QUIRK2_NO_1_8_V, +}; + +static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) +{ + return cmd->data || cmd->flags & MMC_RSP_BUSY; +} + +static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) +{ + if (sdhci_data_line_cmd(mrq->cmd)) + del_timer(&host->data_timer); + else + del_timer(&host->timer); +} + +int bm_platform_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + u16 ctrl; + int tuning_loop_counter = 0; + int err = 0; + unsigned long flags; + unsigned int tuning_count = 0; + bool hs400_tuning; + int hit = 0; + + spin_lock_irqsave(&host->lock, flags); + + hs400_tuning = host->flags & SDHCI_HS400_TUNING; + host->flags &= ~SDHCI_HS400_TUNING; + + if (host->tuning_mode == SDHCI_TUNING_MODE_1) + tuning_count = host->tuning_count; + + switch (host->timing) { + /* HS400 tuning is done in HS200 mode */ + case MMC_TIMING_MMC_HS400: + err = -EINVAL; + goto out_unlock; + + case MMC_TIMING_MMC_HS200: + /* + * Periodic re-tuning for HS400 is not expected to be needed, so + * disable it here. + */ + if (hs400_tuning) + tuning_count = 0; + break; + + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: + break; + + case MMC_TIMING_UHS_SDR50: + if (host->flags & SDHCI_SDR50_NEEDS_TUNING) + break; + + default: + goto out_unlock; + } + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl |= SDHCI_CTRL_EXEC_TUNING; + + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); + + sdhci_writew(host, 0x704b | (0x3<<4) | (0x1<<3), SDHCI_HOST_CONTROL2);/*drv_strength | 1.8v*/ + + sdhci_writel(host, 0, SDHCI_DMA_ADDRESS);/*sdmasa*/ + sdhci_writel(host, 0, SDHCI_MSHC_CTRL); + + sdhci_writel(host, 0x18, SDHCI_AT_CTRL); + + sdhci_writew(host, 0x0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, 0x1040, SDHCI_BLOCK_SIZE); + sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); + + do { + struct mmc_command cmd = {0}; + struct mmc_request mrq = {NULL}; + + cmd.opcode = opcode; + cmd.arg = 0; + cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; + cmd.retries = 0; + cmd.data = NULL; + cmd.mrq = &mrq; + cmd.error = 0; + + sdhci_writel(host, tuning_loop_counter, SDHCI_AT_STAT); + mrq.cmd = &cmd; + sdhci_send_command(host, &cmd); + + host->cmd = NULL; + sdhci_del_timer(host, &mrq); + spin_unlock_irqrestore(&host->lock, flags); + + /* Wait for Buffer Read Ready interrupt */ + wait_event_timeout(host->buf_ready_int, + (host->tuning_done == 1), + msecs_to_jiffies(10)); + + spin_lock_irqsave(&host->lock, flags); + if (host->tuning_done == 1) { + u16 stat; + + stat = sdhci_readw(host, SDHCI_ERR_INT_STATUS) & 0x3F; + if (stat == 0) + hit = tuning_loop_counter; + } + + host->tuning_done = 0; + tuning_loop_counter++; + sdhci_writeb(host, 0xFF, SDHCI_INT_STATUS); + sdhci_writeb(host, 0xFF, SDHCI_ERR_INT_STATUS); + sdhci_writeb(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA, SDHCI_SOFTWARE_RESET); + } while (tuning_loop_counter < MAX_TUNING_STEP); + + if (tuning_loop_counter >= MAX_TUNING_STEP) { + ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING); + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + } + + sdhci_writel(host, 0, SDHCI_AT_CTRL); + sdhci_writeb(host, 0xFF, SDHCI_INT_STATUS);/*clear normal int*/ + sdhci_writeb(host, 0xFF, SDHCI_ERR_INT_STATUS);/*clear error int*/ + sdhci_writel(host, sdhci_readl(host, SDHCI_AT_CTRL) | (0x1<<4), SDHCI_AT_CTRL);/*en sw_tuning_en bit*/ + sdhci_writel(host, (sdhci_readl(host, SDHCI_AT_STAT) & (~0xFF)) | hit, SDHCI_AT_STAT);/*center_ph_code*/ + sdhci_writel(host, sdhci_readl(host, SDHCI_AT_CTRL) & (~(0x1<<4)), SDHCI_AT_CTRL);/*dis sw_tuning_en bit*/ + sdhci_writeb(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA, SDHCI_SOFTWARE_RESET); + + if (tuning_count) + err = 0; + + host->mmc->retune_period = err ? 0 : tuning_count; + + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); +out_unlock: + spin_unlock_irqrestore(&host->lock, flags); + return err; +} + +/* ------------- bm palludium emmc --------------- */ +static const struct sdhci_ops sdhci_bm_pldm_emmc_ops = { + .reset = sdhci_reset, + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = sdhci_bm_set_uhs_signaling, + .get_max_clock = bm_sdhci_get_max_clock, + .get_min_clock = bm_sdhci_get_min_clock, + .platform_execute_tuning = bm_platform_execute_tuning, + .adma_write_desc = dwcmshc_adma_write_desc, +}; + +static const struct sdhci_pltfm_data sdhci_bm_pldm_emmc_pdata = { + .ops = &sdhci_bm_pldm_emmc_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, +}; + +/* ------------ bm asic ------------ */ +static const struct sdhci_ops sdhci_bm_ops = { + .reset = bm_sdhci_reset, + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = sdhci_bm_set_uhs_signaling, + .platform_execute_tuning = sdhci_bm_execute_software_tuning, + .adma_write_desc = dwcmshc_adma_write_desc, +}; + +static const struct sdhci_pltfm_data sdhci_bm_emmc_pdata = { + .ops = &sdhci_bm_ops, + .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 = 0, +}; + +static const struct sdhci_pltfm_data sdhci_bm_sd_pdata = { + .ops = &sdhci_bm_ops, + .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT, + .quirks2 = 0, +}; + +static const struct of_device_id sdhci_bm_dt_match[] = { + {.compatible = "bitmain,bm-pldm-sdcard", .data = &sdhci_bm_pldm_sd_pdata}, + {.compatible = "bitmain,bm-pldm-emmc", .data = &sdhci_bm_pldm_emmc_pdata}, + {.compatible = "bitmain,bm-emmc", .data = &sdhci_bm_emmc_pdata}, + {.compatible = "bitmain,bm-sd", .data = &sdhci_bm_sd_pdata}, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, sdhci_bm_dt_match); + +static int sdhci_bm_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_bm_host *bm_host; + const struct of_device_id *match; + const struct sdhci_pltfm_data *pdata; + int ret; + + match = of_match_device(sdhci_bm_dt_match, &pdev->dev); + if (!match) + return -EINVAL; + + pdata = match->data; + + host = sdhci_pltfm_init(pdev, pdata, sizeof(*bm_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host = sdhci_priv(host); + bm_host = sdhci_pltfm_priv(pltfm_host); + bm_host->mmc = host->mmc; + bm_host->pdev = pdev; + bm_host->core_mem = host->ioaddr; + + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sdhci_get_of_property(pdev); + + if (host->mmc->caps2 & MMC_CAP2_NO_SD) { + bm_host->reset = devm_reset_control_get(&pdev->dev, "emmc"); + if (IS_ERR(bm_host->reset)) { + ret = PTR_ERR(bm_host->reset); + goto pltfm_free; + } + + bm_host->clkaxi = devm_clk_get(&pdev->dev, "clk_gate_axi_emmc"); + if (IS_ERR(bm_host->clkaxi)) + dev_err(&pdev->dev, "get emmc clk axi failed\n"); + else + clk_prepare_enable(bm_host->clkaxi); + bm_host->clk = devm_clk_get(&pdev->dev, "clk_gate_emmc"); + if (IS_ERR(bm_host->clk)) + dev_err(&pdev->dev, "get emmc clk failed\n"); + else + clk_prepare_enable(bm_host->clk); + bm_host->clk100k = devm_clk_get(&pdev->dev, "clk_gate_100k_emmc"); + if (IS_ERR(bm_host->clk100k)) + dev_err(&pdev->dev, "get emmc clk 100k failed\n"); + else + clk_prepare_enable(bm_host->clk100k); + } else if (host->mmc->caps2 & MMC_CAP2_NO_MMC) { + bm_host->reset = devm_reset_control_get(&pdev->dev, "sdio"); + if (IS_ERR(bm_host->reset)) { + ret = PTR_ERR(bm_host->reset); + goto pltfm_free; + } + + bm_host->clkaxi = devm_clk_get(&pdev->dev, "clk_gate_axi_sd"); + if (IS_ERR(bm_host->clkaxi)) + dev_err(&pdev->dev, "get sd clk axi failed\n"); + else + clk_prepare_enable(bm_host->clkaxi); + bm_host->clk = devm_clk_get(&pdev->dev, "clk_gate_sd"); + if (IS_ERR(bm_host->clk)) + dev_err(&pdev->dev, "get sd clk failed\n"); + else + clk_prepare_enable(bm_host->clk); + bm_host->clk100k = devm_clk_get(&pdev->dev, "clk_gate_100k_sd"); + if (IS_ERR(bm_host->clk100k)) + dev_err(&pdev->dev, "get sd clk 100k failed\n"); + else + clk_prepare_enable(bm_host->clk100k); + } + + host->mmc_host_ops.select_drive_strength = sdhci_bm_select_drive_strength; + + ret = sdhci_add_host(host); + if (ret) + goto err_add_host; + + return 0; + +err_add_host: +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_bm_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); + + sdhci_remove_host(host, dead); + sdhci_pltfm_free(pdev); + return 0; +} + +static struct platform_driver sdhci_bm_driver = { + .probe = sdhci_bm_probe, + .remove = sdhci_bm_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = sdhci_bm_dt_match, + }, +}; + +module_platform_driver(sdhci_bm_driver); +MODULE_DESCRIPTION("BitMain Secure Digital Host Controller Interface driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/sdhci-sophgo.h b/drivers/mmc/host/sdhci-sophgo.h new file mode 100644 index 0000000000000..508d0a16d71e9 --- /dev/null +++ b/drivers/mmc/host/sdhci-sophgo.h @@ -0,0 +1,121 @@ +/* + * drivers/mmc/host/sdhci-bm.c - BitMain SDHCI Platform driver + * + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SDHCI_BM_H +#define __SDHCI_BM_H + +#include +#include +#include +#include +#include + +/*register macro */ +#define P_VENDOR_SPECIFIC_AREA 0xE8 +#define P_VENDOR2_SPECIFIC_AREA 0xEA +#define VENDOR_EMMC_CTRL 0x2C +#define SW_RST_R 0x2F +#define SDHCI_NORMAL_INT_STATUS 0x30 +#define SDHCI_ERR_INT_STATUS 0x32 +#define SDHCI_ERR_INT_STATUS_EN 0x36 +#define SDHCI_HOST_CTRL2_R 0x3E +#define SDHCI_MSHC_CTRL 0x508 +#define SDHCI_AT_CTRL 0x540 +#define SDHCI_AT_STAT 0x544 + +/* PHY register */ +#define SDHCI_PHY_R_OFFSET 0x300 + +#define SDHCI_P_PHY_CNFG (SDHCI_PHY_R_OFFSET + 0x00) +#define SDHCI_P_CMDPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x04) +#define SDHCI_P_DATPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x06) +#define SDHCI_P_CLKPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x08) +#define SDHCI_P_STBPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0A) +#define SDHCI_P_RSTNPAD_CNFG (SDHCI_PHY_R_OFFSET + 0x0C) +#define SDHCI_P_PADTEST_CNFG (SDHCI_PHY_R_OFFSET + 0x0E) +#define SDHCI_P_PADTEST_OUT (SDHCI_PHY_R_OFFSET + 0x10) +#define SDHCI_P_PADTEST_IN (SDHCI_PHY_R_OFFSET + 0x12) +#define SDHCI_P_COMMDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1C) +#define SDHCI_P_SDCLKDL_CNFG (SDHCI_PHY_R_OFFSET + 0x1D) +#define SDHCI_P_SDCLKDL_DC (SDHCI_PHY_R_OFFSET + 0x1E) +#define SDHCI_P_SMPLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x20) +#define SDHCI_P_ATDL_CNFG (SDHCI_PHY_R_OFFSET + 0x21) +#define SDHCI_P_DLL_CTRL (SDHCI_PHY_R_OFFSET + 0x24) +#define SDHCI_P_DLL_CNFG1 (SDHCI_PHY_R_OFFSET + 0x25) +#define SDHCI_P_DLL_CNFG2 (SDHCI_PHY_R_OFFSET + 0x26) +#define SDHCI_P_DLLDL_CNFG (SDHCI_PHY_R_OFFSET + 0x28) +#define SDHCI_P_DLL_OFFST (SDHCI_PHY_R_OFFSET + 0x29) +#define SDHCI_P_DLLMST_TSTDC (SDHCI_PHY_R_OFFSET + 0x2A) +#define SDHCI_P_DLLLBT_CNFG (SDHCI_PHY_R_OFFSET + 0x2C) +#define SDHCI_P_DLL_STATUS (SDHCI_PHY_R_OFFSET + 0x2E) +#define SDHCI_P_DLLDBG_MLKDC (SDHCI_PHY_R_OFFSET + 0x30) +#define SDHCI_P_DLLDBG_SLKDC (SDHCI_PHY_R_OFFSET + 0x32) + +#define PHY_CNFG_PHY_RSTN 0 +#define PHY_CNFG_PHY_PWRGOOD 1 +#define PHY_CNFG_PAD_SP 16 +#define PHY_CNFG_PAD_SP_MSK 0xf +#define PHY_CNFG_PAD_SN 20 +#define PHY_CNFG_PAD_SN_MSK 0xf + +#define PAD_CNFG_RXSEL 0 +#define PAD_CNFG_RXSEL_MSK 0x7 +#define PAD_CNFG_WEAKPULL_EN 3 +#define PAD_CNFG_WEAKPULL_EN_MSK 0x3 +#define PAD_CNFG_TXSLEW_CTRL_P 5 +#define PAD_CNFG_TXSLEW_CTRL_P_MSK 0xf +#define PAD_CNFG_TXSLEW_CTRL_N 9 +#define PAD_CNFG_TXSLEW_CTRL_N_MSK 0xf + +#define COMMDL_CNFG_DLSTEP_SEL 0 +#define COMMDL_CNFG_DLOUT_EN 1 + +#define SDCLKDL_CNFG_EXTDLY_EN 0 +#define SDCLKDL_CNFG_BYPASS_EN 1 +#define SDCLKDL_CNFG_INPSEL_CNFG 2 +#define SDCLKDL_CNFG_INPSEL_CNFG_MSK 0x3 +#define SDCLKDL_CNFG_UPDATE_DC 4 + +#define SMPLDL_CNFG_EXTDLY_EN 0 +#define SMPLDL_CNFG_BYPASS_EN 1 +#define SMPLDL_CNFG_INPSEL_CNFG 2 +#define SMPLDL_CNFG_INPSEL_CNFG_MSK 0x3 +#define SMPLDL_CNFG_INPSEL_OVERRIDE 4 + +#define ATDL_CNFG_EXTDLY_EN 0 +#define ATDL_CNFG_BYPASS_EN 1 +#define ATDL_CNFG_INPSEL_CNFG 2 +#define ATDL_CNFG_INPSEL_CNFG_MSK 0x3 + +#define MAX_TUNING_STEP 128 + +struct sdhci_bm_host { + struct platform_device *pdev; + void __iomem *core_mem; /* bm SDCC mapped address */ + struct clk *clk; /* main SD/MMC bus clock */ + struct clk *clk100k; + struct clk *clkaxi; + struct mmc_host *mmc; + struct reset_control *reset; + + struct reset_control *clk_rst_axi_emmc_ctrl; + struct reset_control *clk_rst_emmc_ctrl; + struct reset_control *clk_rst_100k_emmc_ctrl; +}; + +int bm_sdhci_phy_init(struct sdhci_host *host); +bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); +#endif diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9796a3cb3ca62..9c15594af6c3f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -49,7 +49,9 @@ static unsigned int debug_quirks2; static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); +#ifndef CONFIG_ARCH_SOPHGO static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); +#endif void sdhci_dumpregs(struct sdhci_host *host) { @@ -1627,7 +1629,11 @@ static void sdhci_finish_data(struct sdhci_host *host) __sdhci_finish_data(host, false); } +#ifndef CONFIG_ARCH_SOPHGO static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +#else +bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) +#endif { int flags; u32 mask; @@ -1717,6 +1723,9 @@ static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) return true; } +#ifdef CONFIG_ARCH_SOPHGO +EXPORT_SYMBOL_GPL(sdhci_send_command); +#endif static bool sdhci_present_error(struct sdhci_host *host, struct mmc_command *cmd, bool present) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index a315cee698094..a7e82f8dd3df5 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -824,5 +824,8 @@ void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode); void sdhci_switch_external_dma(struct sdhci_host *host, bool en); void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable); void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); +#ifdef CONFIG_ARCH_SOPHGO +bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd); +#endif #endif /* __SDHCI_HW_H */ From 1451df20f11e3adee8692c5be16377b5db195d5e Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 6 Mar 2024 15:57:41 +0800 Subject: [PATCH 15/40] driver: mtd: Add sophgo sg2042 soc support Sophgo SPI Flash Master Controller (SPIFMC) is a master controller to control serial SPI Flash. Enable CONFIG_SPI_SOPHGO_SPIFMC if you have a device with a SPIFMC controller and want to access the Flash as a mtd device. There is GD25LB512ME Serial Flash on SG2042 EVB, controlled by SPIFMC. Signed-off-by: jingyu.li01 --- drivers/mtd/spi-nor/controllers/Kconfig | 11 + drivers/mtd/spi-nor/controllers/Makefile | 1 + .../mtd/spi-nor/controllers/sophgo-spifmc.c | 445 ++++++++++++++++++ drivers/mtd/spi-nor/gigadevice.c | 14 + 4 files changed, 471 insertions(+) create mode 100644 drivers/mtd/spi-nor/controllers/sophgo-spifmc.c diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig index ca45dcd3ffe81..d2138370f1fc0 100644 --- a/drivers/mtd/spi-nor/controllers/Kconfig +++ b/drivers/mtd/spi-nor/controllers/Kconfig @@ -16,3 +16,14 @@ config SPI_NXP_SPIFI SPIFI is a specialized controller for connecting serial SPI Flash. Enable this option if you have a device with a SPIFI controller and want to access the Flash as a mtd device. + +config SPI_SOPHGO_SPIFMC + tristate "Sophgo SPI Flash Master Controller (SPIFMC)" + depends on ARCH_SOPHGO || COMPILE_TEST + depends on HAS_IOMEM + help + Enable support for the Sophgo SPI Flash Master controller. + + SPIFMC is a master controller to control serial SPI Flash. + Enable this option if you have a device with a SPIFMC controller + and want to access the Flash as a mtd device. diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile index 0b8e1d5309138..627ac8850ab17 100644 --- a/drivers/mtd/spi-nor/controllers/Makefile +++ b/drivers/mtd/spi-nor/controllers/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o +obj-$(CONFIG_SPI_SOPHGO_SPIFMC) += sophgo-spifmc.o diff --git a/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c b/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c new file mode 100644 index 0000000000000..f7d85cc031375 --- /dev/null +++ b/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SPI Flash Master Controller (SPIFMC) + * + * Copyright (c) 2023 Sophgo. + */ +#include +#include +#include +#include +#include +#include +#include + +/* Hardware register definitions */ +#define SPIFMC_CTRL 0x00 +#define SPIFMC_CTRL_CPHA BIT(12) +#define SPIFMC_CTRL_CPOL BIT(13) +#define SPIFMC_CTRL_HOLD_OL BIT(14) +#define SPIFMC_CTRL_WP_OL BIT(15) +#define SPIFMC_CTRL_LSBF BIT(20) +#define SPIFMC_CTRL_SRST BIT(21) +#define SPIFMC_CTRL_SCK_DIV_SHIFT 0 +#define SPIFMC_CTRL_FRAME_LEN_SHIFT 16 + +#define SPIFMC_CE_CTRL 0x04 +#define SPIFMC_CE_CTRL_CEMANUAL BIT(0) +#define SPIFMC_CE_CTRL_CEMANUAL_EN BIT(1) + +#define SPIFMC_DLY_CTRL 0x08 +#define SPIFMC_CTRL_FM_INTVL_MASK 0x000f +#define SPIFMC_CTRL_FM_INTVL BIT(0) +#define SPIFMC_CTRL_CET_MASK 0x0f00 +#define SPIFMC_CTRL_CET BIT(8) + +#define SPIFMC_DMMR 0x0c + +#define SPIFMC_TRAN_CSR 0x10 +#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK 0x0003 +#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0) +#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1) +#define SPIFMC_TRAN_CSR_CNTNS_READ BIT(2) +#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3) +#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4) +#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4) +#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4) +#define SPIFMC_TRAN_CSR_DMA_EN BIT(6) +#define SPIFMC_TRAN_CSR_MISO_LEVEL BIT(7) +#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK 0x0700 +#define SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT 8 +#define SPIFMC_TRAN_CSR_WITH_CMD BIT(11) +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK 0x3000 +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE (0x00 << 12) +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_2_BYTE (0x01 << 12) +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE (0x02 << 12) +#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE (0x03 << 12) +#define SPIFMC_TRAN_CSR_GO_BUSY BIT(15) + +#define SPIFMC_TRAN_NUM 0x14 +#define SPIFMC_FIFO_PORT 0x18 +#define SPIFMC_FIFO_PT 0x20 + +#define SPIFMC_INT_STS 0x28 +#define SPIFMC_INT_TRAN_DONE BIT(0) +#define SPIFMC_INT_RD_FIFO BIT(2) +#define SPIFMC_INT_WR_FIFO BIT(3) +#define SPIFMC_INT_RX_FRAME BIT(4) +#define SPIFMC_INT_TX_FRAME BIT(5) + +#define SPIFMC_INT_EN 0x2c +#define SPIFMC_INT_TRAN_DONE_EN BIT(0) +#define SPIFMC_INT_RD_FIFO_EN BIT(2) +#define SPIFMC_INT_WR_FIFO_EN BIT(3) +#define SPIFMC_INT_RX_FRAME_EN BIT(4) +#define SPIFMC_INT_TX_FRAME_EN BIT(5) + +#define SPIFMC_MAX_FIFO_DEPTH 8 + +struct sophgo_spifmc { + struct device *dev; + struct clk *clk; + void __iomem *io_base; + struct spi_nor nor; +}; + +static inline int sophgo_spifmc_wait_int(struct sophgo_spifmc *spifmc, + u8 int_type) +{ + u32 stat; + + return readl_poll_timeout(spifmc->io_base + SPIFMC_INT_STS, stat, + (stat & int_type), 0, 0); +} + +static inline u32 sophgo_spifmc_init_reg(struct sophgo_spifmc *spifmc) +{ + u32 reg; + + reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR); + reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK + | SPIFMC_TRAN_CSR_CNTNS_READ + | SPIFMC_TRAN_CSR_FAST_MODE + | SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT + | SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT + | SPIFMC_TRAN_CSR_DMA_EN + | SPIFMC_TRAN_CSR_ADDR_BYTES_MASK + | SPIFMC_TRAN_CSR_WITH_CMD + | SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK); + + return reg; +} + +/* + * sophgo_spifmc_read_reg is a workaround function: + * AHB bus could only do 32-bit access to SPIFMC fifo, + * so cmd without 3-byte addr will leave 3-byte data in fifo. + * Set TX to mark that these 3-byte data would be sent out. + */ +static int sophgo_spifmc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, + size_t len) +{ + struct sophgo_spifmc *spifmc = nor->priv; + u32 reg; + int ret, i; + + reg = sophgo_spifmc_init_reg(spifmc); + reg |= SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT; + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX | SPIFMC_TRAN_CSR_TRAN_MODE_TX; + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + writeb(opcode, spifmc->io_base + SPIFMC_FIFO_PORT); + + for (i = 0; i < len; i++) + writeb(0, spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_INT_STS); + writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); + reg |= SPIFMC_TRAN_CSR_GO_BUSY; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); + + ret = sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); + if (ret) + return ret; + + while (len--) + *buf++ = readb(spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + return 0; +} + +static int sophgo_spifmc_write_reg(struct spi_nor *nor, u8 opcode, + const u8 *buf, size_t len) +{ + struct sophgo_spifmc *spifmc = nor->priv; + u32 reg; + int i; + + reg = sophgo_spifmc_init_reg(spifmc); + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + + /* + * If write values to the Status Register, + * configure TRAN_CSR register as the same as sophgo_spifmc_read_reg. + */ + if (opcode == SPINOR_OP_WRSR) { + reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX | SPIFMC_TRAN_CSR_TRAN_MODE_TX; + writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); + } + + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + writeb(opcode, spifmc->io_base + SPIFMC_FIFO_PORT); + + for (i = 0; i < len; i++) + writeb(buf[i], spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_INT_STS); + reg |= SPIFMC_TRAN_CSR_GO_BUSY; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); + sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + return 0; +} + +static ssize_t sophgo_spifmc_read(struct spi_nor *nor, loff_t from, + size_t len, u_char *buf) +{ + struct sophgo_spifmc *spifmc = nor->priv; + u32 reg; + int xfer_size, offset; + int i; + + reg = sophgo_spifmc_init_reg(spifmc); + reg |= (nor->addr_nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX; + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + writeb(nor->read_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); + + for (i = nor->addr_nbytes - 1; i >= 0; i--) + writeb((from >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_INT_STS); + writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); + reg |= SPIFMC_TRAN_CSR_GO_BUSY; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); + sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_RD_FIFO); + + offset = 0; + while (offset < len) { + xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset); + + while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != xfer_size) + ; + + for (i = 0; i < xfer_size; i++) + buf[i + offset] = readb(spifmc->io_base + SPIFMC_FIFO_PORT); + + offset += xfer_size; + } + + sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + return len; +} + +static ssize_t sophgo_spifmc_write(struct spi_nor *nor, loff_t to, + size_t len, const u_char *buf) +{ + struct sophgo_spifmc *spifmc = nor->priv; + u32 reg; + int i, offset; + int xfer_size, wait; + + reg = sophgo_spifmc_init_reg(spifmc); + reg |= nor->addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX; + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + writeb(nor->program_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); + + for (i = nor->addr_nbytes - 1; i >= 0; i--) + writeb((to >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_INT_STS); + writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); + reg |= SPIFMC_TRAN_CSR_GO_BUSY; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); + + while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != 0) + ; + + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + offset = 0; + while (offset < len) { + xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset); + + wait = 0; + while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != 0) { + wait++; + udelay(10); + if (wait > 30000) { + dev_warn(spifmc->dev, "Wait to write FIFO timeout.\n"); + return -1; + } + } + + for (i = 0; i < xfer_size; i++) + writeb(buf[i + offset], spifmc->io_base + SPIFMC_FIFO_PORT); + + offset += xfer_size; + } + + sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + return len; +} + +static int sophgo_spifmc_erase(struct spi_nor *nor, loff_t offs) +{ + struct sophgo_spifmc *spifmc = nor->priv; + u32 reg; + int i; + + reg = sophgo_spifmc_init_reg(spifmc); + reg |= nor->addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + writeb(nor->erase_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); + + for (i = nor->addr_nbytes - 1; i >= 0; i--) + writeb((offs >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); + + writel(0, spifmc->io_base + SPIFMC_INT_STS); + reg |= SPIFMC_TRAN_CSR_GO_BUSY; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); + sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); + writel(0, spifmc->io_base + SPIFMC_FIFO_PT); + + return 0; +} + +static const struct spi_nor_controller_ops sophgo_spifmc_controller_ops = { + .read_reg = sophgo_spifmc_read_reg, + .write_reg = sophgo_spifmc_write_reg, + .read = sophgo_spifmc_read, + .write = sophgo_spifmc_write, + .erase = sophgo_spifmc_erase, +}; + +static void sophgo_spifmc_init(struct sophgo_spifmc *spifmc) +{ + u32 reg; + + /* disable DMMR (Direct Memory Mapping Read) */ + writel(0, spifmc->io_base + SPIFMC_DMMR); + /* soft reset */ + writel(readl(spifmc->io_base + SPIFMC_CTRL) | SPIFMC_CTRL_SRST | 0x3, + spifmc->io_base + SPIFMC_CTRL); + /* hardware CE contrl, soft reset cannot change the register */ + writel(0, spifmc->io_base + SPIFMC_CE_CTRL); + reg = spifmc->nor.addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; + reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE; + reg |= SPIFMC_TRAN_CSR_WITH_CMD; + writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); +} + +static int sophgo_spifmc_register(struct device_node *np, + struct sophgo_spifmc *spifmc) +{ + /* TODO: support DUAL and QUAD operations */ + const struct spi_nor_hwcaps hwcaps = { + .mask = SNOR_HWCAPS_READ | + SNOR_HWCAPS_PP, + }; + int ret; + + spifmc->nor.dev = spifmc->dev; + spi_nor_set_flash_node(&spifmc->nor, np); + spifmc->nor.priv = spifmc; + spifmc->nor.controller_ops = &sophgo_spifmc_controller_ops; + + ret = spi_nor_scan(&spifmc->nor, NULL, &hwcaps); + if (ret) { + dev_err(spifmc->dev, "Device scan failed.\n"); + return ret; + } + + ret = mtd_device_register(&spifmc->nor.mtd, NULL, 0); + if (ret) { + dev_err(spifmc->dev, "mtd device parse failed.\n"); + return ret; + } + + return 0; +} + +static int sophgo_spifmc_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct sophgo_spifmc *spifmc; + int ret; + + spifmc = devm_kzalloc(&pdev->dev, sizeof(*spifmc), GFP_KERNEL); + if (!spifmc) + return -ENOMEM; + + spifmc->io_base = devm_platform_ioremap_resource_byname(pdev, "memory"); + if (IS_ERR(spifmc->io_base)) + return PTR_ERR(spifmc->io_base); + + spifmc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(spifmc->clk)) { + dev_err(&pdev->dev, "AHB clock not found.\n"); + return PTR_ERR(spifmc->clk); + } + + ret = clk_prepare_enable(spifmc->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); + return ret; + } + + spifmc->dev = &pdev->dev; + platform_set_drvdata(pdev, spifmc); + sophgo_spifmc_init(spifmc); + + np = of_get_next_available_child(pdev->dev.of_node, NULL); + if (!np) { + dev_err(&pdev->dev, "No SPI flash device to configure.\n"); + ret = -ENODEV; + goto fail; + } + + ret = sophgo_spifmc_register(np, spifmc); + of_node_put(np); + if (ret) { + dev_err(&pdev->dev, "Unable to register spifmc.\n"); + goto fail; + } + + return ret; +fail: + clk_disable_unprepare(spifmc->clk); + return ret; +} + +static int sophgo_spifmc_remove(struct platform_device *pdev) +{ + struct sophgo_spifmc *spifmc = platform_get_drvdata(pdev); + + mtd_device_unregister(&spifmc->nor.mtd); + clk_disable_unprepare(spifmc->clk); + + return 0; +} + +static const struct of_device_id sophgo_spifmc_match[] = { + {.compatible = "sophgo,spifmc"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, sophgo_spifmc_match); + +static struct platform_driver sophgo_spifmc_driver = { + .probe = sophgo_spifmc_probe, + .remove = sophgo_spifmc_remove, + .driver = { + .name = "sophgo-spifmc", + .of_match_table = sophgo_spifmc_match, + }, +}; +module_platform_driver(sophgo_spifmc_driver); + +MODULE_DESCRIPTION("Sophgo SPI Flash Master Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c index d57ddaf1525b3..c606567020635 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -33,6 +33,15 @@ static const struct spi_nor_fixups gd25q256_fixups = { .post_bfpt = gd25q256_post_bfpt, }; +static void gd25lb512me_default_init(struct spi_nor *nor) +{ + nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; +} + +static const struct spi_nor_fixups gd25lb512me_fixups = { + .default_init = gd25lb512me_default_init, +}; + static const struct flash_info gigadevice_nor_parts[] = { { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32) FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) @@ -67,6 +76,11 @@ static const struct flash_info gigadevice_nor_parts[] = { FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) .fixups = &gd25q256_fixups }, + { "gd25lb512me", INFO(0xc8671a, 0, 64 * 1024, 1024) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + .fixups = &gd25lb512me_fixups }, }; const struct spi_nor_manufacturer spi_nor_gigadevice = { From 904c7b11b42eade7c460eb2b7df654bc6525cb58 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 10:59:37 +0800 Subject: [PATCH 16/40] driver: net: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-sophgo.c | 268 ++++++++++++++++++ 2 files changed, 269 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index d6160c8dff18e..93e021a483a72 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o +obj-$(CONFIG_ARCH_SOPHGO) += dwmac-sophgo.o obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c new file mode 100644 index 0000000000000..50a76c8f0df68 --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c @@ -0,0 +1,268 @@ +/* + * DWMAC specific glue layer + * + * Copyright (c) 2018 Bitmain Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +struct bm_mac { + struct device *dev; + struct reset_control *rst; + struct clk *clk_tx; + struct clk *gate_clk_tx; + struct clk *gate_clk_ref; + struct gpio_desc *reset; +}; + +static u64 bm_dma_mask = DMA_BIT_MASK(40); + +static int bm_eth_reset_phy(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + int phy_reset_gpio; + + if (!np) + return 0; + + phy_reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0); + + if (phy_reset_gpio < 0) + return 0; + + if (gpio_request(phy_reset_gpio, "eth-phy-reset")) + return 0; + + /* RESET_PU */ + gpio_direction_output(phy_reset_gpio, 0); + mdelay(100); + + gpio_direction_output(phy_reset_gpio, 1); + /* RC charging time */ + mdelay(100); + + return 0; +} + +static void bm_mac_fix_speed(void *priv, unsigned int speed, unsigned int mode) +{ + struct bm_mac *bsp_priv = priv; + unsigned long rate = 125000000; + bool needs_calibration = false; + int err; + + switch (speed) { + case SPEED_1000: + needs_calibration = true; + rate = 125000000; + break; + + case SPEED_100: + needs_calibration = true; + rate = 25000000; + break; + + case SPEED_10: + needs_calibration = true; + rate = 2500000; + break; + + default: + dev_err(bsp_priv->dev, "invalid speed %u\n", speed); + break; + } + + if (needs_calibration) { + err = clk_set_rate(bsp_priv->clk_tx, rate); + if (err < 0) + dev_err(bsp_priv->dev, "failed to set TX rate: %d\n" + , err); + } +} + +void bm_dwmac_exit(struct platform_device *pdev, void *priv) +{ + struct bm_mac *bsp_priv = priv; + + clk_disable_unprepare(bsp_priv->gate_clk_tx); + clk_disable_unprepare(bsp_priv->gate_clk_ref); +} + +static int bm_validate_ucast_entries(struct device *dev, int ucast_entries) +{ + int x = ucast_entries; + + switch (x) { + case 1 ... 32: + case 64: + case 128: + break; + default: + x = 1; + dev_info(dev, "Unicast table entries set to unexpected value %d\n", + ucast_entries); + break; + } + return x; +} + +static int bm_validate_mcast_bins(struct device *dev, int mcast_bins) +{ + int x = mcast_bins; + + switch (x) { + case HASH_TABLE_SIZE: + case 128: + case 256: + break; + default: + x = 0; + dev_info(dev, "Hash table entries set to unexpected value %d\n", + mcast_bins); + break; + } + return x; +} + +static void bm_dwmac_probe_config_dt(struct platform_device *pdev, struct plat_stmmacenet_data *plat) +{ + struct device_node *np = pdev->dev.of_node; + + of_property_read_u32(np, "snps,multicast-filter-bins", &plat->multicast_filter_bins); + of_property_read_u32(np, "snps,perfect-filter-entries", &plat->unicast_filter_entries); + plat->unicast_filter_entries = bm_validate_ucast_entries(&pdev->dev, + plat->unicast_filter_entries); + plat->multicast_filter_bins = bm_validate_mcast_bins(&pdev->dev, + plat->multicast_filter_bins); + plat->flags |= (STMMAC_FLAG_TSO_EN); + plat->has_gmac4 = 1; + plat->has_gmac = 0; + plat->pmt = 0; +} + +static int bm_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct bm_mac *bsp_priv = NULL; + struct phy_device *phydev = NULL; + struct stmmac_priv *priv = NULL; + struct net_device *ndev = NULL; + int ret; + + pdev->dev.dma_mask = &bm_dma_mask; + pdev->dev.coherent_dma_mask = bm_dma_mask; + + bm_eth_reset_phy(pdev); + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + bm_dwmac_probe_config_dt(pdev, plat_dat); + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_remove_config_dt; + + bsp_priv = devm_kzalloc(&pdev->dev, sizeof(*bsp_priv), GFP_KERNEL); + if (!bsp_priv) + return PTR_ERR(bsp_priv); + + bsp_priv->dev = &pdev->dev; + + /* clock setup */ + bsp_priv->clk_tx = devm_clk_get(&pdev->dev, + "clk_tx"); + if (IS_ERR(bsp_priv->clk_tx)) + dev_warn(&pdev->dev, "Cannot get mac tx clock!\n"); + else + plat_dat->fix_mac_speed = bm_mac_fix_speed; + + bsp_priv->gate_clk_tx = devm_clk_get(&pdev->dev, "gate_clk_tx"); + if (IS_ERR(bsp_priv->gate_clk_tx)) + dev_warn(&pdev->dev, "Cannot get mac tx gating clock!\n"); + else + clk_prepare_enable(bsp_priv->gate_clk_tx); + + bsp_priv->gate_clk_ref = devm_clk_get(&pdev->dev, "gate_clk_ref"); + if (IS_ERR(bsp_priv->gate_clk_ref)) + dev_warn(&pdev->dev, "Cannot get mac ref gating clock!\n"); + else + clk_prepare_enable(bsp_priv->gate_clk_ref); + + plat_dat->bsp_priv = bsp_priv; + plat_dat->exit = bm_dwmac_exit; + + ndev = dev_get_drvdata(&pdev->dev); + priv = netdev_priv(ndev); + phydev = mdiobus_get_phy(priv->mii, 0); + if (phydev == NULL) { + dev_err(&pdev->dev, "Can not get phy in addr 0\n"); + goto err_remove_config_dt; + } + + /* set green LED0 active for transmit, yellow LED1 for link*/ + ret = phy_write_paged(phydev, 0, 0x1f, 0xd04); + if (ret < 0) + dev_err(&pdev->dev, "Can not select page 0xd04\n"); + ret = phy_write_paged(phydev, 0xd04, 0x10, 0x617f); + if (ret < 0) + dev_err(&pdev->dev, "Can not alter LED Configuration\n"); + /* disable eee LED function */ + ret = phy_write_paged(phydev, 0xd04, 0x11, 0x0); + if (ret < 0) + dev_err(&pdev->dev, "Can not disable EEE Configuration\n"); + ret = phy_write_paged(phydev, 0, 0x1f, 0); + if (ret < 0) + dev_err(&pdev->dev, "Can not select page 0\n"); + + return 0; + +err_remove_config_dt: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; +} + +static const struct of_device_id bm_dwmac_match[] = { + { .compatible = "bitmain,ethernet" }, + { } +}; +MODULE_DEVICE_TABLE(of, bm_dwmac_match); + +static struct platform_driver bm_dwmac_driver = { + .probe = bm_dwmac_probe, + .remove_new = stmmac_pltfr_remove, + .driver = { + .name = "bm-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = bm_dwmac_match, + }, +}; +module_platform_driver(bm_dwmac_driver); + +MODULE_AUTHOR("Wei Huang"); +MODULE_DESCRIPTION("Bitmain DWMAC specific glue layer"); +MODULE_LICENSE("GPL"); From e3005eecd84a7afc9c53e5a318c95ca32f1971ec Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Thu, 21 Mar 2024 14:03:47 +0800 Subject: [PATCH 17/40] driver: pcie: Add sophgo sg2042 soc support Signed-off-by: fengchun.li --- drivers/pci/controller/cadence/Kconfig | 11 + drivers/pci/controller/cadence/Makefile | 1 + .../controller/cadence/pcie-cadence-sophgo.c | 964 ++++++++++++++++++ .../controller/cadence/pcie-cadence-sophgo.h | 17 + drivers/soc/Makefile | 1 + drivers/soc/sophgo/Makefile | 1 + drivers/soc/sophgo/top/top_intc.c | 412 ++++++++ 7 files changed, 1407 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-sophgo.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-sophgo.h create mode 100644 drivers/soc/sophgo/Makefile create mode 100644 drivers/soc/sophgo/top/top_intc.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 291d127113632..25c768d5afb45 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,6 +42,17 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. +config PCIE_CADENCE_SOPHGO + bool "Cadence Sophgo PCIe Host controller" + depends on OF + select IRQ_DOMAIN + select PCIE_CADENCE + help + Say Y here if you want to support the Cadence PCIe controller in host mode + for Sophgo SoCs. this PCIe controller is from cadence, integrated into the + Sophgo SoCs. PCIe is one of subsystems, it is choisable, Don't be + care of this if it is not used in your systems. + config PCI_J721E bool diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile index 9bac5fb2f13da..edac7c5e94a31 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) += pci-j721e.o +obj-$(CONFIG_PCIE_CADENCE_SOPHGO) += pcie-cadence-sophgo.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c new file mode 100644 index 0000000000000..dd1e1e215d910 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Cyrille Pitchen + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-sophgo.h" + +#define MAX_MSI_IRQS 512 +#define MAX_MSI_IRQS_PER_CTRL 1 +#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL) +#define MSI_DEF_NUM_VECTORS 512 +#define BYTE_NUM_PER_MSI_VEC 4 + +// mango sideband signals +#define CDNS_PCIE_CFG_MANGO_APB 0x1800000 +#define CDNS_PCIE_IRS_REG0400 0x0400 +#define CDNS_PCIE_IRS_REG0404 0x0404 +#define CDNS_PCIE_IRS_REG0418 0x0418 +#define CDNS_PCIE_IRS_REG041C 0x041C +#define CDNS_PCIE_IRS_REG0804 0x0804 +#define CDNS_PCIE_IRS_REG080C 0x080C +#define CDNS_PCIE_IRS_REG0810 0x0810 +#define CDNS_PCIE_IRS_REG085C 0x085C +#define CDNS_PCIE_IRS_REG0860 0x0860 +#define CDNS_PCIE_IRS_REG0864 0x0864 +#define CDNS_PCIE_IRS_REG0868 0x0868 +#define CDNS_PCIE_IRS_REG086C 0x086C + +#define CDNS_PCIE_IRS_REG0804_CLR_LINK0_MSI_IN_BIT 2 +#define CDNS_PCIE_IRS_REG0804_CLR_LINK1_MSI_IN_BIT 3 +#define CDNS_PCIE_IRS_REG0810_ST_LINK0_MSI_IN_BIT 2 +#define CDNS_PCIE_IRS_REG0810_ST_LINK1_MSI_IN_BIT 3 + +#define CDNS_PLAT_CPU_TO_BUS_ADDR 0xCFFFFFFFFF + +struct cdns_pcie_database { + void __iomem *pcie_reg_base; +}; + +static struct cdns_pcie_database cdns_pcie_db; + +static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie, + u32 reg, u32 value) +{ + writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, + u32 reg) +{ + return readl(pcie->reg_base + CDNS_PCIE_RP_BASE + reg); +} + +/** + * struct cdns_mango_pcie_rc - private data for this PCIe Root Complex driver + * @pcie: Cadence PCIe controller + * @dev: pointer to PCIe device + * @cfg_res: start/end offsets in the physical system memory to map PCI + * configuration space accesses + * @bus_range: first/last buses behind the PCIe host controller + * @cfg_base: IO mapped window to access the PCI configuration space of a + * single function at a time + * @max_regions: maximum number of regions supported by the hardware + * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address + * translation (nbits sets into the "no BAR match" register) + * @vendor_id: PCI vendor ID + * @device_id: PCI device ID + */ +struct cdns_mango_pcie_rc { + struct cdns_pcie pcie; + struct device *dev; + struct resource *cfg_res; + struct resource *bus_range; + void __iomem *cfg_base; + u32 max_regions; + u32 no_bar_nbits; + u16 vendor_id; + u16 device_id; + u16 pcie_id; + u16 link_id; + u32 top_intc_used; + u32 msix_supported; + struct irq_domain *msi_domain; + int msi_irq; + struct irq_domain *irq_domain; + dma_addr_t msi_data; + void *msi_page; + struct irq_chip *msi_irq_chip; + u32 num_vectors; + u32 num_applied_vecs; + u32 irq_mask[MAX_MSI_CTRLS]; + struct pci_bus *root_bus; + raw_spinlock_t lock; + DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); +}; + +static u64 cdns_mango_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) +{ + return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR; +} + +static const struct cdns_pcie_ops cdns_mango_ops = { + .cpu_addr_fixup = cdns_mango_cpu_addr_fixup, +}; + +static void __iomem *cdns_mango_pci_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *bridge = pci_find_host_bridge(bus); + struct cdns_mango_pcie_rc *rc = pci_host_bridge_priv(bridge); + struct cdns_pcie *pcie = &rc->pcie; + unsigned int busn = bus->number; + u32 addr0, desc0; + + if (pci_is_root_bus(bus)) { + /* + * Only the root port (devfn == 0) is connected to this bus. + * All other PCI devices are behind some bridge hence on another + * bus. + */ + if (devfn) + return NULL; + + return pcie->reg_base + CDNS_PCIE_RP_BASE + (where & 0xfff); + } + /* Check that the link is up */ + if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) + return NULL; + /* Clear AXI link-down status */ + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); + + /* Update Output registers for AXI region 0. */ + addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); + + /* Configuration Type 0 or Type 1 access. */ + desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID | + CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0); + /* + * The bus number was already set once for all in desc1 by + * cdns_pcie_host_init_address_translation(). + */ + if (busn == bridge->busnr + 1) + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); + + return rc->cfg_base + (where & 0xfff); +} + +int cdns_pcie_config_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long addr; + unsigned int value, offset; + void __iomem *aligned_addr; + + if ((bus->number != 0) && (bus->number != 0x40) && + (bus->number != 0x80) && (bus->number != 0xc0)) + return pci_generic_config_read(bus, devfn, where, size, val); + + addr = (unsigned long)bus->ops->map_bus(bus, devfn, where); + if (!addr) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + if (size == 1) { + offset = addr & 0x3; + aligned_addr = (void __iomem *)(addr & ~0x3UL); + value = readl(aligned_addr); + *val = (value >> (8 * offset)) & 0xff; + } else if (size == 2) { + WARN_ON((addr & 0x1) != 0); // address should be aligned to 2 bytes + offset = addr & 0x3; + aligned_addr = (void __iomem *)(addr & ~0x3UL); + value = readl(aligned_addr); + *val = (value >> (8 * offset)) & 0xffff; + } else { + WARN_ON((addr & 0x3) != 0); // address should be aligned to 4 bytes + *val = readl((void __iomem *)(addr)); + } + + return PCIBIOS_SUCCESSFUL; +} + +int cdns_pcie_config_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long addr; + unsigned int value, offset; + void __iomem *aligned_addr; + + if ((bus->number != 0) && (bus->number != 0x40) && + (bus->number != 0x80) && (bus->number != 0xc0)) + return pci_generic_config_write(bus, devfn, where, size, val); + + addr = (unsigned long)bus->ops->map_bus(bus, devfn, where); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + + if (size == 1) { + offset = addr & 0x3; + aligned_addr = (void __iomem *)(addr & ~0x3UL); + value = readl(aligned_addr); + value &= ~(0xFF << (8 * offset)); + value |= ((val << (8 * offset)) & (0xFF << (8 * offset))); + writel(value, aligned_addr); + } else if (size == 2) { + WARN_ON((addr & 0x1) != 0); + offset = addr & 0x3; + aligned_addr = (void __iomem *)(addr & ~0x3UL); + value = readl(aligned_addr); + value &= ~(0xFFFF << (8 * offset)); + value |= ((val << (8 * offset)) & (0xFFFF << (8 * offset))); + writel(value, aligned_addr); + } else { + WARN_ON((addr & 0x3) != 0); + writel(val, (void __iomem *)(addr)); + } + + return PCIBIOS_SUCCESSFUL; +} + + +static struct pci_ops cdns_pcie_host_ops = { + .map_bus = cdns_mango_pci_map_bus, + .read = cdns_pcie_config_read, + .write = cdns_pcie_config_write, +}; + +static const struct of_device_id cdns_pcie_host_of_match[] = { + { .compatible = "sophgo,cdns-pcie-host" }, + + { }, +}; + +static int cdns_pcie_host_init_root_port(struct cdns_mango_pcie_rc *rc) +{ + struct cdns_pcie *pcie = &rc->pcie; + u32 value, ctrl; + u32 id; + + /* + * Set the root complex BAR configuration register: + * - disable both BAR0 and BAR1. + * - enable Prefetchable Memory Base and Limit registers in type 1 + * config space (64 bits). + * - enable IO Base and Limit registers in type 1 config + * space (32 bits). + */ + ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED; + value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS; + cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value); + + /* Set root port configuration space */ + if (rc->vendor_id != 0xffff) { + id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) | + CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id); + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + if (rc->device_id != 0xffff) { + value = cdns_pcie_rp_readl(pcie, PCI_VENDOR_ID); + value &= 0x0000FFFF; + value |= (rc->device_id << 16); + cdns_pcie_rp_writel(pcie, PCI_VENDOR_ID, value); + } + + cdns_pcie_rp_writel(pcie, PCI_CLASS_REVISION, PCI_CLASS_BRIDGE_PCI << 16); + + return 0; +} + +static int cdns_pcie_host_init_address_translation(struct cdns_mango_pcie_rc *rc) +{ + struct cdns_pcie *pcie = &rc->pcie; + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc); + struct resource *cfg_res = rc->cfg_res; + struct resource_entry *entry = NULL; + u32 addr0, addr1, desc1; + u64 cpu_addr; + int r, busnr = 0; + + entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr = entry->res->start; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all. + */ + addr1 = 0; /* Should be programmed to zero. */ + desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); + + cpu_addr = cfg_res->start; + addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 = upper_32_bits(cpu_addr); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1); + + r = 1; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res = entry->res; + u64 pci_addr = res->start - entry->offset; + + if (resource_type(res) == IORESOURCE_IO) + cdns_pcie_set_outbound_region(pcie, busnr, 0, r, + true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); + else + cdns_pcie_set_outbound_region(pcie, busnr, 0, r, + false, + res->start, + pci_addr, + resource_size(res)); + + r++; + } + + /* + * Set Root Port no BAR match Inbound Translation registers: + * needed for MSI and DMA. + * Root Port BAR0 and BAR1 are disabled, hence no need to set their + * inbound translation registers. + */ + addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits); + addr1 = 0; + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0); + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1); + + return 0; +} + +static int cdns_pcie_msi_init(struct cdns_mango_pcie_rc *rc) +{ + struct device *dev = rc->dev; + struct cdns_pcie *pcie = &rc->pcie; + u32 apb_base = CDNS_PCIE_CFG_MANGO_APB; + u64 msi_target = 0; + u32 value = 0; + + // support 512 msi vectors + rc->msi_page = dma_alloc_coherent(dev, 2048, &rc->msi_data, + (GFP_KERNEL|GFP_DMA32|__GFP_ZERO)); + if (rc->msi_page == NULL) + return -1; + + dev_info(dev, "msi_data is 0x%llx\n", rc->msi_data); + msi_target = (u64)rc->msi_data; + + if (rc->link_id == 1) { + apb_base -= 0x800000; + /* Program the msi_data */ + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0868), + lower_32_bits(msi_target)); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG086C), + upper_32_bits(msi_target)); + + value = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG080C)); + value = (value & 0xffff0000) | MAX_MSI_IRQS; + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG080C), value); + } else { + /* Program the msi_data */ + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0860), + lower_32_bits(msi_target)); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0864), + upper_32_bits(msi_target)); + + value = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG085C)); + value = (value & 0x0000ffff) | (MAX_MSI_IRQS << 16); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG085C), value); + } + + return 0; +} + +static int cdns_pcie_host_init(struct device *dev, struct cdns_mango_pcie_rc *rc) +{ + int err; + + err = cdns_pcie_host_init_root_port(rc); + if (err) + return err; + + err = cdns_pcie_host_init_address_translation(rc); + if (err) + return err; + + if (rc->top_intc_used == 0) { + rc->num_vectors = MSI_DEF_NUM_VECTORS; + rc->num_applied_vecs = 0; + if (IS_ENABLED(CONFIG_PCI_MSI)) { + err = cdns_pcie_msi_init(rc); + if (err) + return err; + } + } + return 0; +} + + +static void cdns_pcie_msi_ack_irq(struct irq_data *d) +{ + irq_chip_ack_parent(d); +} + +static void cdns_pcie_msi_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void cdns_pcie_msi_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip cdns_pcie_msi_irq_chip = { + .name = "cdns-msi", + .irq_ack = cdns_pcie_msi_ack_irq, + .irq_mask = cdns_pcie_msi_mask_irq, + .irq_unmask = cdns_pcie_msi_unmask_irq, +}; + +static struct msi_domain_info cdns_pcie_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), + .chip = &cdns_pcie_msi_irq_chip, +}; + +static struct msi_domain_info cdns_pcie_top_intr_msi_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS + | MSI_FLAG_PCI_MSIX), + .chip = &cdns_pcie_msi_irq_chip, +}; + +struct vendor_id_list vendor_id_list[] = { + {"Inter X520", 0x8086, 0x10fb}, + {"Inter I40E", 0x8086, 0x1572}, + //{"WangXun RP1000", 0x8088}, + {"Switchtec", 0x11f8,0x4052}, +}; + +size_t vendor_id_list_num = ARRAY_SIZE(vendor_id_list); + +int check_vendor_id(struct pci_dev *dev, struct vendor_id_list vendor_id_list[], + size_t vendor_id_list_num) +{ + uint16_t device_vendor_id; + uint16_t device_id; + + if (pci_read_config_word(dev, PCI_VENDOR_ID, &device_vendor_id) != 0) { + pr_err("Failed to read device vendor ID\n"); + return 0; + } + + if (pci_read_config_word(dev, PCI_DEVICE_ID, &device_id) != 0) { + pr_err("Failed to read device vendor ID\n"); + return 0; + } + + for (int i = 0; i < vendor_id_list_num; ++i) { + if (device_vendor_id == vendor_id_list[i].vendor_id && device_id == vendor_id_list[i].device_id) { + pr_info("dev: %s vendor ID: 0x%04x device ID: 0x%04x Enable MSI-X IRQ\n", + vendor_id_list[i].name, device_vendor_id, device_id); + return 1; + } + } + return 0; +} + + +static int cdns_pcie_msi_setup_for_top_intc(struct cdns_mango_pcie_rc *rc, int intc_id) +{ + struct irq_domain *irq_parent = cdns_pcie_get_parent_irq_domain(intc_id); + struct fwnode_handle *fwnode = of_node_to_fwnode(rc->dev->of_node); + + if (rc->msix_supported == 1) { + rc->msi_domain = pci_msi_create_irq_domain(fwnode, + &cdns_pcie_top_intr_msi_domain_info, + irq_parent); + } else { + rc->msi_domain = pci_msi_create_irq_domain(fwnode, + &cdns_pcie_msi_domain_info, + irq_parent); + } + + if (!rc->msi_domain) { + dev_err(rc->dev, "create msi irq domain failed\n"); + return -ENODEV; + } + + return 0; +} + +/* MSI int handler */ +irqreturn_t cdns_handle_msi_irq(struct cdns_mango_pcie_rc *rc) +{ + u32 i, pos, irq; + unsigned long val; + u32 status, num_vectors; + irqreturn_t ret = IRQ_NONE; + + num_vectors = rc->num_applied_vecs; + for (i = 0; i <= num_vectors; i++) { + status = readl((void *)(rc->msi_page + i * BYTE_NUM_PER_MSI_VEC)); + if (!status) + continue; + + ret = IRQ_HANDLED; + val = status; + pos = 0; + while ((pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, + pos)) != MAX_MSI_IRQS_PER_CTRL) { + irq = irq_find_mapping(rc->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + generic_handle_irq(irq); + pos++; + } + writel(0, ((void *)(rc->msi_page) + i * BYTE_NUM_PER_MSI_VEC)); + } + if (ret == IRQ_NONE) { + ret = IRQ_HANDLED; + for (i = 0; i <= num_vectors; i++) { + for (pos = 0; pos < MAX_MSI_IRQS_PER_CTRL; pos++) { + irq = irq_find_mapping(rc->irq_domain, + (i * MAX_MSI_IRQS_PER_CTRL) + + pos); + if (!irq) + continue; + generic_handle_irq(irq); + } + } + } + + return ret; +} + +static irqreturn_t cdns_pcie_irq_handler(int irq, void *arg) +{ + struct cdns_mango_pcie_rc *rc = arg; + struct cdns_pcie *pcie = &rc->pcie; + u32 apb_base = CDNS_PCIE_CFG_MANGO_APB; + u32 status = 0; + u32 st_msi_in_bit = 0; + u32 clr_msi_in_bit = 0; + + if (rc->link_id == 1) { + apb_base -= 0x800000; + st_msi_in_bit = CDNS_PCIE_IRS_REG0810_ST_LINK1_MSI_IN_BIT; + clr_msi_in_bit = CDNS_PCIE_IRS_REG0804_CLR_LINK1_MSI_IN_BIT; + } else { + st_msi_in_bit = CDNS_PCIE_IRS_REG0810_ST_LINK0_MSI_IN_BIT; + clr_msi_in_bit = CDNS_PCIE_IRS_REG0804_CLR_LINK0_MSI_IN_BIT; + } + + status = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG0810)); + if ((status >> st_msi_in_bit) & 0x1) { + WARN_ON(!IS_ENABLED(CONFIG_PCI_MSI)); + + //clear msi interrupt bit reg0810[2] + status = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG0804)); + status |= ((u32)0x1 << clr_msi_in_bit); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0804), status); + + status &= ~((u32)0x1 << clr_msi_in_bit); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0804), status); + + cdns_handle_msi_irq(rc); + } + + return IRQ_HANDLED; +} + +/* Chained MSI interrupt service routine */ +static void cdns_chained_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + struct cdns_mango_pcie_rc *rc; + struct cdns_pcie *pcie; + u32 apb_base = CDNS_PCIE_CFG_MANGO_APB; + u32 status = 0; + u32 st_msi_in_bit = 0; + u32 clr_msi_in_bit = 0; + + chained_irq_enter(chip, desc); + + rc = irq_desc_get_handler_data(desc); + pcie = &rc->pcie; + if (rc->link_id == 1) { + apb_base -= 0x800000; + st_msi_in_bit = CDNS_PCIE_IRS_REG0810_ST_LINK1_MSI_IN_BIT; + clr_msi_in_bit = CDNS_PCIE_IRS_REG0804_CLR_LINK1_MSI_IN_BIT; + } else { + st_msi_in_bit = CDNS_PCIE_IRS_REG0810_ST_LINK0_MSI_IN_BIT; + clr_msi_in_bit = CDNS_PCIE_IRS_REG0804_CLR_LINK0_MSI_IN_BIT; + } + + status = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG0810)); + if ((status >> st_msi_in_bit) & 0x1) { + WARN_ON(!IS_ENABLED(CONFIG_PCI_MSI)); + + //clear msi interrupt bit reg0810[2] + status = cdns_pcie_readl(pcie, (apb_base + CDNS_PCIE_IRS_REG0804)); + status |= ((u32)0x1 << clr_msi_in_bit); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0804), status); + + status &= ~((u32)0x1 << clr_msi_in_bit); + cdns_pcie_writel(pcie, (apb_base + CDNS_PCIE_IRS_REG0804), status); + + cdns_handle_msi_irq(rc); + } + + chained_irq_exit(chip, desc); +} + +static int cdns_pci_msi_set_affinity(struct irq_data *d, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static void cdns_pci_bottom_mask(struct irq_data *d) +{ +} + +static void cdns_pci_bottom_unmask(struct irq_data *d) +{ +} + +static void cdns_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct cdns_mango_pcie_rc *rc = irq_data_get_irq_chip_data(d); + u64 msi_target; + + msi_target = (u64)rc->msi_data; + + msg->address_lo = lower_32_bits(msi_target) + BYTE_NUM_PER_MSI_VEC * d->hwirq; + msg->address_hi = upper_32_bits(msi_target); + msg->data = 1; + + rc->num_applied_vecs = d->hwirq; + + dev_err(rc->dev, "msi#%d address_hi %#x address_lo %#x\n", + (int)d->hwirq, msg->address_hi, msg->address_lo); +} + +static void cdns_pci_bottom_ack(struct irq_data *d) +{ +} + +static struct irq_chip cdns_pci_msi_bottom_irq_chip = { + .name = "CDNS-PCI-MSI", + .irq_ack = cdns_pci_bottom_ack, + .irq_compose_msi_msg = cdns_pci_setup_msi_msg, + .irq_set_affinity = cdns_pci_msi_set_affinity, + .irq_mask = cdns_pci_bottom_mask, + .irq_unmask = cdns_pci_bottom_unmask, +}; + +static int cdns_pcie_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct cdns_mango_pcie_rc *rc = domain->host_data; + unsigned long flags; + u32 i; + int bit; + + raw_spin_lock_irqsave(&rc->lock, flags); + + bit = bitmap_find_free_region(rc->msi_irq_in_use, rc->num_vectors, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&rc->lock, flags); + + if (bit < 0) + return -ENOSPC; + + for (i = 0; i < nr_irqs; i++) + irq_domain_set_info(domain, virq + i, bit + i, + rc->msi_irq_chip, + rc, handle_edge_irq, + NULL, NULL); + + return 0; +} + +static void cdns_pcie_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct cdns_mango_pcie_rc *rc = irq_data_get_irq_chip_data(d); + unsigned long flags; + + raw_spin_lock_irqsave(&rc->lock, flags); + + bitmap_release_region(rc->msi_irq_in_use, d->hwirq, + order_base_2(nr_irqs)); + + raw_spin_unlock_irqrestore(&rc->lock, flags); +} + +static const struct irq_domain_ops cdns_pcie_msi_domain_ops = { + .alloc = cdns_pcie_irq_domain_alloc, + .free = cdns_pcie_irq_domain_free, +}; + +int cdns_pcie_allocate_domains(struct cdns_mango_pcie_rc *rc) +{ + struct fwnode_handle *fwnode = of_node_to_fwnode(rc->dev->of_node); + + rc->irq_domain = irq_domain_create_linear(fwnode, rc->num_vectors, + &cdns_pcie_msi_domain_ops, rc); + if (!rc->irq_domain) { + dev_err(rc->dev, "Failed to create IRQ domain\n"); + return -ENOMEM; + } + + irq_domain_update_bus_token(rc->irq_domain, DOMAIN_BUS_NEXUS); + + rc->msi_domain = pci_msi_create_irq_domain(fwnode, + &cdns_pcie_msi_domain_info, + rc->irq_domain); + if (!rc->msi_domain) { + dev_err(rc->dev, "Failed to create MSI domain\n"); + irq_domain_remove(rc->irq_domain); + return -ENOMEM; + } + + return 0; +} + +void cdns_pcie_free_msi(struct cdns_mango_pcie_rc *rc) +{ + if (rc->msi_irq) { + irq_set_chained_handler(rc->msi_irq, NULL); + irq_set_handler_data(rc->msi_irq, NULL); + } + + irq_domain_remove(rc->msi_domain); + irq_domain_remove(rc->irq_domain); + + if (rc->msi_page) + dma_free_coherent(rc->dev, 1024, rc->msi_page, rc->msi_data); + +} + +static int cdns_pcie_msi_setup(struct cdns_mango_pcie_rc *rc) +{ + int ret = 0; + + raw_spin_lock_init(&rc->lock); + + if (IS_ENABLED(CONFIG_PCI_MSI)) { + rc->msi_irq_chip = &cdns_pci_msi_bottom_irq_chip; + + ret = cdns_pcie_allocate_domains(rc); + if (ret) + return ret; + + if (rc->msi_irq) + irq_set_chained_handler_and_data(rc->msi_irq, cdns_chained_msi_isr, rc); + } + + return ret; +} + +static int cdns_pcie_host_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct pci_host_bridge *bridge; + struct cdns_mango_pcie_rc *rc; + struct cdns_pcie *pcie; + struct resource *res; + int ret; + int phy_count; + int top_intc_id = -1; + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + rc = pci_host_bridge_priv(bridge); + rc->dev = dev; + + pcie = &rc->pcie; + pcie->is_rc = true; + pcie->ops = &cdns_mango_ops; + + rc->max_regions = 32; + of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions); + + rc->no_bar_nbits = 32; + of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits); + + rc->vendor_id = 0xffff; + of_property_read_u16(np, "vendor-id", &rc->vendor_id); + + rc->device_id = 0xffff; + of_property_read_u16(np, "device-id", &rc->device_id); + + rc->pcie_id = 0xffff; + of_property_read_u16(np, "pcie-id", &rc->pcie_id); + + rc->link_id = 0xffff; + of_property_read_u16(np, "link-id", &rc->link_id); + + rc->msix_supported = 0; + of_property_read_u32(np, "msix-supported", &rc->msix_supported); + + rc->top_intc_used = 0; + of_property_read_u32(np, "top-intc-used", &rc->top_intc_used); + if (rc->top_intc_used == 1) + of_property_read_u32(np, "top-intc-id", &top_intc_id); + + if (rc->link_id == 0) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); + pcie->reg_base = devm_ioremap_resource(dev, res); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + cdns_pcie_db.pcie_reg_base = pcie->reg_base; + } else if (rc->link_id == 1) { + pcie->reg_base = cdns_pcie_db.pcie_reg_base + 0x800000; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + rc->cfg_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(rc->cfg_base)) { + dev_err(dev, "missing \"cfg\"\n"); + return PTR_ERR(rc->cfg_base); + } + rc->cfg_res = res; + + ret = cdns_pcie_init_phy(dev, pcie); + if (ret) { + dev_err(dev, "failed to init phy\n"); + return ret; + } + platform_set_drvdata(pdev, pcie); + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync() failed\n"); + goto err_get_sync; + } + + ret = cdns_pcie_host_init(dev, rc); + if (ret) + goto err_init; + + if ((rc->top_intc_used == 0) && (IS_ENABLED(CONFIG_PCI_MSI))) { + rc->msi_irq = platform_get_irq_byname(pdev, "msi"); + if (rc->msi_irq <= 0) { + dev_err(dev, "failed to get MSI irq\n"); + goto err_init_irq; + } + + ret = devm_request_irq(dev, rc->msi_irq, cdns_pcie_irq_handler, + IRQF_SHARED | IRQF_NO_THREAD, + "cdns-pcie-irq", rc); + + if (ret) { + dev_err(dev, "failed to request MSI irq\n"); + goto err_init_irq; + } + } + + bridge->dev.parent = dev; + bridge->ops = &cdns_pcie_host_ops; + bridge->map_irq = of_irq_parse_and_map_pci; + bridge->swizzle_irq = pci_common_swizzle; + if (rc->top_intc_used == 0) + bridge->sysdata = rc; + + if (rc->top_intc_used == 0) { + ret = cdns_pcie_msi_setup(rc); + if (ret < 0) + goto err_host_probe; + } else if (rc->top_intc_used == 1) { + ret = cdns_pcie_msi_setup_for_top_intc(rc, top_intc_id); + if (ret < 0) + goto err_host_probe; + } + + ret = pci_host_probe(bridge); + if (ret < 0) + goto err_host_probe; + + return 0; + + err_host_probe: + err_init_irq: + if ((rc->top_intc_used == 0) && pci_msi_enabled()) + cdns_pcie_free_msi(rc); + + err_init: + pm_runtime_put_sync(dev); + + err_get_sync: + pm_runtime_disable(dev); + cdns_pcie_disable_phy(pcie); + phy_count = pcie->phy_count; + while (phy_count--) + device_link_del(pcie->link[phy_count]); + + return ret; +} + +static void cdns_pcie_shutdown(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cdns_pcie *pcie = dev_get_drvdata(dev); + int ret; + + ret = pm_runtime_put_sync(dev); + if (ret < 0) + dev_dbg(dev, "pm_runtime_put_sync failed\n"); + + pm_runtime_disable(dev); + cdns_pcie_disable_phy(pcie); +} + +static struct platform_driver cdns_pcie_host_driver = { + .driver = { + .name = "cdns-pcie-host", + .of_match_table = cdns_pcie_host_of_match, + .pm = &cdns_pcie_pm_ops, + }, + .probe = cdns_pcie_host_probe, + .shutdown = cdns_pcie_shutdown, +}; +builtin_platform_driver(cdns_pcie_host_driver); diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.h b/drivers/pci/controller/cadence/pcie-cadence-sophgo.h new file mode 100644 index 0000000000000..ef46c46678eda --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-sophgo.h @@ -0,0 +1,17 @@ +#ifndef PCIE_CADENCE_SOPHGO +#define PCIE_CADENCE_SOPHGO + + +struct vendor_id_list { + const char *name; + uint16_t vendor_id; + uint16_t device_id; +}; + +extern struct vendor_id_list vendor_id_list[]; +extern size_t vendor_id_list_num; + +extern struct irq_domain *cdns_pcie_get_parent_irq_domain(int intc_id); +int check_vendor_id(struct pci_dev *dev, struct vendor_id_list vendor_id_list[], + size_t vendor_id_list_num); +#endif diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 0706a27d13bef..dcc56b7a5a84e 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -29,6 +29,7 @@ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-y += sifive/ +obj-$(CONFIG_ARCH_SOPHGO) += sophgo/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/sophgo/Makefile b/drivers/soc/sophgo/Makefile new file mode 100644 index 0000000000000..3903bd7a2ef16 --- /dev/null +++ b/drivers/soc/sophgo/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_SOPHGO) += top/top_intc.o diff --git a/drivers/soc/sophgo/top/top_intc.c b/drivers/soc/sophgo/top/top_intc.c new file mode 100644 index 0000000000000..2577137fbc4f0 --- /dev/null +++ b/drivers/soc/sophgo/top/top_intc.c @@ -0,0 +1,412 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IRQ_NUMBER 32 +#define TOP_INTC_NUM 2 +/* + * here we assume all plic hwirq and tic hwirq should + * be contiguous. + * topc_intc hwirq is index of bitmap (both software and + * hardware), and starts from 0. + * so we use tic hwirq as index to get plic hwirq and its + * irq data. + * when used as a msi parent, tic hwirq is written to Top + * reg for triggering irq by a PCIe device. + * + * now we pre-requested plic interrupt, but may try request + * plic interrupt when needed, like gicp_irq_domain_alloc. + */ +struct top_intc_data { + struct platform_device *pdev; + int irq_num; + struct irq_domain *domain; + struct irq_chip *chip; + int for_msi; + int reg_bitwidth; + + DECLARE_BITMAP(irq_bitmap, MAX_IRQ_NUMBER); + spinlock_t lock; + + void __iomem *reg_sta; + void __iomem *reg_set; + void __iomem *reg_clr; + + phys_addr_t reg_set_phys; + + irq_hw_number_t plic_hwirqs[MAX_IRQ_NUMBER]; + int plic_irqs[MAX_IRQ_NUMBER]; + struct irq_data *plic_irq_datas[MAX_IRQ_NUMBER]; + int tic_to_plic[MAX_IRQ_NUMBER]; // mapping from tic hwirq to plic hwirq +}; + +// workaround for using in other modules +struct top_intc_data *tic_data[TOP_INTC_NUM]; + +struct irq_domain *cdns_pcie_get_parent_irq_domain(int intc_id) +{ + if (intc_id >= TOP_INTC_NUM) + return NULL; + + if (tic_data[intc_id]) + return tic_data[intc_id]->domain; + else + return NULL; +} + +static int top_intc_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + struct top_intc_data *data = d->host_data; + + if (fwspec->param_count != 2) + return -EINVAL; + if (fwspec->param[1] >= data->irq_num) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + pr_debug("%s hwirq %d, flag %d\n", __func__, fwspec->param[0], fwspec->param[1]); + return 0; +} + +static int top_intc_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + unsigned long flags; + irq_hw_number_t hwirq; + int i, type, ret = -1; + struct top_intc_data *data = domain->host_data; + + if (data->for_msi) { + // dynamically alloc hwirq + spin_lock_irqsave(&data->lock, flags); + ret = bitmap_find_free_region(data->irq_bitmap, data->irq_num, + order_base_2(nr_irqs)); + spin_unlock_irqrestore(&data->lock, flags); + + if (ret < 0) { + pr_err("%s failed to alloc irq %d, total %d\n", __func__, virq, nr_irqs); + return -ENOSPC; + } + + hwirq = ret; + for (i = 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + data->chip, + data, handle_edge_irq, + NULL, NULL); + data->tic_to_plic[hwirq + i] = data->plic_hwirqs[hwirq + i]; + } + } else { + // try use hwirq specified in parameter + ret = top_intc_domain_translate(domain, args, &hwirq, &type); + if (ret) { + pr_err("%s failed to translate virq %d, %d\n", __func__, virq, ret); + return ret; + } + + // try to occupy bitmap for the given hwirq + spin_lock_irqsave(&data->lock, flags); + ret = bitmap_allocate_region(data->irq_bitmap, hwirq, order_base_2(1)); + spin_unlock_irqrestore(&data->lock, flags); + if (ret < 0) { + pr_err("%s virq %d found hwirq %ld occupied\n", __func__, virq, hwirq); + return -EBUSY; + } + + irq_domain_set_info(domain, virq, hwirq, + data->chip, + data, handle_edge_irq, + NULL, NULL); + + // explicitly set parent + data->tic_to_plic[hwirq] = data->plic_hwirqs[hwirq]; + } + + pr_debug("%s hwirq %ld, irq %d, plic irq %d, total %d\n", __func__, + hwirq, virq, data->plic_irqs[hwirq], nr_irqs); + return 0; +} + +static void top_intc_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + unsigned long flags; + + pr_debug("%s hwirq %ld, irq %d, total %d\n", __func__, d->hwirq, virq, nr_irqs); + + spin_lock_irqsave(&data->lock, flags); + bitmap_release_region(data->irq_bitmap, d->hwirq, + order_base_2(nr_irqs)); + spin_unlock_irqrestore(&data->lock, flags); +} + +static const struct irq_domain_ops top_intc_domain_ops = { + .translate = top_intc_domain_translate, + .alloc = top_intc_domain_alloc, + .free = top_intc_domain_free, +}; + +static void top_intc_ack_irq(struct irq_data *d) +{ + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + int reg_off, bit_off; + struct irq_data *plic_irq_data = data->plic_irq_datas[d->hwirq]; + + reg_off = d->hwirq / data->reg_bitwidth; + bit_off = d->hwirq - data->reg_bitwidth * reg_off; + writel(1 << bit_off, (unsigned int *)data->reg_clr + reg_off); + + pr_debug("%s %ld, parent %s/%ld\n", __func__, d->hwirq, + plic_irq_data->domain->name, plic_irq_data->hwirq); + if (plic_irq_data->chip->irq_ack) + plic_irq_data->chip->irq_ack(plic_irq_data); +} + +static void top_intc_mask_irq(struct irq_data *d) +{ + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + struct irq_data *plic_irq_data = data->plic_irq_datas[d->hwirq]; + + pr_debug("%s %ld, parent %s/%ld\n", __func__, d->hwirq, + plic_irq_data->domain->name, plic_irq_data->hwirq); + plic_irq_data->chip->irq_mask(plic_irq_data); +} + +static void top_intc_unmask_irq(struct irq_data *d) +{ + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + struct irq_data *plic_irq_data = data->plic_irq_datas[d->hwirq]; + + pr_debug("%s %ld, parent %s/%ld\n", __func__, d->hwirq, + plic_irq_data->domain->name, plic_irq_data->hwirq); + plic_irq_data->chip->irq_unmask(plic_irq_data); +} + +static void top_intc_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) +{ + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + + msg->address_lo = lower_32_bits(data->reg_set_phys); + msg->address_hi = upper_32_bits(data->reg_set_phys); + msg->data = 1 << d->hwirq; + + pr_debug("%s msi#%d: address_hi %#x, address_lo %#x, data %#x\n", __func__, + (int)d->hwirq, msg->address_hi, msg->address_lo, msg->data); +} + +static int top_intc_set_affinity(struct irq_data *d, + const struct cpumask *mask, bool force) +{ + struct top_intc_data *data = irq_data_get_irq_chip_data(d); + struct irq_data *plic_irq_data = data->plic_irq_datas[d->hwirq]; + + irq_data_update_effective_affinity(d, mask); + if (plic_irq_data->chip->irq_set_affinity) + return plic_irq_data->chip->irq_set_affinity(plic_irq_data, mask, force); + else + return -EINVAL; +} + +static int top_intc_set_type(struct irq_data *d, u32 type) +{ + /* + * dummy function, so __irq_set_trigger can continue to set + * correct trigger type. + */ + return 0; +} + +static struct irq_chip top_intc_irq_chip = { + .name = "top-intc", + .irq_ack = top_intc_ack_irq, + .irq_mask = top_intc_mask_irq, + .irq_unmask = top_intc_unmask_irq, + .irq_compose_msi_msg = top_intc_setup_msi_msg, + .irq_set_affinity = top_intc_set_affinity, + .irq_set_type = top_intc_set_type, +}; + +static void top_intc_irq_handler(struct irq_desc *plic_desc) +{ + struct irq_chip *plic_chip = irq_desc_get_chip(plic_desc); + struct top_intc_data *data = irq_desc_get_handler_data(plic_desc); + irq_hw_number_t plic_hwirq = irq_desc_get_irq_data(plic_desc)->hwirq; + irq_hw_number_t top_intc_hwirq; + int top_intc_irq, i, ret; + + chained_irq_enter(plic_chip, plic_desc); + + for (i = 0; i < data->irq_num; i++) { + if (data->tic_to_plic[i] == plic_hwirq) + break; + } + if (i < data->irq_num) { + top_intc_hwirq = i; + top_intc_irq = irq_find_mapping(data->domain, top_intc_hwirq); + pr_debug("%s plic hwirq %ld, tic hwirq %ld, tic irq %d\n", __func__, + plic_hwirq, top_intc_hwirq, top_intc_irq); + if (top_intc_irq) + ret = generic_handle_irq(top_intc_irq); + pr_debug("%s handled tic irq %d, %d\n", __func__, top_intc_irq, ret); + } else { + pr_debug("%s not found tic hwirq for plic hwirq %ld\n", __func__, plic_hwirq); + // workaround, ack unexpected(unregistered) interrupt + writel(1 << (plic_hwirq - data->plic_hwirqs[0]), data->reg_clr); + } + + chained_irq_exit(plic_chip, plic_desc); +} + +static int top_intc_probe(struct platform_device *pdev) +{ + struct top_intc_data *data; + struct resource *res; + struct fwnode_handle *fwnode = of_node_to_fwnode(pdev->dev.of_node); + int ret = 0, i; + int intc_id = 0; + + device_property_read_u32(&pdev->dev, "top-intc-id", &intc_id); + if (intc_id >= TOP_INTC_NUM) + return -EINVAL; + + // alloc private data + data = kzalloc(sizeof(struct top_intc_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + platform_set_drvdata(pdev, data); + data->pdev = pdev; + spin_lock_init(&data->lock); + + if (device_property_read_bool(&pdev->dev, "for-msi")) { + dev_info(&pdev->dev, "is a msi parent\n"); + data->for_msi = 1; + } + if (device_property_read_u32(&pdev->dev, "reg-bitwidth", &data->reg_bitwidth)) + data->reg_bitwidth = 32; + + // get register address + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sta"); + data->reg_sta = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_sta)) { + dev_err(&pdev->dev, "failed map status register\n"); + ret = PTR_ERR(data->reg_sta); + goto out; + } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "set"); + data->reg_set = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_set)) { + dev_err(&pdev->dev, "failed map set register\n"); + ret = PTR_ERR(data->reg_set); + goto out; + } + data->reg_set_phys = res->start; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "clr"); + data->reg_clr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_clr)) { + dev_err(&pdev->dev, "failed map clear register\n"); + ret = PTR_ERR(data->reg_clr); + goto out; + } + + // get irq numbers + for (i = 0; i < ARRAY_SIZE(data->plic_hwirqs); i++) { + char name[8]; + int irq; + + snprintf(name, ARRAY_SIZE(name), "msi%d", i); + irq = platform_get_irq_byname(pdev, name); + if (irq < 0) + break; + + data->plic_irqs[i] = irq; + data->plic_irq_datas[i] = irq_get_irq_data(irq); + data->plic_hwirqs[i] = data->plic_irq_datas[i]->hwirq; + dev_dbg(&pdev->dev, "%s: plic hwirq %ld, plic irq %d\n", name, + data->plic_hwirqs[i], data->plic_irqs[i]); + } + data->irq_num = i; + dev_dbg(&pdev->dev, "got %d plic irqs\n", data->irq_num); + + // create IRQ domain + data->domain = irq_domain_create_linear(fwnode, data->irq_num, + &top_intc_domain_ops, data); + if (!data->domain) { + dev_err(&pdev->dev, "create linear irq doamin failed\n"); + ret = -ENODEV; + goto out; + } + data->chip = &top_intc_irq_chip; + + /* + * workaround to deal with IRQ conflict with TPU driver, + * skip the firt IRQ and mark it as used. + */ + //bitmap_allocate_region(data->irq_bitmap, 0, order_base_2(1)); + for (i = 0; i < data->irq_num; i++) + irq_set_chained_handler_and_data(data->plic_irqs[i], + top_intc_irq_handler, data); + + if (data->for_msi) { + irq_domain_update_bus_token(data->domain, DOMAIN_BUS_NEXUS); + if (tic_data[intc_id]) + dev_err(&pdev->dev, "tic_data is not empty, %s\n", + dev_name(&tic_data[intc_id]->pdev->dev)); + tic_data[intc_id] = data; + } else { + /* + * populate child nodes. when test device node is a child, it will not be + * automatically enumerated as a platform device. + */ + of_platform_populate(pdev->dev.of_node, NULL, NULL, NULL); + } + return ret; + +out: + if (data->reg_sta) + iounmap(data->reg_sta); + if (data->reg_set) + iounmap(data->reg_set); + if (data->reg_clr) + iounmap(data->reg_clr); + kfree(data); + return ret; +} + +static const struct of_device_id top_intc_of_match[] = { + { + .compatible = "sophgo,top-intc", + }, + {}, +}; + +static struct platform_driver top_intc_driver = { + .driver = { + .name = "sophgo,top-intc", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(top_intc_of_match), + }, + .probe = top_intc_probe, +}; + +static int __init top_intc_init(void) +{ + return platform_driver_register(&top_intc_driver); +} + +arch_initcall(top_intc_init); From 5bbc4250f6a514ed786d1faade0746dd30c5c7ef Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Thu, 21 Mar 2024 09:18:24 +0800 Subject: [PATCH 18/40] drivers: pcie: sophgo: Create msi-x whitelist,turn on msi-x for top intr Turn on msi-x for top intr. Create msi-x whitelist, Limited the number of msi-x interrupts for inter x520 and wangxun NIC. Signed-off-by: chengjun.li --- drivers/net/ethernet/intel/i40e/i40e_common.c | 3 +- drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 2 +- drivers/pci/msi/msi.c | 97 ++++++++++--------- 3 files changed, 54 insertions(+), 48 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c index 4d7caa1199719..0a9efd8c6471d 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c @@ -3213,7 +3213,8 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, p->base_queue = phys_id; break; case I40E_AQ_CAP_ID_MSIX: - p->num_msix_vectors = number; + //p->num_msix_vectors = number; + p->num_msix_vectors = 8; i40e_debug(hw, I40E_DEBUG_INIT, "HW Capability: MSIX vector count = %d\n", p->num_msix_vectors); diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h index c24a72d1e2737..ca8b8d023a8f9 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h @@ -2069,7 +2069,7 @@ enum { #define IXGBE_DEVICE_CAPS 0x2C #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 -#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 +#define IXGBE_MAX_MSIX_VECTORS_82599 0x09 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 2d117cb74832b..b2cc07eb226c1 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -12,6 +12,7 @@ #include "../pci.h" #include "msi.h" +#include "../controller/cadence/pcie-cadence-sophgo.h" int pci_msi_enable = 1; int pci_msi_ignore_mask; @@ -784,66 +785,70 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int { int hwsize, rc, nvec = maxvec; - if (maxvec < minvec) - return -ERANGE; + if (check_vendor_id(dev, vendor_id_list, vendor_id_list_num)) { + if (maxvec < minvec) + return -ERANGE; - if (dev->msi_enabled) { - pci_info(dev, "can't enable MSI-X (MSI already enabled)\n"); - return -EINVAL; - } + if (dev->msi_enabled) { + pci_info(dev, "can't enable MSI-X (MSI already enabled)\n"); + return -EINVAL; + } - if (WARN_ON_ONCE(dev->msix_enabled)) - return -EINVAL; + if (WARN_ON_ONCE(dev->msix_enabled)) + return -EINVAL; - /* Check MSI-X early on irq domain enabled architectures */ - if (!pci_msi_domain_supports(dev, MSI_FLAG_PCI_MSIX, ALLOW_LEGACY)) - return -ENOTSUPP; + /* Check MSI-X early on irq domain enabled architectures */ + if (!pci_msi_domain_supports(dev, MSI_FLAG_PCI_MSIX, ALLOW_LEGACY)) + return -ENOTSUPP; - if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) - return -EINVAL; + if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) + return -EINVAL; - hwsize = pci_msix_vec_count(dev); - if (hwsize < 0) - return hwsize; + hwsize = pci_msix_vec_count(dev); + if (hwsize < 0) + return hwsize; - if (!pci_msix_validate_entries(dev, entries, nvec)) - return -EINVAL; + if (!pci_msix_validate_entries(dev, entries, nvec)) + return -EINVAL; - if (hwsize < nvec) { - /* Keep the IRQ virtual hackery working */ - if (flags & PCI_IRQ_VIRTUAL) - hwsize = nvec; - else - nvec = hwsize; - } + if (hwsize < nvec) { + /* Keep the IRQ virtual hackery working */ + if (flags & PCI_IRQ_VIRTUAL) + hwsize = nvec; + else + nvec = hwsize; + } - if (nvec < minvec) - return -ENOSPC; + if (nvec < minvec) + return -ENOSPC; - rc = pci_setup_msi_context(dev); - if (rc) - return rc; + rc = pci_setup_msi_context(dev); + if (rc) + return rc; - if (!pci_setup_msix_device_domain(dev, hwsize)) - return -ENODEV; + if (!pci_setup_msix_device_domain(dev, hwsize)) + return -ENODEV; - for (;;) { - if (affd) { - nvec = irq_calc_affinity_vectors(minvec, nvec, affd); - if (nvec < minvec) - return -ENOSPC; - } + for (;;) { + if (affd) { + nvec = irq_calc_affinity_vectors(minvec, nvec, affd); + if (nvec < minvec) + return -ENOSPC; + } - rc = msix_capability_init(dev, entries, nvec, affd); - if (rc == 0) - return nvec; + rc = msix_capability_init(dev, entries, nvec, affd); + if (rc == 0) + return nvec; - if (rc < 0) - return rc; - if (rc < minvec) - return -ENOSPC; + if (rc < 0) + return rc; + if (rc < minvec) + return -ENOSPC; - nvec = rc; + nvec = rc; + } + } else { + return -1; } } From 12f1a8fed3be7048394de2e22582a99e6be54689 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 11:01:11 +0800 Subject: [PATCH 19/40] driver: soc: Add sophgo sg2042 soc support Signed-off-by: Xiaoguang Xing --- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sophgo.c | 276 ++++++ drivers/soc/sophgo/Makefile | 2 + drivers/soc/sophgo/tach/sophgo-tach.c | 330 +++++++ drivers/soc/sophgo/umcu/mcu.c | 1144 +++++++++++++++++++++++++ 5 files changed, 1753 insertions(+) create mode 100644 drivers/pwm/pwm-sophgo.c create mode 100644 drivers/soc/sophgo/tach/sophgo-tach.c create mode 100644 drivers/soc/sophgo/umcu/mcu.c diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index e3fb6e95b3896..3afbbb1118b3d 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) += pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o +obj-$(CONFIG_ARCH_SOPHGO) += pwm-sophgo.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o obj-$(CONFIG_PWM_STI) += pwm-sti.o diff --git a/drivers/pwm/pwm-sophgo.c b/drivers/pwm/pwm-sophgo.c new file mode 100644 index 0000000000000..b6297175a5b77 --- /dev/null +++ b/drivers/pwm/pwm-sophgo.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2007 Ben Dooks + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks , + * Copyright (c) 2013 Tomasz Figa + * + * PWM driver for Samsung SoCs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +#define REG_HLPERIOD 0x0 +#define REG_PERIOD 0x4 +#define REG_GROUP 0x8 +#define REG_POLARITY 0x20 + + +/** + * struct sophgo_pwm_channel - private data of PWM channel + * @period_ns: current period in nanoseconds programmed to the hardware + * @duty_ns: current duty time in nanoseconds programmed to the hardware + * @tin_ns: time of one timer tick in nanoseconds with current timer rate + */ +struct sophgo_pwm_channel { + u32 period; + u32 hlperiod; +}; + +/** + * struct sophgo_pwm_chip - private data of PWM chip + * @chip: generic PWM chip + * @variant: local copy of hardware variant data + * @inverter_mask: inverter status for all channels - one bit per channel + * @base: base address of mapped PWM registers + * @base_clk: base clock used to drive the timers + * @tclk0: external clock 0 (can be ERR_PTR if not present) + * @tclk1: external clock 1 (can be ERR_PTR if not present) + */ +struct sophgo_pwm_chip { + struct pwm_chip chip; + void __iomem *base; + struct clk *base_clk; + u8 polarity_mask; + bool no_polarity; +}; + + +static inline +struct sophgo_pwm_chip *to_sophgo_pwm_chip(struct pwm_chip *chip) +{ + return container_of(chip, struct sophgo_pwm_chip, chip); +} + +static int pwm_sophgo_request(struct pwm_chip *chip, struct pwm_device *pwm_dev) +{ + struct sophgo_pwm_channel *channel; + + channel = kzalloc(sizeof(*channel), GFP_KERNEL); + if (!channel) + return -ENOMEM; + + return pwm_set_chip_data(pwm_dev, channel); +} + +static void pwm_sophgo_free(struct pwm_chip *chip, struct pwm_device *pwm_dev) +{ + struct sophgo_pwm_channel *channel = pwm_get_chip_data(pwm_dev); + + pwm_set_chip_data(pwm_dev, NULL); + kfree(channel); +} + +static int pwm_sophgo_config(struct pwm_chip *chip, struct pwm_device *pwm_dev, + int duty_ns, int period_ns) +{ + struct sophgo_pwm_chip *our_chip = to_sophgo_pwm_chip(chip); + struct sophgo_pwm_channel *channel = pwm_get_chip_data(pwm_dev); + u64 cycles; + + cycles = clk_get_rate(our_chip->base_clk); + cycles *= period_ns; + do_div(cycles, NSEC_PER_SEC); + + channel->period = cycles; + cycles = cycles * duty_ns; + do_div(cycles, period_ns); + channel->hlperiod = channel->period - cycles; + + return 0; +} + +static int pwm_sophgo_enable(struct pwm_chip *chip, struct pwm_device *pwm_dev) +{ + struct sophgo_pwm_chip *our_chip = to_sophgo_pwm_chip(chip); + struct sophgo_pwm_channel *channel = pwm_get_chip_data(pwm_dev); + + writel(channel->period, our_chip->base + REG_GROUP * pwm_dev->hwpwm + REG_PERIOD); + writel(channel->hlperiod, our_chip->base + REG_GROUP * pwm_dev->hwpwm + REG_HLPERIOD); + + return 0; +} + +static void pwm_sophgo_disable(struct pwm_chip *chip, + struct pwm_device *pwm_dev) +{ + struct sophgo_pwm_chip *our_chip = to_sophgo_pwm_chip(chip); + + writel(0, our_chip->base + REG_GROUP * pwm_dev->hwpwm + REG_PERIOD); + writel(0, our_chip->base + REG_GROUP * pwm_dev->hwpwm + REG_HLPERIOD); +} + +static int pwm_sophgo_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int ret; + + bool enabled = pwm->state.enabled; + + if (state->polarity != pwm->state.polarity && pwm->state.enabled) { + pwm_sophgo_disable(chip, pwm); + enabled = false; + } + + if (!state->enabled) { + if (enabled) + pwm_sophgo_disable(chip, pwm); + return 0; + } + + ret = pwm_sophgo_config(chip, pwm, state->duty_cycle, state->period); + if (ret) { + dev_err(chip->dev, "pwm apply err\n"); + return ret; + } + dev_dbg(chip->dev, "%s tate->enabled =%d\n", __func__, state->enabled); + if (state->enabled) + ret = pwm_sophgo_enable(chip, pwm); + else + pwm_sophgo_disable(chip, pwm); + + if (ret) { + dev_err(chip->dev, "pwm apply failed\n"); + return ret; + } + return ret; +} + +static const struct pwm_ops pwm_sophgo_ops = { + .request = pwm_sophgo_request, + .free = pwm_sophgo_free, + .apply = pwm_sophgo_apply, + .owner = THIS_MODULE, +}; + +static const struct of_device_id sophgo_pwm_match[] = { + { .compatible = "sophgo,sophgo-pwm" }, + { }, +}; +MODULE_DEVICE_TABLE(of, sophgo_pwm_match); + +static int pwm_sophgo_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct sophgo_pwm_chip *chip; + struct resource *res; + int ret; + + pr_info("%s\n", __func__); + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->chip.dev = &pdev->dev; + chip->chip.ops = &pwm_sophgo_ops; + chip->chip.base = -1; + chip->polarity_mask = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + chip->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + chip->base_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(chip->base_clk)) { + dev_err(dev, "failed to get pwm source clk\n"); + return PTR_ERR(chip->base_clk); + } + + ret = clk_prepare_enable(chip->base_clk); + if (ret < 0) { + dev_err(dev, "failed to enable base clock\n"); + return ret; + } + + //pwm-num default is 4, compatible with sg2042 + if (of_property_read_bool(pdev->dev.of_node, "pwm-num")) + device_property_read_u32(&pdev->dev, "pwm-num", &chip->chip.npwm); + else + chip->chip.npwm = 4; + + //no_polarity default is false(have polarity) , compatible with sg2042 + if (of_property_read_bool(pdev->dev.of_node, "no-polarity")) + chip->no_polarity = true; + else + chip->no_polarity = false; + pr_debug("chip->chip.npwm =%d chip->no_polarity=%d\n", chip->chip.npwm, chip->no_polarity); + + platform_set_drvdata(pdev, chip); + + ret = pwmchip_add(&chip->chip); + if (ret < 0) { + dev_err(dev, "failed to register PWM chip\n"); + clk_disable_unprepare(chip->base_clk); + return ret; + } + + return 0; +} + +static int pwm_sophgo_remove(struct platform_device *pdev) +{ + struct sophgo_pwm_chip *chip = platform_get_drvdata(pdev); + + pwmchip_remove(&chip->chip); + + clk_disable_unprepare(chip->base_clk); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pwm_sophgo_suspend(struct device *dev) +{ + return 0; +} + +static int pwm_sophgo_resume(struct device *dev) +{ + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(pwm_sophgo_pm_ops, pwm_sophgo_suspend, + pwm_sophgo_resume); + +static struct platform_driver pwm_sophgo_driver = { + .driver = { + .name = "sophgo-pwm", + .pm = &pwm_sophgo_pm_ops, + .of_match_table = of_match_ptr(sophgo_pwm_match), + }, + .probe = pwm_sophgo_probe, + .remove = pwm_sophgo_remove, +}; +module_platform_driver(pwm_sophgo_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("chunzhi.lin"); +MODULE_DESCRIPTION("Sophgo PWM driver"); diff --git a/drivers/soc/sophgo/Makefile b/drivers/soc/sophgo/Makefile index 3903bd7a2ef16..1e143d85aa17c 100644 --- a/drivers/soc/sophgo/Makefile +++ b/drivers/soc/sophgo/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_ARCH_SOPHGO) += top/top_intc.o +obj-$(CONFIG_ARCH_SOPHGO) += umcu/mcu.o +obj-$(CONFIG_ARCH_SOPHGO) += tach/sophgo-tach.o diff --git a/drivers/soc/sophgo/tach/sophgo-tach.c b/drivers/soc/sophgo/tach/sophgo-tach.c new file mode 100644 index 0000000000000..77884d80eace9 --- /dev/null +++ b/drivers/soc/sophgo/tach/sophgo-tach.c @@ -0,0 +1,330 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DEV_NAME "sophgo-tach" +#define MHZ 1000000 +#define USER_PORT 100 +#define USER_MSG 30 + +struct fan_state { + unsigned int freq_num; + bool enable; +}; + +struct sophgo_fan_speed_device { + struct device *dev; + struct device *parent; + struct class *class; + dev_t devno; + u32 __iomem *regs; + struct delayed_work poll_queue; + struct fan_state fan_state; + struct mutex enable_lock; + struct mutex freqnum_lock; +}; + +static int fan_index; +static struct class *sophgo_fan_speed_class; +static struct sock *nl_fd; + +static int send_msg(char *pbuf, uint16_t len) +{ + struct sk_buff *nl_skb; + struct nlmsghdr *nlh; + int ret = 0; + + //alloc a new netlink message + nl_skb = nlmsg_new(len, GFP_ATOMIC); + if (!nl_skb) { + pr_err("sophgo_fan_speed, netlink alloc skb error!\n"); + return -ENOMEM; + } + + //add a new netlink message to skb + nlh = nlmsg_put(nl_skb, 0, 0, USER_MSG, len, 0); + if (nlh == NULL) { + pr_err("sophgo_fan_speed, nlmsg_put error!\n"); + nlmsg_free(nl_skb); + return -EFAULT; + } + + memcpy(nlmsg_data(nlh), pbuf, len); + ret = netlink_unicast(nl_fd, nl_skb, USER_PORT, MSG_DONTWAIT); + + return ret; +} + +static void recv_cb(struct sk_buff *skb) +{ + struct nlmsghdr *nlh = NULL; + void *data = NULL; + + if (skb->len >= nlmsg_total_size(0)) { + nlh = nlmsg_hdr(skb); + data = nlmsg_data(nlh); + if (data) { + pr_info("sophgo_fan_speed, kernel receive data: %s\n", (int8_t *)data); + send_msg(data, nlmsg_len(nlh)); + } + } +} + +struct netlink_kernel_cfg cfg = { + .input = recv_cb, +}; + +static void fan_speed_check(struct work_struct *work) +{ + struct sophgo_fan_speed_device *sophgo_fan = container_of(work, + struct sophgo_fan_speed_device, poll_queue.work); + int speed, ret = 0; + char buf[64]; + + speed = readl(sophgo_fan->regs + 1); + if (speed == 0) { + dev_dbg(sophgo_fan->dev, "fan stop!"); + ret = snprintf(buf, 32, "%s fan stop!\n", dev_name(sophgo_fan->dev)); + if (ret <= 0 || ret > 32) { + dev_err(sophgo_fan->dev, "%s snprintf failed\n", __func__); + return; + } + ret = send_msg(buf, sizeof(buf)); + if (ret < 0) + dev_dbg(sophgo_fan->dev, "%s send msg failed, ret=%d\n", __func__, ret); + } + mod_delayed_work(system_freezable_wq, &sophgo_fan->poll_queue, + round_jiffies(msecs_to_jiffies(5000))); +} + +static void fan_speed_enable(bool enalbe, struct sophgo_fan_speed_device *sophgo_fan) +{ + if (enalbe) { + cancel_delayed_work(&sophgo_fan->poll_queue); + writel(sophgo_fan->fan_state.freq_num, sophgo_fan->regs); + mod_delayed_work(system_freezable_wq, &sophgo_fan->poll_queue, + round_jiffies(msecs_to_jiffies(5000))); + sophgo_fan->fan_state.enable = true; + } else { + cancel_delayed_work(&sophgo_fan->poll_queue); + writel(0, sophgo_fan->regs); + sophgo_fan->fan_state.enable = false; + } +} + +static ssize_t freq_num_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sophgo_fan_speed_device *sophgo_fan; + + sophgo_fan = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", sophgo_fan->fan_state.freq_num); +} + +static ssize_t freq_num_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int val, ret = 0; + struct sophgo_fan_speed_device *sophgo_fan; + + sophgo_fan = dev_get_drvdata(dev); + + ret = kstrtoint(buf, 0, &val); + if (ret) + return ret; + + if (val < (MHZ/10) || val > (1000*MHZ)) + ret = -EINVAL; + + mutex_lock(&sophgo_fan->freqnum_lock); + sophgo_fan->fan_state.freq_num = val; + mutex_unlock(&sophgo_fan->freqnum_lock); + + return ret ? : size; +} + +static ssize_t enable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct sophgo_fan_speed_device *sophgo_fan; + + sophgo_fan = dev_get_drvdata(dev); + + return sprintf(buf, "%d\n", sophgo_fan->fan_state.enable); +} + +static ssize_t enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int val, ret = 0; + struct sophgo_fan_speed_device *sophgo_fan; + + sophgo_fan = dev_get_drvdata(dev); + + ret = kstrtoint(buf, 0, &val); + if (ret) + return ret; + + mutex_lock(&sophgo_fan->enable_lock); + switch (val) { + case 0: + fan_speed_enable(false, sophgo_fan); + break; + case 1: + fan_speed_enable(true, sophgo_fan); + break; + default: + ret = -EINVAL; + } + mutex_unlock(&sophgo_fan->enable_lock); + + return ret ? : size; +} + +static ssize_t fan_speed_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + int ret = -1; + struct sophgo_fan_speed_device *sophgo_fan; + + sophgo_fan = dev_get_drvdata(dev); + ret = snprintf(buf, 32, "fan_speed:%d\n", readl(sophgo_fan->regs + 1)); + if (ret <= 0 || ret > 32) { + dev_err(sophgo_fan->dev, "%s snprintf failed %d\n", __func__, ret); + return -EFAULT; + } + dev_dbg(sophgo_fan->dev, "%s\n", buf); + return ret; +} + +static DEVICE_ATTR_RW(enable); +static DEVICE_ATTR_RW(freq_num); +static DEVICE_ATTR_RO(fan_speed); + +static struct attribute *fan_speed_attrs[] = { + &dev_attr_enable.attr, + &dev_attr_freq_num.attr, + &dev_attr_fan_speed.attr, + NULL, +}; +ATTRIBUTE_GROUPS(fan_speed); + +static int sophgo_fan_speed_probe(struct platform_device *pdev) +{ + struct resource *res; + struct sophgo_fan_speed_device *sophgo_fan; + char dev_name[32]; + int ret; + + sophgo_fan = devm_kzalloc(&pdev->dev, sizeof(*sophgo_fan), GFP_KERNEL); + if (sophgo_fan == NULL) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sophgo_fan->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sophgo_fan->regs)) + return PTR_ERR(sophgo_fan->regs); + + ret = snprintf(dev_name, 15, "%s-%d", DEV_NAME, fan_index++); + if (ret <= 0 || ret > 15) { + dev_err(&pdev->dev, "%s snprintf failed\n", __func__); + return -EINVAL; + } + ret = alloc_chrdev_region(&sophgo_fan->devno, 0, 1, dev_name); + if (ret < 0) { + dev_err(&pdev->dev, "register chrdev error\n"); + return ret; + } + sophgo_fan->class = sophgo_fan_speed_class; + sophgo_fan->dev = device_create(sophgo_fan->class, sophgo_fan->parent, + sophgo_fan->devno, sophgo_fan, dev_name); + if (IS_ERR(sophgo_fan->dev)) { + ret = PTR_ERR(sophgo_fan->dev); + dev_err(&pdev->dev, "create device failed\n"); + unregister_chrdev_region(sophgo_fan->devno, 1); + return ret; + } + + //as fan source clk 100M, we advise to set freq num 100M + sophgo_fan->fan_state.freq_num = 100*MHZ; + mutex_init(&sophgo_fan->freqnum_lock); + mutex_init(&sophgo_fan->enable_lock); + + platform_set_drvdata(pdev, sophgo_fan); + INIT_DELAYED_WORK(&sophgo_fan->poll_queue, fan_speed_check); + + return 0; +} + +static int sophgo_fan_speed_remove(struct platform_device *pdev) +{ + struct sophgo_fan_speed_device *sophgo_fan = platform_get_drvdata(pdev); + + cancel_delayed_work(&sophgo_fan->poll_queue); + device_destroy(sophgo_fan->class, sophgo_fan->devno); + unregister_chrdev_region(sophgo_fan->devno, 1); + kfree(sophgo_fan); + sophgo_fan = NULL; + return 0; +} + +static const struct of_device_id sophgo_fan_speed_of_match[] = { + { + .compatible = "sophgo,sophgo-tach", + }, + {} +}; + +static struct platform_driver sophgo_fan_speed_driver = { + .probe = sophgo_fan_speed_probe, + .remove = sophgo_fan_speed_remove, + .driver = { + .name = "sophgo,sophgo-tach", + .of_match_table = sophgo_fan_speed_of_match, + }, +}; + +static int __init sophgo_fan_speed_init(void) +{ + sophgo_fan_speed_class = class_create(DEV_NAME); + if (IS_ERR(sophgo_fan_speed_class)) { + pr_err("class create failed\n"); + return PTR_ERR(sophgo_fan_speed_class); + } + sophgo_fan_speed_class->dev_groups = fan_speed_groups; + + nl_fd = netlink_kernel_create(&init_net, USER_MSG, &cfg); + if (!nl_fd) { + pr_err("sophgo_fan_speed, cannot create netlink socket!\n"); + return -1; + } + fan_index = 0; + return platform_driver_register(&sophgo_fan_speed_driver); +} + +static void __exit sophgo_fan_speed_exit(void) +{ + class_destroy(sophgo_fan_speed_class); + if (nl_fd) { + netlink_kernel_release(nl_fd); + nl_fd = NULL; + } +} + +module_init(sophgo_fan_speed_init); +module_exit(sophgo_fan_speed_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Xiao Wang"); +MODULE_DESCRIPTION("minimal module"); +MODULE_VERSION("ALPHA"); diff --git a/drivers/soc/sophgo/umcu/mcu.c b/drivers/soc/sophgo/umcu/mcu.c new file mode 100644 index 0000000000000..bf419f1821ef2 --- /dev/null +++ b/drivers/soc/sophgo/umcu/mcu.c @@ -0,0 +1,1144 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* fixed MCU registers */ +#define MCU_REG_BOARD_TYPE 0x00 +#define MCU_REG_VERSION 0x01 +#define MCU_REG_SOC_TEMP 0x04 +#define MCU_REG_BOARD_TEMP 0x05 +#define MCU_REG_PWROFF_REASON1 0x06 +#define MCU_REG_PWROFF_REASON2 0x07 + +#define MCU_REG_CRITICAL_ACTIONS 0x65 +#define MCU_REG_CRITICAL_TEMP 0x66 +#define MCU_REG_REPOWERON_TEMP 0x67 +#define MCU_REG_KEEP_DDR_POWERON 0x68 + +#define MCU_CRITICAL_ACTION_POWEROFF 0x2 +#define MCU_CRITICAL_ACTION_REBOOT 0X1 + +#define MANGO_BOARD_TYPE_MASK 1 << 7 + +#ifndef assert +#define assert(exp) WARN_ON(!(exp)) +#endif + +struct mcu_features { + u8 id; + char *proj; + char *soc; + char *chip; + + int board_type; + int mcu_ver; + int pcb_ver; + int soc_tmp; + int board_tmp; + int alert_status; + int alert_mask; + int rst_cnt; + int uptime; + int lock; + int power; + int power_tpu; + int brd_id; + int brd_ip; + + int critical_action; + int critical_temp; + int repoweron_temp; + int keep_ddr_poweron; + + char *alert_table[16]; +}; + +struct mcu_info { + u8 board_type; + u8 mcu_ver; + u8 pcb_ver; + u8 rst_cnt; + int updated; +}; + +struct mcu_ctx { + const struct mcu_features *features; + struct i2c_client *i2c; + struct mcu_info info; + u32 channel_config[4]; + struct hwmon_channel_info temp_info; + const struct hwmon_channel_info *channel_info[3]; + struct hwmon_chip_info chip; + struct mutex update_lock; + unsigned int hwmon_update_interval; /* in milliseconds */ +}; + +const struct mcu_features mcu_list[] = { + { + 0x80, "SG2042 EVB", "SG2042", "GD32", + 0x00, 0x01, 0x02, 0x04, 0x05, 0x06, 0x08, 0x0a, 0x0b, -1, + -1, -1, -1, -1, MCU_REG_CRITICAL_ACTIONS, + MCU_REG_CRITICAL_TEMP, MCU_REG_REPOWERON_TEMP, + MCU_REG_KEEP_DDR_POWERON, + { + "SoC overheat", + "Power supply overheat", + "Board overheat", + "Board overheat and shutdown", + "SoC overheat and shutdown", + "Power supply failure", + "12V power supply failure", + "SoC required reboot", + }, + }, + + { + 0x83, "SG2042 X4", "SG2042", "GD32", + 0x00, 0x01, 0x02, 0x04, 0x05, 0x06, 0x08, 0x0a, 0x0b, -1, + -1, -1, -1, -1, MCU_REG_CRITICAL_ACTIONS, + MCU_REG_CRITICAL_TEMP, MCU_REG_REPOWERON_TEMP, + MCU_REG_KEEP_DDR_POWERON, + { + "SoC overheat", + "Power supply overheat", + "Board overheat", + "Board overheat and shutdown", + "SoC overheat and shutdown", + "Power supply failure", + "12V power supply failure", + "SoC required reboot", + }, + }, + + { + 0x90, "MILKV PIONEER", "SG2042", "GD32", + 0x00, 0x01, 0x02, 0x04, 0x05, 0x06, 0x08, 0x0a, 0x0b, -1, + -1, -1, -1, -1, MCU_REG_CRITICAL_ACTIONS, + MCU_REG_CRITICAL_TEMP, MCU_REG_REPOWERON_TEMP, + MCU_REG_KEEP_DDR_POWERON, + { + "SoC overheat", + "Power supply overheat", + "Board overheat", + "Board overheat and shutdown", + "SoC overheat and shutdown", + "Power supply failure", + "12V power supply failure", + "SoC required reboot", + }, + }, +}; + +static const char help[] = +"\n" +"sys files description\n" +"======================\n" +"Bitmain unified mcu device driver\n" +"You can get/set MCU though read/write operation\n" +"eg. You can get fixed information though command\n" +"$cat /sys/bus/i2c/0-0017/information\n" +"You can set alert mask though command\n" +"$echo 0xffff /sys/bus/i2c/0-0017/alert\n" +"\n" +"information\n" +"-----------\n" +"Fixed information during SoC uptime\n" +"Read this file will return such information\n" +"Write this file to force SoC re-get such information from MCU\n" +"No matter what data you write to or just invoke write with a length of 0\n" +"File pointer will move forward after read,\n" +"write has no effect on file pointer\n" +"\n" +"temperature\n" +"-----------\n" +"Temperature value, sensors located on SoC and on board\n" +"Read this file will return temperature of both in celsius\n" +"Write is forbidden\n" +"\n" +"uptime\n" +"------\n" +"Uptime (from SoC poweron) in seconds\n" +"Read will get this value, write is forbidden\n" +"\n" +"alert\n" +"-----\n" +"Alert control and status\n" +"Read will get current alert status\n" +"Write corresponding bit to 1 will mask this alert\n" +"You can use 0x/0X for hex, 0 for octal\n" +"other leading characters will be considered as decimal\n" +"Values larger than 0xffff is forbidden\n" +"\n"; + +enum { + MCU_I2C_TYPE_U = 0, + MCU_I2C_TYPE_U8, + MCU_I2C_TYPE_U16, + MCU_I2C_TYPE_U32, + MCU_I2C_TYPE_U64, + MCU_I2C_TYPE_D, + MCU_I2C_TYPE_S8, + MCU_I2C_TYPE_S16, + MCU_I2C_TYPE_S32, + MCU_I2C_TYPE_S64, + MCU_I2C_TYPE_MAX, +}; + +static const char *mcu_i2c_type_list[MCU_I2C_TYPE_MAX] = { + [MCU_I2C_TYPE_U] = "u", + [MCU_I2C_TYPE_U8] = "u8", + [MCU_I2C_TYPE_U16] = "u16", + [MCU_I2C_TYPE_U32] = "u32", + [MCU_I2C_TYPE_U64] = "u64", + [MCU_I2C_TYPE_D] = "d", + [MCU_I2C_TYPE_S8] = "s8", + [MCU_I2C_TYPE_S16] = "s16", + [MCU_I2C_TYPE_S32] = "s32", + [MCU_I2C_TYPE_S64] = "s64", +}; + +static int check_token(char *token) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mcu_i2c_type_list); ++i) { + if (strcmp(token, mcu_i2c_type_list[i]) == 0) + return i; + } + return -EINVAL; +} + +static inline struct device *i2c2dev(struct i2c_client *i2c) +{ + return &i2c->dev; +} + +static int mcu_i2c_write_byte(struct i2c_client *i2c, int reg, u8 data) +{ + int err; + + if (reg == -1) + return 0; + err = i2c_smbus_write_byte_data(i2c, reg, data); + dev_dbg(i2c2dev(i2c), "%d : %u\n", reg, data); + return err; +} + +static int mcu_i2c_read_byte(struct i2c_client *i2c, int reg) +{ + int err; + + if (reg == -1) + return 0; + err = i2c_smbus_read_byte_data(i2c, reg); + dev_dbg(i2c2dev(i2c), "%d : %d\n", reg, err); + return err; +} + +static int mcu_i2c_write_block(struct i2c_client *i2c, int reg, + int len, void *data) +{ + int err, i; + + if (reg == -1) + return 0; + + err = i2c_smbus_write_i2c_block_data(i2c, reg, len, data); + for (i = 0; i < len; ++i) + dev_dbg(i2c2dev(i2c), "%d : %u\n", reg + i, ((u8 *)data)[i]); + return err; +} + +static int mcu_i2c_read_block(struct i2c_client *i2c, int reg, + int len, void *data) +{ + int err, i; + + if (reg == -1) + return 0; + + err = i2c_smbus_read_i2c_block_data(i2c, reg, len, data); + for (i = 0; i < len; ++i) + dev_dbg(i2c2dev(i2c), "%d : %u\n", reg + i, ((u8 *)data)[i]); + + return err; +} + +static int mcu_i2c_sreadf(struct i2c_client *i2c, const char *fmt, ...) +{ + va_list arg; + const char *p = fmt; + const char *start, *end; + char token[16]; + int tokenlen; + int ret = -EINVAL; + int idx; + + if (fmt == NULL) + return -EINVAL; + + va_start(arg, fmt); + + while (*p) { + /* skip all % */ + while (*p == '%') + ++p; + start = p; + while (*p && *p != '%') + ++p; + /* now *p is ether \0 or % */ + end = p; + tokenlen = end - start; + if (tokenlen > sizeof(token) - 1) { + ret = -EINVAL; + goto end; + } + if (tokenlen == 0) + continue; + /* get this token */ + memcpy(token, start, tokenlen); + token[tokenlen] = 0; /* terminat this string */ + idx = check_token(token); + if (idx < 0) { + ret = idx; + goto end; + } + + ret = mcu_i2c_read_byte(i2c, va_arg(arg, int)); + if (ret < 0) + goto end; + + switch (idx) { + case MCU_I2C_TYPE_U: + *va_arg(arg, unsigned int *) = ret; + break; + case MCU_I2C_TYPE_U8: + *va_arg(arg, u8 *) = ret; + break; + case MCU_I2C_TYPE_U16: + *va_arg(arg, u16 *) = ret; + break; + case MCU_I2C_TYPE_U32: + *va_arg(arg, u32 *) = ret; + break; + case MCU_I2C_TYPE_U64: + *va_arg(arg, u64 *) = ret; + break; + case MCU_I2C_TYPE_D: + *va_arg(arg, int *) = ret; + break; + case MCU_I2C_TYPE_S8: + *va_arg(arg, s8 *) = ret; + break; + case MCU_I2C_TYPE_S16: + *va_arg(arg, s16 *) = ret; + break; + case MCU_I2C_TYPE_S32: + *va_arg(arg, s32 *) = ret; + break; + case MCU_I2C_TYPE_S64: + *va_arg(arg, s64 *) = ret; + break; + default: + assert(false); + break; + } + } + + ret = 0; +end: + va_end(arg); + return ret; +} + +/* sysfs callbacks */ + +static inline struct i2c_client *dev2i2c(struct device *dev) +{ + return container_of(dev, struct i2c_client, dev); +} + +static const inline struct mcu_features *dev2features(struct device *dev) +{ + struct i2c_client *i2c = dev2i2c(dev); + struct mcu_ctx *ctx = (struct mcu_ctx *)i2c_get_clientdata(i2c); + + return ctx->features; +} + +static ssize_t help_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + buf[0] = 0; + strncpy(buf, help, PAGE_SIZE); + return strlen(buf); +} + +static int mcu_msg_append(char *base, unsigned long limit, + const char *fmt, ...) +{ + int len = strlen(base); + va_list arg; + + va_start(arg, fmt); + len += vsnprintf(base + len, limit - len, fmt, arg); + va_end(arg); + return len; +} + +ssize_t info_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct i2c_client *i2c = dev2i2c(dev); + struct mcu_ctx *ctx = (struct mcu_ctx *)i2c_get_clientdata(i2c); + struct mcu_info *info = &ctx->info; + const struct mcu_features *features = ctx->features; + int err; + + if (info->updated == 0) { + /* get information from mcu through i2c */ + err = mcu_i2c_sreadf(i2c, "%u8%u8%u8%u8", + features->board_type, &info->board_type, + features->mcu_ver, &info->mcu_ver, + features->pcb_ver, &info->pcb_ver, + features->rst_cnt, &info->rst_cnt); + if (err) + return err; + info->updated = 1; + } + + /* convert to json text */ + mcu_msg_append(buf, PAGE_SIZE, "{\n"); + mcu_msg_append(buf, PAGE_SIZE, "\t\"model\": \"%s\",\n", features->proj); + mcu_msg_append(buf, PAGE_SIZE, "\t\"chip\": \"%s\",\n", features->soc); + mcu_msg_append(buf, PAGE_SIZE, "\t\"mcu\": \"%s\",\n", features->chip); + mcu_msg_append(buf, PAGE_SIZE, "\t\"board type\": \"0x%02X\",\n", info->board_type); + mcu_msg_append(buf, PAGE_SIZE, "\t\"mcu version\": \"0x%02X\",\n", info->mcu_ver); + mcu_msg_append(buf, PAGE_SIZE, "\t\"pcb version\": \"0x%02X\",\n", info->pcb_ver); + mcu_msg_append(buf, PAGE_SIZE, "\t\"reset count\": %u\n", info->rst_cnt); + err = mcu_msg_append(buf, PAGE_SIZE, "}\n"); + + return err; +} + +static ssize_t info_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *i2c = dev2i2c(dev); + struct mcu_ctx *ctx = (struct mcu_ctx *)i2c_get_clientdata(i2c); + struct mcu_info *info = &ctx->info; + + info->updated = 0; + return count; +} + +ssize_t brdid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int err = 0; + const struct mcu_features *features = dev2features(dev); + + if (features->brd_id == -1) + return -ENODEV; + + err = mcu_i2c_read_byte(dev2i2c(dev), features->brd_id); + if (err < 0) + return err; + + return sprintf(buf, "brdid:%u\n", err); +} + +ssize_t brdip_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + u8 ip[4]; + int err; + const struct mcu_features *features = dev2features(dev); + + if (features->brd_ip == -1) + return -ENODEV; + + memset(ip, 0, sizeof(ip)); + err = mcu_i2c_read_block(dev2i2c(dev), features->brd_ip, + sizeof(ip), ip); + if (err < 0) + return err; + + return mcu_msg_append(buf, PAGE_SIZE, "brdip:%u.%u.%u.%u\n", + ip[0], ip[1], ip[2], ip[3]); +} + +static ssize_t brdip_store(struct device *dev, struct device_attribute *attr, + const char *ubuf, size_t len) +{ + u8 ip[4]; + char buf[32]; + char *s, *p, *n; + unsigned long res; + int i, err; + const struct mcu_features *features = dev2features(dev); + + if (features->brd_ip == -1) + return -ENODEV; + + memset(buf, 0, sizeof(buf)); + len = min(sizeof(buf), len); + memcpy(buf, ubuf, len); + s = buf; + for (i = 0; i < 4; i++) { + if (i != 3) { + p = strchr(s, '.'); + n = p+1; + *p = '\0'; + } + err = kstrtoul(s, 10, &res); + if (err) + return err; + ip[i] = (u8)res; + dev_dbg(dev, "ip[%d] = %d\n", i, ip[i]); + s = n; + } + err = mcu_i2c_write_block(dev2i2c(dev), features->brd_ip, + sizeof(ip), ip); + if (err < 0) + return err; + + return len; +} +ssize_t uptime_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + u8 t[2]; + int err; + const struct mcu_features *features = dev2features(dev); + + err = mcu_i2c_read_block(dev2i2c(dev), features->uptime, + sizeof(t), t); + if (err < 0) + return err; + + return mcu_msg_append(buf, PAGE_SIZE, + "%u Seconds\n", t[0] | (t[1] << 8)); +} + +ssize_t temp_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + s8 t[2]; + int err; + const struct mcu_features *features = dev2features(dev); + + /* get information from mcu through i2c */ + err = mcu_i2c_sreadf(dev2i2c(dev), "%s8%s8", + features->soc_tmp, t, + features->board_tmp, t + 1); + if (err) + return err; + + mcu_msg_append(buf, PAGE_SIZE, + "SoC temperature: %d Cel\n", t[0]); + return mcu_msg_append(buf, PAGE_SIZE, + "Board temperature: %d Cel\n", t[1]); +} + + +static const char *alert_id2name(const struct mcu_features *features, int id) +{ + if (features->alert_table[id]) + return features->alert_table[id]; + return "Unknown alert"; +} + +ssize_t alert_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int cnt = 0; + int i, err; + u8 t[4]; + u16 mask, status; + const struct mcu_features *features = dev2features(dev); + const char *alt_msg; + + if (features->alert_status == -1) + return 0; + + err = mcu_i2c_read_block(dev2i2c(dev), features->alert_mask, + sizeof(t), t); + /* get information from mcu through i2c */ + if (err < 0) + return err; + + status = t[0] | (t[1] << 8); + mask = t[2] | (t[3] << 8); + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "Mask 0x%02x, Status 0x%02x\n", + mask, status); + + if (status == 0) { + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "Working fine\n"); + } else { + for (i = 0; i < sizeof(status) * 8; ++i) { + if ((status >> i) & 1) { + alt_msg = alert_id2name(features, i); + cnt += snprintf(buf + cnt, + PAGE_SIZE - cnt, + "%d: %s\n", + i, alt_msg); + } + } + } + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "**************************************************\n"); + + for (i = 0; i < 16; ++i) { + if (features->alert_table[i] == NULL) + continue; + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, + "%d: %s\n", i, alert_id2name(features, i)); + } + + return cnt; +} + +static ssize_t alert_store(struct device *dev, struct device_attribute *attr, + const char *ubuf, size_t len) +{ + char buf[32]; + u8 t[2]; + unsigned long res; + int err; + const struct mcu_features *features = dev2features(dev); + + if (features->alert_mask == -1) + return -ENODEV; + + len = min(sizeof(buf) - 1, len); + memcpy(buf, ubuf, len); + + buf[len] = 0; // zero terminated + err = kstrtoul(buf, 0, &res); + if (err) + return err; + if (res > 0xffff) + return -EINVAL; + + t[0] = res & 0xff; + t[1] = (res >> 8) & 0xff; + err = mcu_i2c_write_block(dev2i2c(dev), features->alert_mask, + sizeof(t), t); + if (err < 0) + return err; + + return len; +} + +ssize_t lock_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int err; + const struct mcu_features *features = dev2features(dev); + + if (features->lock == -1) + return -ENODEV; + + err = mcu_i2c_read_byte(dev2i2c(dev), features->lock); + + if (err < 0) + return err; + + return mcu_msg_append(buf, PAGE_SIZE, + "%d", err ? 1 : 0); +} + +static ssize_t lock_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned long res; + const u8 *code[] = { "CK", "LO", }; + const u8 *p; + const struct mcu_features *features = dev2features(dev); + + if (features->lock == -1) + return -ENODEV; + + err = kstrtoul(buf, 0, &res); + if (err) + return err; + + res = res ? 1 : 0; + + for (p = code[res]; *p; ++p) { + err = mcu_i2c_write_byte(dev2i2c(dev), features->lock, *p); + if (err < 0) + return err; + } + + return len; +} + +ssize_t power_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + u8 t[2]; + int err; + const struct mcu_features *features = dev2features(dev); + + if (features->power < 0) + return -EOPNOTSUPP; + + err = mcu_i2c_read_block(dev2i2c(dev), features->power, sizeof(t), t); + if (err < 0) + return err; + + err = sprintf(buf, "%umW\n", ((u16)t[0]) | (t[1] << 8)); + + return err; +} + +static ssize_t power_tpu_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned long res; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + if (features->power_tpu < 0) + return -EOPNOTSUPP; + + err = kstrtoul(buf, 0, &res); + if (err) + return err; + + data = res ? 1 : 0; + + err = mcu_i2c_write_block(dev2i2c(dev), features->power_tpu, + sizeof(data), &data); + return len; +} + +static ssize_t power_tpu_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + if (features->power_tpu < 0) + return -EOPNOTSUPP; + + err = mcu_i2c_read_block(dev2i2c(dev), features->power_tpu, sizeof(data), &data); + if (err < 0) + return err; + + err = sprintf(buf, "%u\n", data); + + return err; +} + +static ssize_t mcu_critical_action_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + + if (!strcmp(buf, "reboot\n")) + data = MCU_CRITICAL_ACTION_REBOOT; + else if (!strcmp(buf, "poweroff\n")) + data = MCU_CRITICAL_ACTION_POWEROFF; + else + data = 0; + + if (data) { + err = mcu_i2c_write_block(dev2i2c(dev), + features->critical_action, sizeof(data), &data); + } + return len; +} + +static ssize_t mcu_critical_action_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = mcu_i2c_read_block(dev2i2c(dev), features->critical_action, + sizeof(data), &data); + if (err < 0) + return err; + + if (data == MCU_CRITICAL_ACTION_REBOOT) + err = sprintf(buf, "reboot\n"); + else if (data == MCU_CRITICAL_ACTION_POWEROFF) + err = sprintf(buf, "poweroff\n"); + else + err = sprintf(buf, "unknown critical action\n"); + + return err; +} + + +static ssize_t mcu_critical_temp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned long res; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = kstrtoul(buf, 0, &res); + if (err) + return err; + + data = res; + + err = mcu_i2c_write_block(dev2i2c(dev), features->critical_temp, + sizeof(data), &data); + return len; +} + +static ssize_t mcu_critical_temp_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = mcu_i2c_read_block(dev2i2c(dev), features->critical_temp, + sizeof(data), &data); + if (err < 0) + return err; + + err = sprintf(buf, "%u Cel\n", data); + + return err; +} + + +static ssize_t mcu_repoweron_temp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned long res; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = kstrtoul(buf, 0, &res); + if (err) + return err; + + data = res; + + err = mcu_i2c_write_block(dev2i2c(dev), features->repoweron_temp, + sizeof(data), &data); + return len; +} + +static ssize_t mcu_repoweron_temp_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = mcu_i2c_read_block(dev2i2c(dev), features->repoweron_temp, + sizeof(data), &data); + if (err < 0) + return err; + + err = sprintf(buf, "%u Cel\n", data); + + return err; +} + + +static ssize_t mcu_keep_ddr_poweron_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + if (!strcmp(buf, "disable\n")) + data = 1; + else if (!strcmp(buf, "enable\n")) + data = 0; + else + return 0; + + err = mcu_i2c_write_block(dev2i2c(dev), features->keep_ddr_poweron, + sizeof(data), &data); + return len; +} + +static ssize_t mcu_keep_ddr_poweron_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int err; + unsigned char data; + const struct mcu_features *features = dev2features(dev); + + err = mcu_i2c_read_block(dev2i2c(dev), features->keep_ddr_poweron, + sizeof(data), &data); + if (err < 0) + return err; + + if (data == 1) + err = sprintf(buf, "disable\n"); + else if (data == 0) + err = sprintf(buf, "enable\n"); + else + err = sprintf(buf, "unknown states\n"); + + return err; +} + +/* end of sysfs callbacks */ + +const struct device_attribute mcu_attrs[] = { + {{"help", 0444}, help_show, NULL}, + {{"information", 0644}, info_show, info_store}, + {{"temperature", 0444}, temp_show, NULL}, + {{"uptime", 0444}, uptime_show, NULL}, + {{"alert", 0644}, alert_show, alert_store}, + {{"lock", 0644}, lock_show, lock_store}, + {{"power-now", 0444}, power_show, NULL}, + {{"power-tpu", 0644}, power_tpu_show, power_tpu_store}, + {{"board-id", 0444}, brdid_show, NULL}, + {{"board-ip", 0644}, brdip_show, brdip_store}, + {{"critical-action", 0644}, mcu_critical_action_show, + mcu_critical_action_store}, + {{"critical-temp", 0644}, mcu_critical_temp_show, + mcu_critical_temp_store}, + {{"repoweron-temp", 0664}, mcu_repoweron_temp_show, + mcu_repoweron_temp_store}, + {{"keep-ddr-poweron", 0664}, mcu_keep_ddr_poweron_show, + mcu_keep_ddr_poweron_store}, +}; + +static umode_t mcu_chip_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_chip: + return 0444; + case hwmon_temp: + return 0444; + default: + return 0; + } +} + +static int mcu_hwmon_chip_read(struct device *dev, u32 attr, int channel, long *val) +{ + struct mcu_ctx *ctx = dev_get_drvdata(dev); + + switch (attr) { + case hwmon_chip_update_interval: + *val = ctx->hwmon_update_interval; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int mcu_hwmon_temp_read(struct device *dev, u32 attr, int channel, long *val) +{ + int soc_temp, board_temp; + + struct mcu_ctx *ctx = dev_get_drvdata(dev); + struct i2c_client *i2c = ctx->i2c; + mutex_lock(&ctx->update_lock); + soc_temp = mcu_i2c_read_byte(i2c, MCU_REG_SOC_TEMP); + mutex_unlock(&ctx->update_lock); + + mutex_lock(&ctx->update_lock); + board_temp = mcu_i2c_read_byte(i2c, MCU_REG_BOARD_TEMP); + mutex_unlock(&ctx->update_lock); + + switch (attr) { + case hwmon_temp_input: + if (channel == 0) + *val = soc_temp * 1000; + else if (channel == 1) + *val = board_temp * 1000; + else + *val = 0; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + + +static int mcu_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + + switch (type) { + case hwmon_chip: + return mcu_hwmon_chip_read(dev, attr, channel, val); + case hwmon_temp: + return mcu_hwmon_temp_read(dev, attr, channel, val); + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static const struct hwmon_ops mcu_ops = { + .is_visible = mcu_chip_is_visible, + .read = mcu_hwmon_read, + .read_string = NULL, + .write = NULL, +}; + +static int register_hwmon_temp_sensor(struct i2c_client *i2c, + struct mcu_ctx *ctx) +{ + struct device *dev = &i2c->dev; + struct hwmon_channel_info *info; + struct device *hwmon_dev; + + mutex_init(&ctx->update_lock); + + ctx->i2c = i2c; + ctx->hwmon_update_interval = 1000; + + ctx->chip.ops = &mcu_ops; + ctx->chip.info = ctx->channel_info; + ctx->channel_info[0] = HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL); + ctx->channel_info[1] = &ctx->temp_info; + + info = &ctx->temp_info; + info->type = hwmon_temp; + info->config = ctx->channel_config; + + ctx->channel_config[0] = HWMON_T_INPUT; + ctx->channel_config[1] = HWMON_T_INPUT; + hwmon_dev = devm_hwmon_device_register_with_info( + dev, + dev->driver->name, + ctx, + &ctx->chip, + NULL); + + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + return 0; +} + +static int sub_probe(struct i2c_client *i2c, + const struct mcu_features *features) +{ + struct mcu_ctx *ctx; + int i, err; + + ctx = devm_kzalloc(i2c2dev(i2c), sizeof(*ctx), GFP_KERNEL); + if (ctx == NULL) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(mcu_attrs); ++i) { + err = device_create_file(i2c2dev(i2c), mcu_attrs + i); + if (err) + return err; + } + + ctx->features = features; + + assert(features->alert_status + 2 == features->alert_mask); + + if ((features->id & MANGO_BOARD_TYPE_MASK) == 0x80 ) { + err = register_hwmon_temp_sensor(i2c, ctx); + if (err) + dev_warn(i2c2dev(i2c), "mcu board id %u register hwmon failed\n", features->id); + } + + i2c_set_clientdata(i2c, ctx); + return 0; +} + +static int mcu_i2c_probe(struct i2c_client *i2c) +{ + int id; + int err; + int i; + uint8_t regs[3]; + + /* get information from mcu through i2c */ + err = mcu_i2c_sreadf(i2c, "%u8%u8%u8", + MCU_REG_VERSION, regs, + MCU_REG_PWROFF_REASON1, regs + 1, + MCU_REG_PWROFF_REASON2, regs + 2); + if (err) + return err; + + dev_info(i2c2dev(i2c), "MCU: version 0x%x, reason 0x%x/0x%x\n", + regs[0], regs[1], regs[2]); + + id = mcu_i2c_read_byte(i2c, MCU_REG_BOARD_TYPE); + if (id < 0) + return id; + + for (i = 0; i < ARRAY_SIZE(mcu_list); ++i) { + if (mcu_list[i].id == id) + return sub_probe(i2c, mcu_list + i); + } + + dev_warn(i2c2dev(i2c), "not registered mcu id %u\n", id); + return -ENODEV; +} + +static void mcu_i2c_remove(struct i2c_client *i2c) +{ + return; +} + +static const struct of_device_id mcu_i2c_dt_table[] = { + { .compatible = "sophgo,sg20xx-mcu" }, + {}, +}; + +static const struct i2c_device_id mcu_i2c_id_table[] = { + { "sg20xx-mcu", 0 }, + {}, +}; + +static struct i2c_driver mcu_i2c_drv = { + .driver = { + .name = "sg20xx-mcu", + .of_match_table = mcu_i2c_dt_table, + }, + .probe = mcu_i2c_probe, + .remove = mcu_i2c_remove, + .id_table = mcu_i2c_id_table, +}; + +module_i2c_driver(mcu_i2c_drv); + +MODULE_DESCRIPTION("MCU I2C driver for bm16xx soc platform"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chao.Wei@bitmain.com>"); From fbc46f78e95de716f658b8ee781f632bc4bc2cf1 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 24 Feb 2023 17:23:17 +0800 Subject: [PATCH 20/40] ttm: disallow cached mapping Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 6 ++++-- drivers/gpu/drm/ttm/ttm_module.c | 3 ++- drivers/gpu/drm/ttm/ttm_resource.c | 7 ++++--- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- 5 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index b67eafa557159..5ebe418bd383b 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c +++ b/drivers/gpu/drm/drm_gem_vram_helper.c @@ -870,7 +870,7 @@ static struct ttm_tt *bo_driver_ttm_tt_create(struct ttm_buffer_object *bo, if (!tt) return NULL; - ret = ttm_tt_init(tt, bo, page_flags, ttm_cached, 0); + ret = ttm_tt_init(tt, bo, page_flags, ttm_write_combined, 0); if (ret < 0) goto err_ttm_tt_init; diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 0b3f4267130c4..e4580efeae372 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -353,7 +353,7 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, ret = ttm_tt_populate(bo->bdev, ttm, &ctx); if (ret) return ret; - +#if 0 if (num_pages == 1 && ttm->caching == ttm_cached && !(man->use_tt && (ttm->page_flags & TTM_TT_FLAG_DECRYPTED))) { /* @@ -364,7 +364,9 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, map->bo_kmap_type = ttm_bo_map_kmap; map->page = ttm->pages[start_page]; map->virtual = kmap(map->page); - } else { + } else +#endif + { /* * We need to use vmap to get the desired page protection * or to make the buffer object look contiguous. diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index b3fffe7b5062a..aa137ead5cc59 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) #endif /* CONFIG_UML */ #endif /* __i386__ || __x86_64__ */ #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \ + defined(__riscv) if (caching == ttm_write_combined) tmp = pgprot_writecombine(tmp); else diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 46ff9c75bb124..63a9b8d41b947 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -187,7 +187,7 @@ void ttm_resource_init(struct ttm_buffer_object *bo, res->bus.addr = NULL; res->bus.offset = 0; res->bus.is_iomem = false; - res->bus.caching = ttm_cached; + res->bus.caching = ttm_write_combined; res->bo = bo; man = ttm_manager_type(bo->bdev, place->mem_type); @@ -670,17 +670,18 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, } else { iter_io->needs_unmap = true; memset(&iter_io->dmap, 0, sizeof(iter_io->dmap)); - if (mem->bus.caching == ttm_write_combined) + if (mem->bus.caching == ttm_write_combined || mem->bus.caching == ttm_cached) iosys_map_set_vaddr_iomem(&iter_io->dmap, ioremap_wc(mem->bus.offset, mem->size)); +#if 0 else if (mem->bus.caching == ttm_cached) iosys_map_set_vaddr(&iter_io->dmap, memremap(mem->bus.offset, mem->size, MEMREMAP_WB | MEMREMAP_WT | MEMREMAP_WC)); - +#endif /* If uncached requested or if mapping cached or wc failed */ if (iosys_map_is_null(&iter_io->dmap)) iosys_map_set_vaddr_iomem(&iter_io->dmap, diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index bf9601351fa35..af3ab03200c09 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -154,7 +154,7 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm, ttm->dma_address = NULL; ttm->swap_storage = NULL; ttm->sg = bo->sg; - ttm->caching = caching; + ttm->caching = ttm_write_combined; } int ttm_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, From da1043d0e12a294cee972288cd9cf55d21d93fe5 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 24 Feb 2023 17:23:59 +0800 Subject: [PATCH 21/40] amdgpu: disable rebar Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index eb663eb811563..02d842ede5b1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1109,6 +1109,8 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) u16 cmd; int r; + return 0; + if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; From b79fed491c8e669dace17b901d714c6dffde996f Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 25 Feb 2023 21:56:45 +0800 Subject: [PATCH 22/40] radeon hack: force 64-bit msi to fit top intc Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 ++ sound/pci/hda/hda_intel.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index c4dda908666cf..33b56ca7af6f6 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -250,10 +250,12 @@ static bool radeon_msi_ok(struct radeon_device *rdev) * of address for "64-bit" MSIs which breaks on some platforms, notably * IBM POWER servers, so we limit them */ +#if 0 if (rdev->family < CHIP_BONAIRE) { dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n"); rdev->pdev->no_64bit_msi = 1; } +#endif /* force MSI on */ if (radeon_msi == 1) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 49f8f9aac70b7..4fb9acf3f24fe 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -299,8 +299,7 @@ enum { /* quirks for ATI/AMD HDMI */ #define AZX_DCAPS_PRESET_ATI_HDMI \ - (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ - AZX_DCAPS_NO_MSI64) + (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB) /* quirks for ATI HDMI with snoop off */ #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ From 582c866b04c668582db6971dba41c59ab4ebe2a3 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 26 Feb 2023 10:34:58 +0800 Subject: [PATCH 23/40] nvidia hda: force msi Signed-off-by: Icenowy Zheng --- sound/pci/hda/hda_intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 4fb9acf3f24fe..7fce79a4c7bd5 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -313,7 +313,7 @@ enum { /* quirks for Nvidia */ #define AZX_DCAPS_PRESET_NVIDIA \ - (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ + (AZX_DCAPS_CORBRP_SELF_CLEAR |\ AZX_DCAPS_SNOOP_TYPE(NVIDIA)) #define AZX_DCAPS_PRESET_CTHDA \ From 73cdd0e19857f0b0d8b0fa8ed73c5fda76d62e51 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Fri, 26 Jan 2024 20:08:21 +0800 Subject: [PATCH 24/40] mango pci hack:broadcast when no MSI source known Signed-off-by: Xiaoguang Xing --- drivers/pci/pcie/portdrv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 46fad0d813b2b..560b3a236d84f 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -598,7 +598,7 @@ void pcie_port_service_unregister(struct pcie_port_service_driver *drv) } /* If this switch is set, PCIe port native services should not be enabled. */ -bool pcie_ports_disabled; +bool pcie_ports_disabled = true; /* * If the user specified "pcie_ports=native", use the PCIe services regardless From 731f114350d45c54ecafa6f1dcd8dcd3e25f37c1 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 6 Mar 2024 15:08:26 +0800 Subject: [PATCH 25/40] riscv: Add support for kernel-mode FPU This is needed to support recent hardware in the amdgpu DRM driver. The FPU code in that driver is not performance-critical, so only provide the minimal support. Signed-off-by: Samuel Holland Signed-off-by: Icenowy Zheng --- arch/riscv/include/asm/switch_to.h | 15 +++++++++++++++ arch/riscv/kernel/process.c | 3 +++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index a727be723c561..1da3f54d52f06 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -63,6 +63,21 @@ static __always_inline bool has_fpu(void) return riscv_has_extension_likely(RISCV_ISA_EXT_f) || riscv_has_extension_likely(RISCV_ISA_EXT_d); } + + +static inline void kernel_fpu_begin(void) +{ + preempt_disable(); + fstate_save(current, task_pt_regs(current)); + csr_set(CSR_SSTATUS, SR_FS); +} + +static inline void kernel_fpu_end(void) +{ + csr_clear(CSR_SSTATUS, SR_FS); + fstate_restore(current, task_pt_regs(current)); + preempt_enable(); +} #else static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 83e223318822a..dd973216e31cf 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -204,3 +204,6 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.sp = (unsigned long)childregs; /* kernel sp */ return 0; } + +EXPORT_SYMBOL_GPL(__fstate_save); +EXPORT_SYMBOL_GPL(__fstate_restore); From d200297069819225c2eca7fbcb9cee658b2c651e Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 6 Mar 2024 15:25:50 +0800 Subject: [PATCH 26/40] riscv: Factor out riscv-march-y to a separate Makefile Since it is not possible to incrementally add/remove extensions from the compiler's ISA string by appending arguments, any code that wants to modify the ISA string must recreate the whole thing. To support this, factor out the logic for generating the -march argument so it can be reused where needed. Signed-off-by: Samuel Holland Signed-off-by: Icenowy Zheng --- arch/riscv/Makefile | 17 +---------------- arch/riscv/Makefile.isa | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 16 deletions(-) create mode 100644 arch/riscv/Makefile.isa diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4d06f34026740..a040fd5f83ad6 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -54,22 +54,7 @@ endif endif endif -# ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima -riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c -riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v - -ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC -KBUILD_CFLAGS += -Wa,-misa-spec=2.2 -KBUILD_AFLAGS += -Wa,-misa-spec=2.2 -else -riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei -endif - -# Check if the toolchain supports Zihintpause extension -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause +include $(srctree)/arch/riscv/Makefile.isa # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by # matching non-v and non-multi-letter extensions out with the filter ([^v_]*) diff --git a/arch/riscv/Makefile.isa b/arch/riscv/Makefile.isa new file mode 100644 index 0000000000000..322a83958b968 --- /dev/null +++ b/arch/riscv/Makefile.isa @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ISA string setting +riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima +riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima +riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v + +ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC +KBUILD_CFLAGS += -Wa,-misa-spec=2.2 +KBUILD_AFLAGS += -Wa,-misa-spec=2.2 +else +riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei +endif + +# Check if the toolchain supports Zihintpause extension +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause From f1f734142fd1761bf74a9164f91ed8a83a272a6a Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 6 Mar 2024 15:26:42 +0800 Subject: [PATCH 27/40] drm/amd/display: Support DRM_AMD_DC_FP on RISC-V RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other architectures. Enabling hardware FP requires overriding the ISA string for the relevant compilation units. Signed-off-by: Samuel Holland Signed-off-by: Icenowy Zheng --- drivers/gpu/drm/amd/display/Kconfig | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 6 ++++-- drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 ++++++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 901d1961b7392..90489b55efa74 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -9,6 +9,7 @@ config DRM_AMD_DC select SND_HDA_COMPONENT if SND_HDA_CORE # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) + select DRM_AMD_DC_DCN if RISCV && FPU help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index 172aa10a8800f..53a7122ba98d5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -35,6 +35,8 @@ #include #elif defined(CONFIG_LOONGARCH) #include +#elif defined(CONFIG_RISCV) +#include #endif /** @@ -90,7 +92,7 @@ void dc_fpu_begin(const char *function_name, const int line) *pcpu += 1; if (*pcpu == 1) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) migrate_disable(); kernel_fpu_begin(); #elif defined(CONFIG_PPC64) @@ -130,7 +132,7 @@ void dc_fpu_end(const char *function_name, const int line) pcpu = get_cpu_ptr(&fpu_recursion_depth); *pcpu -= 1; if (*pcpu <= 0) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) kernel_fpu_end(); migrate_enable(); #elif defined(CONFIG_PPC64) diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 0ba9a7997d561..abd04d13997d9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -43,6 +43,12 @@ dml_ccflags := -mfpu=64 dml_rcflags := -msoft-float endif +ifdef CONFIG_RISCV +include $(srctree)/arch/riscv/Makefile.isa +# Remove V from the ISA string, like in arch/riscv/Makefile, but keep F and D. +dml_ccflags := -march=$(subst v0p7,,$(riscv-march-y)) +endif + ifdef CONFIG_CC_IS_GCC ifneq ($(call gcc-min-version, 70100),y) IS_OLD_GCC = 1 From c803daeaa91d49b2011a1da899548822e13aabe0 Mon Sep 17 00:00:00 2001 From: "xiaoguang.xing" Date: Thu, 16 Feb 2023 10:39:03 +0800 Subject: [PATCH 28/40] riscv: kexec: Add image loader for kexec file --- arch/riscv/Kconfig | 1 + arch/riscv/include/asm/kexec.h | 1 + arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/image_kexec.c | 305 +++++++++++++++++++++++++ arch/riscv/kernel/machine_kexec_file.c | 1 + arch/riscv/mm/init.c | 2 +- 6 files changed, 310 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/kernel/image_kexec.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c785a02005738..2a3d25251eeaa 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_VDSO_DATA + select ARCH_KEEP_MEMBLOCK select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/include/asm/kexec.h b/arch/riscv/include/asm/kexec.h index 2b56769cb530c..62f3ddc7c4983 100644 --- a/arch/riscv/include/asm/kexec.h +++ b/arch/riscv/include/asm/kexec.h @@ -56,6 +56,7 @@ extern riscv_kexec_method riscv_kexec_norelocate; #ifdef CONFIG_KEXEC_FILE extern const struct kexec_file_ops elf_kexec_ops; +extern const struct kexec_file_ops image_kexec_ops; struct purgatory_info; int arch_kexec_apply_relocations_add(struct purgatory_info *pi, diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 03968c06258ce..4150470644182 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -88,7 +88,7 @@ endif obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_KEXEC_CORE) += kexec_relocate.o crash_save_regs.o machine_kexec.o -obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o machine_kexec_file.o +obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o image_kexec.o machine_kexec_file.o obj-$(CONFIG_CRASH_DUMP) += crash_dump.o obj-$(CONFIG_CRASH_CORE) += crash_core.o diff --git a/arch/riscv/kernel/image_kexec.c b/arch/riscv/kernel/image_kexec.c new file mode 100644 index 0000000000000..37c5bd813958e --- /dev/null +++ b/arch/riscv/kernel/image_kexec.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kexec image loader + + * Adapted from arch/arm64/kernel/kexec_image.c + * Copyright (C) 2018 Linaro Limited + * Author: AKASHI Takahiro + */ +#define pr_fmt(fmt) "kexec_file(Image): " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int prepare_elf_headers(void **addr, unsigned long *sz) +{ + struct crash_mem *cmem; + unsigned int nr_ranges; + int ret; + u64 i; + phys_addr_t start, end; + + nr_ranges = 2; /* for exclusion of crashkernel region */ + for_each_mem_range(i, &start, &end) + nr_ranges++; + + cmem = kmalloc(struct_size(cmem, ranges, nr_ranges), GFP_KERNEL); + if (!cmem) + return -ENOMEM; + + cmem->max_nr_ranges = nr_ranges; + cmem->nr_ranges = 0; + for_each_mem_range(i, &start, &end) { + cmem->ranges[cmem->nr_ranges].start = start; + cmem->ranges[cmem->nr_ranges].end = end - 1; + cmem->nr_ranges++; + } + + /* Exclude crashkernel region */ + ret = crash_exclude_mem_range(cmem, crashk_res.start, crashk_res.end); + if (ret) + goto out; + + if (crashk_low_res.end) { + ret = crash_exclude_mem_range(cmem, crashk_low_res.start, crashk_low_res.end); + if (ret) + goto out; + } + + ret = crash_prepare_elf64_headers(cmem, true, addr, sz); + +out: + kfree(cmem); + return ret; +} + +/* + * Tries to add the initrd and DTB to the image. If it is not possible to find + * valid locations, this function will undo changes to the image and return non + * zero. + */ +static int load_other_segments(struct kimage *image, + unsigned long kernel_load_addr, + unsigned long kernel_size, + char *initrd, unsigned long initrd_len, + char *cmdline) +{ + struct kexec_buf kbuf; + void *headers, *fdt = NULL; + unsigned long headers_sz, initrd_load_addr = 0, + orig_segments = image->nr_segments; + int ret = 0; + + kbuf.image = image; + /* not allocate anything below the kernel */ + kbuf.buf_min = kernel_load_addr + kernel_size; + + /* load elf core header */ + if (image->type == KEXEC_TYPE_CRASH) { + ret = prepare_elf_headers(&headers, &headers_sz); + if (ret) { + pr_err("Preparing elf core header failed\n"); + goto out_err; + } + + kbuf.buffer = headers; + kbuf.bufsz = headers_sz; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = headers_sz; + kbuf.buf_align = PAGE_SIZE; + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = true; + + ret = kexec_add_buffer(&kbuf); + if (ret) { + vfree(headers); + goto out_err; + } + image->elf_headers = headers; + image->elf_load_addr = kbuf.mem; + image->elf_headers_sz = headers_sz; + + pr_debug("Loaded elf core header at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + image->elf_load_addr, kbuf.bufsz, kbuf.memsz); + } + + /* load initrd */ + if (initrd) { + kbuf.buffer = initrd; + kbuf.bufsz = initrd_len; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = initrd_len; + kbuf.buf_align = PAGE_SIZE; + /* avoid to overlap kernel address */ + kbuf.buf_min = round_up(kernel_load_addr, SZ_1G); + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = false; + + ret = kexec_add_buffer(&kbuf); + if (ret) + goto out_err; + initrd_load_addr = kbuf.mem; + + pr_debug("Loaded initrd at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + initrd_load_addr, kbuf.bufsz, kbuf.memsz); + } + + /* load dtb */ + fdt = of_kexec_alloc_and_setup_fdt(image, initrd_load_addr, + initrd_len, cmdline, 0); + if (!fdt) { + pr_err("Preparing for new dtb failed\n"); + ret = -EINVAL; + goto out_err; + } + + /* trim it */ + fdt_pack(fdt); + kbuf.buffer = fdt; + kbuf.bufsz = kbuf.memsz = fdt_totalsize(fdt); + kbuf.buf_align = PAGE_SIZE; + kbuf.buf_max = ULONG_MAX; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.top_down = false; + + ret = kexec_add_buffer(&kbuf); + if (ret) + goto out_err; + /* Cache the fdt buffer address for memory cleanup */ + image->arch.fdt = fdt; + image->arch.fdt_addr = kbuf.mem; + + pr_debug("Loaded dtb at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + kbuf.mem, kbuf.bufsz, kbuf.memsz); + + return 0; + +out_err: + image->nr_segments = orig_segments; + kvfree(fdt); + return ret; +} + +static int image_probe(const char *kernel_buf, unsigned long kernel_len) +{ + const struct riscv_image_header *h = + (const struct riscv_image_header *)(kernel_buf); + + if (!h || (kernel_len < sizeof(*h))) + return -EINVAL; + + if (memcmp(&h->magic2, RISCV_IMAGE_MAGIC2, sizeof(h->magic2))) + return -EINVAL; + + return 0; +} + +static void *image_load(struct kimage *image, + char *kernel, unsigned long kernel_len, + char *initrd, unsigned long initrd_len, + char *cmdline, unsigned long cmdline_len) +{ + struct riscv_image_header *h; + u64 flags; + bool be_image, be_kernel; + struct kexec_buf kbuf; + unsigned long text_offset, kernel_segment_number; + unsigned long kernel_start; + struct kexec_segment *kernel_segment; + int ret; + + h = (struct riscv_image_header *)kernel; + if (!h->image_size) + return ERR_PTR(-EINVAL); + + /* Check cpu features */ + flags = le64_to_cpu(h->flags); + be_image = __HEAD_FLAG(BE); + be_kernel = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); + if (be_image != be_kernel) + return ERR_PTR(-EINVAL); + + /* Load the kernel */ + kbuf.image = image; + kbuf.buf_min = 0; + kbuf.buf_max = ULONG_MAX; + kbuf.top_down = false; + + kbuf.buffer = kernel; + kbuf.bufsz = kernel_len; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + kbuf.memsz = le64_to_cpu(h->image_size); + text_offset = le64_to_cpu(h->text_offset); + kbuf.buf_align = PMD_SIZE; + + /* Adjust kernel segment with TEXT_OFFSET */ + kbuf.memsz += text_offset; + + kernel_segment_number = image->nr_segments; + + /* + * The location of the kernel segment may make it impossible to satisfy + * the other segment requirements, so we try repeatedly to find a + * location that will work. + */ + while ((ret = kexec_add_buffer(&kbuf)) == 0) { + /* Try to load additional data */ + kernel_segment = &image->segment[kernel_segment_number]; + ret = load_other_segments(image, kernel_segment->mem, + kernel_segment->memsz, initrd, + initrd_len, cmdline); + if (!ret) + break; + + /* + * We couldn't find space for the other segments; erase the + * kernel segment and try the next available hole. + */ + image->nr_segments -= 1; + kbuf.buf_min = kernel_segment->mem + kernel_segment->memsz; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + } + + if (ret) { + pr_err("Could not find any suitable kernel location!"); + return ERR_PTR(ret); + } + + kernel_segment = &image->segment[kernel_segment_number]; + kernel_segment->mem += text_offset; + kernel_segment->memsz -= text_offset; + kernel_start = kernel_segment->mem; + image->start = kernel_start; + + + pr_debug("Loaded kernel at 0x%lx bufsz=0x%lx memsz=0x%lx\n", + kernel_segment->mem, kbuf.bufsz, + kernel_segment->memsz); + +#ifdef CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY + /* Add purgatory to the image */ + kbuf.top_down = true; + kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; + ret = kexec_load_purgatory(image, &kbuf); + if (ret) { + pr_err("Error loading purgatory ret=%d\n", ret); + return ERR_PTR(ret); + } + ret = kexec_purgatory_get_set_symbol(image, "riscv_kernel_entry", + &kernel_start, + sizeof(kernel_start), 0); + if (ret) + pr_err("Error update purgatory ret=%d\n", ret); +#endif /* CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY */ + + return ret ? ERR_PTR(ret) : NULL; +} + +#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG +static int image_verify_sig(const char *kernel, unsigned long kernel_len) +{ + return verify_pefile_signature(kernel, kernel_len, NULL, + VERIFYING_KEXEC_PE_SIGNATURE); +} +#endif + +const struct kexec_file_ops image_kexec_ops = { + .probe = image_probe, + .load = image_load, +#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG + .verify_sig = image_verify_sig, +#endif +}; diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c index b0bf8c1722c0c..401edfd1774fa 100644 --- a/arch/riscv/kernel/machine_kexec_file.c +++ b/arch/riscv/kernel/machine_kexec_file.c @@ -9,6 +9,7 @@ #include const struct kexec_file_ops * const kexec_file_loaders[] = { + &image_kexec_ops, &elf_kexec_ops, NULL }; diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index abe7a7a7686c1..5529723397616 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -1279,7 +1279,7 @@ static void __init create_linear_mapping_page_table(void) __pa(PAGE_OFFSET) < end) start = __pa(PAGE_OFFSET); - create_linear_mapping_range(start, end, 0); + create_linear_mapping_range(start, end, PMD_SIZE); } #ifdef CONFIG_STRICT_KERNEL_RWX From bcc9729f05aa10abb3c9b6c28149fa72f899c75e Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 20 Mar 2024 11:00:40 +0800 Subject: [PATCH 29/40] riscv/kexec: handle R_RISCV_ADD16 and R_RISCV_SUB16 relocation types refs: https://lore.kernel.org/lkml/f75c763d86529a47eb23d46c5ef9bcbaaf118200.1690274483.git.petr.tesarik.ext@huawei.com/ Signed-off-by: Xiaoguang Xing --- arch/riscv/kernel/elf_kexec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kernel/elf_kexec.c b/arch/riscv/kernel/elf_kexec.c index e60fbd8660c4a..3b80befe05192 100644 --- a/arch/riscv/kernel/elf_kexec.c +++ b/arch/riscv/kernel/elf_kexec.c @@ -450,6 +450,12 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi, case R_RISCV_SUB32: *(u32 *)loc -= val; break; + case R_RISCV_ADD16: + *(u16 *)loc += val; + break; + case R_RISCV_SUB16: + *(u16 *)loc -= val; + break; /* It has been applied by R_RISCV_PCREL_HI20 sym */ case R_RISCV_PCREL_LO12_I: case R_RISCV_ALIGN: From 210058fb8d2b20eb86a6d6f79f8e57bcdb377b8c Mon Sep 17 00:00:00 2001 From: "xiaoguang.xing" Date: Thu, 16 Feb 2023 11:16:00 +0800 Subject: [PATCH 30/40] riscv: kernel: Optimize apply_relocate_add() --- arch/riscv/kernel/module.c | 83 ++++++++++++++++++++++++-------------- 1 file changed, 53 insertions(+), 30 deletions(-) diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c index df4f6fec5d174..ced5a09abaaa7 100644 --- a/arch/riscv/kernel/module.c +++ b/arch/riscv/kernel/module.c @@ -337,6 +337,45 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, }; +static inline unsigned int apply_calc_pcrel_lo12(Elf_Shdr *sechdrs, + Elf_Rela *rel, Elf_Sym *sym, unsigned int idx, + unsigned int symindex, unsigned int relsec, + struct module *me, Elf_Addr *v) +{ + unsigned long hi20_loc = + sechdrs[sechdrs[relsec].sh_info].sh_addr + + rel[idx].r_offset; + u32 hi20_type = ELF_RISCV_R_TYPE(rel[idx].r_info); + unsigned int found = 0; + + /* Find the corresponding HI20 relocation entry */ + if (hi20_loc == sym->st_value + && (hi20_type == R_RISCV_PCREL_HI20 + || hi20_type == R_RISCV_GOT_HI20)) { + s32 hi20, lo12; + Elf_Sym *hi20_sym = + (Elf_Sym *)sechdrs[symindex].sh_addr + + ELF_RISCV_R_SYM(rel[idx].r_info); + unsigned long hi20_sym_val = + hi20_sym->st_value + rel[idx].r_addend; + + /* Calculate lo12 */ + size_t offset = hi20_sym_val - hi20_loc; + if (IS_ENABLED(CONFIG_MODULE_SECTIONS) + && hi20_type == R_RISCV_GOT_HI20) { + offset = module_emit_got_entry(me, hi20_sym_val); + offset = offset - hi20_loc; + } + hi20 = (offset + 0x800) & 0xfffff000; + lo12 = offset - hi20; + *v = (Elf_Addr)lo12; + + found = 1; + } + + return found; +} + int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relsec, struct module *me) @@ -385,40 +424,24 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, if (type == R_RISCV_PCREL_LO12_I || type == R_RISCV_PCREL_LO12_S) { unsigned int j; + unsigned int found = 0; - for (j = 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) { - unsigned long hi20_loc = - sechdrs[sechdrs[relsec].sh_info].sh_addr - + rel[j].r_offset; - u32 hi20_type = ELF_RISCV_R_TYPE(rel[j].r_info); - - /* Find the corresponding HI20 relocation entry */ - if (hi20_loc == sym->st_value - && (hi20_type == R_RISCV_PCREL_HI20 - || hi20_type == R_RISCV_GOT_HI20)) { - s32 hi20, lo12; - Elf_Sym *hi20_sym = - (Elf_Sym *)sechdrs[symindex].sh_addr - + ELF_RISCV_R_SYM(rel[j].r_info); - unsigned long hi20_sym_val = - hi20_sym->st_value - + rel[j].r_addend; - - /* Calculate lo12 */ - size_t offset = hi20_sym_val - hi20_loc; - if (IS_ENABLED(CONFIG_MODULE_SECTIONS) - && hi20_type == R_RISCV_GOT_HI20) { - offset = module_emit_got_entry( - me, hi20_sym_val); - offset = offset - hi20_loc; - } - hi20 = (offset + 0x800) & 0xfffff000; - lo12 = offset - hi20; - v = lo12; + if (i > 0) { + j = i - 1; + found = apply_calc_pcrel_lo12(sechdrs, rel, sym, j, + symindex, relsec, me, &v); + } - break; + if (found == 0) { + for (j = 0; j < sechdrs[relsec].sh_size/sizeof(*rel); j++) { + found = apply_calc_pcrel_lo12(sechdrs, rel, sym, + j, symindex, relsec, me, &v); + if (found) { + break; + } } } + if (j == sechdrs[relsec].sh_size / sizeof(*rel)) { pr_err( "%s: Can not find HI20 relocation information\n", From ee623f7eaa25dd4d0fbcb8a898576e71102fbdd0 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Tue, 29 Aug 2023 14:49:06 +0800 Subject: [PATCH 31/40] kernel: schedule: Fix set_task_cpu() bug The bug is triggered when run WARN_ON_ONCE(is_migration_disabled(p)). [ 3298.725394] WARNING: CPU: 73 PID: 0 at kernel/sched/core.c:3147 set_task_cpu+0x18a/0x18e [ 3298.733591] Modules linked in: nf_conntrack_netlink xt_addrtype xt_statistic xt_nat xt_MASQUERADE nft_chain_nat nf_nat xt_mark xt_conntrack xt_comment nft_compat tls nf_tables nfnetlink overlay rfkill qrtr sunrpc ofpart ipmi_si vfat sophgo_spifmc ipmi_devintf spi_nor fat ipmi_msghandler mtd uio_pdrv_genirq uio loop zram ast drm_vram_helper drm_ttm_helper spi_dw_mmio ixgbe spi_dw gpio_dwapb r8169 ttm mdio scsi_dh_rdac scsi_dh_emc scsi_dh_alua ip6_tables ip_tables dm_multipath ip_vs_sh ip_vs_wrr ip_vs_rr ip_vs nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 br_netfilter bridge stp llc [ 3298.785070] CPU: 73 PID: 0 Comm: swapper/73 Not tainted 6.1.31 #1 [ 3298.791220] Hardware name: Sophgo Mango (DT) [ 3298.795504] epc : set_task_cpu+0x18a/0x18e [ 3298.799649] ra : load_balance+0x51c/0xb5c [ 3298.803766] epc : ffffffff8004cef6 ra : ffffffff8005dae0 sp : ffffffc80a60bab0 [ 3298.810995] gp : ffffffff81e75e48 tp : ffffffe7feaf1f40 t0 : ffffffc80a60bad0 [ 3298.818216] t1 : 0000000002e2c8d6 t2 : 0000000008016002 s0 : ffffffc80a60baf0 [ 3298.825436] s1 : fffffff00038ddc0 a0 : fffffff00038ddc0 a1 : 000000000000002d [ 3298.832659] a2 : fffffffffe45afe4 a3 : 0000000000000000 a4 : ffffffff81e9c098 [ 3298.839878] a5 : 0000000000000001 a6 : 0000000000000001 a7 : ffffffffffffffff [ 3298.847099] s2 : fffffff00038dea8 s3 : 000000000000002d s4 : 000000000000002d [ 3298.854320] s5 : fffffff65f4fe800 s6 : ffffffff81efb588 s7 : 0000000000000001 [ 3298.861539] s8 : 0000000000000002 s9 : ffffffff81e75d78 s10: ffffffc80a60bbc0 [ 3298.868757] s11: fffffff65f4fe800 t3 : 0000000002845dfc t4 : 00000000000065f9 [ 3298.875983] t5 : 0000000000013dc2 t6 : 000000000000032e [ 3298.881294] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003 [ 3298.889211] [] set_task_cpu+0x18a/0x18e [ 3298.894621] [] load_balance+0x51c/0xb5c [ 3298.900026] [] rebalance_domains+0x1f0/0x382 [ 3298.905862] [] run_rebalance_domains+0x6a/0x8a [ 3298.911869] [] __do_softirq+0x18c/0x336 [ 3298.917280] [] __irq_exit_rcu+0x116/0x148 [ 3298.922866] [] irq_exit+0x18/0x28 [ 3298.927745] [] generic_handle_arch_irq+0x64/0x74 [ 3298.933929] [] ret_from_exception+0x0/0x16 [ 3298.939595] [] ct_idle_enter+0x12/0x1a [ 3298.944912] ---[ end trace 0000000000000000 ]--- Signed-off-by: Xiaoguang Xing --- kernel/sched/fair.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index b2e1009e5706e..cdf4368944ffe 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -8830,6 +8830,9 @@ int can_migrate_task(struct task_struct *p, struct lb_env *env) if (kthread_is_per_cpu(p)) return 0; + if (is_migration_disabled(p)) + return 0; + if (!cpumask_test_cpu(env->dst_cpu, p->cpus_ptr)) { int cpu; From 57cbbcefb8dfc6d01f702eb28269aaf815ab27fe Mon Sep 17 00:00:00 2001 From: Khem Raj Date: Mon, 23 Jan 2023 13:04:10 -0800 Subject: [PATCH 32/40] perf cpumap: Make counter as unsigned ints These are loop counters which is inherently unsigned. Therefore make them unsigned. Moreover it also fixes alloc-size-larger-than error with gcc-13, where malloc can be called with (-1) due to tmp_len being an int type. Fixes | cpumap.c:366:20: error: argument 1 range [18446744065119617024, 18446744073709551612] exceeds maximum object size 9223372036854775807 [-Werror=alloc-size-larger-than=] | 366 | tmp_cpus = malloc(tmp_len * sizeof(struct perf_cpu)); | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Khem Raj Cc: Peter Zijlstra Cc: Ingo Molnar Cc: Arnaldo Carvalho de Melo Cc: Mark Rutland Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Namhyung Kim Upstream-Status: Submitted [https://lore.kernel.org/linux-perf-users/20230123211310.127532-1-raj.khem@gmail.com/T/#u] --- tools/lib/perf/cpumap.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c index 2a5a292173740..b53c22b909b81 100644 --- a/tools/lib/perf/cpumap.c +++ b/tools/lib/perf/cpumap.c @@ -405,8 +405,8 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, struct perf_cpu_map *other) { struct perf_cpu *tmp_cpus; - int tmp_len; - int i, j, k; + unsigned int tmp_len; + unsigned int i, j, k; struct perf_cpu_map *merged; if (perf_cpu_map__is_subset(orig, other)) @@ -423,7 +423,7 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, /* Standard merge algorithm from wikipedia */ i = j = k = 0; - while (i < __perf_cpu_map__nr(orig) && j < __perf_cpu_map__nr(other)) { + while (i < (unsigned int)(__perf_cpu_map__nr(orig)) && j < (unsigned int)(__perf_cpu_map__nr(other))) { if (__perf_cpu_map__cpu(orig, i).cpu <= __perf_cpu_map__cpu(other, j).cpu) { if (__perf_cpu_map__cpu(orig, i).cpu == __perf_cpu_map__cpu(other, j).cpu) j++; @@ -432,10 +432,10 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++); } - while (i < __perf_cpu_map__nr(orig)) + while (i < (unsigned int)(__perf_cpu_map__nr(orig))) tmp_cpus[k++] = __perf_cpu_map__cpu(orig, i++); - while (j < __perf_cpu_map__nr(other)) + while (j < (unsigned int)(__perf_cpu_map__nr(other))) tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++); assert(k <= tmp_len); From a87cd4fcdb2d6503dbfd1923719e8a35db5e2e34 Mon Sep 17 00:00:00 2001 From: Xiaoguang Xing Date: Wed, 12 Jul 2023 15:31:13 +0800 Subject: [PATCH 33/40] riscv: configs: Add sophgo sg2042 soc defconfig Signed-off-by: Xiaoguang Xing --- .../configs/sophgo_mango_fedora_defconfig | 3482 ++++++++++++ .../configs/sophgo_mango_normal_defconfig | 190 + .../configs/sophgo_mango_ubuntu_defconfig | 4997 +++++++++++++++++ 3 files changed, 8669 insertions(+) create mode 100644 arch/riscv/configs/sophgo_mango_fedora_defconfig create mode 100644 arch/riscv/configs/sophgo_mango_normal_defconfig create mode 100644 arch/riscv/configs/sophgo_mango_ubuntu_defconfig diff --git a/arch/riscv/configs/sophgo_mango_fedora_defconfig b/arch/riscv/configs/sophgo_mango_fedora_defconfig new file mode 100644 index 0000000000000..5f350babdd58d --- /dev/null +++ b/arch/riscv/configs/sophgo_mango_fedora_defconfig @@ -0,0 +1,3482 @@ +CONFIG_UAPI_HEADER_TEST=y +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_WATCH_QUEUE=y +CONFIG_USELIB=y +CONFIG_NO_HZ_FULL=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_PRELOAD=y +CONFIG_BPF_LSM=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_PRINTK_INDEX=y +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_INITRAMFS_PRESERVE_MTIME is not set +CONFIG_EXPERT=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_PC104=y +CONFIG_PROFILING=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_SOPHGO=y +CONFIG_SOC_STARFIVE=y +CONFIG_SOC_VIRT=y +# CONFIG_ERRATA_SIFIVE_CIP_453 is not set +# CONFIG_ERRATA_SIFIVE_CIP_1200 is not set +CONFIG_ERRATA_THEAD=y +CONFIG_SMP=y +CONFIG_NR_CPUS=128 +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=3 +# CONFIG_RISCV_ISA_SVNAPOT is not set +# CONFIG_RISCV_ISA_SVPBMT is not set +# CONFIG_RISCV_ISA_ZICBOM is not set +# CONFIG_RISCV_ISA_ZICBOZ is not set +CONFIG_HZ_100=y +CONFIG_RISCV_BOOT_SPINWAIT=y +CONFIG_PM_DEBUG=y +CONFIG_CPU_IDLE=y +# CONFIG_STACKPROTECTOR_STRONG is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_COMPRESS_GZIP=y +CONFIG_MODPROBE_PATH="/usr/sbin/modprobe" +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLK_WBT=y +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_FLAT_OLD=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_MISC=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=y +CONFIG_ZSMALLOC=y +# CONFIG_SLAB_MERGE_DEFAULT is not set +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SPARSEMEM_VMEMMAP is not set +CONFIG_KSM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CMA_DEBUGFS=y +CONFIG_CMA_SYSFS=y +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_USERFAULTFD=y +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX_DIAG=y +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_UDP_DIAG=y +CONFIG_INET_RAW_DIAG=y +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_CFM=y +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_DEBUGFS=y +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_DCB=y +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_TRACING=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_NETLINK_DIAG=y +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_NCSI_OEM_CMD_KEEP_PHY=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_CMTP=m +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_VIRTIO=m +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_RXRPC_DEBUG=y +CONFIG_RXKAD=y +CONFIG_AF_KCM=m +CONFIG_MCTP=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIE_ECRC=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCIE_CADENCE_SOPHGO=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_FU740=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_CXL_BUS=y +CONFIG_CXL_MEM=m +CONFIG_PCCARD=y +# CONFIG_PCMCIA is not set +CONFIG_YENTA=m +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DMA_ENGINE=y +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_DEBUG_DEVRES=y +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_CONNECTOR=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB_SIMPLEFB=y +# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_EFI_TEST=m +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_EFI_COCO_SECRET=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_ECC_MXIC=y +CONFIG_MTD_SPI_NOR=m +CONFIG_SPI_SOPHGO_SPIFMC=m +CONFIG_MTD_UBI=m +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_UBLK=m +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +CONFIG_NVME_AUTH=y +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_AUTH=y +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ECHO=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_ISCSI_TCP=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=4 +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_FLASHPOINT=y +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=3 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_PIIX=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OF_PLATFORM=m +CONFIG_ATA_GENERIC=m +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BCACHE=m +CONFIG_BLK_DEV_DM=y +CONFIG_DM_DEBUG=y +CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=y +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=y +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_INIT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=40 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_RIONET=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_ATM_TCP=m +CONFIG_ATM_ENI=m +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_HE=m +CONFIG_ATM_SOLOS=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +# CONFIG_NET_DSA_REALTEK_MDIO is not set +# CONFIG_NET_DSA_REALTEK_SMI is not set +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ET131X=m +# CONFIG_NET_VENDOR_ALACRITECH is not set +CONFIG_ACENIC=m +CONFIG_ALTERA_TSE=m +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_AQTION=m +CONFIG_SPI_AX88796C=m +CONFIG_SPI_AX88796C_COMPRESSION=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_B44=m +CONFIG_BCMGENET=m +CONFIG_TIGON3=m +CONFIG_BNX2X=m +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_MACB=m +CONFIG_MACB_PCI=m +# CONFIG_NET_VENDOR_CAVIUM is not set +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_ENIC=m +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +CONFIG_TULIP_MMIO=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_BE2NET_HWMON is not set +CONFIG_TSNEP=m +# CONFIG_NET_VENDOR_EZCHIP is not set +CONFIG_FUN_ETH=m +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_DCB=y +CONFIG_IXGBEVF=m +CONFIG_I40E=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_JME=m +CONFIG_ADIN1110=m +CONFIG_LITEX_LITEETH=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +CONFIG_OCTEON_EP=m +CONFIG_PRESTERA=m +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SF=y +CONFIG_MLXSW_CORE=m +CONFIG_KSZ884X_PCI=m +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +# CONFIG_NET_VENDOR_NI is not set +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_S2IO=m +CONFIG_NFP=m +# CONFIG_NFP_APP_ABM_NIC is not set +CONFIG_NE2K_PCI=m +CONFIG_FORCEDETH=m +CONFIG_ETHOC=m +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_IONIC=m +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_BNA=m +# CONFIG_NET_VENDOR_QUALCOMM is not set +CONFIG_R6040=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +CONFIG_8139TOO_8129=y +CONFIG_R8169=m +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_ROCKER=m +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SC92031=m +CONFIG_SIS900=m +CONFIG_SIS190=m +# CONFIG_NET_VENDOR_SOLARFLARE is not set +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +# CONFIG_NET_VENDOR_SOCIONEXT is not set +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_STMMAC_PCI=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +# CONFIG_NET_VENDOR_SYNOPSYS is not set +CONFIG_TEHUTI=m +CONFIG_TLAN=m +CONFIG_MSE102X=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NGBE=m +CONFIG_TXGBE=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_FDDI=m +CONFIG_LED_TRIGGER_PHY=y +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +CONFIG_AQUANTIA_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=y +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_CAN327=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_MCTP_SERIAL=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_MVUSB=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH5K=m +CONFIG_ATH5K_DEBUG=y +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_DEBUGFS=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_ATH6KL_DEBUG=y +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +CONFIG_ATH10K_DEBUGFS=y +CONFIG_WCN36XX=m +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_B43=m +CONFIG_B43_SDIO=y +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_WLAN_VENDOR_CISCO is not set +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLEGACY_DEBUG=y +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_PLX_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_MESH=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +# CONFIG_WLAN_VENDOR_PURELIFI is not set +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2X00_LIB_DEBUGFS=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW89=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852CE=m +CONFIG_RSI_91X=m +# CONFIG_WLAN_VENDOR_SILABS is not set +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SPI=m +CONFIG_WLCORE_SDIO=m +CONFIG_ZD1211RW=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_MAC80211_HWSIM=m +CONFIG_VIRT_WIFI=m +CONFIG_WAN=y +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_MCR20A=m +CONFIG_WWAN=y +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_MTK_T7XX=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_ISDN=y +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_CYPRESS_SF=m +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_IMAGIS=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA9063_ONKEY=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F55=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_ARC_PS2=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_FINTEK=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_KGDB_NMI=y +CONFIG_SERIAL_MAX3100=m +CONFIG_SERIAL_MAX310X=m +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SC16IS7XX=m +# CONFIG_SERIAL_SC16IS7XX_I2C is not set +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_LITEUART=y +CONFIG_SERIAL_LITEUART_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_N_HDLC=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=m +CONFIG_VIRTIO_CONSOLE=m +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_OCORES=y +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIRTIO=m +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_SPI=y +CONFIG_SPI_ALTERA_DFL=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_SIFIVE=y +CONFIG_SPI_AMD=y +CONFIG_SPI_MUX=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_DP83640_PHY=m +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_EXAR=m +CONFIG_GPIO_GENERIC_PLATFORM=m +CONFIG_GPIO_SIFIVE=y +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_VIRTIO=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_SAMSUNG_SDI=y +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_SMB347=m +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_BATTERY_UG3105=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDPE152=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=y +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_DA9063_WATCHDOG=m +CONFIG_MAX77620_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_DA9063=m +CONFIG_MFD_DLN2=m +CONFIG_MFD_MAX77650=m +CONFIG_MFD_MAX77714=m +CONFIG_MFD_RT4831=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_VX855=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_DA9063=m +CONFIG_REGULATOR_MAX77650=m +CONFIG_REGULATOR_MAX8893=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_TPS6286X=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_RC_CORE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_LIRC=y +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_VIDEO_FIXED_MINOR_RANGES=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_SMIPCIE=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_DVB_FIREDTV=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +CONFIG_AUXDISPLAY=y +CONFIG_HD44780=m +CONFIG_HT16K33=m +CONFIG_DRM=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC_SI=y +CONFIG_DEBUG_KERNEL_DC=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_VGEM=m +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_SIMPLEDRM=y +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +CONFIG_FB=y +CONFIG_FB_ASILIANT=y +CONFIG_FB_IMSTT=y +CONFIG_FB_EFI=y +CONFIG_FB_NVIDIA=y +CONFIG_FB_NVIDIA_I2C=y +CONFIG_FB_RADEON=y +CONFIG_FB_ATY128=m +CONFIG_FB_ATY=m +CONFIG_FB_SSD1307=m +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_TILEBLITTING=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_PLATFORM=m +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_BT87X=m +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +CONFIG_SND_HDA_PREALLOC_SIZE=2048 +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_VIRTIO=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_MON=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_PCI_RENESAS=y +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ONBOARD_HUB=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_NOP_USB_XCEIV=m +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +CONFIG_USB_ROLE_SWITCH=y +CONFIG_MMC=y +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_SDIO_UART=m +CONFIG_MMC_CRYPTO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_SPI=y +CONFIG_MMC_SDHCI_SOPHGO=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_CQHCI=y +CONFIG_MMC_HSQ=m +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_LITEX=y +CONFIG_MEMSTICK=m +CONFIG_MSPRO_BLOCK=m +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_REGULATOR=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_DS3232=m +# CONFIG_RTC_DRV_DS3232_HWMON is not set +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_STK17TA8=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_R7301=m +CONFIG_DMADEVICES=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +CONFIG_SF_PDMA=y +CONFIG_ASYNC_TX_DMA=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_SYSFS_STATS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA_NET=m +CONFIG_VP_VDPA=m +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +CONFIG_STAGING=y +CONFIG_RTLLIB=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_STAGING_MEDIA=y +CONFIG_QLGE=m +CONFIG_VME_BUS=y +CONFIG_COMMON_CLK_SI544=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_XILINX_VCU=m +CONFIG_HWSPINLOCK=y +CONFIG_MAILBOX=y +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +CONFIG_REMOTEPROC=y +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_LITEX_SOC_CONTROLLER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=m +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMC150_ACCEL=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD10=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_KXCJK1013=m +CONFIG_MMA7660=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_SCA3300=m +CONFIG_AD7124=m +CONFIG_AD7292=m +CONFIG_AD7766=m +CONFIG_AD7949=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MCP3911=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS8344=m +CONFIG_TI_ADS131E08=m +CONFIG_TI_TSC2046=m +CONFIG_AD74413R=m +CONFIG_IIO_RESCALE=m +CONFIG_HMC425=m +CONFIG_BME680=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_AD3552R=m +CONFIG_LTC2688=m +CONFIG_AD5766=m +CONFIG_AD5770R=m +CONFIG_AD7293=m +CONFIG_DPOT_DAC=m +CONFIG_LTC1660=m +CONFIG_TI_DAC7311=m +CONFIG_ADXRS290=m +CONFIG_FXAS21002C=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050_I2C=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_MAX30100=m +CONFIG_DHT11=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_ADIS16475=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_ADUX1020=m +CONFIG_AL3010=m +CONFIG_BH1750=m +CONFIG_CM32181=m +CONFIG_CM3605=m +CONFIG_GP2AP002=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_RPR0521=m +CONFIG_LTR501=m +CONFIG_LV0104CS=m +CONFIG_MAX44009=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_STK3310=m +CONFIG_ST_UVIS25=m +CONFIG_TSL2772=m +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_IIO_MUX=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +CONFIG_AD5110=m +CONFIG_AD5272=m +CONFIG_MCP4018=m +CONFIG_MCP41010=m +CONFIG_LMP91000=m +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_ICP10100=m +CONFIG_MPL115_I2C=m +CONFIG_MB1232=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +CONFIG_TMP117=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_PWM=y +CONFIG_PWM_DWC=m +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_STMPE=y +CONFIG_RESET_TI_TPS380X=m +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_POWERCAP=y +CONFIG_DTPM=y +CONFIG_USB4=y +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_NVMEM_RMEM=m +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_MUX_ADG792A=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +CONFIG_INTERCONNECT=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_EXT2_FS=m +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_DEBUG=y +CONFIG_JBD2_DEBUG=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_PROC_INFO=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +# CONFIG_OCFS2_FS_STATS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QFMT_V2=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_64BIT_CLUSTER=y +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_ORANGEFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_ATIME_SUPPORT=y +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_MINIX_FS=m +CONFIG_ROMFS_FS=m +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_BLK=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_NFS_FS=m +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_AFS_DEBUG=y +CONFIG_AFS_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_BIG_KEYS=y +CONFIG_TRUSTED_KEYS=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_INFINIBAND=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_LSM_MMAP_MIN_ADDR=65535 +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_SMACK_NETFILTER=y +CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_SECURITY_SAFESETID=y +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_IMA=y +CONFIG_IMA_KEXEC=y +CONFIG_IMA_DEFAULT_HASH_SHA256=y +CONFIG_IMA_WRITE_POLICY=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_ARCH_POLICY=y +CONFIG_IMA_APPRAISE_MODSIG=y +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y +CONFIG_EVM=y +CONFIG_EVM_EXTRA_SMACK_XATTRS=y +CONFIG_EVM_ADD_XATTRS=y +CONFIG_LSM="lockdown,yama,integrity,selinux,bpf,landlock" +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_USER=m +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=y +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_AEAD=y +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +CONFIG_CRYPTO_STATS=y +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +CONFIG_SYSTEM_EXTRA_CERTIFICATE=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRC4=m +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_6x10=y +CONFIG_FONT_TER16x32=y +CONFIG_FONT_6x8=y +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DEBUG_MISC is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_HEADERS_INSTALL=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +CONFIG_KGDB=y +CONFIG_KGDB_TESTS=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_DEBUG_WX=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_KFENCE=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_LOCK_TORTURE_TEST=m +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +CONFIG_LATENCYTOP=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_SYNTH_EVENTS=y +CONFIG_RING_BUFFER_BENCHMARK=m +CONFIG_TRACE_EVAL_MAP_FILE=y +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_KUNIT=m +CONFIG_KUNIT_ALL_TESTS=m +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_TEST_LIST_SORT is not set +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_TEST_KSTRTOX=y +CONFIG_TEST_VMALLOC=m +CONFIG_TEST_BPF=m +CONFIG_LINEAR_RANGES_TEST=m diff --git a/arch/riscv/configs/sophgo_mango_normal_defconfig b/arch/riscv/configs/sophgo_mango_normal_defconfig new file mode 100644 index 0000000000000..b7a867f5bc8e2 --- /dev/null +++ b/arch/riscv/configs/sophgo_mango_normal_defconfig @@ -0,0 +1,190 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="mango" +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_CPU_MAX_BUF_SHIFT=13 +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +# CONFIG_PROC_PID_CPUSET is not set +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_PERF_EVENTS=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_ARCH_SOPHGO=y +CONFIG_ERRATA_THEAD=y +CONFIG_SMP=y +CONFIG_NR_CPUS=128 +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=3 +# CONFIG_RISCV_ISA_SVPBMT is not set +# CONFIG_RISCV_ISA_ZICBOM is not set +# CONFIG_RISCV_ISA_ZICBOZ is not set +CONFIG_HZ_100=y +# CONFIG_STACKPROTECTOR is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMDLINE_PARTITION=y +# CONFIG_SWAP is not set +# CONFIG_SPARSEMEM_VMEMMAP is not set +CONFIG_PAGE_REPORTING=y +CONFIG_KSM=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_NET_SCHED=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_SOPHGO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_SOPHGO_SPIFMC=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_NETDEVICES=y +CONFIG_ETHOC=y +CONFIG_R8169=y +CONFIG_STMMAC_ETH=y +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_LEGACY_PTY_COUNT=10 +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_HW_RANDOM=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_SPI=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DWAPB=y +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_PWM_FAN=y +CONFIG_THERMAL=y +CONFIG_DRM=y +CONFIG_DRM_RADEON=y +CONFIG_DRM_AMDGPU=y +CONFIG_FB=y +CONFIG_FB_RADEON=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC2=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_SOPHGO=y +CONFIG_RTC_CLASS=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_SIFIVE=y +CONFIG_GENERIC_PHY=y +CONFIG_RAS=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_ISO9660_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_SECURITYFS=y +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_PER_CPU_MAPS=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_DEBUG_TIMEKEEPING=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_RWSEMS=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_PLIST=y +CONFIG_DEBUG_SG=y +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_EQS_DEBUG=y +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y diff --git a/arch/riscv/configs/sophgo_mango_ubuntu_defconfig b/arch/riscv/configs/sophgo_mango_ubuntu_defconfig new file mode 100644 index 0000000000000..fa6be46eda9a6 --- /dev/null +++ b/arch/riscv/configs/sophgo_mango_ubuntu_defconfig @@ -0,0 +1,4997 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_WATCH_QUEUE=y +CONFIG_USELIB=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_LSM=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_EXPERT=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PC104=y +CONFIG_PROFILING=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_SOPHGO=y +CONFIG_SOC_VIRT=y +CONFIG_ERRATA_THEAD=y +CONFIG_SMP=y +CONFIG_NR_CPUS=128 +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=3 +# CONFIG_RISCV_ISA_SVNAPOT is not set +# CONFIG_RISCV_ISA_SVPBMT is not set +# CONFIG_RISCV_ISA_ZICBOM is not set +# CONFIG_RISCV_ISA_ZICBOZ is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=m +CONFIG_JUMP_LABEL=y +# CONFIG_VMAP_STACK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG_SHA512=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLK_WBT=y +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_MQ_IOSCHED_KYBER=m +CONFIG_IOSCHED_BFQ=m +CONFIG_BINFMT_FLAT=y +CONFIG_BINFMT_FLAT_OLD=y +CONFIG_BINFMT_ZFLAT=y +CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SPARSEMEM_VMEMMAP is not set +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CMA=y +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=m +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_MPTCP=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_IP_SET=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +CONFIG_IP_DCCP=m +# CONFIG_IP_DCCP_CCID3 is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_TIPC=m +CONFIG_TIPC_MEDIA_IB=y +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_CFM=y +CONFIG_NET_DSA=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=y +CONFIG_BATMAN_ADV=m +# CONFIG_BATMAN_ADV_BATMAN_V is not set +CONFIG_BATMAN_ADV_NC=y +CONFIG_OPENVSWITCH=m +CONFIG_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_HSR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +CONFIG_HAMRADIO=y +CONFIG_AX25=m +CONFIG_NETROM=m +CONFIG_ROSE=m +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_CMTP=m +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_VIRTIO=m +CONFIG_AF_RXRPC_IPV6=y +CONFIG_RXKAD=y +CONFIG_AF_KCM=m +CONFIG_MCTP=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +CONFIG_CAIF=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y +CONFIG_NFC_TRF7970A=m +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +CONFIG_NFC_FDP=m +CONFIG_NFC_FDP_I2C=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_MRVL_SPI=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +CONFIG_NET_IFE=m +CONFIG_PCI=y +CONFIG_PCIEAER=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=m +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCIE_CADENCE_SOPHGO=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_NTB=m +CONFIG_CXL_BUS=m +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DMA_ENGINE=y +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_MOXTET=m +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +CONFIG_CONNECTOR=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_EFI_VARS_PSTORE=m +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_EFI_TEST=m +CONFIG_RESET_ATTACK_MITIGATION=y +CONFIG_EFI_COCO_SECRET=y +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +CONFIG_SM_FTL=m +CONFIG_MTD_OOPS=m +CONFIG_MTD_PSTORE=m +CONFIG_MTD_SWAP=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +CONFIG_MTD_PMC551=m +CONFIG_MTD_DATAFLASH=m +CONFIG_MTD_DATAFLASH_OTP=y +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_SST25L=m +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m +CONFIG_MTD_NAND_DENALI_PCI=m +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_LPDDR=m +CONFIG_MTD_SPI_NOR=m +CONFIG_SPI_SOPHGO_SPIFMC=m +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_OF_OVERLAY=y +CONFIG_PARPORT=m +CONFIG_PARPORT_PC=m +CONFIG_PARPORT_SERIAL=m +CONFIG_PARPORT_PC_FIFO=y +CONFIG_PARPORT_1284=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +CONFIG_AD525X_DPOT_SPI=m +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +CONFIG_APDS9802ALS=m +CONFIG_ISL29003=m +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +CONFIG_LATTICE_ECP3_CONFIG=m +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_OPEN_DICE=m +CONFIG_C2PORT=m +CONFIG_EEPROM_AT24=m +CONFIG_EEPROM_AT25=m +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93XX46=m +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +CONFIG_TI_ST=m +CONFIG_SENSORS_LIS3_SPI=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_GENWQE=m +CONFIG_ECHO=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_ISCSI_TCP=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_SCSI_AIC79XX=m +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_PPA=m +CONFIG_SCSI_IMM=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_IPR=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_ATA=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_MOBILE_LPM_POLICY=3 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_CEVA=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_OF_PLATFORM=m +CONFIG_PATA_RZ1000=m +CONFIG_ATA_GENERIC=m +CONFIG_PATA_LEGACY=m +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +CONFIG_BCACHE_ASYNC_REGISTRATION=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_INIT=y +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_TUN=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_ARCNET=m +CONFIG_ARCNET_1201=m +CONFIG_ARCNET_1051=m +CONFIG_ARCNET_RAW=m +CONFIG_ARCNET_CAP=m +CONFIG_ARCNET_COM90xx=m +CONFIG_ARCNET_COM90xxIO=m +CONFIG_ARCNET_RIM_I=m +CONFIG_ARCNET_COM20020=m +CONFIG_ARCNET_COM20020_PCI=m +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_IDT77252=m +CONFIG_ATM_IA=m +CONFIG_ATM_FORE200E=m +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +CONFIG_CAIF_DRIVERS=y +CONFIG_CAIF_TTY=m +CONFIG_CAIF_VIRTIO=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_SEVILLE=m +CONFIG_NET_DSA_AR9331=m +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_ET131X=m +CONFIG_SLICOSS=m +CONFIG_ACENIC=m +CONFIG_ALTERA_TSE=m +CONFIG_ENA_ETHERNET=m +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_AQTION=m +CONFIG_SPI_AX88796C=m +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_B44=m +CONFIG_BCMGENET=m +CONFIG_TIGON3=m +CONFIG_BNX2X=m +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_DCB=y +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_ENIC=m +CONFIG_GEMINI_ETHERNET=m +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_TULIP=m +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +CONFIG_TSNEP=m +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_FUN_ETH=m +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_DCB=y +CONFIG_IXGBEVF=m +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_JME=m +CONFIG_ADIN1110=m +CONFIG_LITEX_LITEETH=m +CONFIG_MVMDIO=m +CONFIG_SKGE=m +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +CONFIG_OCTEON_EP=m +CONFIG_PRESTERA=m +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SF=y +CONFIG_MLXSW_CORE=m +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_ENC28J60=m +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_S2IO=m +CONFIG_NFP=m +CONFIG_NE2K_PCI=m +CONFIG_FORCEDETH=m +CONFIG_ETHOC=m +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_IONIC=m +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QEDE=m +CONFIG_BNA=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_R6040=m +CONFIG_8139CP=m +CONFIG_8139TOO=m +CONFIG_8139TOO_8129=y +CONFIG_R8169=m +CONFIG_ROCKER=m +CONFIG_SXGBE_ETH=m +CONFIG_SC92031=m +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_SFC=m +CONFIG_SFC_FALCON=m +CONFIG_SFC_SIENA=m +CONFIG_SFC_SIENA_SRIOV=y +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_STMMAC_PCI=m +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_TEHUTI=m +CONFIG_TLAN=m +CONFIG_MSE102X=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_TXGBE=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_FDDI=y +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_LED_TRIGGER_PHY=y +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +CONFIG_ADIN1100_PHY=m +CONFIG_AQUANTIA_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM84881_PHY=m +CONFIG_BCM87XX_PHY=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_DP83TD510_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_GRCAN=m +CONFIG_CAN_JANZ_ICAN3=m +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_C_CAN=m +CONFIG_CAN_C_CAN_PLATFORM=m +CONFIG_CAN_C_CAN_PCI=m +CONFIG_CAN_CC770=m +CONFIG_CAN_CC770_ISA=m +CONFIG_CAN_CC770_PLATFORM=m +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PLX_PCI=m +CONFIG_CAN_SJA1000_ISA=m +CONFIG_CAN_SJA1000_PLATFORM=m +CONFIG_CAN_SOFTING=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_MCP251X=m +CONFIG_CAN_MCP251XFD=m +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +CONFIG_MCTP_SERIAL=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m +CONFIG_PLIP=m +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_ADM8211=m +CONFIG_ATH5K=m +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_DEBUGFS=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HTC_DEBUGFS=y +CONFIG_ATH9K_HWRNG=y +CONFIG_ATH9K_COMMON_SPECTRAL=y +CONFIG_CARL9170=m +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_TRACING=y +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_SPECTRAL=y +CONFIG_ATH10K_TRACING=y +CONFIG_WCN36XX=m +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m +CONFIG_ATH11K_DEBUGFS=y +CONFIG_ATH11K_TRACING=y +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_B43=m +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCM_TRACING=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IWL4965=m +CONFIG_IWL3945=m +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLWIFI=m +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HERMES=m +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +CONFIG_P54_SPI=m +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +CONFIG_LIBERTAS_SPI=m +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_WILC1000_SDIO=m +CONFIG_WILC1000_SPI=m +CONFIG_WILC1000_HW_OOB_INTR=y +CONFIG_PLFXLC=m +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_DEBUG=y +CONFIG_RTW88_DEBUGFS=y +CONFIG_RTW89=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_DEBUGMSG=y +CONFIG_RTW89_DEBUGFS=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_WFX=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_WL1251=m +CONFIG_WL1251_SPI=m +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE_SPI=m +CONFIG_WLCORE_SDIO=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_MAC80211_HWSIM=m +CONFIG_VIRT_WIFI=m +CONFIG_WAN=y +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_PCI200SYN=m +CONFIG_WANXL=m +CONFIG_PC300TOO=m +CONFIG_FARSYNC=m +CONFIG_LAPBETHER=m +CONFIG_IEEE802154_FAKELB=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_ATUSB=m +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m +CONFIG_WWAN=m +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_MTK_T7XX=m +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_ISDN=y +CONFIG_MISDN=m +CONFIG_MISDN_DSP=m +CONFIG_MISDN_L1OIP=m +CONFIG_MISDN_HFCPCI=m +CONFIG_MISDN_HFCMULTI=m +CONFIG_MISDN_HFCUSB=m +CONFIG_MISDN_AVMFRITZ=m +CONFIG_MISDN_SPEEDFAX=m +CONFIG_MISDN_INFINEON=m +CONFIG_MISDN_W6692=m +CONFIG_MISDN_NETJET=m +CONFIG_INPUT_LEDS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_ADC=m +CONFIG_KEYBOARD_ADP5520=m +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_GOLDFISH_EVENTS=m +CONFIG_KEYBOARD_STOWAWAY=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_STMPE=m +CONFIG_KEYBOARD_IQS62X=m +CONFIG_KEYBOARD_OMAP4=m +CONFIG_KEYBOARD_TC3589X=m +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_TWL4030=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +CONFIG_KEYBOARD_BCM=m +CONFIG_KEYBOARD_MTK_PMIC=m +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_SENSEHAT=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_88PM860X=m +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_AD7877=m +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +CONFIG_TOUCHSCREEN_AD7879_SPI=m +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP_SPI=m +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +CONFIG_TOUCHSCREEN_CYTTSP4_SPI=m +CONFIG_TOUCHSCREEN_DA9034=m +CONFIG_TOUCHSCREEN_DA9052=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_IMAGIS=m +CONFIG_TOUCHSCREEN_IMX6UL_TSC=m +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM831X=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_MC13783=m +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2004=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_PCAP=m +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_STMPE=m +CONFIG_TOUCHSCREEN_SUR40=m +CONFIG_TOUCHSCREEN_SURFACE3_SPI=m +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_88PM860X_ONKEY=m +CONFIG_INPUT_88PM80X_ONKEY=m +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ARIZONA_HAPTICS=m +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_E3X0_BUTTON=m +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MAX77693_HAPTIC=m +CONFIG_INPUT_MAX8925_ONKEY=m +CONFIG_INPUT_MAX8997_HAPTIC=m +CONFIG_INPUT_MC13783_PWRBUTTON=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_GPIO_BEEPER=m +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RETU_PWRBUTTON=m +CONFIG_INPUT_TPS65218_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_TWL4030_PWRBUTTON=m +CONFIG_INPUT_TWL4030_VIBRA=m +CONFIG_INPUT_TWL6040_VIBRA=m +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_PALMAS_PWRBUTTON=m +CONFIG_INPUT_PCF50633_PMU=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_DA9052_ONKEY=m +CONFIG_INPUT_DA9055_ONKEY=m +CONFIG_INPUT_DA9063_ONKEY=m +CONFIG_INPUT_WM831X_ON=m +CONFIG_INPUT_PCAP=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_RAVE_SP_PWRBUTTON=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +CONFIG_SERIO_ARC_PS2=m +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_FINTEK=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_MEN_MCB=m +CONFIG_SERIAL_8250_NR_UARTS=48 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_KGDB_NMI=y +CONFIG_SERIAL_MAX3100=m +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_UARTLITE=m +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_SERIAL_SCCNXP=y +CONFIG_SERIAL_SCCNXP_CONSOLE=y +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_ALTERA_JTAGUART=m +CONFIG_SERIAL_ALTERA_UART=m +CONFIG_SERIAL_XILINX_PS_UART=m +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_CONEXANT_DIGICOLOR=m +CONFIG_SERIAL_MEN_Z135=m +CONFIG_SERIAL_SPRD=m +CONFIG_SERIAL_LITEUART=m +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_PRINTER=m +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_POLARFIRE_SOC=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_APPLICOM=m +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RK3X=m +CONFIG_I2C_SIMTEC=m +CONFIG_I2C_XILINX=m +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m +CONFIG_I2C_FSI=m +CONFIG_I2C_VIRTIO=m +CONFIG_I2C_STUB=m +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +CONFIG_SPI_ALTERA=m +CONFIG_SPI_ALTERA_DFL=m +CONFIG_SPI_AXI_SPI_ENGINE=m +CONFIG_SPI_BUTTERFLY=m +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_FSI=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_LM70_LLP=m +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_PXA2XX=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=y +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m +CONFIG_SPI_MUX=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +CONFIG_SPI_TLE62X0=m +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_CHAR=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_DP83640_PHY=m +CONFIG_PTP_1588_CLOCK_INES=m +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_DA9062=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +CONFIG_PINCTRL_OCELOT=y +CONFIG_PINCTRL_PALMAS=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_74XX_MMIO=m +CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +CONFIG_GPIO_EXAR=m +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +CONFIG_GPIO_HLWD=m +CONFIG_GPIO_LOGICVC=m +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_MENZ127=m +CONFIG_GPIO_SIFIVE=y +CONFIG_GPIO_SIOX=m +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_WCD934X=m +CONFIG_GPIO_ADNP=m +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +CONFIG_GPIO_ADP5520=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DA9052=m +CONFIG_GPIO_DA9055=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_JANZ_TTL=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_RC5T583=y +CONFIG_GPIO_STMPE=y +CONFIG_GPIO_TC3589X=y +CONFIG_GPIO_TPS65086=m +CONFIG_GPIO_TPS65218=m +CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TPS65912=m +CONFIG_GPIO_TWL4030=m +CONFIG_GPIO_TWL6040=m +CONFIG_GPIO_WM831X=m +CONFIG_GPIO_WM8350=m +CONFIG_GPIO_WM8994=m +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +CONFIG_GPIO_RDC321X=m +CONFIG_GPIO_74X164=m +CONFIG_GPIO_MAX3191X=m +CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MC33880=m +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +CONFIG_GPIO_VIPERBOARD=m +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_MASTER_SGI=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +CONFIG_POWER_RESET_AS3722=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_MT6323=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_TPS65086=y +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_GENERIC_ADC_BATTERY=m +CONFIG_IP5XXX_POWER=m +CONFIG_MAX8925_POWER=m +CONFIG_WM831X_BACKUP=m +CONFIG_WM831X_POWER=m +CONFIG_WM8350_POWER=m +CONFIG_TEST_POWER=m +CONFIG_BATTERY_88PM860X=m +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_ACT8945A=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_SAMSUNG_SDI=y +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_DA9030=m +CONFIG_BATTERY_DA9052=m +CONFIG_CHARGER_DA9150=m +CONFIG_BATTERY_DA9150=m +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_BATTERY_TWL4030_MADC=m +CONFIG_CHARGER_88PM860X=m +CONFIG_CHARGER_PCF50633=m +CONFIG_BATTERY_RX51=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_TWL4030=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_LP8788=m +CONFIG_CHARGER_GPIO=m +CONFIG_CHARGER_MANAGER=y +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_PWM_FAN=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +CONFIG_DA9052_WATCHDOG=m +CONFIG_DA9055_WATCHDOG=m +CONFIG_DA9063_WATCHDOG=m +CONFIG_DA9062_WATCHDOG=m +CONFIG_GPIO_WATCHDOG=m +CONFIG_MENF21BMC_WATCHDOG=m +CONFIG_MENZ069_WATCHDOG=m +CONFIG_WM831X_WATCHDOG=m +CONFIG_WM8350_WATCHDOG=m +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_RAVE_SP_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +CONFIG_RN5T618_WATCHDOG=m +CONFIG_TWL4030_WATCHDOG=m +CONFIG_MAX63XX_WATCHDOG=m +CONFIG_MAX77620_WATCHDOG=m +CONFIG_RETU_WATCHDOG=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_MFD_ACT8945A=m +CONFIG_MFD_AS3711=y +CONFIG_MFD_AS3722=y +CONFIG_PMIC_ADP5520=y +CONFIG_MFD_AAT2870_CORE=y +CONFIG_MFD_ATMEL_FLEXCOM=m +CONFIG_MFD_ATMEL_HLCDC=m +CONFIG_MFD_BCM590XX=m +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +CONFIG_PMIC_DA903X=y +CONFIG_MFD_DA9052_SPI=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9055=y +CONFIG_MFD_DA9062=m +CONFIG_MFD_DA9063=y +CONFIG_MFD_DA9150=m +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +CONFIG_MFD_MC13XXX_SPI=m +CONFIG_MFD_MC13XXX_I2C=m +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_LPC_ICH=m +CONFIG_MFD_IQS62X=m +CONFIG_MFD_JANZ_CMODIO=m +CONFIG_MFD_KEMPLD=m +CONFIG_MFD_88PM800=m +CONFIG_MFD_88PM805=m +CONFIG_MFD_88PM860X=y +CONFIG_MFD_MAX14577=y +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX77693=y +CONFIG_MFD_MAX77714=m +CONFIG_MFD_MAX77843=y +CONFIG_MFD_MAX8907=m +CONFIG_MFD_MAX8925=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +CONFIG_MFD_MT6360=m +CONFIG_MFD_MT6397=m +CONFIG_MFD_MENF21BMC=m +CONFIG_EZX_PCAP=y +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +CONFIG_MFD_RETU=m +CONFIG_MFD_PCF50633=m +CONFIG_PCF50633_ADC=m +CONFIG_PCF50633_GPIO=m +CONFIG_MFD_RT4831=m +CONFIG_MFD_RT5033=m +CONFIG_MFD_RC5T583=y +CONFIG_MFD_RN5T618=m +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_SI476X_CORE=m +CONFIG_MFD_SM501=m +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SKY81452=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_LP3943=m +CONFIG_MFD_LP8788=y +CONFIG_MFD_TI_LMU=m +CONFIG_MFD_PALMAS=y +CONFIG_TPS6105X=m +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +CONFIG_MFD_TPS65086=m +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +CONFIG_MFD_TPS65218=m +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_TPS65912_I2C=y +CONFIG_MFD_TPS65912_SPI=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL6040_CORE=y +CONFIG_MFD_LM3533=m +CONFIG_MFD_TC3589X=y +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_CS47L24=y +CONFIG_MFD_WM5102=y +CONFIG_MFD_WM5110=y +CONFIG_MFD_WM8997=y +CONFIG_MFD_WM8998=y +CONFIG_MFD_WM8400=y +CONFIG_MFD_WM831X_I2C=y +CONFIG_MFD_WM831X_SPI=y +CONFIG_MFD_WM8350_I2C=y +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_WCD934X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +CONFIG_RAVE_SP_CORE=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +CONFIG_REGULATOR_VIRTUAL_CONSUMER=m +CONFIG_REGULATOR_USERSPACE_CONSUMER=m +CONFIG_REGULATOR_88PG86X=m +CONFIG_REGULATOR_88PM800=m +CONFIG_REGULATOR_88PM8607=m +CONFIG_REGULATOR_ACT8865=m +CONFIG_REGULATOR_ACT8945A=m +CONFIG_REGULATOR_AD5398=m +CONFIG_REGULATOR_AAT2870=m +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_AS3711=m +CONFIG_REGULATOR_AS3722=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BCM590XX=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA903X=m +CONFIG_REGULATOR_DA9052=m +CONFIG_REGULATOR_DA9055=m +CONFIG_REGULATOR_DA9062=m +CONFIG_REGULATOR_DA9063=m +CONFIG_REGULATOR_DA9121=m +CONFIG_REGULATOR_DA9210=m +CONFIG_REGULATOR_DA9211=m +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +CONFIG_REGULATOR_ISL6271A=m +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +CONFIG_REGULATOR_LP3971=m +CONFIG_REGULATOR_LP3972=m +CONFIG_REGULATOR_LP872X=m +CONFIG_REGULATOR_LP873X=m +CONFIG_REGULATOR_LP8755=m +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LP8788=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +CONFIG_REGULATOR_MAX14577=m +CONFIG_REGULATOR_MAX1586=m +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +CONFIG_REGULATOR_MAX8649=m +CONFIG_REGULATOR_MAX8660=m +CONFIG_REGULATOR_MAX8893=m +CONFIG_REGULATOR_MAX8907=m +CONFIG_REGULATOR_MAX8925=m +CONFIG_REGULATOR_MAX8952=m +CONFIG_REGULATOR_MAX8997=m +CONFIG_REGULATOR_MAX8998=m +CONFIG_REGULATOR_MAX20086=m +CONFIG_REGULATOR_MAX77686=m +CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77802=m +CONFIG_REGULATOR_MAX77826=m +CONFIG_REGULATOR_MC13783=m +CONFIG_REGULATOR_MC13892=m +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +CONFIG_REGULATOR_MT6311=m +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6323=m +CONFIG_REGULATOR_MT6358=m +CONFIG_REGULATOR_MT6359=m +CONFIG_REGULATOR_MT6360=m +CONFIG_REGULATOR_MT6397=m +CONFIG_REGULATOR_PALMAS=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PCAP=m +CONFIG_REGULATOR_PCF50633=m +CONFIG_REGULATOR_PF8X00=m +CONFIG_REGULATOR_PFUZE100=m +CONFIG_REGULATOR_PV88060=m +CONFIG_REGULATOR_PV88080=m +CONFIG_REGULATOR_PV88090=m +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RC5T583=m +CONFIG_REGULATOR_RN5T618=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5033=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_S2MPA01=m +CONFIG_REGULATOR_S2MPS11=m +CONFIG_REGULATOR_S5M8767=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +CONFIG_REGULATOR_TPS51632=m +CONFIG_REGULATOR_TPS62360=m +CONFIG_REGULATOR_TPS6286X=m +CONFIG_REGULATOR_TPS65023=m +CONFIG_REGULATOR_TPS6507X=m +CONFIG_REGULATOR_TPS65086=m +CONFIG_REGULATOR_TPS65090=m +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65218=m +CONFIG_REGULATOR_TPS6524X=m +CONFIG_REGULATOR_TPS6586X=m +CONFIG_REGULATOR_TPS65910=m +CONFIG_REGULATOR_TPS65912=m +CONFIG_REGULATOR_TWL4030=m +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM831X=m +CONFIG_REGULATOR_WM8350=m +CONFIG_REGULATOR_WM8400=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +CONFIG_DVB_DDBRIDGE=m +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_SI476X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m +CONFIG_VIDEO_CAFE_CCIC=m +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_DVB_FIREDTV=m +CONFIG_SMS_SIANO_DEBUGFS=y +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +CONFIG_SDR_MAX2175=m +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_L64781=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_CXD2880=m +CONFIG_DVB_MN88443X=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_DUMMY_FE=m +CONFIG_HD44780=m +CONFIG_KS0108=m +CONFIG_IMG_ASCII_LCD=m +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PANEL=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m +CONFIG_DRM_KOMEDA=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC_SI=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_AST=m +CONFIG_FB=y +CONFIG_FB_CIRRUS=m +CONFIG_FB_PM2=m +CONFIG_FB_PM2_FIFO_DISCONNECT=y +CONFIG_FB_CYBER2000=m +CONFIG_FB_ASILIANT=y +CONFIG_FB_IMSTT=y +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +CONFIG_FB_OPENCORES=m +CONFIG_FB_S1D13XXX=m +CONFIG_FB_NVIDIA=m +CONFIG_FB_NVIDIA_I2C=y +CONFIG_FB_RIVA=m +CONFIG_FB_RIVA_I2C=y +CONFIG_FB_I740=m +CONFIG_FB_MATROX=m +CONFIG_FB_MATROX_MILLENIUM=y +CONFIG_FB_MATROX_MYSTIQUE=y +CONFIG_FB_MATROX_G=y +CONFIG_FB_MATROX_I2C=m +CONFIG_FB_MATROX_MAVEN=m +CONFIG_FB_RADEON=m +CONFIG_FB_ATY128=m +CONFIG_FB_ATY=m +CONFIG_FB_ATY_CT=y +CONFIG_FB_ATY_GX=y +CONFIG_FB_S3=m +CONFIG_FB_SAVAGE=m +CONFIG_FB_SAVAGE_I2C=y +CONFIG_FB_SIS=m +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +CONFIG_FB_NEOMAGIC=m +CONFIG_FB_KYRO=m +CONFIG_FB_3DFX=m +# CONFIG_FB_3DFX_I2C is not set +CONFIG_FB_VOODOO1=m +CONFIG_FB_VT8623=m +CONFIG_FB_TRIDENT=m +CONFIG_FB_ARK=m +CONFIG_FB_PM3=m +CONFIG_FB_CARMINE=m +CONFIG_FB_SM501=m +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +CONFIG_FB_GOLDFISH=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_SIMPLE=m +CONFIG_FB_SSD1307=m +CONFIG_FB_SM712=m +CONFIG_FIRMWARE_EDID=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_LCD_L4F00242T03=m +CONFIG_LCD_LMS283GF05=m +CONFIG_LCD_LTV350QV=m +CONFIG_LCD_ILI922X=m +CONFIG_LCD_TDO24M=m +CONFIG_LCD_VGG2432A4=m +CONFIG_LCD_PLATFORM=m +CONFIG_LCD_AMS369FG06=m +CONFIG_LCD_LMS501KF03=m +CONFIG_LCD_HX8357=m +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_DA903X=m +CONFIG_BACKLIGHT_DA9052=m +CONFIG_BACKLIGHT_MAX8925=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_WM831X=m +CONFIG_BACKLIGHT_ADP5520=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_88PM860X=m +CONFIG_BACKLIGHT_PCF50633=m +CONFIG_BACKLIGHT_AAT2870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_LP8788=m +CONFIG_BACKLIGHT_PANDORA=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_AS3711=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_RAVE_SP=m +CONFIG_BACKLIGHT_LED=m +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_HRTIMER=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +CONFIG_SND_ATMEL_SOC=m +CONFIG_SND_SOC_MIKROE_PROTO=m +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_IMX_AUDMUX=m +CONFIG_SND_I2S_HI6210_I2S=m +CONFIG_SND_SOC_IMG=y +CONFIG_SND_SOC_IMG_I2S_IN=m +CONFIG_SND_SOC_IMG_I2S_OUT=m +CONFIG_SND_SOC_IMG_PARALLEL_OUT=m +CONFIG_SND_SOC_IMG_SPDIF_IN=m +CONFIG_SND_SOC_IMG_SPDIF_OUT=m +CONFIG_SND_SOC_IMG_PISTACHIO_INTERNAL_DAC=m +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_INNO_RK3036=m +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +CONFIG_SND_SOC_PCM3168A_I2C=m +CONFIG_SND_SOC_PCM3168A_SPI=m +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD9335=m +CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8315=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_VIRTIO=m +CONFIG_HID=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_CONN_GPIO=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_MON=m +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_POLARFIRE_SOC=m +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_PCI=m +CONFIG_USB_CHIPIDEA=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_USS720=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_TAHVO_USB=m +CONFIG_TAHVO_USB_HOST_BY_DEFAULT=y +CONFIG_USB_ISP1301=m +CONFIG_USB_GADGET=m +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_GR_UDC=m +CONFIG_USB_R8A66597=m +CONFIG_USB_PXA27X=m +CONFIG_USB_MV_UDC=m +CONFIG_USB_MV_U3D=m +CONFIG_USB_SNP_UDC_PLAT=m +CONFIG_USB_BDC_UDC=m +CONFIG_USB_AMD5536UDC=m +CONFIG_USB_NET2272=m +CONFIG_USB_NET2272_DMA=y +CONFIG_USB_NET2280=m +CONFIG_USB_GOKU=m +CONFIG_USB_EG20T=m +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_GADGET_UAC1=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_MT6360=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_SDIO_UART=m +CONFIG_MMC_CRYPTO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=m +CONFIG_MMC_SDHCI_OF_AT91=m +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +CONFIG_MMC_SDHCI_MILBEAUT=m +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +CONFIG_MMC_SPI=y +CONFIG_MMC_SDHCI_SOPHGO=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_LITEX=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFSHCD_PCI=m +CONFIG_SCSI_UFS_DWC_TC_PCI=m +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +CONFIG_SCSI_UFS_DWC_TC_PLATFORM=m +CONFIG_MEMSTICK=m +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_88PM860X=m +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +CONFIG_LEDS_BCM6328=m +CONFIG_LEDS_BCM6358=m +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_MT6323=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8788=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +CONFIG_LEDS_WM831X_STATUS=m +CONFIG_LEDS_WM8350=m +CONFIG_LEDS_DA903X=m +CONFIG_LEDS_DA9052=m +CONFIG_LEDS_DAC124S085=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_REGULATOR=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_ADP5520=m +CONFIG_LEDS_MC13783=m +CONFIG_LEDS_TCA6507=m +CONFIG_LEDS_TLC591XX=m +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_MAX8997=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m +CONFIG_LEDS_AAT1290=m +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_KTD2692=m +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_MAX77693=m +CONFIG_LEDS_MT6360=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +# CONFIG_INFINIBAND_MTHCA_DEBUG is not set +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_VMWARE_PVRDMA=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +# CONFIG_INFINIBAND_IPOIB_DEBUG is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC=y +# CONFIG_EDAC_LEGACY_SYSFS is not set +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_88PM860X=m +CONFIG_RTC_DRV_88PM80X=m +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_AS3722=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_LP8788=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX8907=m +CONFIG_RTC_DRV_MAX8925=m +CONFIG_RTC_DRV_MAX8998=m +CONFIG_RTC_DRV_MAX8997=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_TWL4030=m +CONFIG_RTC_DRV_PALMAS=m +CONFIG_RTC_DRV_TPS6586X=m +CONFIG_RTC_DRV_TPS65910=m +CONFIG_RTC_DRV_RC5T583=m +CONFIG_RTC_DRV_RC5T619=m +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_S5M=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_DS1302=m +CONFIG_RTC_DRV_DS1305=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RX4581=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RX6110=m +CONFIG_RTC_DRV_DS1286=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1742=m +CONFIG_RTC_DRV_DS2404=m +CONFIG_RTC_DRV_DA9052=m +CONFIG_RTC_DRV_DA9055=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_EFI=m +CONFIG_RTC_DRV_STK17TA8=m +CONFIG_RTC_DRV_M48T86=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_WM831X=m +CONFIG_RTC_DRV_WM8350=m +CONFIG_RTC_DRV_PCF50633=m +CONFIG_RTC_DRV_ZYNQMP=m +CONFIG_RTC_DRV_NTXEC=m +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_PCAP=m +CONFIG_RTC_DRV_MC13XXX=m +CONFIG_RTC_DRV_MT6397=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_DMADEVICES=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +CONFIG_INTEL_IDMA64=m +CONFIG_PLX_DMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +CONFIG_SF_PDMA=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +CONFIG_UIO_PRUSS=m +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_NOIOMMU=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA_NET=m +CONFIG_VP_VDPA=m +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +CONFIG_COMEDI=m +CONFIG_COMEDI_MISC_DRIVERS=y +CONFIG_COMEDI_BOND=m +CONFIG_COMEDI_TEST=m +CONFIG_COMEDI_PARPORT=m +CONFIG_COMEDI_PCI_DRIVERS=m +CONFIG_COMEDI_8255_PCI=m +CONFIG_COMEDI_ADDI_APCI_1032=m +CONFIG_COMEDI_ADDI_APCI_1500=m +CONFIG_COMEDI_ADDI_APCI_1516=m +CONFIG_COMEDI_ADDI_APCI_1564=m +CONFIG_COMEDI_ADDI_APCI_16XX=m +CONFIG_COMEDI_ADDI_APCI_2032=m +CONFIG_COMEDI_ADDI_APCI_2200=m +CONFIG_COMEDI_ADDI_APCI_3120=m +CONFIG_COMEDI_ADDI_APCI_3501=m +CONFIG_COMEDI_ADDI_APCI_3XXX=m +CONFIG_COMEDI_ADL_PCI6208=m +CONFIG_COMEDI_ADL_PCI7X3X=m +CONFIG_COMEDI_ADL_PCI8164=m +CONFIG_COMEDI_ADV_PCI1720=m +CONFIG_COMEDI_ADV_PCI1723=m +CONFIG_COMEDI_ADV_PCI1724=m +CONFIG_COMEDI_ADV_PCI1760=m +CONFIG_COMEDI_AMPLC_PC236_PCI=m +CONFIG_COMEDI_AMPLC_PC263_PCI=m +CONFIG_COMEDI_CONTEC_PCI_DIO=m +CONFIG_COMEDI_DT3000=m +CONFIG_COMEDI_DYNA_PCI10XX=m +CONFIG_COMEDI_GSC_HPDI=m +CONFIG_COMEDI_MF6X4=m +CONFIG_COMEDI_ICP_MULTI=m +CONFIG_COMEDI_DAQBOARD2000=m +CONFIG_COMEDI_JR3_PCI=m +CONFIG_COMEDI_KE_COUNTER=m +CONFIG_COMEDI_CB_PCIDAS64=m +CONFIG_COMEDI_CB_PCIDDA=m +CONFIG_COMEDI_CB_PCIMDDA=m +CONFIG_COMEDI_ME_DAQ=m +CONFIG_COMEDI_NI_6527=m +CONFIG_COMEDI_NI_65XX=m +CONFIG_COMEDI_NI_660X=m +CONFIG_COMEDI_NI_670X=m +CONFIG_COMEDI_NI_PCIDIO=m +CONFIG_COMEDI_NI_PCIMIO=m +CONFIG_COMEDI_S626=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_TESTS=m +CONFIG_COMEDI_TESTS_EXAMPLE=m +CONFIG_COMEDI_TESTS_NI_ROUTES=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m +CONFIG_ADIS16203=m +CONFIG_ADIS16240=m +CONFIG_AD7816=m +CONFIG_ADT7316=m +CONFIG_ADT7316_I2C=m +CONFIG_AD9832=m +CONFIG_AD9834=m +CONFIG_AD5933=m +CONFIG_AD2S1210=m +CONFIG_FB_SM750=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_MAX96712=m +CONFIG_LTE_GDM724X=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_MOST_COMPONENTS=m +CONFIG_MOST_NET=m +CONFIG_MOST_VIDEO=m +CONFIG_MOST_DIM2=m +CONFIG_MOST_I2C=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +CONFIG_VME_BUS=y +CONFIG_VME_TSI148=m +CONFIG_VME_FAKE=m +CONFIG_VME_USER=m +CONFIG_GOLDFISH_PIPE=m +CONFIG_COMMON_CLK_WM831X=m +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_SI5341=m +CONFIG_COMMON_CLK_SI5351=m +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +CONFIG_COMMON_CLK_SI570=m +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_S2MPS11=m +CONFIG_CLK_TWL6040=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PALMAS=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_XILINX_VCU=m +CONFIG_HWSPINLOCK=y +CONFIG_MAILBOX=y +CONFIG_PLATFORM_MHU=m +CONFIG_ALTERA_MBOX=m +CONFIG_MAILBOX_TEST=m +CONFIG_POLARFIRE_SOC_MAILBOX=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_LITEX_SOC_CONTROLLER=m +CONFIG_POLARFIRE_SOC_SYS_CTRL=m +CONFIG_SOC_TI=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON_ADC_JACK=m +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX14577=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_MAX77693=m +CONFIG_EXTCON_MAX77843=m +CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_PALMAS=m +CONFIG_EXTCON_PTN5150=m +CONFIG_EXTCON_RT8973A=m +CONFIG_EXTCON_SM5502=m +CONFIG_EXTCON_USB_GPIO=m +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_FPGA_DFL_EMIF=m +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_ADIS16201=m +CONFIG_ADIS16209=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMI088_ACCEL=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_KXSD9=m +CONFIG_KXCJK1013=m +CONFIG_MC3230=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +CONFIG_MMA8452=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_SCA3000=m +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +CONFIG_AD7192=m +CONFIG_AD7266=m +CONFIG_AD7280=m +CONFIG_AD7291=m +CONFIG_AD7292=m +CONFIG_AD7298=m +CONFIG_AD7476=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +CONFIG_AD7780=m +CONFIG_AD7791=m +CONFIG_AD7793=m +CONFIG_AD7887=m +CONFIG_AD7923=m +CONFIG_AD7949=m +CONFIG_AD799X=m +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +CONFIG_CC10001_ADC=m +CONFIG_CPCAP_ADC=m +CONFIG_DA9150_GPADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LP8788_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +CONFIG_MAX1027=m +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX9611=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_MCP3911=m +CONFIG_MEDIATEK_MT6360_ADC=m +CONFIG_MEN_Z188_ADC=m +CONFIG_MP2629_ADC=m +CONFIG_NAU7802=m +CONFIG_PALMAS_GPADC=m +CONFIG_QCOM_SPMI_IADC=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RN5T618_ADC=m +CONFIG_SD_ADC_MODULATOR=m +CONFIG_STMPE_ADC=m +CONFIG_TI_ADC081C=m +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +CONFIG_TI_ADC128S052=m +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +CONFIG_TI_ADS8688=m +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +CONFIG_TWL4030_MADC=m +CONFIG_TWL6030_GPADC=m +CONFIG_VF610_ADC=m +CONFIG_VIPERBOARD_ADC=m +CONFIG_XILINX_XADC=m +CONFIG_AD74413R=m +CONFIG_IIO_RESCALE=m +CONFIG_AD8366=m +CONFIG_ADA4250=m +CONFIG_HMC425=m +CONFIG_AD7150=m +CONFIG_AD7746=m +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +CONFIG_SENSIRION_SGP30=m +CONFIG_SENSIRION_SGP40=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +CONFIG_IIO_SSP_SENSORS_COMMONS=m +CONFIG_IIO_SSP_SENSORHUB=m +CONFIG_AD3552R=m +CONFIG_AD5064=m +CONFIG_AD5360=m +CONFIG_AD5380=m +CONFIG_AD5421=m +CONFIG_AD5446=m +CONFIG_AD5449=m +CONFIG_AD5592R=m +CONFIG_AD5593R=m +CONFIG_AD5504=m +CONFIG_AD5624R_SPI=m +CONFIG_LTC2688=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +CONFIG_AD5755=m +CONFIG_AD5758=m +CONFIG_AD5761=m +CONFIG_AD5764=m +CONFIG_AD5766=m +CONFIG_AD5770R=m +CONFIG_AD5791=m +CONFIG_AD7293=m +CONFIG_AD7303=m +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +CONFIG_MAX517=m +CONFIG_MAX5821=m +CONFIG_MCP4725=m +CONFIG_MCP4922=m +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +CONFIG_VF610_DAC=m +CONFIG_IIO_SIMPLE_DUMMY=m +CONFIG_ADMV8818=m +CONFIG_AD9523=m +CONFIG_ADF4350=m +CONFIG_ADF4371=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +CONFIG_ADRF6780=m +CONFIG_ADIS16080=m +CONFIG_ADIS16130=m +CONFIG_ADIS16136=m +CONFIG_ADIS16260=m +CONFIG_ADXRS290=m +CONFIG_ADXRS450=m +CONFIG_BMG160=m +CONFIG_FXAS21002C=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050_I2C=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_ITG3200=m +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +CONFIG_AM2315=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTU21=m +CONFIG_SI7005=m +CONFIG_SI7020=m +CONFIG_ADIS16400=m +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +CONFIG_ADIS16480=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_ADJD_S311=m +CONFIG_ADUX1020=m +CONFIG_AL3010=m +CONFIG_AL3320A=m +CONFIG_APDS9300=m +CONFIG_APDS9960=m +CONFIG_AS73211=m +CONFIG_BH1750=m +CONFIG_BH1780=m +CONFIG_CM32181=m +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +CONFIG_CM36651=m +CONFIG_GP2AP002=m +CONFIG_GP2AP020A00F=m +CONFIG_IQS621_ALS=m +CONFIG_SENSORS_ISL29018=m +CONFIG_SENSORS_ISL29028=m +CONFIG_ISL29125=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_RPR0521=m +CONFIG_SENSORS_LM3533=m +CONFIG_LTR501=m +CONFIG_LV0104CS=m +CONFIG_MAX44000=m +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +CONFIG_STK3310=m +CONFIG_ST_UVIS25=m +CONFIG_TCS3414=m +CONFIG_TCS3472=m +CONFIG_SENSORS_TSL2563=m +CONFIG_TSL2583=m +CONFIG_TSL2591=m +CONFIG_TSL2772=m +CONFIG_TSL4531=m +CONFIG_US5182D=m +CONFIG_VCNL4000=m +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +CONFIG_VEML6070=m +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +CONFIG_AK8974=m +CONFIG_AK09911=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_MAG3110=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +CONFIG_MMC35240=m +CONFIG_SENSORS_HMC5843_I2C=m +CONFIG_SENSORS_HMC5843_SPI=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_YAMAHA_YAS530=m +CONFIG_IIO_MUX=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_IIO_HRTIMER_TRIGGER=m +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_IQS624_POS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +CONFIG_AD5110=m +CONFIG_AD5272=m +CONFIG_DS1803=m +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +CONFIG_MCP4131=m +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +CONFIG_LMP91000=m +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +CONFIG_HP03=m +CONFIG_ICP10100=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +CONFIG_MPL3115=m +CONFIG_MS5611=m +CONFIG_MS5611_I2C=m +CONFIG_MS5611_SPI=m +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_T5403=m +CONFIG_HP206C=m +CONFIG_ZPA2326=m +CONFIG_AS3935=m +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +CONFIG_AD2S90=m +CONFIG_AD2S1200=m +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +CONFIG_TMP006=m +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_NTB=m +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +CONFIG_NTB_EPF=m +CONFIG_NTB_SWITCHTEC=m +CONFIG_NTB_PINGPONG=m +CONFIG_NTB_TOOL=m +CONFIG_NTB_PERF=m +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_DWC=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +CONFIG_PWM_PCA9685=m +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_STMPE=y +CONFIG_PWM_TWL=m +CONFIG_PWM_TWL_LED=m +CONFIG_PWM_XILINX=m +CONFIG_AL_FIC=y +CONFIG_XILINX_INTC=y +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_BCM_KONA_USB2_PHY=m +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_LAN966X_SERDES=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_TUSB1210=m +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +CONFIG_DTPM=y +CONFIG_MCB=m +CONFIG_MCB_PCI=m +CONFIG_MCB_LPC=m +CONFIG_USB4=m +CONFIG_LIBNVDIMM=y +CONFIG_BLK_DEV_PMEM=m +CONFIG_OF_PMEM=m +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_STM=m +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +CONFIG_STM_DUMMY=m +CONFIG_STM_SOURCE_CONSOLE=m +CONFIG_STM_SOURCE_HEARTBEAT=m +CONFIG_STM_SOURCE_FTRACE=m +CONFIG_INTEL_TH=m +CONFIG_INTEL_TH_PCI=m +CONFIG_INTEL_TH_GTH=m +CONFIG_INTEL_TH_STH=m +CONFIG_INTEL_TH_MSU=m +CONFIG_INTEL_TH_PTI=m +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FSI=m +CONFIG_FSI_MASTER_GPIO=m +CONFIG_FSI_MASTER_HUB=m +CONFIG_FSI_MASTER_ASPEED=m +CONFIG_FSI_SCOM=m +CONFIG_FSI_SBEFIFO=m +CONFIG_FSI_OCC=m +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +CONFIG_SIOX=m +CONFIG_SIOX_BUS_GPIO=m +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_INTERCONNECT=y +CONFIG_MOST=m +CONFIG_MOST_USB_HDM=m +CONFIG_MOST_CDEV=m +CONFIG_MOST_SND=m +CONFIG_PECI=m +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_COMPRESSION=y +# CONFIG_F2FS_IOSTAT is not set +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_VERITY=y +CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_FUSE_FS=y +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +CONFIG_OVERLAY_FS_XINO_AUTO=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_CACHEFILES_ERROR_INJECTION=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_LZX_XPRESS=y +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_INODE64=y +CONFIG_HUGETLBFS=y +CONFIG_EFIVAR_FS=y +CONFIG_ORANGEFS_FS=m +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=y +CONFIG_ECRYPT_FS_MESSAGING=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_CMODE_FAVOURLZO=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_CRAMFS=m +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_OMFS_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_QNX6FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_PSTORE=y +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_BLK=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_EROFS_FS=m +CONFIG_NFS_FS=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_SMB_SERVER=m +CONFIG_SMB_SERVER_SMBDIRECT=y +CONFIG_SMB_SERVER_KERBEROS5=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_AFS_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_DLM=m +CONFIG_UNICODE=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=y +CONFIG_USER_DECRYPTED_DATA=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITY_INFINIBAND=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_LSM_MMAP_MIN_ADDR=0 +CONFIG_HARDENED_USERCOPY=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SMACK=y +CONFIG_SECURITY_SMACK_NETFILTER=y +CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y +CONFIG_SECURITY_TOMOYO=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_YAMA=y +CONFIG_SECURITY_SAFESETID=y +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_MACHINE_KEYRING=y +CONFIG_IMA=y +CONFIG_IMA_KEXEC=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_ARCH_POLICY=y +CONFIG_IMA_APPRAISE_MODSIG=y +CONFIG_EVM=y +CONFIG_EVM_EXTRA_SMACK_XATTRS=y +CONFIG_EVM_ADD_XATTRS=y +CONFIG_DEFAULT_SECURITY_APPARMOR=y +CONFIG_LSM="landlock,lockdown,yama,integrity,apparmor" +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_AEGIS128=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_842=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +CONFIG_CRYPTO_STATS=y +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_TEST_KEY=m +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +CONFIG_SYSTEM_EXTRA_CERTIFICATE=y +CONFIG_SECONDARY_TRUSTED_KEYRING=y +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_REVOCATION_LIST=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_TEST=m +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_6x10=y +CONFIG_FONT_TER16x32=y +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_FRAME_WARN=1024 +CONFIG_VMLINUX_MAP=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x01b6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_PAGE_POISONING=y +CONFIG_DEBUG_WX=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_KFENCE=y +CONFIG_KFENCE_SAMPLE_INTERVAL=0 +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SCHEDSTATS=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_SYNTH_EVENTS=y +CONFIG_TRACE_EVENT_INJECT=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_TRACE_PRINTK=m +CONFIG_SAMPLE_TRACE_ARRAY=m +CONFIG_NOTIFIER_ERROR_INJECTION=m +CONFIG_FUNCTION_ERROR_INJECTION=y +CONFIG_TEST_BPF=m +CONFIG_TEST_BLACKHOLE_DEV=m +CONFIG_MEMTEST=y From b342de0b305357ff27f5eba952d88a2541c110fa Mon Sep 17 00:00:00 2001 From: "fengchun.li" Date: Sat, 23 Mar 2024 18:48:32 +0800 Subject: [PATCH 34/40] drivers:pci:remove the err log of parsing pci dirvers:pci:remove the err log of parsing pci Signed-off-by: fengchun.li --- drivers/pci/controller/cadence/pcie-cadence-sophgo.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c index dd1e1e215d910..c0dd61e31adce 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c +++ b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c @@ -793,6 +793,11 @@ static int cdns_pcie_msi_setup(struct cdns_mango_pcie_rc *rc) return ret; } +static int cdns_pcie_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return 0; /* Proper return code 0 == NO_IRQ */ +} + static int cdns_pcie_host_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -899,7 +904,10 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) bridge->dev.parent = dev; bridge->ops = &cdns_pcie_host_ops; - bridge->map_irq = of_irq_parse_and_map_pci; + if (rc->top_intc_used == 1) + bridge->map_irq = of_irq_parse_and_map_pci; + else + bridge->map_irq = cdns_pcie_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; if (rc->top_intc_used == 0) bridge->sysdata = rc; From b7c58dc5ce5194e299911c5e52b7e7962ed4f30e Mon Sep 17 00:00:00 2001 From: "chunzhi.lin" Date: Thu, 28 Mar 2024 13:57:58 +0800 Subject: [PATCH 35/40] riscv:dts:modify dw gpio clock name Modified the gpio clock-names in GPIO nodes so mango dts could adapt to Designware gpio controller driver, then gpio bus clock and gpio debounce clock would be enabled. I also force enable the gpio interrupt clock in sophgo clock system so that the gpio interrupt trigger could take effect. Signed-off-by: chunzhi.lin --- arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi | 3 +-- arch/riscv/boot/dts/sophgo/mango.dtsi | 9 +++------ drivers/clk/sophgo/clk-mango.c | 4 ++-- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi index 97de3fdcad388..8c6e22c33cef0 100644 --- a/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi +++ b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi @@ -558,9 +558,8 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&s1_div_clk GATE_CLK_APB_GPIO>, - <&s1_div_clk GATE_CLK_APB_GPIO_INTR>, <&s1_div_clk GATE_CLK_GPIO_DB>; - clock-names = "base_clk", "intr_clk", "db_clk"; + clock-names = "bus", "db"; port3a: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; diff --git a/arch/riscv/boot/dts/sophgo/mango.dtsi b/arch/riscv/boot/dts/sophgo/mango.dtsi index 8c1ba532531ca..57f304fc778f7 100644 --- a/arch/riscv/boot/dts/sophgo/mango.dtsi +++ b/arch/riscv/boot/dts/sophgo/mango.dtsi @@ -558,9 +558,8 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&div_clk GATE_CLK_APB_GPIO>, - <&div_clk GATE_CLK_APB_GPIO_INTR>, <&div_clk GATE_CLK_GPIO_DB>; - clock-names = "base_clk", "intr_clk", "db_clk"; + clock-names = "bus", "db"; port0a: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -582,9 +581,8 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&div_clk GATE_CLK_APB_GPIO>, - <&div_clk GATE_CLK_APB_GPIO_INTR>, <&div_clk GATE_CLK_GPIO_DB>; - clock-names = "base_clk", "intr_clk", "db_clk"; + clock-names = "bus", "db"; port1a: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; @@ -606,9 +604,8 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&div_clk GATE_CLK_APB_GPIO>, - <&div_clk GATE_CLK_APB_GPIO_INTR>, <&div_clk GATE_CLK_GPIO_DB>; - clock-names = "base_clk", "intr_clk", "db_clk"; + clock-names = "bus", "db"; port2a: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; diff --git a/drivers/clk/sophgo/clk-mango.c b/drivers/clk/sophgo/clk-mango.c index 70e17f65c6fb4..7f386092f764f 100644 --- a/drivers/clk/sophgo/clk-mango.c +++ b/drivers/clk/sophgo/clk-mango.c @@ -233,7 +233,7 @@ static const struct mango_gate_clock s0_gate_clks[] = { { GATE_CLK_APB_GPIO, "clk_gate_apb_gpio", "clk_gate_top_axi0", 0, 0x2000, 22, 0 }, { GATE_CLK_APB_GPIO_INTR, "clk_gate_apb_gpio_intr", "clk_gate_top_axi0", - 0, 0x2000, 23, 0 }, + CLK_IS_CRITICAL, 0x2000, 23, 0 }, { GATE_CLK_APB_I2C, "clk_gate_apb_i2c", "clk_gate_top_axi0", 0, 0x2000, 26, 0 }, { GATE_CLK_APB_WDT, "clk_gate_apb_wdt", "clk_gate_top_axi0", @@ -539,7 +539,7 @@ static const struct mango_gate_clock s1_gate_clks[] = { { GATE_CLK_APB_GPIO, "s1_clk_gate_apb_gpio", "s1_clk_gate_top_axi0", 0, 0x2000, 22, 0 }, { GATE_CLK_APB_GPIO_INTR, "s1_clk_gate_apb_gpio_intr", "s1_clk_gate_top_axi0", - 0, 0x2000, 23, 0 }, + CLK_IS_CRITICAL, 0x2000, 23, 0 }, { GATE_CLK_APB_I2C, "s1_clk_gate_apb_i2c", "s1_clk_gate_top_axi0", 0, 0x2000, 26, 0 }, { GATE_CLK_APB_WDT, "s1_clk_gate_apb_wdt", "s1_clk_gate_top_axi0", From 49e3043768c61a7449b25e93d4e96f09c47415d8 Mon Sep 17 00:00:00 2001 From: "chunzhi.lin" Date: Tue, 23 Apr 2024 11:16:37 +0800 Subject: [PATCH 36/40] dts:sophgo:add i2c-rtc ds1307 device node for single chip Signed-off-by: chunzhi.lin --- arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts | 7 +++++++ arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts | 7 +++++++ arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts | 7 +++++++ 3 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts index 00f2d5e2c6743..3e9bd7ca6793e 100644 --- a/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts @@ -7,6 +7,13 @@ }; }; +&i2c0 { + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { mcu: sg2042mcu@17 { compatible = "sophgo,sg20xx-mcu"; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts index 78495159bbb41..3fe655eaf69a9 100644 --- a/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts @@ -7,6 +7,13 @@ }; }; +&i2c0 { + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { mcu: sg2042mcu@17 { compatible = "sophgo,sg20xx-mcu"; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts index 83e4f1411f2ee..9e0cf5348051e 100644 --- a/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts @@ -7,6 +7,13 @@ }; }; +&i2c0 { + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { mcu: sg2042mcu@17 { compatible = "sophgo,sg20xx-mcu"; From 564e66d40e020260e8122f7e67f769546e93dafe Mon Sep 17 00:00:00 2001 From: "chunzhi.lin" Date: Mon, 20 May 2024 14:00:57 +0800 Subject: [PATCH 37/40] dts:sophgo:x4evb:Apply top interrupt instead of msi on x16 slot Signed-off-by: chunzhi.lin --- arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi index 9c4c9641e1c04..bae6fa388e18d 100644 --- a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi @@ -91,10 +91,10 @@ device-id = /bits/ 16 <0x2042>; pcie-id = /bits/ 16 <0x1>; link-id = /bits/ 16 <0x0>; - top-intc-used = <0>; - interrupt-parent = <&intc>; - interrupts = ; - interrupt-names = "msi"; + top-intc-used = <1>; + top-intc-id = <0>; + msix-supported = <0>; + interrupt-parent = <&intc1>; reg = <0x70 0x62000000 0x0 0x02000000>, <0x48 0x00000000 0x0 0x00001000>; reg-names = "reg", "cfg"; From 529aa9ce193408e6c340faa4009aa8a974153ee7 Mon Sep 17 00:00:00 2001 From: "chunzhi.lin" Date: Thu, 23 May 2024 20:04:29 +0800 Subject: [PATCH 38/40] riscv:dts:capricorn:add i2c-rtc device Signed-off-by: chunzhi.lin --- arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts index 94892b74467f8..65ecd2fd64b95 100644 --- a/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts @@ -45,6 +45,15 @@ }; }; + +&i2c0 { + status = "okay"; + ds1307: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + / { board-info { /* compatible MUST be sophgo,board-info */ From c0fe5277aa97eb8e9ff441e8c6acf35b50ecb8de Mon Sep 17 00:00:00 2001 From: Felix Yan Date: Tue, 28 May 2024 08:43:41 +0300 Subject: [PATCH 39/40] pcie: whitelist and support mellanox connectx-2 Basic functionalities have been tested to work fine on pioneer board. --- drivers/pci/controller/cadence/pcie-cadence-sophgo.c | 1 + include/linux/mlx4/device.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c index c0dd61e31adce..9db142c5465ad 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c +++ b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c @@ -465,6 +465,7 @@ struct vendor_id_list vendor_id_list[] = { {"Inter I40E", 0x8086, 0x1572}, //{"WangXun RP1000", 0x8088}, {"Switchtec", 0x11f8,0x4052}, + {"Mellanox ConnectX-2", 0x15b3, 0x6750} }; size_t vendor_id_list_num = ARRAY_SIZE(vendor_id_list); diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index 27f42f713c891..7617930d3157c 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -47,7 +47,7 @@ #define DEFAULT_UAR_PAGE_SHIFT 12 -#define MAX_MSIX 128 +#define MAX_MSIX 16 #define MIN_MSIX_P_PORT 5 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ (dev_cap).num_ports * MIN_MSIX_P_PORT) From 2722614a74e4adb96740b258cd8f73009e083f78 Mon Sep 17 00:00:00 2001 From: lin peng Date: Sat, 17 Aug 2024 14:13:03 +0800 Subject: [PATCH 40/40] add null event check logic in riscv_pmu_sbi.c Signed-off-by: lin peng --- drivers/perf/riscv_pmu_sbi.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 901da688ea3f8..18c8c20066c5f 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -650,18 +650,20 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, /* Reinitialize and start all the counter that overflowed */ while (ctr_ovf_mask) { if (ctr_ovf_mask & 0x01) { - event = cpu_hw_evt->events[idx]; - hwc = &event->hw; - max_period = riscv_pmu_ctr_get_width_mask(event); - init_val = local64_read(&hwc->prev_count) & max_period; + if(event) { + event = cpu_hw_evt->events[idx]; + hwc = &event->hw; + max_period = riscv_pmu_ctr_get_width_mask(event); + init_val = local64_read(&hwc->prev_count) & max_period; #if defined(CONFIG_32BIT) - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, init_val >> 32, 0); + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); #else - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, 0, 0); + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, 0, 0); #endif - perf_event_update_userpage(event); + perf_event_update_userpage(event); + } } ctr_ovf_mask = ctr_ovf_mask >> 1; idx++;