[X86][MC] Support Enc/Dec for EGPR for promoted MOVDIR instruction (l…

…lvm#74713) R16-R31 was added into GPRs in llvm#70958, This patch supports the encoding/decoding for promoted MOVDIR instruction in EVEX space. RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
dhruvachak · Dec 15, 2023 · 295415e · 295415e
1 parent c1a6974
commit 295415e
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Showing 11 changed files with 98 additions and 10 deletions.
diff --git a/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h b/llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
@@ -140,6 +140,8 @@ enum attributeBits {
  ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
  ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
  ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
+ ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \
+ "requires EVEX, OPSIZE and the ADSIZE prefix") \
  ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
  ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
  ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \

diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -1330,7 +1330,8 @@ static int getInstructionID(struct InternalInstruction *insn,
  // any position.
  if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
  (insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
- (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
+ (insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8) ||
+ (insn->opcodeType == MAP4 && insn->opcode == 0xF8)) {
  // Make sure we observed the prefixes in any position.
  if (insn->hasAdSize)
  attrMask |= ATTR_ADSIZE;

diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1497,11 +1497,19 @@ let SchedRW = [WriteStore] in {
 def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
  "movdiri\t{$src, $dst|$dst, $src}",
  [(int_x86_directstore32 addr:$dst, GR32:$src)]>,
- T8PS, Requires<[HasMOVDIRI]>;
+ T8PS, Requires<[HasMOVDIRI, NoEGPR]>;
 def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
  "movdiri\t{$src, $dst|$dst, $src}",
  [(int_x86_directstore64 addr:$dst, GR64:$src)]>,
- T8PS, Requires<[In64BitMode, HasMOVDIRI]>;
+ T8PS, Requires<[In64BitMode, HasMOVDIRI, NoEGPR]>;
+def MOVDIRI32_EVEX : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
+ "movdiri\t{$src, $dst|$dst, $src}",
+ [(int_x86_directstore32 addr:$dst, GR32:$src)]>,
+ EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
+def MOVDIRI64_EVEX : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
+ "movdiri\t{$src, $dst|$dst, $src}",
+ [(int_x86_directstore64 addr:$dst, GR64:$src)]>,
+ EVEX_NoCD8, T_MAP4PS, Requires<[In64BitMode, HasMOVDIRI, HasEGPR]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
@@ -1514,11 +1522,19 @@ def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem_GR16:$src),
 def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
  "movdir64b\t{$src, $dst|$dst, $src}",
  [(int_x86_movdir64b GR32:$dst, addr:$src)]>,
- T8PD, AdSize32, Requires<[HasMOVDIR64B]>;
+ T8PD, AdSize32, Requires<[HasMOVDIR64B, NoEGPR]>;
 def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
  "movdir64b\t{$src, $dst|$dst, $src}",
  [(int_x86_movdir64b GR64:$dst, addr:$src)]>,
- T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>;
+ T8PD, AdSize64, Requires<[HasMOVDIR64B, NoEGPR, In64BitMode]>;
+def MOVDIR64B32_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem_GR32:$src),
+ "movdir64b\t{$src, $dst|$dst, $src}",
+ [(int_x86_movdir64b GR32:$dst, addr:$src)]>,
+ EVEX_NoCD8, T_MAP4PD, AdSize32, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>;
+def MOVDIR64B64_EVEX : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem_GR64:$src),
+ "movdir64b\t{$src, $dst|$dst, $src}",
+ [(int_x86_movdir64b GR64:$dst, addr:$src)]>,
+ EVEX_NoCD8, T_MAP4PD, AdSize64, Requires<[HasMOVDIR64B, HasEGPR, In64BitMode]>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt b/llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: movdir64b 291(%r28d,%r29d,4), %r18d
+# INTEL: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
+0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: movdir64b 291(%r28,%r29,4), %r19
+# INTEL: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/movdiri.txt b/llvm/test/MC/Disassembler/X86/apx/movdiri.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: movdiri %r18d, 291(%r28,%r29,4)
+# INTEL: movdiri dword ptr [r28 + 4*r29 + 291], r18d
+0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: movdiri %r19, 291(%r28,%r29,4)
+# INTEL: movdiri qword ptr [r28 + 4*r29 + 291], r19
+0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/movdir64b-att.s b/llvm/test/MC/X86/apx/movdir64b-att.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-2: error:
+# ERROR-NOT: error:
+# CHECK: movdir64b 291(%r28d,%r29d,4), %r18d
+# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ movdir64b 291(%r28d,%r29d,4), %r18d
+
+# CHECK: movdir64b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ movdir64b 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/movdir64b-intel.s b/llvm/test/MC/X86/apx/movdir64b-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
+# CHECK: encoding: [0x67,0x62,0x8c,0x79,0x08,0xf8,0x94,0xac,0x23,0x01,0x00,0x00]
+ movdir64b r18d, zmmword ptr [r28d + 4*r29d + 291]
+
+# CHECK: movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf8,0x9c,0xac,0x23,0x01,0x00,0x00]
+ movdir64b r19, zmmword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/apx/movdiri-att.s b/llvm/test/MC/X86/apx/movdiri-att.s
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-2: error:
+# ERROR-NOT: error:
+# CHECK: movdiri %r18d, 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00]
+ movdiri %r18d, 291(%r28,%r29,4)
+
+# CHECK: movdiri %r19, 291(%r28,%r29,4)
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00]
+ movdiri %r19, 291(%r28,%r29,4)
diff --git a/llvm/test/MC/X86/apx/movdiri-intel.s b/llvm/test/MC/X86/apx/movdiri-intel.s
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: movdiri dword ptr [r28 + 4*r29 + 291], r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf9,0x94,0xac,0x23,0x01,0x00,0x00]
+ movdiri dword ptr [r28 + 4*r29 + 291], r18d
+
+# CHECK: movdiri qword ptr [r28 + 4*r29 + 291], r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf9,0x9c,0xac,0x23,0x01,0x00,0x00]
+ movdiri qword ptr [r28 + 4*r29 + 291], r19
diff --git a/llvm/utils/TableGen/X86DisassemblerTables.cpp b/llvm/utils/TableGen/X86DisassemblerTables.cpp
@@ -213,6 +213,8 @@ static inline bool inheritsFrom(InstructionContext child,
  (WIG && inheritsFrom(child, IC_EVEX_W_OPSIZE)) ||
  (VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
  (VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
+ case IC_EVEX_OPSIZE_ADSIZE:
+ return false;
  case IC_EVEX_K:
  return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
  (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L2_W_K)) ||
@@ -885,7 +887,9 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
  for (unsigned index = 0; index < ATTR_max; ++index) {
  o.indent(i * 2);
 
- if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
+ if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
+ o << "IC_EVEX_OPSIZE_ADSIZE";
+ else if ((index & ATTR_EVEX) || (index & ATTR_VEX) || (index & ATTR_VEXL)) {
  if (index & ATTR_EVEX)
  o << "IC_EVEX";
  else
@@ -906,7 +910,7 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
  else if (index & ATTR_XS)
  o << "_XS";
 
- if ((index & ATTR_EVEX)) {
+ if (index & ATTR_EVEX) {
  if (index & ATTR_EVEXKZ)
  o << "_KZ";
  else if (index & ATTR_EVEXK)

diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -265,9 +265,12 @@ InstructionContext RecognizableInstr::insnContext() const {
  }
  }
  // No L, no W
- else if (OpPrefix == X86Local::PD)
- insnContext = EVEX_KB(IC_EVEX_OPSIZE);
- else if (OpPrefix == X86Local::XD)
+ else if (OpPrefix == X86Local::PD) {
+ if (AdSize == X86Local::AdSize32)
+ insnContext = IC_EVEX_OPSIZE_ADSIZE;
+ else
+ insnContext = EVEX_KB(IC_EVEX_OPSIZE);
+ } else if (OpPrefix == X86Local::XD)
  insnContext = EVEX_KB(IC_EVEX_XD);
  else if (OpPrefix == X86Local::XS)
  insnContext = EVEX_KB(IC_EVEX_XS);