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nvme.c
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/*
* QEMU NVM Express Controller
*
* Copyright (c) 2012, Intel Corporation
*
* Written by Keith Busch <keith.busch@intel.com>
*
* This code is licensed under the GNU GPL v2 or later.
*/
/**
* Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
*
* http://www.nvmexpress.org/resources/
*/
/**
* Usage: add options:
* -drive file=<file>,if=none,id=<drive_id>
* -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>
*
* The "file" option must point to a path to a real file that you will use as
* the backing storage for your NVMe device. It must be a non-zero length, as
* this will be the disk image that your nvme controller will use to carve up
* namespaces for storage.
*
* Note the "drive" option's "id" name must match the "device nvme" drive's
* name to link the block device used for backing storage to the nvme
* interface.
*
* Advanced optional options:
*
* namespaces=<int> : Namespaces to make out of the backing storage, Default:1
* queues=<int> : Number of possible IO Queues, Default:64
* entries=<int> : Maximum number of Queue entires possible, Default:0x7ff
* max_cqes=<int> : Maximum completion queue entry size, Default:0x4
* max_sqes=<int> : Maximum submission queue entry size, Default:0x6
* mpsmin=<int> : Minimum page size supported, Default:0
* mpsmax=<int> : Maximum page size supported, Default:0
* stride=<int> : Doorbell stride, Default:0
* aerl=<int> : Async event request limit, Default:3
* acl=<int> : Abort command limit, Default:3
* elpe=<int> : Error log page entries, Default:3
* mdts=<int> : Maximum data transfer size, Default:5
* cqr=<int> : Contiguous queues required, Default:1
* vwc=<int> : Volatile write cache enabled, Default:0
* intc=<int> : Interrupt configuration disabled, Default:0
* intc_thresh=<int>: Interrupt coalesce threshold, Default:0
* intc_ttime=<int> : Interrupt coalesce time 100's of usecs, Default:0
* nlbaf=<int> : Number of logical block formats, Default:1
* lba_index=<int> : Default namespace block format index, Default:0
* extended=<int> : Use extended-lba for meta-data, Default:0
* dpc=<int> : Data protection capabilities, Default:0
* dps=<int> : Data protection settings, Default:0
* mc=<int> : Meta-data capabilities, Default:0
* meta=<int> : Meta-data size, Default:0
* oncs=<oncs> : Optional NVMe command support, Default:DSM
* oacs=<oacs> : Optional Admin command support, Default:Format
* cmbsz=<cmbsz> : Controller Memory Buffer CMBSZ register, Default:0
* cmbloc=<cmbloc> : Controller Memory Buffer CMBLOC register, Default:0
* lsec_per_chk=<int> : Number of sectors in a chunk. Default: 65536
* lws_min=<int> : Mininum write size for device in sectors. Default: 4
* lws_opt=<int> : Optimal write size for device in sectors. Default: 8
* lmw_cunits=<int> : Number of written sectors required in chunk before read. Default: 32
* lmax_sec_per_rq=<int> : Maximum number of sectors per I/O request. Default: 64
* lnum_grp=<int> : Number of controller group. Default: 1. ONLY 1 supported!
* lnum_pu=<int> : Number of parallel units per group, Default:1
* lchunktable=<file> : Load state table from file destination (Provide path
* to file. If no file is provided a state table will be generated.
* lmetadata=<file> : Load metadata from file destination
* lmetasize=<int> : LightNVM metadata (OOB) size. Default: 16
* lb_err_write : First ppa to inject write error. Default: 0 (disabled)
* ln_err_write : Number of ppas affected by write error injection
* ldebug : Enable LightNVM debugging. Default: 0 (disabled)
* lstrict : Enable strict checks. Necessary for pblk (disabled)
*
*
* The logical block formats all start at 512 byte blocks and double for the
* next index. If meta-data is non-zero, half the logical block formats will
* have 0 meta-data, the remaining will start the block size over at 512, but
* with the meta-data size set accordingly. Multiple meta-data sizes are not
* supported.
*
* Parameters will be verified against conflicting capabilities and attributes
* and fail to load if there is a conflict or a configuration the emulated
* device is unable to handle.
*
* Note that when a CMB is requested the NVMe version is set to 1.2,
* for all other cases it is set to 1.1.
*
*/
/**
* Hot-plug support
*
* To hot add a new nvme device, startup the qemu monitor. The easiest way is
* to add '-monitor stdio' option on your startup. At the monitor command line,
* run:
*
* (qemu) drive_add "" if=none,id=<new_drive_id>,file=</path/to/backing/file>
* (qemu) device_add nvme,drive=<new_drive_id>,serial=<serial>,id=<new_id>[,<optional options>]
*
* To hot remove the device, run:
*
* (qemu) device_del <id>
*
* You must have provided the "id" field for device_del to work. You may query
* the available devices by running "info pci" from the qemu monitor.
*
* To query what disks are available to be used as a backing storage, run "info
* block". You cannot assign the same block device to more than one storage
* interface.
*/
/**
* Controller Memory Buffer: For now, you can only turn it on or off, but can't
* tune the exact settings.
*/
#include <block/block_int.h>
#include <block/qapi.h>
#include <exec/memory.h>
#include <hw/block/block.h>
#include <hw/hw.h>
#include <hw/pci/msix.h>
#include <hw/pci/msi.h>
#include <hw/pci/pci.h>
#include <qapi/visitor.h>
#include <qemu/bitops.h>
#include <qemu/bitmap.h>
#include <sysemu/sysemu.h>
#include <sysemu/block-backend.h>
#include <qemu/main-loop.h>
#include "nvme.h"
#include "trace.h"
#define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE
#define NVME_MAX_QUEUE_ENTRIES 0xffff
#define NVME_MAX_STRIDE 12
#define NVME_MAX_NUM_NAMESPACES 256
#define NVME_MAX_QUEUE_ES 0xf
#define NVME_MIN_CQUEUE_ES 0x4
#define NVME_MIN_SQUEUE_ES 0x6
#define NVME_SPARE_THRESHOLD 20
#define NVME_TEMPERATURE 0x143
#define NVME_OP_ABORTED 0xff
#define LNVM_MAX_GRPS_PR_IDENT (20)
#define LNVM_FEAT_EXT_START 64
#define LNVM_FEAT_EXT_END 127
#define LNVM_PBA_UNMAPPED UINT64_MAX
#define LNVM_LBA_UNMAPPED UINT64_MAX
static void nvme_process_sq(void *opaque);
static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
} else {
pci_dma_read(&n->parent_obj, addr, buf, size);
}
}
static void nvme_addr_write(NvmeCtrl *n, hwaddr addr, void *buf, int size)
{
if (n->cmbsz && addr >= n->ctrl_mem.addr &&
addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
memcpy((void *)&n->cmbuf[addr - n->ctrl_mem.addr], buf, size);
return;
} else {
pci_dma_write(&n->parent_obj, addr, buf, size);
}
}
static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
{
return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
}
static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
{
return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
}
static void nvme_inc_cq_tail(NvmeCQueue *cq)
{
cq->tail++;
if (cq->tail >= cq->size) {
cq->tail = 0;
cq->phase = !cq->phase;
}
}
static int nvme_cqes_pending(NvmeCQueue *cq)
{
return cq->tail > cq->head ?
cq->head + (cq->size - cq->tail) :
cq->head - cq->tail;
}
static void nvme_inc_sq_head(NvmeSQueue *sq)
{
sq->head = (sq->head + 1) % sq->size;
}
static void nvme_update_cq_head(NvmeCQueue *cq)
{
if (cq->db_addr) {
nvme_addr_read(cq->ctrl, cq->db_addr, &cq->head, sizeof(cq->head));
}
}
static uint8_t nvme_cq_full(NvmeCQueue *cq)
{
nvme_update_cq_head(cq);
return (cq->tail + 1) % cq->size == cq->head;
}
static uint8_t nvme_sq_empty(NvmeSQueue *sq)
{
return sq->head == sq->tail;
}
static void nvme_isr_notify(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeCtrl *n = cq->ctrl;
if (cq->irq_enabled) {
if (msix_enabled(&(n->parent_obj))) {
msix_notify(&(n->parent_obj), cq->vector);
} else if (msi_enabled(&(n->parent_obj))) {
if (!(n->bar.intms & (1 << cq->vector))) {
msi_notify(&(n->parent_obj), cq->vector);
}
} else {
pci_irq_pulse(&n->parent_obj);
}
}
}
static uint64_t *nvme_setup_discontig(NvmeCtrl *n, uint64_t prp_addr,
uint16_t queue_depth, uint16_t entry_size)
{
int i;
uint16_t prps_per_page = n->page_size >> 3;
uint64_t prp[prps_per_page];
uint16_t total_prps = DIV_ROUND_UP(queue_depth * entry_size, n->page_size);
uint64_t *prp_list = g_malloc0(total_prps * sizeof(*prp_list));
for (i = 0; i < total_prps; i++) {
if (i % prps_per_page == 0 && i < total_prps - 1) {
if (!prp_addr || prp_addr & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
nvme_addr_write(n, prp_addr, (uint8_t *)&prp, sizeof(prp));
prp_addr = le64_to_cpu(prp[prps_per_page - 1]);
}
prp_list[i] = le64_to_cpu(prp[i % prps_per_page]);
if (!prp_list[i] || prp_list[i] & (n->page_size - 1)) {
g_free(prp_list);
return NULL;
}
}
return prp_list;
}
static hwaddr nvme_discontig(uint64_t *dma_addr, uint16_t page_size,
uint16_t queue_idx, uint16_t entry_size)
{
uint16_t entries_per_page = page_size / entry_size;
uint16_t prp_index = queue_idx / entries_per_page;
uint16_t index_in_prp = queue_idx % entries_per_page;
return dma_addr[prp_index] + index_in_prp * entry_size;
}
static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov,
uint64_t prp1, uint64_t prp2, uint32_t len, NvmeCtrl *n)
{
hwaddr trans_len = n->page_size - (prp1 % n->page_size);
trans_len = MIN(len, trans_len);
int num_prps = (len >> n->page_bits) + 1;
bool cmb = false;
if (!prp1) {
return NVME_INVALID_FIELD | NVME_DNR;
} else if (n->cmbsz && prp1 >= n->ctrl_mem.addr &&
prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
cmb = true;
qsg->nsg = 0;
qemu_iovec_init(iov, num_prps);
qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
} else {
pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
qemu_sglist_add(qsg, prp1, trans_len);
}
len -= trans_len;
if (len) {
if (!prp2) {
goto unmap;
}
if (len > n->page_size) {
uint64_t prp_list[n->max_prp_ents];
uint32_t nents, prp_trans;
int i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
while (len != 0) {
uint64_t prp_ent = le64_to_cpu(prp_list[i]);
if (i == n->max_prp_ents - 1 && len > n->page_size) {
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
i = 0;
nents = (len + n->page_size - 1) >> n->page_bits;
prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
nvme_addr_read(n, prp_ent, (void *)prp_list,
prp_trans);
prp_ent = le64_to_cpu(prp_list[i]);
}
if (!prp_ent || prp_ent & (n->page_size - 1)) {
goto unmap;
}
trans_len = MIN(len, n->page_size);
if (!cmb){
qemu_sglist_add(qsg, prp_ent, trans_len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
}
len -= trans_len;
i++;
}
} else {
if (prp2 & (n->page_size - 1)) {
goto unmap;
}
if (!cmb) {
qemu_sglist_add(qsg, prp2, len);
} else {
qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
}
}
}
return NVME_SUCCESS;
unmap:
if (!cmb){
qemu_sglist_destroy(qsg);
} else {
qemu_iovec_destroy(iov);
}
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_write(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_from_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
uint64_t prp1, uint64_t prp2)
{
QEMUSGList qsg;
QEMUIOVector iov;
uint16_t status = NVME_SUCCESS;
if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (qsg.nsg > 0) {
if (dma_buf_read(ptr, len, &qsg)) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_sglist_destroy(&qsg);
} else {
if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
status = NVME_INVALID_FIELD | NVME_DNR;
}
qemu_iovec_destroy(&iov);
}
return status;
}
static void lnvm_inject_w_err(LnvmCtrl *ln, NvmeRequest *req, NvmeCqe *cqe)
{
if (ln->err_write && req->is_write) {
if (ln->debug)
printf("nvme:err_stat:err_write_cnt:%d,nppas:%d,err_write:%d, n_err_write:%d\n",
ln->err_write_cnt, req->nlb, ln->err_write, ln->n_err_write);
if ((ln->err_write_cnt + req->nlb) > ln->err_write) {
int i;
int bit;
/* kill n_err_write sectors in ppa list */
for (i = 0; i < req->nlb; i++) {
if (ln->err_write_cnt + i < ln->err_write)
continue;
bit = i;
bitmap_set(&cqe->res64, bit, ln->n_err_write);
break;
}
if (ln->debug)
printf("nvme: injected error:%u, n:%u, bitmap:%lu\n",
bit, ln->n_err_write, cqe->res64);
req->status = 0x40ff; /* FAIL WRITE status code */
ln->err_write_cnt = 0;
}
ln->err_write_cnt += req->nlb;
}
}
static void lnvm_post_cqe(NvmeCtrl *n, NvmeRequest *req)
{
LnvmCtrl *ln = &n->lnvm_ctrl;
NvmeCqe *cqe = &req->cqe;
/* Do post-completion processing depending on the type of command. This is
* used primarily to inject different types of errors.
*/
switch (req->cmd_opcode) {
case NVME_CMD_WRITE:
case LNVM_CMD_VECT_WRITE:
lnvm_inject_w_err(ln, req, cqe);
}
}
static void nvme_post_cqe(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
NvmeSQueue *sq = req->sq;
NvmeCqe *cqe = &req->cqe;
uint8_t phase = cq->phase;
hwaddr addr;
if (cq->phys_contig) {
addr = cq->dma_addr + cq->tail * n->cqe_size;
} else {
addr = nvme_discontig(cq->prp_list, cq->tail, n->page_size,
n->cqe_size);
}
lnvm_post_cqe(n, req);
cqe->status = cpu_to_le16((req->status << 1) | phase);
cqe->sq_id = cpu_to_le16(sq->sqid);
cqe->sq_head = cpu_to_le16(sq->head);
nvme_addr_write(n, addr, (void *)cqe, sizeof(*cqe));
nvme_inc_cq_tail(cq);
QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
}
static void nvme_post_cqes(void *opaque)
{
NvmeCQueue *cq = opaque;
NvmeRequest *req, *next;
QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
if (nvme_cq_full(cq)) {
break;
}
QTAILQ_REMOVE(&cq->req_list, req, entry);
nvme_post_cqe(cq, req);
}
nvme_isr_notify(cq);
}
static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
{
NvmeCtrl *n = cq->ctrl;
uint64_t time_ns = NVME_INTC_TIME(n->features.int_coalescing) * 100 * 1000;
uint8_t thresh = NVME_INTC_THR(n->features.int_coalescing) + 1;
uint8_t coalesce_disabled =
(n->features.int_vector_config[cq->vector] >> 16) & 1;
uint8_t notify;
assert(cq->cqid == req->sq->cqid);
QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
if (nvme_cq_full(cq) || !QTAILQ_EMPTY(&cq->req_list)) {
QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
return;
}
nvme_post_cqe(cq, req);
notify = coalesce_disabled || !req->sq->sqid || !time_ns ||
req->status != NVME_SUCCESS || nvme_cqes_pending(cq) >= thresh;
if (!notify) {
if (!timer_pending(cq->timer)) {
timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
time_ns);
}
} else {
nvme_isr_notify(cq);
if (timer_pending(cq->timer)) {
timer_del(cq->timer);
}
}
}
static void nvme_set_error_page(NvmeCtrl *n, uint16_t sqid, uint16_t cid,
uint16_t status, uint16_t location, uint64_t lba, uint32_t nsid)
{
NvmeErrorLog *elp;
elp = &n->elpes[n->elp_index];
elp->error_count = n->error_count++;
elp->sqid = sqid;
elp->cid = cid;
elp->status_field = status;
elp->param_error_location = location;
elp->lba = lba;
elp->nsid = nsid;
n->elp_index = (n->elp_index + 1) % n->elpe;
++n->num_errors;
}
static void nvme_enqueue_event(NvmeCtrl *n, uint8_t event_type,
uint8_t event_info, uint8_t log_page)
{
NvmeAsyncEvent *event;
if (!(n->bar.csts & NVME_CSTS_READY))
return;
event = (NvmeAsyncEvent *)g_malloc0(sizeof(*event));
event->result.event_type = event_type;
event->result.event_info = event_info;
event->result.log_page = log_page;
QSIMPLEQ_INSERT_TAIL(&(n->aer_queue), event, entry);
timer_mod(n->aer_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
}
static void nvme_aer_process_cb(void *param)
{
NvmeCtrl *n = param;
NvmeRequest *req;
NvmeAerResult *result;
NvmeAsyncEvent *event, *next;
QSIMPLEQ_FOREACH_SAFE(event, &n->aer_queue, entry, next) {
if (n->outstanding_aers <= 0) {
break;
}
if (n->aer_mask & (1 << event->result.event_type)) {
continue;
}
QSIMPLEQ_REMOVE_HEAD(&n->aer_queue, entry);
n->aer_mask |= 1 << event->result.event_type;
n->outstanding_aers--;
req = n->aer_reqs[n->outstanding_aers];
result = (NvmeAerResult *)&req->cqe.n.result;
result->event_type = event->result.event_type;
result->event_info = event->result.event_info;
result->log_page = event->result.log_page;
g_free(event);
req->status = NVME_SUCCESS;
nvme_enqueue_req_completion(n->cq[0], req);
}
}
static void nvme_rw_cb(void *opaque, int ret)
{
NvmeRequest *req = opaque;
NvmeSQueue *sq = req->sq;
NvmeCtrl *n = sq->ctrl;
NvmeCQueue *cq = n->cq[sq->cqid];
NvmeNamespace *ns = req->ns;
block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
if (!ret) {
req->status = NVME_SUCCESS;
} else {
req->status = NVME_INTERNAL_DEV_ERROR;
}
if (req->status != NVME_SUCCESS) {
nvme_set_error_page(n, sq->sqid, req->cqe.cid, req->status,
offsetof(NvmeRwCmd, slba), req->slba, ns->id);
if (req->is_write) {
bitmap_clear(ns->util, req->slba, req->nlb);
}
}
if (req->qsg.nsg) {
qemu_sglist_destroy(&req->qsg);
} else {
qemu_iovec_destroy(&req->iov);
}
nvme_enqueue_req_completion(cq, req);
}
static uint16_t nvme_rw_check_req(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
NvmeRequest *req, uint64_t slba, uint64_t elba, uint32_t nlb, uint16_t ctrl,
uint64_t data_size, uint64_t meta_size)
{
if (elba > le64_to_cpu(ns->id_ns.nsze)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(NvmeRwCmd, nlb), elba, ns->id);
return NVME_LBA_RANGE | NVME_DNR;
}
if (n->id_ctrl.mdts && data_size > n->page_size * (1 << n->id_ctrl.mdts)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, nlb), nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if ((ctrl & NVME_RW_PRINFO_PRACT) && !(ns->id_ns.dps & DPS_TYPE_MASK)) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_INVALID_FIELD,
offsetof(NvmeRwCmd, control), ctrl, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
if (!req->is_write && find_next_bit(ns->uncorrectable, elba, slba) < elba) {
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_UNRECOVERED_READ,
offsetof(NvmeRwCmd, slba), elba, ns->id);
return NVME_UNRECOVERED_READ;
}
return 0;
}
static uint16_t lnvm_rw_check_req(NvmeCtrl *n, LnvmCtrl *ln, NvmeNamespace *ns,
NvmeCmd *cmd, NvmeRequest *req, uint64_t sppa, uint64_t eppa,
uint32_t nlb, uint16_t ctrl, uint64_t data_size, uint64_t meta_size)
{
Lnvm_IdWrt *wrt = &ln->id_ctrl.wrt;
LnvmRwCmd *lrw = (LnvmRwCmd *)cmd;
if (sppa == -1 || eppa == -1) {
return NVME_INVALID_FIELD | NVME_DNR;
}
if (nlb > ln->params.max_sec_per_rq) {
printf("lnvm_rw: npages too large (%u). Max:%u supported\n",
nlb, ln->params.max_sec_per_rq);
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(LnvmRwCmd, slba), lrw->slba + nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
} else if ((req->is_write) && (nlb < wrt->ws_min)) {
printf("lnvm_rw: I/O does not respect device write constrains."
"Sectors send: (%u). Min:%u sectors required\n",
nlb, wrt->ws_min);
nvme_set_error_page(n, req->sq->sqid, cmd->cid, NVME_LBA_RANGE,
offsetof(LnvmRwCmd, slba), lrw->slba + nlb, ns->id);
return NVME_INVALID_FIELD | NVME_DNR;
}
/* Reuse check logic from nvme_rw */
return nvme_rw_check_req(n, ns, cmd, req, sppa, eppa, nlb, ctrl,
data_size, meta_size);
}
static void print_ppa(LnvmCtrl *ln, uint64_t ppa)
{
uint64_t ch = (ppa & ln->lbaf.ch_mask) >> ln->lbaf.ch_offset;
uint64_t lun = (ppa & ln->lbaf.lun_mask) >> ln->lbaf.lun_offset;
uint64_t chk = (ppa & ln->lbaf.chk_mask) >> ln->lbaf.chk_offset;
uint64_t sec = (ppa & ln->lbaf.sec_mask) >> ln->lbaf.sec_offset;
printf("ppa: ch(%lu), lun(%lu), chunk(%lu), sec(%lu)\n",
ch, lun, chk, sec);
}
static void print_rq(LnvmCtrl *ln, uint64_t *psl, uint32_t nlb)
{
uint32_t i;
for (i = 0; i < nlb; i++)
print_ppa(ln, psl[i]);
}
struct lnvm_metadata_format {
uint32_t state;
uint64_t rsv[2];
} __attribute__((__packed__));
struct lnvm_tgt_meta {
uint64_t lba;
uint64_t rsvd;
} __attribute__((__packed__));
/**
*/
/**
* Write a single out-of-bound area entry
*
* NOTE: Ensure that `lnvm_set_written_state` has been called prior to this
* function to ensure correct file offset of ln->metadata?
*/
static inline int lnvm_meta_write(LnvmCtrl *ln, uint64_t ppa, void *meta)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
uint32_t seek = ppa * meta_len;
size_t ret;
if (fseek(meta_fp, seek, SEEK_SET)) {
perror("_set_written: fseek");
return -1;
}
ret = fwrite(meta, tgt_oob_len, 1, meta_fp);
if (ret != 1) {
perror("lnvm_meta_write: fwrite");
return -1;
}
if (fflush(meta_fp)) {
perror("lnvm_meta_write: fflush");
return -1;
}
return 0;
}
/**
* Read a single out-of-bound area entry
*
* NOTE: Ensure that `lnvm_meta_state_get` has been called to have the correct
* file offset in ln->metadata?
*/
static inline int lnvm_meta_read(LnvmCtrl *ln, uint64_t ppa, void *meta)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
uint32_t seek = ppa * meta_len;
size_t ret;
if (fseek(meta_fp, seek, SEEK_SET)) {
perror("lnvm_meta_state_get: fseek");
printf("Could not seek to offset in metadata file\n");
return -1;
}
ret = fread(meta, tgt_oob_len, 1, meta_fp);
if (ret != 1) {
if (errno == EAGAIN)
return 0;
perror("lnvm_meta_read: fread");
return -1;
}
return 0;
}
static inline int64_t lnvm_bbt_pos_get(LnvmCtrl *ln, uint64_t r)
{
Lnvm_IdGeo *geo = &ln->id_ctrl.geo;
uint64_t lun = (r & ln->lbaf.lun_mask) >> ln->lbaf.lun_offset;
uint64_t chk = (r & ln->lbaf.chk_mask) >> ln->lbaf.chk_offset;
uint64_t lun_off = lun * geo->num_chk;
return chk + lun_off;
}
static inline int64_t lnvm_ppa_to_off(LnvmCtrl *ln, uint64_t r)
{
uint64_t ch = (r & ln->lbaf.ch_mask) >> ln->lbaf.ch_offset;
uint64_t lun = (r & ln->lbaf.lun_mask) >> ln->lbaf.lun_offset;
uint64_t chk = (r & ln->lbaf.chk_mask) >> ln->lbaf.chk_offset;
uint64_t sec = (r & ln->lbaf.sec_mask) >> ln->lbaf.sec_offset;
uint64_t off = sec;
off += chk * ln->params.chk_units;
off += lun * ln->params.lun_units;
if (off > ln->params.total_units) {
printf("lnvm: ppa OOB:ch:%lu,lun:%lu,chk:%lu,sec:%lu\n",
ch, lun, chk, sec);
return -1;
}
return off;
}
static inline int lnvm_meta_state_get(LnvmCtrl *ln, uint64_t ppa,
uint32_t *state)
{
FILE *meta_fp = ln->metadata;
size_t tgt_oob_len = ln->params.sos;
size_t int_oob_len = ln->int_meta_size;
size_t meta_len = tgt_oob_len + int_oob_len;
uint32_t seek = ppa * meta_len;
size_t ret;
if (fseek(meta_fp, seek, SEEK_SET)) {
perror("lnvm_meta_state_get: fseek");
printf("Could not seek to offset in metadata file\n");
return -1;
}
ret = fread(state, int_oob_len, 1, meta_fp);
if (ret != 1) {
if (errno == EAGAIN)
return 0;
perror("lnvm_meta_state_get: fread");
printf("lnvm_meta_state_get: ppa(%lu), ret(%lu)\n", ppa, ret);
return -1;
}
return 0;
}
static inline int64_t lnvm_chunk_pos_from_ppa(LnvmCtrl *ln, uint64_t ppa)
{
uint64_t ch = (ppa & ln->lbaf.ch_mask) >> ln->lbaf.ch_offset;
uint64_t lun = (ppa & ln->lbaf.lun_mask) >> ln->lbaf.lun_offset;
uint64_t chk = (ppa & ln->lbaf.chk_mask) >> ln->lbaf.chk_offset;
uint64_t pos = chk;
pos += lun * ln->params.chk_per_lun;
pos += ch * ln->params.chk_per_ch;
if (pos > ln->params.total_chks) {
printf("lnvm: chunk meta OOB: ch:%lu, lun:%lu, chk:%lu\n", ch, lun, chk);
return -1;
}
return pos;
}
static inline int32_t lnvm_chunk_sec_from_ppa(LnvmCtrl *ln, uint64_t ppa)
{
uint64_t pos = (ppa & ln->lbaf.sec_mask) >> ln->lbaf.sec_offset;
if (pos > ln->params.sec_per_chk) {
uint64_t ch = (ppa & ln->lbaf.ch_mask) >> ln->lbaf.ch_offset;
uint64_t lun = (ppa & ln->lbaf.lun_mask) >> ln->lbaf.lun_offset;
uint64_t chk = (ppa & ln->lbaf.chk_mask) >> ln->lbaf.chk_offset;
printf("lnvm: chunk OOB: ch:%lu, lun:%lu, chk:%lu\n", ch, lun, chk);
return -1;
}
return pos;
}
static inline int lnvm_check_state_table(NvmeNamespace *ns, LnvmCtrl *ln,
uint64_t ppa)
{
LnvmCS chunk_meta;
chunk_meta = ns->chunk_meta[lnvm_chunk_pos_from_ppa(ln, ppa)];
return chunk_meta.state & LNVM_CHUNK_CLOSED;
}
static inline void *lnvm_meta_index(LnvmCtrl *ln, void *meta, uint32_t index)
{
return meta + (index * ln->params.sos);
}
static LnvmCS *lnvm_chunk_get_state(NvmeNamespace *ns, LnvmCtrl *ln,
uint64_t ppa)
{
return &ns->chunk_meta[lnvm_chunk_pos_from_ppa(ln, ppa)];
}
static int lnvm_chunk_set_free(NvmeNamespace *ns, LnvmCtrl *ln, uint64_t ppa)
{
LnvmCS *chunk_meta;
chunk_meta = lnvm_chunk_get_state(ns, ln, ppa);
if (!(chunk_meta->state & LNVM_CHUNK_CLOSED) ||
(chunk_meta->state & (LNVM_CHUNK_OPEN ||
LNVM_CHUNK_BAD ||
LNVM_CHUNK_FREE))) {
printf("nvme: reset: invalid chunk state (%" PRIu64 " -> %d (wp: %" PRIu64 "))\n", ppa, chunk_meta->state, chunk_meta->wp);
}
chunk_meta->state = LNVM_CHUNK_FREE;
chunk_meta->wear_index++;
chunk_meta->wp = 0;
//TODO: Should we save to file here?
return 0;
}
static int lnvm_chunk_advance_wp(NvmeNamespace *ns, LnvmCtrl *ln, uint64_t ppa)
{
LnvmCS *chunk_meta;
chunk_meta = lnvm_chunk_get_state(ns, ln, ppa);
if (chunk_meta->state & LNVM_CHUNK_FREE) {
chunk_meta->state &= ~LNVM_CHUNK_FREE;
chunk_meta->state |= LNVM_CHUNK_OPEN;
}
if (!(chunk_meta->state & LNVM_CHUNK_OPEN)) {
printf("nvme: advance: bad chunk state (state:%d, wp:%lu)\n",
chunk_meta->state, chunk_meta->wp);
return -1;
}
chunk_meta->wp++;
if (chunk_meta->wp == ln->params.sec_per_chk) {
chunk_meta->state &= ~LNVM_CHUNK_OPEN;
chunk_meta->state |= LNVM_CHUNK_CLOSED;
}
return 0;
}
static uint16_t lnvm_rw_free_rq(uint64_t *aio_sector_list)
{
g_free(aio_sector_list);
return NVME_INVALID_FIELD | NVME_DNR;
}
static uint16_t lnvm_rw_setup_rq(NvmeCtrl *n, NvmeNamespace *ns, LnvmRwCmd *lrw,
uint64_t **aio_sector_list, NvmeRequest *req,
uint64_t *psl, uint64_t data_shift, uint32_t nlb)
{
LnvmCtrl *ln = &n->lnvm_ctrl;
void *msl;
uint64_t meta = le64_to_cpu(lrw->metadata);
uint64_t ppa_off;
uint8_t i;
uint16_t err;
*aio_sector_list = g_malloc0(sizeof(uint64_t) * ln->params.max_sec_per_rq);
if (!*aio_sector_list)
return -ENOMEM;
msl = g_malloc0(ln->params.sos * ln->params.max_sec_per_rq);
if (!msl) {
err = -ENOMEM;
goto fail_free_aio_sector_list;
}
if (meta && req->is_write)
nvme_addr_read(n, meta, (void *)msl, nlb * ln->params.sos);
/* If several LUNs are set up, the ppa list sent by the host will not be
* sequential. In this case, we need to pass on the list of ppas to the dma
* handlers to write/read data to/from the right physical sector
*/
for (i = 0; i < nlb; i++) {
ppa_off = lnvm_ppa_to_off(ln, psl[i]);
(*aio_sector_list)[i] =
ns->start_block + (ppa_off << (data_shift - BDRV_SECTOR_BITS));
if (req->is_write) {
if (lnvm_chunk_advance_wp(ns, ln, psl[i])) {
printf("lnvm_rw: advance chunk wp failed\n");
print_ppa(ln, psl[i]);
err = NVME_INVALID_FIELD | NVME_DNR;
goto fail_free_msl;
}
if (meta) {
if (lnvm_meta_write(ln, ppa_off, lnvm_meta_index(ln, msl, i))) {
printf("lnvm_rw: write metadata failed\n");
print_ppa(ln, psl[i]);