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target.cfg
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target.cfg
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transport select swd
adapter speed 5000
#source [find target/swj-dp.tcl]
# ARM Debug Interface V5 (ADI_V5) utility
# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
# SW-DP and JTAG-DP targets don't need to switch based
# on which transport is active.
#
# declare a JTAG or SWD Debug Access Point (DAP)
# based on the transport in use with this session.
# You can't access JTAG ops when SWD is active, etc.
# params are currently what "jtag newtap" uses
# because OpenOCD internals are still strongly biased
# to JTAG .... but for SWD, "irlen" etc are ignored,
# and the internals work differently
# for now, ignore non-JTAG and non-SWD transports
# (e.g. initial flash programming via SPI or UART)
# split out "chip" and "tag" so we can someday handle
# them more uniformly irlen too...)
if [catch {transport select}] {
echo "Error: unable to select a session transport. Can't continue."
shutdown
}
proc swj_newdap {chip tag args} {
if [using_jtag] {
eval jtag newtap $chip $tag $args
} elseif [using_swd] {
eval swd newdap $chip $tag $args
} else {
echo "Error: transport '[ transport select ]' not supported by swj_newdap"
shutdown
}
}
#source [find mem_helper.tcl]
# Helper for common memory read/modify/write procedures
# mrw: "memory read word", returns value of $reg
proc mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
add_usage_text mrw "address"
add_help_text mrw "Returns value of word in memory."
# mrh: "memory read halfword", returns value of $reg
proc mrh {reg} {
set value ""
mem2array value 16 $reg 1
return $value(0)
}
add_usage_text mrh "address"
add_help_text mrh "Returns value of halfword in memory."
# mrb: "memory read byte", returns value of $reg
proc mrb {reg} {
set value ""
mem2array value 8 $reg 1
return $value(0)
}
add_usage_text mrb "address"
add_help_text mrb "Returns value of byte in memory."
# mmw: "memory modify word", updates value of $reg
# $reg <== ((value & ~$clearbits) | $setbits)
proc mmw {reg setbits clearbits} {
set old [mrw $reg]
set new [expr ($old & ~$clearbits) | $setbits]
mww $reg $new
}
add_usage_text mmw "address setbits clearbits"
add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"
set _CHIPNAME rp2040
set _CPUTAPID 0x01002927
set _ENDIAN little
swj_newdap $_CHIPNAME.core0 cpu -dp-id $_CPUTAPID -instance-id 0
swj_newdap $_CHIPNAME.core1 cpu -dp-id $_CPUTAPID -instance-id 1
# NOTE target smp makes both targets act a single virtual target on one port for gdb
# (without it you should be able to debug separately on two ports)
# NOTE: "-rtos hwthread" creates a thread per core in smp mode (otherwise it is a single thread for the virtual target)
# Give OpenOCD SRAM1 (64k) to use for e.g. flash programming bounce buffers (should avoid algo stack etc)
# Don't require save/restore, because this isn't something we'd do whilst a user app is running
set _WORKSIZE 0x10000
set _WORKBASE 0x20010000
#core 0
set _TARGETNAME_0 $_CHIPNAME.core0
dap create $_TARGETNAME_0.dap -chain-position $_CHIPNAME.core0.cpu
target create $_TARGETNAME_0 cortex_m -endian $_ENDIAN -coreid 0 -dap $_TARGETNAME_0.dap -rtos hwthread
$_TARGETNAME_0 configure -work-area-phys $_WORKBASE -work-area-size $_WORKSIZE -work-area-backup 0
cortex_m reset_config sysresetreq
#core 1
set _TARGETNAME_1 $_CHIPNAME.core1
dap create $_TARGETNAME_1.dap -chain-position $_CHIPNAME.core1.cpu
target create $_TARGETNAME_1 cortex_m -endian $_ENDIAN -coreid 1 -dap $_TARGETNAME_1.dap -rtos hwthread
$_TARGETNAME_1 configure -work-area-phys $_WORKBASE -work-area-size $_WORKSIZE -work-area-backup 0
cortex_m reset_config sysresetreq
target smp $_TARGETNAME_0 $_TARGETNAME_1
set _FLASHNAME $_CHIPNAME.flash
set _FLASHSIZE 0x200000
set _FLASHBASE 0x10000000
# name driver base, size in bytes, chip_width, bus_width, target used to access
flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME_0
# srst is not fitted so use SYSRESETREQ to perform a soft reset
reset_config srst_nogate
gdb_flash_program enable
gdb_memory_map enable