params.out

32_64_isa   =   32
acq_rel   =   0
alloc_latency   =   1
alloc_to_exec_latency   =   1
alu_cdb_duty_cycle   =   1
alu_duty_cycle   =   1
arbitration_policy   =   0
arr_100   =   0
arr_adv   =   0
arr_delta   =   0
arr_threshold   =   50
assign_blocks_greedily_initially   =   0
batch_processing_overhead   =   50000
block_key_size   =   103
blocks_to_simulate   =   0
bp_dir_mech   =   gshare
bp_hist_length   =   5
btb_assoc   =   4
btb_bank_num   =   1
btb_entries   =   1024
bug_detector_enable   =   0
byte_level_access   =   0
cache_use_pseudo_lru   =   0
clock_cpu   =   4
clock_gpu   =   1.5
clock_llc   =   1
clock_mc   =   0.8
clock_noc   =   1
collect_cache_info   =   0
collect_cpi_info   =   0
collect_cpi_info_for_multi_gpu   =   0
compute_capability   =   2
const_cache_assoc   =   
const_cache_banks   =   
const_cache_cycles   =   
const_cache_line_size   =   @
const_cache_size   =   1024
core_enable_begin   =   0
core_enable_end   =   0
core_thread_sched   =   greedy
core_type   =   x86
count_hmc_removed_in_max_insts   =   0
cpu_fetch_ratio   =   1
cpu_vc_partition   =   2
dcache_infinite_port   =   0
dcache_throughput   =   3
debug_alloc_stage   =   0
debug_bp_dir   =   0
debug_btb   =   0
debug_cache_lib   =   0
debug_core_id   =   0
debug_cycle_start   =   0
debug_cycle_stop   =   0
debug_dcu_stage   =   0
debug_dram   =   0
debug_exec_stage   =   0
debug_front_stage   =   0
debug_hmc   =   0
debug_inst_start   =   0
debug_inst_stop   =   0
debug_map_stage   =   0
debug_mem   =   0
debug_mem_trace   =   0
debug_mmu   =   0
debug_noc   =   0
debug_port   =   0
debug_pref   =   0
debug_pref_stride   =   0
debug_print_trace   =   0
debug_retire_stage   =   0
debug_schedule_stage   =   0
debug_sim   =   1
debug_sim_thread_schedule   =   0
debug_tlb   =   0
debug_trace_read   =   0
dec_rr_freq   =   1
dec_stream_buf_size   =   16
default_interleaving   =   1
dram_activate   =   6
dram_additional_latency   =   0
dram_bank_xor_index   =   1
dram_buffer_size   =   128
dram_bus_width   =   8
dram_clockrate   =   0.2
dram_column   =   6
dram_ddr_factor   =   2
dram_interleave_factor   =   128
dram_merge_requests   =   1
dram_num_banks   =   8
dram_num_channel   =   1
dram_num_mc   =   1
dram_one_cycle   =   10
dram_precharge   =   6
dram_rowbuffer_size   =   2048
dram_scheduling_policy   =   FRFCFS
dyfr_cpu_budget   =   30
dyfr_cpu_freq_max   =   40
dyfr_cpu_freq_min   =   15
dyfr_gpu_budget   =   30
dyfr_gpu_freq_max   =   21
dyfr_gpu_freq_min   =   6
dyfr_mem_budget   =   40
dyfr_pll_lock   =   100000
dyfr_sample_period   =   4000000
ei_commit_width   =   2
ei_decode_width   =   2
ei_exec_width   =   2
ei_issue_width   =   2
enable_adaptive_ring_routing   =   0
enable_btb   =   0
enable_cache_coherence   =   0
enable_channel_partition   =   0
enable_conditional_execution   =   0
enable_dyfr   =   0
enable_energy_introspector   =   0
enable_heterogeneous_link   =   0
enable_heterogeneous_link_width   =   0
enable_hmc_bypass_cache   =   1
enable_hmc_double_fence   =   0
enable_hmc_fence   =   0
enable_hmc_inst   =   0
enable_hmc_inst_skip   =   0
enable_hmc_trans   =   0
enable_iris   =   0
enable_lock_skip   =   0
enable_new_noc   =   1
enable_noc_vc_partition   =   0
enable_nonhmc_stat   =   0
enable_physical_mapping   =   0
enable_pref_large_core   =   0
enable_pref_medium_core   =   0
enable_pref_small_core   =   0
enable_trace_max_thread   =   0
exec_retire_latency   =   1
extra_ld_latency   =   0
extra_recovery_cycles   =   0
fault_buffer_size   =   512
fe_size   =   256
feature_size   =   32
fence_enable   =   0
fence_pref_enable   =   0
fetch_fair_merge   =   0
fetch_fair_merge_th   =   3
fetch_fair_period   =   200
fetch_fair_tshare   =   0
fetch_fair_tshare_freq   =   5
fetch_fair_tshare_th   =   3
fetch_large_wdith   =   4
fetch_latency   =   1
fetch_medium_wdith   =   4
fetch_only_load_ready   =   0
fetch_only_sched_ready   =   0
fetch_policy   =   rr
fetch_ratio   =   1
fetch_wdith   =   4
fiaq_index   =   2
file_tag   =   NULL
forward_progress_limit   =   100000
fp_inst_window_size   =   64
fp_regfile_size   =   128
fpu_cdb_duty_cycle   =   0.3
fpu_duty_cycle   =   0.3
fq_large_size   =   32
fq_medium_size   =   32
fq_size   =   32
fsched_large_rate   =   2
fsched_large_size   =   24
fsched_medium_rate   =   2
fsched_medium_size   =   24
fsched_rate   =   2
fsched_size   =   24
giaq_index   =   0
giaq_large_size   =   32
giaq_medium_size   =   32
giaq_size   =   32
gpu_sched   =   0
gpu_share_iaqs_between_threads   =   1
gpu_use_single_iaq_type   =   1
gpu_vc_partition   =   2
gpu_warp_size   =   32
gpu_width   =   32
graph_queue_cycle   =   0
graph_queue_method   =   pr
graph_schedule_method   =   0
graph_skip_shmem   =   0
heartbeat_interval   =   0
hetero_gpu_core_disable   =   -2
hetero_mem_priority_cpu   =   0
hetero_mem_priority_gpu   =   0
hetero_noc_use_same_queue   =   1
hetero_static_cache_partition   =   0
hetero_static_cpu_partition   =   1
hetero_static_gpu_partition   =   1
hmc_add_dep   =   1
hmc_test_overhead   =   8
icache_assoc   =   8
icache_banks   =   32
icache_by_pass   =   0
icache_cycles   =   1
icache_large_assoc   =   8
icache_large_banks   =   32
icache_large_by_pass   =   0
icache_large_cycles   =   1
icache_large_line_size   =   64
icache_large_num_set   =   64
icache_line_size   =   64
icache_medium_assoc   =   8
icache_medium_banks   =   32
icache_medium_by_pass   =   0
icache_medium_cycles   =   1
icache_medium_line_size   =   64
icache_medium_num_set   =   64
icache_num_set   =   64
icache_read_ports   =   1
icache_throughput   =   8
icache_write_ports   =   1
ideal_noc   =   0
ideal_noc_latency   =   2
ifu_duty_cycle   =   1
ignore_dep   =   0
infinite_port   =   0
inst_buf_size   =   32
inst_length   =   32
int_regfile_size   =   128
iris_credit   =   4
iris_gridsize   =   3
iris_int_buff_width   =   4
iris_link_width   =   128
iris_memory_latencY   =   1
iris_num_vc   =   4
iris_rc_method   =   ring_routing
iris_resp_payload_len   =   1
iris_self_assign_dest_id   =   1
iris_topology   =   ring
is_fermi   =   1
is_gpu   =   0
isched_large_rate   =   2
isched_large_size   =   16
isched_medium_rate   =   2
isched_medium_size   =   16
isched_rate   =   2
isched_size   =   16
l1_large_assoc   =   8
l1_large_bypass   =   0
l1_large_latency   =   3
l1_large_line_size   =   64
l1_large_num_bank   =   4
l1_large_num_set   =   64
l1_medium_assoc   =   8
l1_medium_bypass   =   0
l1_medium_latency   =   3
l1_medium_line_size   =   64
l1_medium_num_bank   =   4
l1_medium_num_set   =   64
l1_read_ports   =   4
l1_small_assoc   =   8
l1_small_bypass   =   0
l1_small_latency   =   3
l1_small_line_size   =   64
l1_small_num_bank   =   4
l1_small_num_set   =   64
l1_write_ports   =   4
l2_clockrate   =   3.4
l2_large_assoc   =   8
l2_large_bypass   =   0
l2_large_latency   =   8
l2_large_line_size   =   64
l2_large_num_bank   =   8
l2_large_num_set   =   512
l2_medium_assoc   =   8
l2_medium_bypass   =   0
l2_medium_latency   =   8
l2_medium_line_size   =   64
l2_medium_num_bank   =   8
l2_medium_num_set   =   512
l2_read_ports   =   2
l2_small_assoc   =   8
l2_small_bypass   =   0
l2_small_latency   =   8
l2_small_line_size   =   64
l2_small_num_bank   =   8
l2_small_num_set   =   512
l2_throughput   =   8
l2_write_ports   =   2
l3_assoc   =   16
l3_interleave_factor   =   64
l3_latency   =   25
l3_line_size   =   64
l3_num_bank   =   16
l3_num_set   =   8192
l3_read_ports   =   1
l3_write_ports   =   1
large_core_alloc_latency   =   1
large_core_fetch_latency   =   1
large_core_schedule   =   io
large_core_type   =   x86
large_width   =   2
ldst_per_sm   =   16
link_latency   =   1
link_width   =   16
llc_assoc   =   16
llc_clockrate   =   0.85
llc_interleave_factor   =   64
llc_latency   =   25
llc_line_size   =   64
llc_num_bank   =   16
llc_num_set   =   8192
llc_read_ports   =   1
llc_throughput   =   16
llc_type   =   default
llc_write_ports   =   1
load_buf_size   =   16
log2_pref_polbv_size   =   10
lsu_duty_cycle   =   0.5
max_block_per_core   =   4
max_block_per_core_super   =   0
max_blocks_to_simulate   =   0
max_insts   =   1000
max_insts1   =   10000000000
max_num_core_per_appl   =   0
max_threads_per_core   =   3
max_threads_per_large_core   =   3
max_threads_per_medium_core   =   3
max_transaction_size   =   64
max_warp_per_sm   =   48
medium_core_alloc_latency   =   1
medium_core_fetch_latency   =   1
medium_core_schedule   =   io
medium_core_type   =   x86
medium_width   =   2
mem_d_duty_cycle   =   0.5
mem_i_duty_cycle   =   1
mem_mshr_size   =   128
mem_obey_store_dep   =   1
mem_ooo_stores   =   1
mem_queue_size   =   128
mem_size_amp   =   1
memory_size   =   4294967296
memory_type   =   llc_cn
meu_large_nlb   =   64
meu_large_nsb   =   64
meu_medium_nlb   =   64
meu_medium_nsb   =   64
meu_nlb   =   64
meu_nsb   =   64
miaq_index   =   1
miaq_large_size   =   16
miaq_medium_size   =   16
miaq_size   =   16
micro_opcode_width   =   8
msched_large_rate   =   1
msched_large_size   =   8
msched_medium_rate   =   1
msched_medium_size   =   8
msched_rate   =   1
msched_size   =   8
mt_no_fetch_br   =   0
mt_stop_fair_init   =   1
mul_cdb_duty_cycle   =   0.3
mul_duty_cycle   =   0.3
new_interleaving_diff_granularity   =   0
new_interleaving_same_granularity   =   0
no_fetch_on_icache_miss   =   0
noc_dimension   =   1
noc_topology   =   ring
num_channel_cpu   =   1
num_channel_gpu   =   1
num_cpu_application   =   4
num_inst_to_fetch_after_load   =   1
num_l3   =   1
num_llc   =   1
num_port   =   3
num_sim_cores   =   80
num_sim_large_cores   =   0
num_sim_medium_cores   =   0
num_sim_small_cores   =   80
num_switch   =   1
num_switch_cpu   =   1
num_switch_gpu   =   1
num_switch_iter   =   1
num_switch_iter_cpu   =   1
num_switch_iter_gpu   =   1
num_switch_iter_mem   =   1
num_switch_mem   =   1
num_vc   =   4
num_warp_scheduler   =   1
one_cycle_exec   =   0
opcode_width   =   16
orig_pipeline_stages   =   20
out   =   .
page_eviction_latency   =   1000
page_fault_latency   =   1000
page_mapping_policy   =   REGION_FCFS
page_size   =   4096
page_table_walk_latency   =   200
pcie_bus_size   =   1
pcie_init   =   33250
pcie_tr   =   16
perfect_bp   =   0
perfect_btb   =   1
perfect_dcache   =   0
perfect_icache   =   0
pht_ctr_bits   =   2
phy_addr_width   =   32
power_print_level   =   2
pref_acc_study   =   0
pref_acc_thresh_1   =   0.9
pref_acc_thresh_2   =   0.7
pref_acc_thresh_3   =   0.6
pref_acc_update_interval   =   1000000
pref_analyze_load   =   0
pref_degfb_statphasefile   =   0
pref_degfb_useonlyacc   =   0
pref_degfb_useonlylate   =   0
pref_degfb_useonlypol   =   0
pref_dhal   =   0
pref_dhal_maxdeg   =   64
pref_dhal_sentthresh   =   16
pref_dhal_usethresh_max   =   12
pref_dhal_usethresh_min1   =   4
pref_dhal_usethresh_min2   =   8
pref_dl0_hit_on   =   1
pref_dl0_miss_on   =   1
pref_dl0req_add_filter_on   =   1
pref_dl0req_queue_filter_on   =   1
pref_dl0req_queue_overwrite_on_full   =   0
pref_dl0req_queue_size   =   32
pref_dl0schedule_num   =   4
pref_framework_on   =   0
pref_hybrid_default   =   

pref_hybrid_default_timeperiod   =   100000
pref_hybrid_min_memused   =   10
pref_hybrid_min_sent   =   10
pref_hybrid_on   =   0
pref_hybrid_sort_on_acc   =   1
pref_hybrid_sort_on_cov   =   0
pref_hybrid_update_multiple   =   100
pref_numtracking_regions   =   2048
pref_pol_thresh_1   =   0.25
pref_pol_thresh_2   =   0.1
pref_polbv_on   =   0
pref_polbv_size   =   1024
pref_polpf_thresh   =   0.01
pref_region_on   =   0
pref_region_size   =   256
pref_stride_degree   =   4
pref_stride_distance   =   16
pref_stride_multi_thresh   =   6
pref_stride_on   =   0
pref_stride_on_large_core   =   0
pref_stride_on_medium_core   =   0
pref_stride_region_bits   =   16
pref_stride_single_stride_mode   =   0
pref_stride_single_thresh   =   6
pref_stride_startdistance   =   1
pref_stride_table_n   =   256
pref_thread_index   =   0
pref_timely_thresh   =   0.05
pref_timely_thresh_2   =   0.005
pref_trace_on   =   0
pref_train_inst_once   =   0
pref_ul1req_add_fillter_on   =   1
pref_ul1req_queue_filter_on   =   1
pref_ul1req_queue_overwrite_on_full   =   0
pref_ul1req_queue_size   =   128
pref_ul1schedule_num   =   4
pref_update_interval   =   0
pref_useregion_tocalc_acc   =   0
print_heartbeat   =   1
ptx_common_cache   =   0
ptx_dispatch_latency_factor   =   2
ptx_exec_ratio   =   4
ptx_inst_latency   =   20
qsim_bench   =   
qsim_state   =   'state.1'
ramulator_cacheline_size   =   128
ramulator_config_file   =   ../src/ramulator/configs/DDR4-config.cfg
ras_size   =   64
region_size   =   1048576
repeat_trace   =   0
repeat_trace_n   =   0
rob_large_size   =   128
rob_medium_size   =   128
rob_size   =   128
router_placement   =   0
sched_clock   =   1
sched_to_large_width   =   2
sched_to_medium_width   =   2
sched_to_width   =   2
schedule   =   io
schedule_ratio   =   1
sfu_per_sm   =   4
shared_mem_assoc   =   
shared_mem_banks   =   
shared_mem_cycles   =   
shared_mem_line_size   =   
shared_mem_ports   =   2
shared_mem_size   =   4096
siaq_index   =   3
siaq_large_size   =   32
siaq_medium_size   =   32
siaq_size   =   32
sim_cycle_count   =   1000000
simulate_last_blocks   =   0
sp_per_sm   =   32
ssched_large_rate   =   1
ssched_large_size   =   32
ssched_medium_rate   =   1
ssched_medium_size   =   32
ssched_rate   =   1
ssched_size   =   32
stderr   =   NULL
stdout   =   NULL
store_buf_size   =   12
temperature   =   320
texture_cache_assoc   =   
texture_cache_banks   =   
texture_cache_cycles   =   
texture_cache_line_size   =   @
texture_cache_size   =   256
tlb_num_entry   =   2048
trace_max_thread_count   =   8
trace_name_file   =   trace_file_list
trace_uses_64_bit_addr   =   1
uop_latency_map   =   x86
use_branch_prediction   =   1
use_const_and_tex_caches   =   1
use_incoming_tid_cid_for_wb   =   0
use_memhierarchy   =   0
use_new_coalescing   =   0
use_new_oracle   =   0
use_vaultsim_link   =   0
use_wb   =   0
use_zero_latency_noc   =   0
wb_fifo   =   0
wb_size   =   32
width   =   2