GPIO: Wrong mask for PIN PULL UP/DOWN in gpio_ll_get_io_config() (IDFGH-14072)

[IhorNehrutsa]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

General issue report

In all MCU soc and hal:
Defined as bit:

#define FUN_PD_M (BIT(7))
#define FUN_PU_M (BIT(8))

Used as mask:

    *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
    *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;

Also, need to check BIT or MASK:

[suda-morris]

Not sure if I understood your question. But

#define BIT(nr)                 (1UL << (nr))

It's a mask, not a bit.