From e8ca34c4cb3a9d516ec00dbc58878913e70e94fb Mon Sep 17 00:00:00 2001 From: Jim McCarron Date: Mon, 6 Jan 2025 12:59:07 -0500 Subject: [PATCH] fix vCPU count on BX520 --- docs/velos_components_new.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/velos_components_new.rst b/docs/velos_components_new.rst index 6852034..2f15329 100644 --- a/docs/velos_components_new.rst +++ b/docs/velos_components_new.rst @@ -306,7 +306,7 @@ The BX520 blade is a next generation data plane/line card. It has 2 high speed ( :align: center :scale: 60% -The BX520 has 56 physical cores, which are hyperthreaded into 112 vCPUs. Eighteen of the vCPUs are reserved for the F5OS-C platform layer, leaving 96 vCPUs available for multitenancy. Each blade comes with a 4TB SSD drive and is populated with 512GB of RAM. Each BX520 has three Field Programmable Gate Arrays (FPGA's), which provide hardware offload for certain functions and workloads. The Traffic Aggregation Module (TAM) FPGA handles all front panel connections. The Application Traffic Service Engine (ATSE) handles initial classifications and offload, while the VELOS Queuing FPGA (VQF), is the “back panel FPGA” that implements queuing and CoS through the chassis backplane. The CPU complex provides hardware offload for SSL/TLS and compression, like previous generations of BIG-IP (such as iSeries and VIPRION B4450) performed these operations, but with a newer generation of processor. +The BX520 has 56 physical cores, which are hyperthreaded into 112 vCPUs. Sixteen of the vCPUs are reserved for the F5OS-C platform layer, leaving 96 vCPUs available for multitenancy. Each blade comes with a 4TB SSD drive and is populated with 512GB of RAM. Each BX520 has three Field Programmable Gate Arrays (FPGA's), which provide hardware offload for certain functions and workloads. The Traffic Aggregation Module (TAM) FPGA handles all front panel connections. The Application Traffic Service Engine (ATSE) handles initial classifications and offload, while the VELOS Queuing FPGA (VQF), is the “back panel FPGA” that implements queuing and CoS through the chassis backplane. The CPU complex provides hardware offload for SSL/TLS and compression, like previous generations of BIG-IP (such as iSeries and VIPRION B4450) performed these operations, but with a newer generation of processor. .. image:: images/velos_components/image18a.png :align: center