MPSCache: Efficient Multi-ported Scalable Reconfigurable Cache Design

MPSCache:Efficient Multi-ported Scalable Reconfigurable Cache Design

Team Number: xohw21-248

This project was carried out within the scope of the EEM464 course at the Department of Electrical and Electronics Engineering at Eskişehir Technical University.

Project Description

While approaching the end of Moore's Law regarding physical limits in silicon technology, parallel multi-core hardware system design and parallel-programming environments are concentrated solutions to get more performance. Today, varying computing platforms solve problems of different high-computational tasks with varying architectures of memory. In the end, heterogeneous computing platforms are presenting a better performance for application-specific solutions since they have customized logic units and the transactions between compute and memory units. Computing and communication specialization for a specific task can achieve high performance or high energy efficiency in computing with computing and communication specialization in a particular study. Reconfigurable computing platforms allow us to tailor our design to perform better in terms of performance and area. In this project, our main objective is to develop a cache design that supports many ports to get more acceleration in the hardware by keeping execution stages all busy. Even if we have accelerated computing with specialized accelerators, memory access, especially to off-chip memory access, is the bottleneck in many application fields, e.g., memory-intensive applications such as neural networks, matrix operations, and graph processing. Memory hierarchy with different cache levels is the solution to the memory access problem, and it will reduce the overall memory access latency of the application. Since reconfigurable platforms perform better performance, in this project, we propose high-level multi-ported cache designs and introduce a novel and efficient approach to improve the memory access in FPGA. Various methods have been used in multi-port memory studies to improve memory access. In this study, BRAM-based multi-port cache design is proposed based on the XOR method to increase read ports and write ports. So far we have observed 8x acceleration in the inline cache design. In addition, we achieved approximately 30 times acceleration in the multi-port memory design we designed.

Participants

• Fatma ÖZÜDOĞRU
  • Contact: ozudogrufatma26@gmail.com
• Seray ÖZCAN
  • Contact: serayyozcann@gmail.com

Supervisor

• Assist. Prof. Dr. İsmail San
  • Contact: isan@eskisehir.edu.tr

Platform and Tools

• Zedboard ZYNQ-7000
• Xilinx Vivado High-Level Synthesis 2017.4
• Xilinx Vivado Design Suit 2017.4
• Xilinx Software Development Kit 2017.4

Report

Project phases and more detail about project is shared in this repository as MPSCache_report_xohw21-248.pdf

Video Link

1. Youtube
2. Youtube

Our project has been motivated from Inline Cache Study and its open source project files

• Inline cache proposed by Ma et al, and you can find at
• Github

Multi-Ported Memory study has been examined to design multi-port system, and its open source Github repo

• Github

Step-by-step Building and Testing Instructions

Running the multiport memory design Creating IP with HLS:

The following detailed steps are required to build and test our project with HLS.

1. Open Vivado HLS 2017.4
2. Create New Project
3. Name of the top function should be "multiport" for xor-based multi-port memory.
4. Click C synthesis.
5. When synthesis is finished, click Export RTL. Creating SoC Design with All Components:
6. Open Vivado 2017.4
7. Create project
8. Choose ZedBoard Development Kit as destination board
9. Create block design
10. Add ip --> zynq processing system
11. Add ip --> Axi_timer
12. Add source --> Axi_smartconnect and Axi_interconnect
13. Click Window --> Add ip catalog --> click right click on list --> select your the path of the multiport IP you exported --> click OK
14. click right click on block design --> ip catalog --> select ip files which you created with HLS
15. Make neccessary connections as seen in VIVADO/Multi_port_memory/design1.pdf, make sure the connections are exactly the same with design1.pdf
16. Click Generate Bitstream
17. Right click on design file and click Create HDL Wrapper.
18. Right click on design and click Generate Output Products.
19. Click on Generate Bitstream.

When generate bitstream finished, export hardware (include bitstream should be marked) and launch SDK.

1. Create new Hello World application project in SDK.
2. Replace the contents of the Hello world project with SDK/Multi_port_memory/main.c
3. Ready to run.

Experimental Results

1. Inline Cache

2. Multi-port Memory