diff --git a/build.sbt b/build.sbt
index ce10149..66b4e71 100644
--- a/build.sbt
+++ b/build.sbt
@@ -16,7 +16,8 @@ lazy val publishSettings = Seq (
 
   // disable publish with scala version, otherwise artifact name will include scala version 
   // e.g cassper_2.11
-  crossPaths := false,
+  // MS: maybe we should enable this again
+  crossPaths := true,
 
   // add sonatype repository settings
   // snapshot versions publish to sonatype snapshot repository
@@ -45,6 +46,6 @@ lazy val root = (project in file("."))
       "-Xcheckinit",
     ),
     addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.5" cross CrossVersion.full),
-    addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
+    // addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full)
   )
   .settings(publishSettings: _*)
diff --git a/src/main/scala/chisel/lib/dclib/DCCredit.scala b/src/main/scala/chisel/lib/dclib/DCCredit.scala
index a5e10e4..b2ec1f3 100644
--- a/src/main/scala/chisel/lib/dclib/DCCredit.scala
+++ b/src/main/scala/chisel/lib/dclib/DCCredit.scala
@@ -33,8 +33,8 @@ class DCCreditSender[D <: Data](data: D, maxCredit: Int) extends Module {
     curCredit := curCredit - 1.U
   }
   io.enq.ready := curCredit > 0.U
-  val dataOut = RegEnable(next = io.enq.bits, enable = io.enq.fire)
-  val validOut = RegNext(next = io.enq.fire, init = false.B)
+  val dataOut = RegEnable(io.enq.bits, io.enq.fire)
+  val validOut = RegNext(io.enq.fire, false.B)
   io.deq.valid := validOut
   io.deq.bits := dataOut
   io.curCredit := curCredit
diff --git a/src/main/scala/chisel/lib/dclib/DCOutput.scala b/src/main/scala/chisel/lib/dclib/DCOutput.scala
index c00f597..87493f0 100644
--- a/src/main/scala/chisel/lib/dclib/DCOutput.scala
+++ b/src/main/scala/chisel/lib/dclib/DCOutput.scala
@@ -19,7 +19,7 @@ class DCOutput[D <: Data](data: D) extends Module {
 
   io.enq.ready := io.deq.ready || !rValid
   rValid := io.enq.fire || (rValid && !io.deq.ready)
-  io.deq.bits := RegEnable(next = io.enq.bits, enable = io.enq.fire)
+  io.deq.bits := RegEnable(io.enq.bits, io.enq.fire)
   io.deq.valid := rValid
 }