From a2ad73069f1ec6c89a99026bbea8317efbb294bd Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Fredrik=20S=C3=A6vland?= <Fredrik@saevland.com>
Date: Mon, 5 Aug 2024 11:38:14 +0200
Subject: [PATCH] Update README.md

---
 README.md | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 374ac1b..ad2773c 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,19 @@
 # Project-Fetchie
-My attempt  to make a superscalar RISC CPU
+Small 3-stage superscalar RV32I CPU. As of now this is nothing more than a personal pet project. I'm learning as I go, so things might not be right, convensional, clear or efficient to begin with.
+
+Progress (Checkmark means I have something working, not that it's done):
+* Registers ✅
+* I-Cache ✅
+* Fetch ✅
+* Decode
+* Execute
+* D-Cache
+* Microcode + Compiler
+
+Future extensions:
+* Two-level branch prediction
+* Debug interface
+* Instruction merging (e.g. LUI + ADDI)
+* RV32M instructions for multiplication and division
+* RV32C instructions for compressed instructions
+* RV32E variant of Fetchie for embedded applications