Move flags to variable

fsaev · Aug 10, 2024 · d8642c0 · d8642c0
1 parent 7271d32
commit d8642c0
Showing 1 changed file with 7 additions and 5 deletions.
diff --git a/Makefile b/Makefile
@@ -13,6 +13,8 @@ TARGET_VERILOG_FOLDER=./verilog
 TARGET_VERILOG_TB_FOLDER=./verilog_tb
 TARGET_VERILATOR_FOLDER=./verilator_testbench
 
+VERILATOR_FLAGS=-cc --exe -trace --build -j 12 -Wall
+
 ######################################
 # source
 ######################################
@@ -28,19 +30,19 @@ all: toptrace.vcd ice40_bin
 # This requires a newer version of Verilator than I have with my distro
 # Hence we have the `ifdef inside gpu.v
 top_verilator: $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/top.sv
-		$(VERILATOR) -cc --exe -trace --build -j 12 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module top $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/top.sv
+		$(VERILATOR) $(VERILATOR_FLAGS) -I"$(TARGET_VERILOG_FOLDER)" --top-module top $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/top.sv $(YOSYS_CELLS_SIM)
 
 queue_tb: $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/queue.sv
-		$(VERILATOR) -cc --exe -trace --build -j 12 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module queue_tb $(TARGET_VERILATOR_FOLDER)/queue_tb.cpp $(TARGET_VERILOG_FOLDER)/queue.sv $(TARGET_VERILOG_TB_FOLDER)/queue_tb.sv
+		$(VERILATOR) $(VERILATOR_FLAGS) -I"$(TARGET_VERILOG_FOLDER)" --top-module queue_tb $(TARGET_VERILATOR_FOLDER)/queue_tb.cpp $(TARGET_VERILOG_FOLDER)/queue.sv $(TARGET_VERILOG_TB_FOLDER)/queue_tb.sv
 
 registers_tb: $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/registers.sv
-		$(VERILATOR) -cc --exe -trace --build -j 12 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module registers_tb $(TARGET_VERILATOR_FOLDER)/registers_tb.cpp $(TARGET_VERILOG_FOLDER)/registers.sv $(TARGET_VERILOG_TB_FOLDER)/registers_tb.sv
+		$(VERILATOR) $(VERILATOR_FLAGS) -I"$(TARGET_VERILOG_FOLDER)" --top-module registers_tb $(TARGET_VERILATOR_FOLDER)/registers_tb.cpp $(TARGET_VERILOG_FOLDER)/registers.sv $(TARGET_VERILOG_TB_FOLDER)/registers_tb.sv
 
 fetch_tb: $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/fetch.sv
-		$(VERILATOR) -cc --exe -trace --build -j 12 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module fetch_tb $(TARGET_VERILATOR_FOLDER)/fetch_tb.cpp $(TARGET_VERILOG_FOLDER)/fetch.sv $(TARGET_VERILOG_TB_FOLDER)/fetch_tb.sv
+		$(VERILATOR) $(VERILATOR_FLAGS) -I"$(TARGET_VERILOG_FOLDER)" --top-module fetch_tb $(TARGET_VERILATOR_FOLDER)/fetch_tb.cpp $(TARGET_VERILOG_FOLDER)/fetch.sv $(TARGET_VERILOG_TB_FOLDER)/fetch_tb.sv
 
 decode_tb: $(CXX_SOURCES) $(TARGET_VERILOG_FOLDER)/decode.sv
-		$(VERILATOR) -cc --exe -trace --build -j 12 -Wall -I"$(TARGET_VERILOG_FOLDER)" --top-module decode_tb $(TARGET_VERILATOR_FOLDER)/decode_tb.cpp $(TARGET_VERILOG_FOLDER)/decode.sv $(TARGET_VERILOG_TB_FOLDER)/decode_tb.sv
+		$(VERILATOR) $(VERILATOR_FLAGS) -I"$(TARGET_VERILOG_FOLDER)" --top-module decode_tb $(TARGET_VERILATOR_FOLDER)/decode_tb.cpp $(TARGET_VERILOG_FOLDER)/decode.sv $(TARGET_VERILOG_TB_FOLDER)/decode_tb.sv
 
 toptrace.vcd: top_verilator obj_dir/Vtop
 	obj_dir/Vtop