diff --git a/packages/v/verilator/abi_used_symbols b/packages/v/verilator/abi_used_symbols
index fb018a039ed..f12352db6ef 100644
--- a/packages/v/verilator/abi_used_symbols
+++ b/packages/v/verilator/abi_used_symbols
@@ -6,8 +6,11 @@ libc.so.6:__duplocale
libc.so.6:__errno_location
libc.so.6:__fprintf_chk
libc.so.6:__freelocale
-libc.so.6:__isoc99_fscanf
-libc.so.6:__isoc99_sscanf
+libc.so.6:__isoc23_fscanf
+libc.so.6:__isoc23_sscanf
+libc.so.6:__isoc23_strtol
+libc.so.6:__isoc23_strtoll
+libc.so.6:__isoc23_strtoul
libc.so.6:__iswctype_l
libc.so.6:__libc_single_threaded
libc.so.6:__libc_start_main
@@ -111,6 +114,7 @@ libc.so.6:putwc
libc.so.6:read
libc.so.6:readdir
libc.so.6:realloc
+libc.so.6:secure_getenv
libc.so.6:setenv
libc.so.6:sprintf
libc.so.6:srand
@@ -127,13 +131,9 @@ libc.so.6:strerror
libc.so.6:strlen
libc.so.6:strncmp
libc.so.6:strncpy
-libc.so.6:strrchr
libc.so.6:strstr
libc.so.6:strtod
-libc.so.6:strtol
libc.so.6:strtold_l
-libc.so.6:strtoll
-libc.so.6:strtoul
libc.so.6:syscall
libc.so.6:system
libc.so.6:time
diff --git a/packages/v/verilator/package.yml b/packages/v/verilator/package.yml
index f42579e719c..f006592c4e6 100644
--- a/packages/v/verilator/package.yml
+++ b/packages/v/verilator/package.yml
@@ -1,8 +1,8 @@
name : verilator
-version : '5.016'
-release : 39
+version : '5.018'
+release : 40
source :
- - https://github.com/verilator/verilator/archive/refs/tags/v5.016.tar.gz : 66fc36f65033e5ec904481dd3d0df56500e90c0bfca23b2ae21b4a8d39e05ef1
+ - https://github.com/verilator/verilator/archive/refs/tags/v5.018.tar.gz : 8b544273eedee379e3c1a3bb849e14c754c9b5035d61ad03acdf3963092ba6c0
license :
- LGPL-3.0-only
- Artistic-2.0
diff --git a/packages/v/verilator/pspec_x86_64.xml b/packages/v/verilator/pspec_x86_64.xml
index 13ff358fa73..1ab44b644f7 100644
--- a/packages/v/verilator/pspec_x86_64.xml
+++ b/packages/v/verilator/pspec_x86_64.xml
@@ -3,8 +3,8 @@
verilator
https://www.veripool.org/wiki/verilator
- Silke Hofstra
- silke@slxh.eu
+ David Harder
+ david@davidjharder.ca
LGPL-3.0-only
Artistic-2.0
@@ -12,7 +12,7 @@
Verilator converts synthesizable (generally not behavioral) Verilog code into C++ or SystemC code.
Verilator converts synthesizable (generally not behavioral) Verilog code into C++ or SystemC code. It is not a complete simulator, just a translator.
- https://getsol.us/sources/README.Solus
+ https://sources.getsol.us/README.Solus
verilator
@@ -115,7 +115,6 @@
/usr/share/verilator/include/verilated_timing.cpp
/usr/share/verilator/include/verilated_timing.h
/usr/share/verilator/include/verilated_trace.h
- /usr/share/verilator/include/verilated_trace_defs.h
/usr/share/verilator/include/verilated_trace_imp.h
/usr/share/verilator/include/verilated_types.h
/usr/share/verilator/include/verilated_vcd_c.cpp
@@ -125,6 +124,7 @@
/usr/share/verilator/include/verilated_vpi.cpp
/usr/share/verilator/include/verilated_vpi.h
/usr/share/verilator/include/verilatedos.h
+ /usr/share/verilator/include/vltstd/sv_vpi_user.h
/usr/share/verilator/include/vltstd/svdpi.h
/usr/share/verilator/include/vltstd/vpi_user.h
/usr/share/verilator/verilator-config-version.cmake
@@ -138,19 +138,19 @@
programming.devel
- verilator
+ verilator
/usr/share/pkgconfig/verilator.pc
-
- 2023-09-20
- 5.016
+
+ 2023-11-11
+ 5.018
Packaging update
- Silke Hofstra
- silke@slxh.eu
+ David Harder
+ david@davidjharder.ca
\ No newline at end of file