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error.log
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rm -rf ./obj_dir/ blinky_tb blinky.vcd blinky/ blinky.bin blinky.rpt
rm -rf blinky.json ulx3s_out.config ulx3s.bit
yosys blinky.ys
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)
-- Executing script file `blinky.ys' --
1. Executing Verilog-2005 frontend.
Parsing Verilog input from `blinky.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing SYNTH_ECP5 pass.
2.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:411) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:412) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:413) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:414) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_SLICE'.
Generating RTLIL representation for module `\DP16KD'.
Successfully finished Verilog frontend.
2.2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Successfully finished Verilog frontend.
2.3. Executing HIERARCHY pass (managing design hierarchy).
2.3.1. Finding top of design hierarchy..
root of 0 design levels: top
Automatically selected top as design top module.
2.3.2. Analyzing design hierarchy..
Top module: \top
2.3.3. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
2.4. Executing PROC pass (convert processes to netlists).
2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.4.3. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$blinky.v:24$3'.
Set init value: \ctr = 0
2.4.4. Executing PROC_ARST pass (detect async resets in processes).
2.4.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$blinky.v:24$3'.
1/1: $1\ctr[31:0]
Creating decoders for process `\top.$proc$blinky.v:26$1'.
1/4: $0\o_led[7:0] [5:0]
2/4: $0\o_led[7:0] [6]
3/4: $0\o_led[7:0] [7]
4/4: $0\ctr[31:0]
2.4.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.4.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\o_led' using process `\top.$proc$blinky.v:26$1'.
created $dff cell `$procdff$102' with positive edge clock.
Creating register for signal `\top.\ctr' using process `\top.$proc$blinky.v:26$1'.
created $dff cell `$procdff$103' with positive edge clock.
2.4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$blinky.v:24$3'.
Removing empty process `top.$proc$blinky.v:26$1'.
Cleaned up 0 empty switches.
2.5. Executing FLATTEN pass (flatten design).
No more expansions possible.
2.6. Executing TRIBUF pass.
2.7. Executing DEMINOUT pass (demote inout ports to input or output).
2.8. Executing SYNTH pass.
2.8.1. Executing PROC pass (convert processes to netlists).
2.8.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.8.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.8.1.3. Executing PROC_INIT pass (extract init attributes).
2.8.1.4. Executing PROC_ARST pass (detect async resets in processes).
2.8.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
2.8.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).
2.8.1.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.8.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.8.2. Executing OPT_EXPR pass (perform const folding).
2.8.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
removed 3 unused temporary wires.
Removed 0 unused cells and 3 unused wires.
2.8.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
2.8.5. Executing OPT pass (performing simple optimizations).
2.8.5.1. Executing OPT_EXPR pass (perform const folding).
2.8.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.8.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.8.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.5.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.8.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.5.8. Executing OPT_EXPR pass (perform const folding).
2.8.5.9. Finished OPT passes. (There is nothing left to do.)
2.8.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell top.$add$blinky.v:27$2 ($add).
2.8.7. Executing TECHMAP pass (map to technology primitives).
2.8.7.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
No more expansions possible.
2.8.8. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
creating $macc model for $add$blinky.v:27$2 ($add).
creating $alu model for $macc $add$blinky.v:27$2.
creating $alu cell for $add$blinky.v:27$2: $auto$alumacc.cc:474:replace_alu$104
created 1 $alu and 0 $macc cells.
2.8.9. Executing SHARE pass (SAT-based resource sharing).
2.8.10. Executing OPT pass (performing simple optimizations).
2.8.10.1. Executing OPT_EXPR pass (perform const folding).
2.8.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.8.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.8.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.8.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.10.8. Executing OPT_EXPR pass (perform const folding).
2.8.10.9. Finished OPT passes. (There is nothing left to do.)
2.8.11. Executing FSM pass (extract and optimize FSM).
2.8.11.1. Executing FSM_DETECT pass (finding FSMs in design).
2.8.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
2.8.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
2.8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
2.8.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
2.8.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
2.8.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
2.8.12. Executing OPT pass (performing simple optimizations).
2.8.12.1. Executing OPT_EXPR pass (perform const folding).
2.8.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.8.12.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.8.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.12.5. Finished fast OPT passes.
2.8.13. Executing MEMORY pass.
2.8.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
2.8.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
2.8.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.8.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).
2.8.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.9. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
2.10. Executing TECHMAP pass (map to technology primitives).
2.10.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
Successfully finished Verilog frontend.
No more expansions possible.
2.11. Executing OPT pass (performing simple optimizations).
2.11.1. Executing OPT_EXPR pass (perform const folding).
2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.11.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.11.5. Finished fast OPT passes.
2.12. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
2.13. Executing OPT pass (performing simple optimizations).
2.13.1. Executing OPT_EXPR pass (perform const folding).
2.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
2.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
2.13.6. Executing OPT_RMDFF pass (remove dff with constant values).
2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
2.13.8. Executing OPT_EXPR pass (perform const folding).
2.13.9. Finished OPT passes. (There is nothing left to do.)
2.14. Executing TECHMAP pass (map to technology primitives).
2.14.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
2.14.2. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'.
Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 1
Parameter \B_WIDTH = 32
Parameter \Y_WIDTH = 32
Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32'.
2.14.3. Continuing TECHMAP pass.
Mapping top.$auto$alumacc.cc:474:replace_alu$104 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32.
Mapping top.$procdff$102 ($dff) with simplemap.
Mapping top.$procdff$103 ($dff) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$xor$<techmap.v>:262$155 ($xor) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$xor$<techmap.v>:263$156 ($xor) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154 ($and) with simplemap.
2.14.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_lcu'.
Parameter \WIDTH = 32
Generating RTLIL representation for module `$paramod\_90_lcu\WIDTH=32'.
2.14.5. Executing PROC pass (convert processes to netlists).
2.14.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
2.14.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
2.14.5.3. Executing PROC_INIT pass (extract init attributes).
2.14.5.4. Executing PROC_ARST pass (detect async resets in processes).
2.14.5.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
1/64: $0\p[31:0] [30]
2/64: $0\g[31:0] [30]
3/64: $0\p[31:0] [28]
4/64: $0\g[31:0] [28]
5/64: $0\p[31:0] [26]
6/64: $0\g[31:0] [26]
7/64: $0\p[31:0] [24]
8/64: $0\g[31:0] [24]
9/64: $0\p[31:0] [22]
10/64: $0\g[31:0] [22]
11/64: $0\p[31:0] [20]
12/64: $0\g[31:0] [20]
13/64: $0\p[31:0] [18]
14/64: $0\g[31:0] [18]
15/64: $0\p[31:0] [16]
16/64: $0\g[31:0] [16]
17/64: $0\p[31:0] [14]
18/64: $0\g[31:0] [14]
19/64: $0\p[31:0] [12]
20/64: $0\g[31:0] [12]
21/64: $0\p[31:0] [10]
22/64: $0\g[31:0] [10]
23/64: $0\p[31:0] [8]
24/64: $0\g[31:0] [8]
25/64: $0\p[31:0] [6]
26/64: $0\g[31:0] [6]
27/64: $0\p[31:0] [4]
28/64: $0\g[31:0] [4]
29/64: $0\p[31:0] [2]
30/64: $0\g[31:0] [2]
31/64: $0\p[31:0] [29]
32/64: $0\g[31:0] [29]
33/64: $0\p[31:0] [25]
34/64: $0\g[31:0] [25]
35/64: $0\p[31:0] [21]
36/64: $0\g[31:0] [21]
37/64: $0\p[31:0] [17]
38/64: $0\g[31:0] [17]
39/64: $0\p[31:0] [13]
40/64: $0\g[31:0] [13]
41/64: $0\p[31:0] [9]
42/64: $0\g[31:0] [9]
43/64: $0\p[31:0] [5]
44/64: $0\g[31:0] [5]
45/64: $0\p[31:0] [27]
46/64: $0\g[31:0] [27]
47/64: $0\p[31:0] [19]
48/64: $0\g[31:0] [19]
49/64: $0\p[31:0] [11]
50/64: $0\g[31:0] [11]
51/64: $0\p[31:0] [23]
52/64: $0\g[31:0] [23]
53/64: $0\p[31:0] [31]
54/64: $0\g[31:0] [31]
55/64: $0\p[31:0] [15]
56/64: $0\g[31:0] [15]
57/64: $0\p[31:0] [7]
58/64: $0\g[31:0] [7]
59/64: $0\p[31:0] [3]
60/64: $0\g[31:0] [3]
61/64: $0\p[31:0] [1]
62/64: $0\g[31:0] [1]
63/64: $0\g[31:0] [0]
64/64: $0\p[31:0] [0]
2.14.5.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod\_90_lcu\WIDTH=32.\p' from process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
No latch inferred for signal `$paramod\_90_lcu\WIDTH=32.\g' from process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
2.14.5.7. Executing PROC_DFF pass (convert process syncs to FFs).
2.14.5.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
Cleaned up 0 empty switches.
2.14.6. Executing OPT pass (performing simple optimizations).
2.14.6.1. Executing OPT_EXPR pass (perform const folding).
2.14.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\_90_lcu\WIDTH=32'.
Removed a total of 0 cells.
2.14.6.3. Executing OPT_RMDFF pass (remove dff with constant values).
2.14.6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\_90_lcu\WIDTH=32..
removing unused `$and' cell `$and$<techmap.v>:222$366'.
removing unused `$and' cell `$and$<techmap.v>:222$414'.
removing unused `$and' cell `$and$<techmap.v>:222$438'.
removing unused `$and' cell `$and$<techmap.v>:222$450'.
removing unused `$and' cell `$and$<techmap.v>:222$456'.
removing unused `$and' cell `$and$<techmap.v>:230$459'.
removing unused `$and' cell `$and$<techmap.v>:230$462'.
removing unused `$and' cell `$and$<techmap.v>:230$465'.
removing unused `$and' cell `$and$<techmap.v>:230$468'.
removing unused `$and' cell `$and$<techmap.v>:230$471'.
removing unused `$and' cell `$and$<techmap.v>:230$474'.
removing unused `$and' cell `$and$<techmap.v>:230$477'.
removing unused `$and' cell `$and$<techmap.v>:230$480'.
removing unused `$and' cell `$and$<techmap.v>:230$483'.
removing unused `$and' cell `$and$<techmap.v>:230$486'.
removing unused `$and' cell `$and$<techmap.v>:230$489'.
removing unused `$and' cell `$and$<techmap.v>:230$492'.
removing unused `$and' cell `$and$<techmap.v>:230$495'.
removing unused `$and' cell `$and$<techmap.v>:230$498'.
removing unused `$and' cell `$and$<techmap.v>:230$501'.
removing unused `$and' cell `$and$<techmap.v>:230$504'.
removing unused `$and' cell `$and$<techmap.v>:230$507'.
removing unused `$and' cell `$and$<techmap.v>:230$510'.
removing unused `$and' cell `$and$<techmap.v>:230$513'.
removing unused `$and' cell `$and$<techmap.v>:230$516'.
removing unused `$and' cell `$and$<techmap.v>:230$519'.
removing unused `$and' cell `$and$<techmap.v>:230$522'.
removing unused `$and' cell `$and$<techmap.v>:230$525'.
removing unused `$and' cell `$and$<techmap.v>:230$528'.
removing unused `$and' cell `$and$<techmap.v>:230$531'.
removing unused `$and' cell `$and$<techmap.v>:230$534'.
removing unused non-port wire \j.
removing unused non-port wire \i.
removed 67 unused temporary wires.
Removed 31 unused cells and 70 unused wires.
2.14.6.5. Finished fast OPT passes.
2.14.7. Continuing TECHMAP pass.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.lcu using $paramod\_90_lcu\WIDTH=32.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$ternary$<techmap.v>:258$153 ($mux) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$not$<techmap.v>:258$152 ($not) with simplemap.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.B_conv ($pos) with simplemap.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.A_conv ($pos) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:212$362 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$364 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$367 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$370 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$373 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$376 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$379 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$382 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$385 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$388 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$391 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$394 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$397 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$400 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$403 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$406 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$409 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$412 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$415 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$418 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$421 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$424 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$427 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$430 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$433 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$436 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$439 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$442 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$445 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$448 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$451 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$454 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$369 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$372 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$375 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$378 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$381 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$384 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$387 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$390 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$393 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$396 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$399 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$402 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$405 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$408 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$411 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$417 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$420 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$423 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$426 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$429 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$432 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$435 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$441 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$444 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$447 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$453 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$457 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$460 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$463 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$466 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$469 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$472 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$475 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$478 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$481 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$484 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$487 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$490 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$493 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$496 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$499 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$502 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$505 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$508 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$511 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$514 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$517 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$520 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$523 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$526 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$529 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$532 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:212$363 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$365 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$368 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$371 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$374 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$377 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$380 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$383 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$386 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$389 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$392 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$395 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$398 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$401 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$404 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$407 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$410 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$413 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$416 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$419 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$422 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$425 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$428 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$431 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$434 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$437 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$440 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$443 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$446 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$449 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$452 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$455 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$458 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$461 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$464 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$467 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$470 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$473 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$476 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$479 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$482 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$485 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$488 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$491 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$494 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$497 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$500 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$503 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$506 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$509 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$512 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$515 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$518 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$521 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$524 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$527 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$530 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$533 ($or) with simplemap.
No more expansions possible.
2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
2.16. Executing dff2dffs pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into DFFs in top.
2.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$189'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$190'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$191'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$192'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$193'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$194'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$195'.
removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$196'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$221'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$222'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$223'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$224'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$225'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$226'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$227'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$228'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$253'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$254'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$255'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$256'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$257'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$258'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$259'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$260'.
removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$261'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$285'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$286'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$287'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$288'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$289'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$290'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$291'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$292'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$293'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$559'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$560'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$561'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$562'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$563'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$564'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$565'.
removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$566'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$591'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$592'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$593'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$594'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$595'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$596'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$597'.
removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$598'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$611'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$612'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$613'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$614'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$615'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$621'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$622'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$623'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$626'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$627'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$629'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$630'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$641'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$642'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$643'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$644'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$645'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$650'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$651'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$652'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$654'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$655'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$656'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$657'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$660'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$666'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$667'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$679'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$680'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$681'.
removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$682'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$695'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$696'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$697'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$698'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$699'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$705'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$706'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$707'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$710'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$711'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$713'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$714'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$715'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$718'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$724'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$725'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$737'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$738'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$739'.
removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$740'.
removed 61 unused temporary wires.
Removed 132 unused cells and 131 unused wires.
2.18. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
$__DFFS_PP1_ -> $__DFFSE_PP1
$__DFFS_PP0_ -> $__DFFSE_PP0
$__DFFS_PN1_ -> $__DFFSE_PN1
$__DFFS_PN0_ -> $__DFFSE_PN0
$__DFFS_NP1_ -> $__DFFSE_NP1
$__DFFS_NP0_ -> $__DFFSE_NP0
$__DFFS_NN1_ -> $__DFFSE_NN1
$__DFFS_NN0_ -> $__DFFSE_NN0
$_DFF_PP1_ -> $__DFFE_PP1
$_DFF_PP0_ -> $__DFFE_PP0
$_DFF_PN1_ -> $__DFFE_PN1
$_DFF_PN0_ -> $__DFFE_PN0
$_DFF_NP1_ -> $__DFFE_NP1
$_DFF_NP0_ -> $__DFFE_NP0
$_DFF_NN1_ -> $__DFFE_NN1
$_DFF_NN0_ -> $__DFFE_NN0
$_DFF_N_ -> $_DFFE_NP_
$_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:
2.19. Executing TECHMAP pass (map to technology primitives).
2.19.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFS_NN0_'.
Generating RTLIL representation for module `\$__DFFS_NN1_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PN1_'.
Generating RTLIL representation for module `\$__DFFS_NP0_'.
Generating RTLIL representation for module `\$__DFFS_NP1_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$__DFFSE_NN0'.
Generating RTLIL representation for module `\$__DFFSE_NN1'.
Generating RTLIL representation for module `\$__DFFSE_PN0'.
Generating RTLIL representation for module `\$__DFFSE_PN1'.
Generating RTLIL representation for module `\$__DFFSE_NP0'.
Generating RTLIL representation for module `\$__DFFSE_NP1'.
Generating RTLIL representation for module `\$__DFFSE_PP0'.
Generating RTLIL representation for module `\$__DFFSE_PP1'.
Successfully finished Verilog frontend.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$183 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$157 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$184 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$158 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$185 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$159 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$186 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$160 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$187 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$161 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$188 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$162 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$163 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$164 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$165 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$166 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$167 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$168 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$169 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$170 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$171 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$172 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$173 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$174 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$175 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$176 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$177 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$178 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$179 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$180 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$181 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$182 using \$_DFF_P_.
No more expansions possible.
2.20. Executing OPT_EXPR pass (perform const folding).
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$535' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [0] = \ctr [0]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$536' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [1] = \ctr [1]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$198' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [1] = \ctr [1]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$537' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [2] = \ctr [2]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$199' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [2] = \ctr [2]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$538' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [3] = \ctr [3]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$200' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [3] = \ctr [3]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$539' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [4] = \ctr [4]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$201' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [4] = \ctr [4]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$540' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [5] = \ctr [5]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$202' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [5] = \ctr [5]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$541' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [6] = \ctr [6]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$203' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [6] = \ctr [6]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$542' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [7] = \ctr [7]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$204' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [7] = \ctr [7]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$543' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [8] = \ctr [8]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$205' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [8] = \ctr [8]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$544' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [9] = \ctr [9]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$206' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [9] = \ctr [9]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$545' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [10] = \ctr [10]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$207' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [10] = \ctr [10]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$546' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [11] = \ctr [11]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$208' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [11] = \ctr [11]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$547' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [12] = \ctr [12]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$209' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [12] = \ctr [12]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$548' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [13] = \ctr [13]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$210' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [13] = \ctr [13]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$549' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [14] = \ctr [14]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$211' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [14] = \ctr [14]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$550' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [15] = \ctr [15]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$212' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [15] = \ctr [15]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$551' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [16] = \ctr [16]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$213' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [16] = \ctr [16]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$552' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [17] = \ctr [17]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$214' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [17] = \ctr [17]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$553' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [18] = \ctr [18]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$215' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [18] = \ctr [18]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$554' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [19] = \ctr [19]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$216' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [19] = \ctr [19]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$555' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [20] = \ctr [20]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$217' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [20] = \ctr [20]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$556' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [21] = \ctr [21]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$218' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [21] = \ctr [21]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$557' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [22] = \ctr [22]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$219' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [22] = \ctr [22]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$558' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [23] = \ctr [23]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$220' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [23] = \ctr [23]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$229' (?0) in module `\top' with constant driver `$0\ctr[31:0] [0] = $auto$alumacc.cc:474:replace_alu$104.lcu.p [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$262' (and_or_buffer) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [0] = \ctr [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$599' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:212$362_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$683' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [0] = \ctr [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$263' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [1] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$684' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [1] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$364_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$264' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [2] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$726' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [2] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$490_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$265' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [3] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$601' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$367_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$685' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$368_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$700' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [3] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$412_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$266' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [4] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$727' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [4] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$493_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$267' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [5] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$602' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$370_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$686' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$371_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$719' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [5] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$469_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$268' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [6] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$728' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [6] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$496_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$617' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$415_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$269' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [7] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$603' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$373_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$687' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$374_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$701' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$416_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$708' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [7] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$436_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$270' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [8] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$729' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [8] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$499_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$271' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [9] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$604' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$376_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$688' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$377_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$720' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [9] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$472_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$272' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [10] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$730' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [10] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$502_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$618' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$418_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$273' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [11] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$605' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$379_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$689' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$380_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$702' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$419_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$716' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [11] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$460_Y'.