working.log

rm -rf ./obj_dir/ blinky_tb blinky.vcd blinky/ blinky.bin blinky.rpt
rm -rf blinky.json ulx3s_out.config ulx3s.bit
yosys blinky.ys 

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)


-- Executing script file `blinky.ys' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `blinky.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing SYNTH_ECP5 pass.

2.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:411) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:412) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:413) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `assert' (at /usr/local/bin/../share/yosys/ecp5/cells_sim.v:414) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_SLICE'.
Generating RTLIL representation for module `\DP16KD'.
Successfully finished Verilog frontend.

2.2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Successfully finished Verilog frontend.

2.3. Executing HIERARCHY pass (managing design hierarchy).

2.3.1. Finding top of design hierarchy..
root of   0 design levels: top                 
Automatically selected top as design top module.

2.3.2. Analyzing design hierarchy..
Top module:  \top

2.3.3. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.4. Executing PROC pass (convert processes to netlists).

2.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.4.3. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$blinky.v:24$3'.
  Set init value: \ctr = 0

2.4.4. Executing PROC_ARST pass (detect async resets in processes).

2.4.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$blinky.v:24$3'.
     1/1: $1\ctr[31:0]
Creating decoders for process `\top.$proc$blinky.v:26$1'.
     1/4: $0\o_led[7:0] [5:0]
     2/4: $0\o_led[7:0] [6]
     3/4: $0\o_led[7:0] [7]
     4/4: $0\ctr[31:0]

2.4.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.4.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\o_led' using process `\top.$proc$blinky.v:26$1'.
  created $dff cell `$procdff$102' with positive edge clock.
Creating register for signal `\top.\ctr' using process `\top.$proc$blinky.v:26$1'.
  created $dff cell `$procdff$103' with positive edge clock.

2.4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$blinky.v:24$3'.
Removing empty process `top.$proc$blinky.v:26$1'.
Cleaned up 0 empty switches.

2.5. Executing FLATTEN pass (flatten design).
No more expansions possible.

2.6. Executing TRIBUF pass.

2.7. Executing DEMINOUT pass (demote inout ports to input or output).

2.8. Executing SYNTH pass.

2.8.1. Executing PROC pass (convert processes to netlists).

2.8.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.8.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.8.1.3. Executing PROC_INIT pass (extract init attributes).

2.8.1.4. Executing PROC_ARST pass (detect async resets in processes).

2.8.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.8.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.8.1.7. Executing PROC_DFF pass (convert process syncs to FFs).

2.8.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.8.2. Executing OPT_EXPR pass (perform const folding).

2.8.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removed 3 unused temporary wires.
Removed 0 unused cells and 3 unused wires.

2.8.4. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.

2.8.5. Executing OPT pass (performing simple optimizations).

2.8.5.1. Executing OPT_EXPR pass (perform const folding).

2.8.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.8.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.8.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.8.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.8.5.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.8.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.5.8. Executing OPT_EXPR pass (perform const folding).

2.8.5.9. Finished OPT passes. (There is nothing left to do.)

2.8.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell top.$add$blinky.v:27$2 ($add).

2.8.7. Executing TECHMAP pass (map to technology primitives).

2.8.7.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
No more expansions possible.

2.8.8. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $add$blinky.v:27$2 ($add).
  creating $alu model for $macc $add$blinky.v:27$2.
  creating $alu cell for $add$blinky.v:27$2: $auto$alumacc.cc:474:replace_alu$104
  created 1 $alu and 0 $macc cells.

2.8.9. Executing SHARE pass (SAT-based resource sharing).

2.8.10. Executing OPT pass (performing simple optimizations).

2.8.10.1. Executing OPT_EXPR pass (perform const folding).

2.8.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.8.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.8.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.8.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.8.10.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.8.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.10.8. Executing OPT_EXPR pass (perform const folding).

2.8.10.9. Finished OPT passes. (There is nothing left to do.)

2.8.11. Executing FSM pass (extract and optimize FSM).

2.8.11.1. Executing FSM_DETECT pass (finding FSMs in design).

2.8.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.8.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.8.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.8.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.8.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.8.12. Executing OPT pass (performing simple optimizations).

2.8.12.1. Executing OPT_EXPR pass (perform const folding).

2.8.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.8.12.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.8.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.12.5. Finished fast OPT passes.

2.8.13. Executing MEMORY pass.

2.8.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

2.8.13.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.8.13.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.8.13.5. Executing MEMORY_COLLECT pass (generating $mem cells).

2.8.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.9. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.10. Executing TECHMAP pass (map to technology primitives).

2.10.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD'.
Successfully finished Verilog frontend.
No more expansions possible.

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.11.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.11.5. Finished fast OPT passes.

2.12. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

2.13. Executing OPT pass (performing simple optimizations).

2.13.1. Executing OPT_EXPR pass (perform const folding).

2.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

2.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

2.13.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.

2.13.8. Executing OPT_EXPR pass (perform const folding).

2.13.9. Finished OPT passes. (There is nothing left to do.)

2.14. Executing TECHMAP pass (map to technology primitives).

2.14.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.14.2. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_alu'.
Parameter \A_SIGNED = 0
Parameter \B_SIGNED = 0
Parameter \A_WIDTH = 1
Parameter \B_WIDTH = 32
Parameter \Y_WIDTH = 32
Generating RTLIL representation for module `$paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32'.

2.14.3. Continuing TECHMAP pass.
Mapping top.$auto$alumacc.cc:474:replace_alu$104 using $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=32\Y_WIDTH=32.
Mapping top.$procdff$102 ($dff) with simplemap.
Mapping top.$procdff$103 ($dff) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$xor$<techmap.v>:262$155 ($xor) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$xor$<techmap.v>:263$156 ($xor) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154 ($and) with simplemap.

2.14.4. Executing AST frontend in derive mode using pre-parsed AST for module `\_90_lcu'.
Parameter \WIDTH = 32
Generating RTLIL representation for module `$paramod\_90_lcu\WIDTH=32'.

2.14.5. Executing PROC pass (convert processes to netlists).

2.14.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.14.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.14.5.3. Executing PROC_INIT pass (extract init attributes).

2.14.5.4. Executing PROC_ARST pass (detect async resets in processes).

2.14.5.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
     1/64: $0\p[31:0] [30]
     2/64: $0\g[31:0] [30]
     3/64: $0\p[31:0] [28]
     4/64: $0\g[31:0] [28]
     5/64: $0\p[31:0] [26]
     6/64: $0\g[31:0] [26]
     7/64: $0\p[31:0] [24]
     8/64: $0\g[31:0] [24]
     9/64: $0\p[31:0] [22]
    10/64: $0\g[31:0] [22]
    11/64: $0\p[31:0] [20]
    12/64: $0\g[31:0] [20]
    13/64: $0\p[31:0] [18]
    14/64: $0\g[31:0] [18]
    15/64: $0\p[31:0] [16]
    16/64: $0\g[31:0] [16]
    17/64: $0\p[31:0] [14]
    18/64: $0\g[31:0] [14]
    19/64: $0\p[31:0] [12]
    20/64: $0\g[31:0] [12]
    21/64: $0\p[31:0] [10]
    22/64: $0\g[31:0] [10]
    23/64: $0\p[31:0] [8]
    24/64: $0\g[31:0] [8]
    25/64: $0\p[31:0] [6]
    26/64: $0\g[31:0] [6]
    27/64: $0\p[31:0] [4]
    28/64: $0\g[31:0] [4]
    29/64: $0\p[31:0] [2]
    30/64: $0\g[31:0] [2]
    31/64: $0\p[31:0] [29]
    32/64: $0\g[31:0] [29]
    33/64: $0\p[31:0] [25]
    34/64: $0\g[31:0] [25]
    35/64: $0\p[31:0] [21]
    36/64: $0\g[31:0] [21]
    37/64: $0\p[31:0] [17]
    38/64: $0\g[31:0] [17]
    39/64: $0\p[31:0] [13]
    40/64: $0\g[31:0] [13]
    41/64: $0\p[31:0] [9]
    42/64: $0\g[31:0] [9]
    43/64: $0\p[31:0] [5]
    44/64: $0\g[31:0] [5]
    45/64: $0\p[31:0] [27]
    46/64: $0\g[31:0] [27]
    47/64: $0\p[31:0] [19]
    48/64: $0\g[31:0] [19]
    49/64: $0\p[31:0] [11]
    50/64: $0\g[31:0] [11]
    51/64: $0\p[31:0] [23]
    52/64: $0\g[31:0] [23]
    53/64: $0\p[31:0] [31]
    54/64: $0\g[31:0] [31]
    55/64: $0\p[31:0] [15]
    56/64: $0\g[31:0] [15]
    57/64: $0\p[31:0] [7]
    58/64: $0\g[31:0] [7]
    59/64: $0\p[31:0] [3]
    60/64: $0\g[31:0] [3]
    61/64: $0\p[31:0] [1]
    62/64: $0\g[31:0] [1]
    63/64: $0\g[31:0] [0]
    64/64: $0\p[31:0] [0]

2.14.5.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod\_90_lcu\WIDTH=32.\p' from process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
No latch inferred for signal `$paramod\_90_lcu\WIDTH=32.\g' from process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.

2.14.5.7. Executing PROC_DFF pass (convert process syncs to FFs).

2.14.5.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod\_90_lcu\WIDTH=32.$proc$<techmap.v>:207$361'.
Cleaned up 0 empty switches.

2.14.6. Executing OPT pass (performing simple optimizations).

2.14.6.1. Executing OPT_EXPR pass (perform const folding).

2.14.6.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod\_90_lcu\WIDTH=32'.
Removed a total of 0 cells.

2.14.6.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.14.6.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod\_90_lcu\WIDTH=32..
  removing unused `$and' cell `$and$<techmap.v>:222$366'.
  removing unused `$and' cell `$and$<techmap.v>:222$414'.
  removing unused `$and' cell `$and$<techmap.v>:222$438'.
  removing unused `$and' cell `$and$<techmap.v>:222$450'.
  removing unused `$and' cell `$and$<techmap.v>:222$456'.
  removing unused `$and' cell `$and$<techmap.v>:230$459'.
  removing unused `$and' cell `$and$<techmap.v>:230$462'.
  removing unused `$and' cell `$and$<techmap.v>:230$465'.
  removing unused `$and' cell `$and$<techmap.v>:230$468'.
  removing unused `$and' cell `$and$<techmap.v>:230$471'.
  removing unused `$and' cell `$and$<techmap.v>:230$474'.
  removing unused `$and' cell `$and$<techmap.v>:230$477'.
  removing unused `$and' cell `$and$<techmap.v>:230$480'.
  removing unused `$and' cell `$and$<techmap.v>:230$483'.
  removing unused `$and' cell `$and$<techmap.v>:230$486'.
  removing unused `$and' cell `$and$<techmap.v>:230$489'.
  removing unused `$and' cell `$and$<techmap.v>:230$492'.
  removing unused `$and' cell `$and$<techmap.v>:230$495'.
  removing unused `$and' cell `$and$<techmap.v>:230$498'.
  removing unused `$and' cell `$and$<techmap.v>:230$501'.
  removing unused `$and' cell `$and$<techmap.v>:230$504'.
  removing unused `$and' cell `$and$<techmap.v>:230$507'.
  removing unused `$and' cell `$and$<techmap.v>:230$510'.
  removing unused `$and' cell `$and$<techmap.v>:230$513'.
  removing unused `$and' cell `$and$<techmap.v>:230$516'.
  removing unused `$and' cell `$and$<techmap.v>:230$519'.
  removing unused `$and' cell `$and$<techmap.v>:230$522'.
  removing unused `$and' cell `$and$<techmap.v>:230$525'.
  removing unused `$and' cell `$and$<techmap.v>:230$528'.
  removing unused `$and' cell `$and$<techmap.v>:230$531'.
  removing unused `$and' cell `$and$<techmap.v>:230$534'.
  removing unused non-port wire \j.
  removing unused non-port wire \i.
  removed 67 unused temporary wires.
Removed 31 unused cells and 70 unused wires.

2.14.6.5. Finished fast OPT passes.

2.14.7. Continuing TECHMAP pass.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.lcu using $paramod\_90_lcu\WIDTH=32.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$ternary$<techmap.v>:258$153 ($mux) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.$not$<techmap.v>:258$152 ($not) with simplemap.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.B_conv ($pos) with simplemap.
Mapping top.$auto$alumacc.cc:474:replace_alu$104.A_conv ($pos) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:212$362 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$364 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$367 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$370 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$373 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$376 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$379 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$382 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$385 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$388 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$391 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$394 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$397 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$400 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$403 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$406 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$409 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$412 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$415 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$418 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$421 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$424 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$427 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$430 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$433 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$436 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$439 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$442 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$445 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$448 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$451 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$454 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$369 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$372 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$375 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$378 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$381 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$384 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$387 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$390 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$393 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$396 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$399 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$402 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$405 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$408 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$411 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$417 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$420 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$423 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$426 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$429 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$432 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$435 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$441 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$444 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$447 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:222$453 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$457 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$460 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$463 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$466 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$469 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$472 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$475 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$478 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$481 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$484 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$487 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$490 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$493 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$496 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$499 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$502 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$505 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$508 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$511 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$514 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$517 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$520 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$523 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$526 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$529 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$532 ($and) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:212$363 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$365 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$368 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$371 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$374 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$377 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$380 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$383 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$386 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$389 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$392 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$395 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$398 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$401 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$404 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$407 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$410 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$413 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$416 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$419 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$422 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$425 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$428 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$431 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$434 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$437 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$440 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$443 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$446 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$449 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$452 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$455 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$458 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$461 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$464 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$467 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$470 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$473 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$476 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$479 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$482 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$485 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$488 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$491 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$494 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$497 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$500 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$503 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$506 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$509 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$512 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$515 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$518 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$521 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$524 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$527 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$530 ($or) with simplemap.
Mapping top.$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:229$533 ($or) with simplemap.
No more expansions possible.

2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).

2.16. Executing dff2dffs pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into DFFs in top.

2.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$189'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$190'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$191'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$192'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$193'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$194'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$195'.
  removing unused `$_DFF_P_' cell `$auto$simplemap.cc:420:simplemap_dff$196'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$221'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$222'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$223'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$224'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$225'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$226'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$227'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$228'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$253'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$254'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$255'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$256'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$257'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$258'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$259'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$260'.
  removing unused `$_XOR_' cell `$auto$simplemap.cc:85:simplemap_bitop$261'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$285'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$286'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$287'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$288'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$289'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$290'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$291'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$292'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$293'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$559'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$560'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$561'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$562'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$563'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$564'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$565'.
  removing unused `$_MUX_' cell `$auto$simplemap.cc:277:simplemap_mux$566'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$591'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$592'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$593'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$594'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$595'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$596'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$597'.
  removing unused `$_NOT_' cell `$auto$simplemap.cc:37:simplemap_not$598'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$611'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$612'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$613'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$614'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$615'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$621'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$622'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$623'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$626'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$627'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$629'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$630'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$641'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$642'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$643'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$644'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$645'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$650'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$651'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$652'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$654'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$655'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$656'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$657'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$660'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$666'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$667'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$679'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$680'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$681'.
  removing unused `$_AND_' cell `$auto$simplemap.cc:85:simplemap_bitop$682'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$695'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$696'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$697'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$698'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$699'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$705'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$706'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$707'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$710'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$711'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$713'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$714'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$715'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$718'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$724'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$725'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$737'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$738'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$739'.
  removing unused `$_OR_' cell `$auto$simplemap.cc:85:simplemap_bitop$740'.
  removed 61 unused temporary wires.
Removed 132 unused cells and 131 unused wires.

2.18. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $__DFFS_PP1_ -> $__DFFSE_PP1
  $__DFFS_PP0_ -> $__DFFSE_PP0
  $__DFFS_PN1_ -> $__DFFSE_PN1
  $__DFFS_PN0_ -> $__DFFSE_PN0
  $__DFFS_NP1_ -> $__DFFSE_NP1
  $__DFFS_NP0_ -> $__DFFSE_NP0
  $__DFFS_NN1_ -> $__DFFSE_NN1
  $__DFFS_NN0_ -> $__DFFSE_NN0
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:

2.19. Executing TECHMAP pass (map to technology primitives).

2.19.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFS_NN0_'.
Generating RTLIL representation for module `\$__DFFS_NN1_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PN1_'.
Generating RTLIL representation for module `\$__DFFS_NP0_'.
Generating RTLIL representation for module `\$__DFFS_NP1_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$__DFFSE_NN0'.
Generating RTLIL representation for module `\$__DFFSE_NN1'.
Generating RTLIL representation for module `\$__DFFSE_PN0'.
Generating RTLIL representation for module `\$__DFFSE_PN1'.
Generating RTLIL representation for module `\$__DFFSE_NP0'.
Generating RTLIL representation for module `\$__DFFSE_NP1'.
Generating RTLIL representation for module `\$__DFFSE_PP0'.
Generating RTLIL representation for module `\$__DFFSE_PP1'.
Successfully finished Verilog frontend.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$183 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$157 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$184 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$158 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$185 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$159 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$186 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$160 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$187 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$161 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$188 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$162 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$163 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$164 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$165 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$166 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$167 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$168 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$169 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$170 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$171 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$172 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$173 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$174 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$175 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$176 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$177 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$178 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$179 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$180 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$181 using \$_DFF_P_.
Mapping top.$auto$simplemap.cc:420:simplemap_dff$182 using \$_DFF_P_.
No more expansions possible.

2.20. Executing OPT_EXPR pass (perform const folding).
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$535' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [0] = \ctr [0]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$536' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [1] = \ctr [1]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$198' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [1] = \ctr [1]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$537' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [2] = \ctr [2]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$199' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [2] = \ctr [2]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$538' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [3] = \ctr [3]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$200' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [3] = \ctr [3]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$539' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [4] = \ctr [4]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$201' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [4] = \ctr [4]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$540' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [5] = \ctr [5]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$202' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [5] = \ctr [5]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$541' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [6] = \ctr [6]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$203' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [6] = \ctr [6]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$542' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [7] = \ctr [7]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$204' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [7] = \ctr [7]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$543' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [8] = \ctr [8]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$205' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [8] = \ctr [8]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$544' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [9] = \ctr [9]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$206' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [9] = \ctr [9]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$545' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [10] = \ctr [10]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$207' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [10] = \ctr [10]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$546' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [11] = \ctr [11]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$208' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [11] = \ctr [11]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$547' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [12] = \ctr [12]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$209' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [12] = \ctr [12]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$548' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [13] = \ctr [13]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$210' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [13] = \ctr [13]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$549' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [14] = \ctr [14]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$211' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [14] = \ctr [14]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$550' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [15] = \ctr [15]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$212' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [15] = \ctr [15]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$551' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [16] = \ctr [16]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$213' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [16] = \ctr [16]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$552' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [17] = \ctr [17]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$214' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [17] = \ctr [17]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$553' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [18] = \ctr [18]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$215' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [18] = \ctr [18]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$554' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [19] = \ctr [19]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$216' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [19] = \ctr [19]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$555' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [20] = \ctr [20]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$217' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [20] = \ctr [20]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$556' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [21] = \ctr [21]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$218' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [21] = \ctr [21]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$557' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [22] = \ctr [22]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$219' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [22] = \ctr [22]'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$558' (??0) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.BB [23] = \ctr [23]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$220' (0?) in module `\top' with constant driver `$auto$alumacc.cc:490:replace_alu$105 [23] = \ctr [23]'.
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$229' (?0) in module `\top' with constant driver `$0\ctr[31:0] [0] = $auto$alumacc.cc:474:replace_alu$104.lcu.p [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$262' (and_or_buffer) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [0] = \ctr [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$599' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:212$362_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$683' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [0] = \ctr [0]'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$263' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [1] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$684' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [1] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$364_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$264' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [2] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$726' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [2] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$490_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$265' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [3] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$601' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$367_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$685' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$368_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$700' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [3] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$412_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$266' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [4] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$727' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [4] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$493_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$267' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [5] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$602' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$370_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$686' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$371_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$719' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [5] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$469_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$268' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [6] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$728' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [6] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$496_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$617' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$415_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$269' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [7] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$603' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$373_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$687' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$374_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$701' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$416_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$708' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [7] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$436_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$270' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [8] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$729' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [8] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$499_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$271' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [9] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$604' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$376_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$688' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$377_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$720' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [9] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$472_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$272' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [10] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$730' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [10] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$502_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$618' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$418_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$273' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [11] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$605' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$379_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$689' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$380_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$702' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$419_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$716' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [11] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$460_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$274' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [12] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$731' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [12] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$505_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$275' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [13] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$606' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$382_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$690' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$383_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$721' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [13] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$475_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$276' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [14] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$732' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [14] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$508_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$625' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$439_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$619' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$421_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$277' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [15] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$607' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$385_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$691' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$386_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$703' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$422_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$709' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$440_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$712' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [15] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$448_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$278' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [16] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$733' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [16] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$511_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$279' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [17] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$608' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$388_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$692' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$389_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$722' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [17] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$478_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$280' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [18] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$734' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [18] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$514_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$620' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$424_Y = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$281' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [19] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$609' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$391_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$693' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$392_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$704' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$425_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$717' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [19] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$463_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$282' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [20] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$735' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [20] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$517_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$283' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [21] = 1'0'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$610' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:221$394_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$694' (00) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$or$<techmap.v>:221$395_Y = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$723' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [21] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$481_Y'.
Replacing $_AND_ cell `$auto$simplemap.cc:85:simplemap_bitop$284' (const_and) in module `\top' with constant driver `$techmap$auto$alumacc.cc:474:replace_alu$104.$and$<techmap.v>:260$154_Y [22] = 1'0'.
Replacing $_OR_ cell `$auto$simplemap.cc:85:simplemap_bitop$736' (and_or_buffer) in module `\top' with constant driver `$auto$alumacc.cc:474:replace_alu$104.lcu.g [22] = $techmap$auto$alumacc.cc:474:replace_alu$104.lcu.$and$<techmap.v>:229$520_Y'.

2.21. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.22. Executing TECHMAP pass (map to technology primitives).

2.22.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
No more expansions possible.

2.23. Executing ABC pass (technology mapping using ABC).

2.23.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 85 gates and 110 wires to a netlist network with 24 inputs and 24 outputs.

2.23.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + write_blif <abc-temp-dir>/output.blif 

2.23.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:       62
ABC RESULTS:        internal signals:       62
ABC RESULTS:           input signals:       24
ABC RESULTS:          output signals:       24
Removing temp directory.
Removed 0 unused cells and 218 unused wires.

2.24. Executing TECHMAP pass (map to technology primitives).

2.24.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFS_NN0_'.
Generating RTLIL representation for module `\$__DFFS_NN1_'.
Generating RTLIL representation for module `\$__DFFS_PN0_'.
Generating RTLIL representation for module `\$__DFFS_PN1_'.
Generating RTLIL representation for module `\$__DFFS_NP0_'.
Generating RTLIL representation for module `\$__DFFS_NP1_'.
Generating RTLIL representation for module `\$__DFFS_PP0_'.
Generating RTLIL representation for module `\$__DFFS_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$__DFFSE_NN0'.
Generating RTLIL representation for module `\$__DFFSE_NN1'.
Generating RTLIL representation for module `\$__DFFSE_PN0'.
Generating RTLIL representation for module `\$__DFFSE_PN1'.
Generating RTLIL representation for module `\$__DFFSE_NP0'.
Generating RTLIL representation for module `\$__DFFSE_NP1'.
Generating RTLIL representation for module `\$__DFFSE_PP0'.
Generating RTLIL representation for module `\$__DFFSE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

2.24.2. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'1000000000000000
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'1000000000000000'.

2.24.3. Continuing TECHMAP pass.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$799 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$798 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$797 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$796 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$795 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$794 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.

2.24.4. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 4
Parameter \LUT = 16'0111111110000000
Generating RTLIL representation for module `$paramod\$lut\WIDTH=4\LUT=16'0111111110000000'.

2.24.5. Continuing TECHMAP pass.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$793 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$801 using $paramod\$lut\WIDTH=4\LUT=16'1000000000000000.

2.24.6. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 2
Parameter \LUT = 4'0110
Generating RTLIL representation for module `$paramod\$lut\WIDTH=2\LUT=4'0110'.

2.24.7. Continuing TECHMAP pass.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$803 using $paramod\$lut\WIDTH=2\LUT=4'0110.

2.24.8. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 3
Parameter \LUT = 8'01111000
Generating RTLIL representation for module `$paramod\$lut\WIDTH=3\LUT=8'01111000'.

2.24.9. Continuing TECHMAP pass.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$804 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$805 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$808 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$810 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$812 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$816 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$818 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$822 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$800 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$802 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$806 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$813 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$819 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$807 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$809 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$814 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$820 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$815 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$821 using $paramod\$lut\WIDTH=3\LUT=8'01111000.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$811 using $paramod\$lut\WIDTH=2\LUT=4'0110.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$817 using $paramod\$lut\WIDTH=4\LUT=16'0111111110000000.

2.24.10. Executing AST frontend in derive mode using pre-parsed AST for module `\$lut'.
Parameter \WIDTH = 1
Parameter \LUT = 2'01
Generating RTLIL representation for module `$paramod\$lut\WIDTH=1\LUT=2'01'.

2.24.11. Continuing TECHMAP pass.
Mapping top.$abc$792$auto$blifparse.cc:492:parse_blif$823 using $paramod\$lut\WIDTH=1\LUT=2'01.
No more expansions possible.
Removed 0 unused cells and 62 unused wires.

2.25. Executing HIERARCHY pass (managing design hierarchy).

2.25.1. Analyzing design hierarchy..
Top module:  \top

2.25.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.

2.25.3. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Generating RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.4. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Generating RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.5. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.6. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.7. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.8. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.9. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.10. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Generating RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.11. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'1000000000000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'1000000000000000'.

2.25.12. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Generating RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.13. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.14. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.15. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.16. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.17. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.18. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.19. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.20. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.21. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.22. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.23. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.24. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.25. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.26. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.27. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.28. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 4'0110
Found cached RTLIL representation for module `$paramod\LUT4\INIT=4'0110'.

2.25.29. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.30. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 16'0111111110000000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=16'0111111110000000'.

2.25.31. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.32. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 8'01111000
Found cached RTLIL representation for module `$paramod\LUT4\INIT=8'01111000'.

2.25.33. Executing AST frontend in derive mode using pre-parsed AST for module `\LUT4'.
Parameter \INIT = 2'01
Generating RTLIL representation for module `$paramod\LUT4\INIT=2'01'.

2.25.34. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Generating RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.35. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.36. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.37. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.38. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.39. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.40. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.41. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.42. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.43. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.44. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.45. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.46. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.47. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.48. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.49. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.50. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.51. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.52. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.53. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.54. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.55. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.56. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.57. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.58. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.59. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.60. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.61. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.62. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.63. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.64. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.25.65. Executing AST frontend in derive mode using pre-parsed AST for module `\TRELLIS_FF'.
Parameter \GSR = 64'0100010001001001010100110100000101000010010011000100010101000100
Parameter \CEMUX = 8'00110001
Parameter \CLKMUX = 24'010000110100110001001011
Parameter \LSRMUX = 24'010011000101001101010010
Parameter \REGSET = 40'0101001001000101010100110100010101010100
Found cached RTLIL representation for module `$paramod$eb5f78d57eb6e7a9ce07d78f16121643b3067b1f\TRELLIS_FF'.

2.26. Printing statistics.

=== top ===

   Number of wires:                 15
   Number of wire bits:             97
   Number of public wires:           7
   Number of public wire bits:      58
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 63
     LUT4                           31
     TRELLIS_FF                     32

2.27. Executing CHECK pass (checking for obvious problems).
checking module top..
Warning: Wire top.ctr has an unprocessed 'init' attribute.
found and reported 1 problems.

2.28. Executing JSON backend.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: bf827bd3d8
CPU: user 0.55s system 0.47s, MEM: 217.89 MB total, 197.80 MB resident
Yosys 0.8+147 (git sha1 266511b2, clang 6.0.0-1ubuntu2 -fPIC -Os)
Time spent: 76% 11x read_verilog (0 sec), 6% 1x abc (0 sec), ...
nextpnr-ecp5 --25k --json blinky.json  \
	--lpf ulx3s_v20.lpf \
	--textcfg ulx3s_out.config 
Info: Importing module top
Info: Rule checker, verifying imported design
Info: Checksum: 0x77638610

Warning:     ignoring unsupported LPF command 'BLOCK RESETPATHS'
Warning:     ignoring unsupported LPF command 'BLOCK ASYNCPATHS'
Warning:     ignoring unsupported LPF command 'FREQUENCY PORT "clk_25mhz" 25 MHZ'
Warning:     ignoring unsupported LPF command 'SYSCONFIG CONFIG_IOVOLTAGE=3.3 COMPRESS_CONFIG=ON MCCLK_FREQ=62 MASTER_SPI_PORT=DISABLE SLAVE_SPI_PORT=DISABLE SLAVE_PARALLEL_PORT=DISABLE'
Warning: unmatched LPF 'LOCATE COMP' 'ftdi_rxd'
Warning: unmatched LPF 'LOCATE COMP' 'ftdi_txd'
Warning: unmatched LPF 'LOCATE COMP' 'ftdi_nrts'
Warning: unmatched LPF 'LOCATE COMP' 'ftdi_ndtr'
Warning: unmatched LPF 'LOCATE COMP' 'ftdi_txden'
Warning: unmatched LPF 'IOBUF PORT' 'ftdi_rxd'
Warning: unmatched LPF 'IOBUF PORT' 'ftdi_txd'
Warning: unmatched LPF 'IOBUF PORT' 'ftdi_nrts'
Warning: unmatched LPF 'IOBUF PORT' 'ftdi_ndtr'
Warning: unmatched LPF 'IOBUF PORT' 'ftdi_txden'
Warning: unmatched LPF 'LOCATE COMP' 'sw[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sw[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sw[2]'
Warning: unmatched LPF 'LOCATE COMP' 'sw[3]'
Warning: unmatched LPF 'IOBUF PORT' 'sw[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sw[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sw[2]'
Warning: unmatched LPF 'IOBUF PORT' 'sw[3]'
Warning: unmatched LPF 'LOCATE COMP' 'oled_clk'
Warning: unmatched LPF 'LOCATE COMP' 'oled_mosi'
Warning: unmatched LPF 'LOCATE COMP' 'oled_dc'
Warning: unmatched LPF 'LOCATE COMP' 'oled_resn'
Warning: unmatched LPF 'LOCATE COMP' 'oled_csn'
Warning: unmatched LPF 'IOBUF PORT' 'oled_clk'
Warning: unmatched LPF 'IOBUF PORT' 'oled_mosi'
Warning: unmatched LPF 'IOBUF PORT' 'oled_dc'
Warning: unmatched LPF 'IOBUF PORT' 'oled_resn'
Warning: unmatched LPF 'IOBUF PORT' 'oled_csn'
Warning: unmatched LPF 'LOCATE COMP' 'flash_csn'
Warning: unmatched LPF 'LOCATE COMP' 'flash_mosi'
Warning: unmatched LPF 'LOCATE COMP' 'flash_miso'
Warning: unmatched LPF 'LOCATE COMP' 'flash_holdn'
Warning: unmatched LPF 'LOCATE COMP' 'flash_wpn'
Warning: unmatched LPF 'IOBUF PORT' 'flash_csn'
Warning: unmatched LPF 'IOBUF PORT' 'flash_mosi'
Warning: unmatched LPF 'IOBUF PORT' 'flash_miso'
Warning: unmatched LPF 'IOBUF PORT' 'flash_holdn'
Warning: unmatched LPF 'IOBUF PORT' 'flash_wpn'
Warning: unmatched LPF 'LOCATE COMP' 'sd_clk'
Warning: unmatched LPF 'LOCATE COMP' 'sd_cmd'
Warning: unmatched LPF 'LOCATE COMP' 'sd_d[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sd_d[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sd_d[2]'
Warning: unmatched LPF 'LOCATE COMP' 'sd_d[3]'
Warning: unmatched LPF 'LOCATE COMP' 'sd_wp'
Warning: unmatched LPF 'LOCATE COMP' 'sd_cdn'
Warning: unmatched LPF 'IOBUF PORT' 'sd_clk'
Warning: unmatched LPF 'IOBUF PORT' 'sd_cmd'
Warning: unmatched LPF 'IOBUF PORT' 'sd_d[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sd_d[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sd_d[2]'
Warning: unmatched LPF 'IOBUF PORT' 'sd_d[3]'
Warning: unmatched LPF 'IOBUF PORT' 'sd_wp'
Warning: unmatched LPF 'IOBUF PORT' 'sd_cdn'
Warning: unmatched LPF 'LOCATE COMP' 'adc_csn'
Warning: unmatched LPF 'LOCATE COMP' 'adc_mosi'
Warning: unmatched LPF 'LOCATE COMP' 'adc_miso'
Warning: unmatched LPF 'LOCATE COMP' 'adc_sclk'
Warning: unmatched LPF 'IOBUF PORT' 'adc_csn'
Warning: unmatched LPF 'IOBUF PORT' 'adc_mosi'
Warning: unmatched LPF 'IOBUF PORT' 'adc_miso'
Warning: unmatched LPF 'IOBUF PORT' 'adc_sclk'
Warning: unmatched LPF 'LOCATE COMP' 'audio_l[3]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_l[2]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_l[1]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_l[0]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_r[3]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_r[2]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_r[1]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_r[0]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_v[3]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_v[2]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_v[1]'
Warning: unmatched LPF 'LOCATE COMP' 'audio_v[0]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_l[3]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_l[2]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_l[1]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_l[0]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_r[3]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_r[2]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_r[1]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_r[0]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_v[3]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_v[2]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_v[1]'
Warning: unmatched LPF 'IOBUF PORT' 'audio_v[0]'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_en'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_rxd'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_txd'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_gpio5'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_gpio16'
Warning: unmatched LPF 'LOCATE COMP' 'wifi_gpio17'
Warning: unmatched LPF 'IOBUF PORT' 'wifi_en'
Warning: unmatched LPF 'IOBUF PORT' 'wifi_rxd'
Warning: unmatched LPF 'IOBUF PORT' 'wifi_txd'
Warning: unmatched LPF 'IOBUF PORT' 'wifi_gpio16'
Warning: unmatched LPF 'IOBUF PORT' 'wifi_gpio17'
Warning: unmatched LPF 'LOCATE COMP' 'ant_433mhz'
Warning: unmatched LPF 'IOBUF PORT' 'ant_433mhz'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_dp'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_dn'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_dp'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_dn'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_bd_dp'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_bd_dn'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_bd_dp'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_bd_dn'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_pu_dp'
Warning: unmatched LPF 'LOCATE COMP' 'usb_fpga_pu_dn'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_pu_dp'
Warning: unmatched LPF 'IOBUF PORT' 'usb_fpga_pu_dn'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_clk'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_cke'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_csn'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_wen'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_rasn'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_casn'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[2]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[3]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[4]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[5]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[6]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[7]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[8]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[9]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[10]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[11]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_a[12]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_ba[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_ba[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_dqm[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_dqm[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[0]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[1]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[2]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[3]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[4]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[5]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[6]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[7]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[8]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[9]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[10]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[11]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[12]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[13]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[14]'
Warning: unmatched LPF 'LOCATE COMP' 'sdram_d[15]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_clk'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_cke'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_csn'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_wen'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_rasn'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_casn'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[2]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[3]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[4]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[5]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[6]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[7]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[8]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[9]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[10]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[11]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_a[12]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_ba[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_ba[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_dqm[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_dqm[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[0]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[1]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[2]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[3]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[4]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[5]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[6]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[7]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[8]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[9]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[10]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[11]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[12]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[13]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[14]'
Warning: unmatched LPF 'IOBUF PORT' 'sdram_d[15]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dp[0]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dn[0]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dp[1]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dn[1]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dp[2]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dn[2]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dp[3]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_dn[3]'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_ethp'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_ethn'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_cec'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_sda'
Warning: unmatched LPF 'LOCATE COMP' 'gpdi_scl'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dp[0]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dn[0]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dp[1]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dn[1]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dp[2]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dn[2]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dp[3]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_dn[3]'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_ethp'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_ethn'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_cec'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_sda'
Warning: unmatched LPF 'IOBUF PORT' 'gpdi_scl'
Warning: unmatched LPF 'LOCATE COMP' 'gp[0]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[0]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[1]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[1]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[2]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[2]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[3]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[3]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[4]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[4]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[5]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[5]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[6]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[6]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[0]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[0]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[1]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[1]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[2]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[2]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[3]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[3]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[4]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[4]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[5]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[5]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[6]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[6]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[7]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[7]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[8]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[8]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[9]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[9]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[10]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[10]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[11]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[11]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[12]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[12]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[13]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[13]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[7]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[7]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[8]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[8]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[9]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[9]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[10]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[10]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[11]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[11]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[12]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[12]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[13]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[13]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[14]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[14]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[15]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[15]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[16]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[16]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[17]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[17]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[18]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[18]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[19]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[19]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[20]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[20]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[14]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[14]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[15]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[15]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[16]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[16]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[17]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[17]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[18]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[18]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[19]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[19]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[20]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[20]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[21]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[21]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[22]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[22]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[23]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[23]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[24]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[24]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[25]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[25]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[26]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[26]'
Warning: unmatched LPF 'LOCATE COMP' 'gp[27]'
Warning: unmatched LPF 'LOCATE COMP' 'gn[27]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[21]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[21]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[22]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[22]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[23]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[23]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[24]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[24]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[25]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[25]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[26]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[26]'
Warning: unmatched LPF 'IOBUF PORT' 'gp[27]'
Warning: unmatched LPF 'IOBUF PORT' 'gn[27]'
Warning: unmatched LPF 'LOCATE COMP' 'user_programn'
Warning: unmatched LPF 'IOBUF PORT' 'user_programn'
Warning: unmatched LPF 'LOCATE COMP' 'shutdown'
Warning: unmatched LPF 'IOBUF PORT' 'shutdown'

Info: Packing IOs..
Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: pin 'clk_25mhz$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: pin 'btn[0]$tr_io' constrained to Bel 'X6/Y0/PIOB'.
Info: pin 'btn[1]$tr_io' constrained to Bel 'X4/Y50/PIOA'.
Info: pin 'btn[2]$tr_io' constrained to Bel 'X4/Y50/PIOB'.
Info: pin 'btn[3]$tr_io' constrained to Bel 'X72/Y44/PIOB'.
Info: pin 'btn[4]$tr_io' constrained to Bel 'X6/Y50/PIOB'.
Info: pin 'btn[5]$tr_io' constrained to Bel 'X6/Y50/PIOA'.
Info: pin 'btn[6]$tr_io' constrained to Bel 'X72/Y8/PIOD'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: Packing constants..
Info: Packing carries...
Info: Finding LUTFF pairs...
Info: Packing LUT5-7s...
Info: Finding LUT-LUT pairs...
Info: Packing paired LUTs into a SLICE...
Info: Packing unpaired LUTs into a SLICE...
Info: Packing unpaired FFs into a SLICE...
Info: Promoting globals...
Info:     promoting clock net clk_25mhz to global network
Info: Checksum: 0x7bbee851

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x268f4fbc

Info: Device utilisation:
Info: 	       TRELLIS_SLICE:    25/12144     0%
Info: 	          TRELLIS_IO:    17/  196     8%
Info: 	                DCCA:     1/   56     1%
Info: 	              DP16KD:     0/   56     0%
Info: 	          MULT18X18D:     0/   28     0%
Info: 	              ALU54B:     0/   14     0%
Info: 	             EHXPLLL:     0/    2     0%
Info: 	             EXTREFB:     0/    1     0%
Info: 	                DCUA:     0/    1     0%
Info: 	           PCSCLKDIV:     0/    2     0%
Info: 	             IOLOGIC:     0/  128     0%
Info: 	            SIOLOGIC:     0/   68     0%
Info: 	                 GSR:     0/    1     0%
Info: 	               JTAGG:     0/    1     0%
Info: 	                OSCG:     0/    1     0%
Info: 	               SEDGA:     0/    1     0%
Info: 	                 DTR:     0/    1     0%
Info: 	             USRMCLK:     0/    1     0%
Info: 	             CLKDIVF:     0/    4     0%
Info: 	           ECLKSYNCB:     0/    8     0%
Info: 	             DLLDELD:     0/    8     0%
Info: 	              DDRDLL:     0/    4     0%
Info: 	             DQSBUFM:     0/    8     0%

Info: Placed 17 cells based on constraints.
Info: Creating initial placement for remaining 25 cells.
Info:   initial placement placed 25/25 cells
Info: Initial placement time 0.04s
Info: Running simulated annealing placer.
Info:   at iteration #1: temp = 10000.000000, cost = 3846, est tns = -34.21ns
Info:   at iteration #5: temp = 10000.000000, cost = 2676, est tns = -16.57ns
Info:   at iteration #10: temp = 7000.000000, cost = 2901, est tns = -16.27ns
Info:   at iteration #15: temp = 1680.699951, cost = 4401, est tns = -57.11ns
Info:   at iteration #20: temp = 576.480103, cost = 2415, est tns = -8.77ns
Info:   at iteration #25: temp = 197.732681, cost = 2478, est tns = -9.88ns
Info:   at iteration #30: temp = 197.732681, cost = 1923, est tns = -2.07ns
Info:   at iteration #35: temp = 144.147125, cost = 1486, est tns = 0.00ns
Info:   at iteration #40: temp = 94.574921, cost = 2018, est tns = -0.13ns
Info:   at iteration #45: temp = 80.861557, cost = 1829, est tns = -3.25ns
Info:   at iteration #50: temp = 72.775398, cost = 1229, est tns = 0.00ns
Info:   at iteration #55: temp = 56.312214, cost = 1584, est tns = -3.62ns
Info:   at iteration #60: temp = 53.496605, cost = 1383, est tns = 0.00ns
Info:   at iteration #65: temp = 45.866650, cost = 1311, est tns = 0.00ns
Info:   at iteration #70: temp = 41.394653, cost = 1162, est tns = 0.00ns
Info:   at iteration #75: temp = 37.358673, cost = 1164, est tns = 0.00ns
Info:   at iteration #80: temp = 35.490738, cost = 1400, est tns = 0.00ns
Info:   at iteration #85: temp = 33.716202, cost = 1090, est tns = 0.00ns
Info:   at iteration #90: temp = 32.030392, cost = 1199, est tns = -0.74ns
Info:   at iteration #95: temp = 32.030392, cost = 1047, est tns = 0.00ns
Info:   at iteration #100: temp = 32.030392, cost = 1049, est tns = 0.00ns
Info:   at iteration #105: temp = 32.030392, cost = 1364, est tns = 0.00ns
Info:   at iteration #110: temp = 32.030392, cost = 1120, est tns = -2.53ns
Info:   at iteration #115: temp = 32.030392, cost = 1137, est tns = -1.81ns
Info:   at iteration #120: temp = 32.030392, cost = 909, est tns = 0.00ns
Info:   at iteration #125: temp = 32.030392, cost = 1165, est tns = 0.00ns
Info:   at iteration #130: temp = 30.428871, cost = 1096, est tns = 0.00ns
Info:   at iteration #135: temp = 30.428871, cost = 1117, est tns = 0.00ns
Info:   at iteration #140: temp = 28.907427, cost = 852, est tns = 0.00ns
Info:   at iteration #145: temp = 24.784506, cost = 946, est tns = 0.00ns
Info:   at iteration #150: temp = 22.368017, cost = 720, est tns = 0.00ns
Info:   at iteration #155: temp = 20.187136, cost = 791, est tns = 0.00ns
Info:   at iteration #160: temp = 19.177778, cost = 734, est tns = 0.00ns
Info:   at iteration #165: temp = 17.307945, cost = 750, est tns = 0.00ns
Info:   at iteration #170: temp = 16.442549, cost = 748, est tns = 0.00ns
Info:   at iteration #175: temp = 14.839400, cost = 700, est tns = 0.00ns
Info:   at iteration #180: temp = 13.392559, cost = 663, est tns = 0.00ns
Info:   at iteration #185: temp = 11.482445, cost = 656, est tns = 0.00ns
Info:   at iteration #190: temp = 10.908322, cost = 629, est tns = 0.00ns
Info:   at iteration #195: temp = 10.362906, cost = 509, est tns = 0.00ns
Info:   at iteration #200: temp = 9.844761, cost = 454, est tns = 0.00ns
Info:   at iteration #205: temp = 9.352523, cost = 533, est tns = 0.00ns
Info:   at iteration #210: temp = 8.440652, cost = 533, est tns = 0.00ns
Info:   at iteration #215: temp = 7.617689, cost = 376, est tns = 0.00ns
Info:   at iteration #220: temp = 6.874964, cost = 370, est tns = 0.00ns
Info:   at iteration #225: temp = 6.204655, cost = 331, est tns = 0.00ns
Info:   at iteration #230: temp = 5.894422, cost = 286, est tns = 0.00ns
Info:   at iteration #235: temp = 4.801044, cost = 255, est tns = 0.00ns
Info:   at iteration #240: temp = 4.801044, cost = 265, est tns = 0.00ns
Info:   at iteration #245: temp = 4.560991, cost = 322, est tns = 0.00ns
Info:   at iteration #250: temp = 3.714956, cost = 295, est tns = 0.00ns
Info:   at iteration #255: temp = 3.529208, cost = 181, est tns = 0.00ns
Info:   at iteration #260: temp = 3.185110, cost = 241, est tns = 0.00ns
Info:   at iteration #265: temp = 2.874562, cost = 225, est tns = 0.00ns
Info:   at iteration #270: temp = 2.341349, cost = 211, est tns = 0.00ns
Info:   at iteration #275: temp = 2.113067, cost = 178, est tns = 0.00ns
Info:   at iteration #280: temp = 1.811691, cost = 170, est tns = 0.00ns
Info:   at iteration #285: temp = 1.721107, cost = 147, est tns = 0.00ns
Info:   at iteration #290: temp = 1.553299, cost = 156, est tns = 0.00ns
Info:   at iteration #295: temp = 1.201913, cost = 165, est tns = 0.00ns
Info:   at iteration #300: temp = 1.141817, cost = 134, est tns = 0.00ns
Info: Legalising relative constraints...
Info:     moved 0 cells, 0 unplaced (after legalising chains)
Info:   at iteration #305: temp = 0.659514, cost = 140, est tns = 0.00ns
Info:   at iteration #310: temp = 0.527611, cost = 122, est tns = 0.00ns
Info:   at iteration #315: temp = 0.422089, cost = 121, est tns = 0.00ns
Info:   at iteration #320: temp = 0.270137, cost = 117, est tns = 0.00ns
Info:   at iteration #325: temp = 0.088518, cost = 116, est tns = 0.00ns
Info:   at iteration #330: temp = 0.029006, cost = 116, est tns = 0.00ns
Info:   at iteration #335: temp = 0.009505, cost = 116, est tns = 0.00ns
Info:   at iteration #340: temp = 0.003114, cost = 116, est tns = 0.00ns
Info:   at iteration #345: temp = 0.001021, cost = 116, est tns = 0.00ns
Info:   at iteration #346: temp = 0.000816, cost = 116.000000
Info: SA placement time 0.30s

Info: Max frequency for clock '$glbnet$clk_25mhz': 188.93 MHz (PASS at 12.00 MHz)

Info: Max delay posedge $glbnet$clk_25mhz -> <async>: 6.53 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 76808,  77097) |* 
Info: [ 77097,  77386) | 
Info: [ 77386,  77675) | 
Info: [ 77675,  77964) | 
Info: [ 77964,  78253) |** 
Info: [ 78253,  78542) |** 
Info: [ 78542,  78831) | 
Info: [ 78831,  79120) |* 
Info: [ 79120,  79409) |** 
Info: [ 79409,  79698) | 
Info: [ 79698,  79987) | 
Info: [ 79987,  80276) |* 
Info: [ 80276,  80565) |** 
Info: [ 80565,  80854) | 
Info: [ 80854,  81143) |* 
Info: [ 81143,  81432) |** 
Info: [ 81432,  81721) |** 
Info: [ 81721,  82010) |**** 
Info: [ 82010,  82299) |**** 
Info: [ 82299,  82588) |******** 
Info: Checksum: 0xc15a03b5
Info: Routing globals...
Info:     routing clock net $glbnet$clk_25mhz using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 139 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs
Info:        155 |       15        140 |   15   140 |         0
Info: Routing complete.
Info: Route time 0.34s
Info: Checksum: 0x6425f4f4

Info: Critical path report for clock '$glbnet$clk_25mhz' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source $abc$792$auto$blifparse.cc:492:parse_blif$803_SLICE.Q0
Info:  1.0  1.5    Net ctr[1] budget 8.992000 ns (13,18) -> (13,18)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$799_SLICE.A0
Info:  0.2  1.7  Source $abc$792$auto$blifparse.cc:492:parse_blif$799_SLICE.F0
Info:  1.0  2.8    Net $abc$792$n56_1 budget 8.991000 ns (13,18) -> (12,18)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$798_SLICE.A0
Info:  0.2  3.0  Source $abc$792$auto$blifparse.cc:492:parse_blif$798_SLICE.F0
Info:  0.9  3.9    Net $abc$792$n55 budget 8.991000 ns (12,18) -> (12,18)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$797_SLICE.A0
Info:  0.2  4.1  Source $abc$792$auto$blifparse.cc:492:parse_blif$797_SLICE.F0
Info:  1.1  5.2    Net $abc$792$n54_1 budget 8.991000 ns (12,18) -> (10,18)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$796_SLICE.A0
Info:  0.2  5.5  Source $abc$792$auto$blifparse.cc:492:parse_blif$796_SLICE.F0
Info:  1.1  6.6    Net $abc$792$n53 budget 8.991000 ns (10,18) -> (8,18)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$795_SLICE.A0
Info:  0.2  6.8  Source $abc$792$auto$blifparse.cc:492:parse_blif$795_SLICE.F0
Info:  1.4  8.2    Net $abc$792$n52 budget 8.991000 ns (8,18) -> (5,17)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$794_SLICE.A0
Info:  0.2  8.4  Source $abc$792$auto$blifparse.cc:492:parse_blif$794_SLICE.F0
Info:  1.1  9.5    Net $abc$792$n51 budget 8.991000 ns (5,17) -> (3,17)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$793_SLICE.A1
Info:  0.2  9.8  Source $abc$792$auto$blifparse.cc:492:parse_blif$793_SLICE.F1
Info:  1.0 10.8    Net $abc$792$n58_1 budget 8.991000 ns (3,17) -> (2,17)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$800_SLICE.A1
Info:  0.2 11.0  Source $abc$792$auto$blifparse.cc:492:parse_blif$800_SLICE.F1
Info:  0.1 11.2    Net $0\ctr[31:0][23] budget 8.991000 ns (2,17) -> (2,17)
Info:                Sink $abc$792$auto$blifparse.cc:492:parse_blif$800_SLICE.DI1
Info:  0.0 11.2  Setup $abc$792$auto$blifparse.cc:492:parse_blif$800_SLICE.DI1
Info: 2.4 ns logic, 8.8 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_25mhz' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source $auto$simplemap.cc:420:simplemap_dff$163_SLICE.Q0
Info:  2.1  2.6    Net led[6] budget 82.807999 ns (3,39) -> (0,17)
Info:                Sink led[6]$tr_io.I
Info: 0.5 ns logic, 2.1 ns routing

Info: Max frequency for clock '$glbnet$clk_25mhz': 89.55 MHz (PASS at 12.00 MHz)

Info: Max delay posedge $glbnet$clk_25mhz -> <async>: 2.59 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 72166,  72653) |** 
Info: [ 72653,  73140) | 
Info: [ 73140,  73627) |** 
Info: [ 73627,  74114) |* 
Info: [ 74114,  74601) | 
Info: [ 74601,  75088) |** 
Info: [ 75088,  75575) |* 
Info: [ 75575,  76062) | 
Info: [ 76062,  76549) |** 
Info: [ 76549,  77036) |* 
Info: [ 77036,  77523) | 
Info: [ 77523,  78010) |*** 
Info: [ 78010,  78497) | 
Info: [ 78497,  78984) | 
Info: [ 78984,  79471) |*** 
Info: [ 79471,  79958) | 
Info: [ 79958,  80445) |*** 
Info: [ 80445,  80932) |* 
Info: [ 80932,  81419) |*** 
Info: [ 81419,  81906) |******** 
335 warnings, 0 errors
ecppack ulx3s_out.config ulx3s.bit --idcode 0x21111043