qsim-arm64-regs.h

#ifndef __ARM64_REGS_H
#define __ARM64_REGS_H

#ifdef __cplusplus
extern "C" {
#endif

//> ARM64 register info from capstone
typedef enum qsim_arm64_reg {
	QSIM_ARM64_INVALID = 0,

	QSIM_ARM64_X29,
	QSIM_ARM64_X30,
	QSIM_ARM64_NZCV,
	QSIM_ARM64_SP,
	QSIM_ARM64_WSP,
	QSIM_ARM64_WZR,
	QSIM_ARM64_XZR,
	QSIM_ARM64_B0,
	QSIM_ARM64_B1,
	QSIM_ARM64_B2,
	QSIM_ARM64_B3,
	QSIM_ARM64_B4,
	QSIM_ARM64_B5,
	QSIM_ARM64_B6,
	QSIM_ARM64_B7,
	QSIM_ARM64_B8,
	QSIM_ARM64_B9,
	QSIM_ARM64_B10,
	QSIM_ARM64_B11,
	QSIM_ARM64_B12,
	QSIM_ARM64_B13,
	QSIM_ARM64_B14,
	QSIM_ARM64_B15,
	QSIM_ARM64_B16,
	QSIM_ARM64_B17,
	QSIM_ARM64_B18,
	QSIM_ARM64_B19,
	QSIM_ARM64_B20,
	QSIM_ARM64_B21,
	QSIM_ARM64_B22,
	QSIM_ARM64_B23,
	QSIM_ARM64_B24,
	QSIM_ARM64_B25,
	QSIM_ARM64_B26,
	QSIM_ARM64_B27,
	QSIM_ARM64_B28,
	QSIM_ARM64_B29,
	QSIM_ARM64_B30,
	QSIM_ARM64_B31,
	QSIM_ARM64_D0,
	QSIM_ARM64_D1,
	QSIM_ARM64_D2,
	QSIM_ARM64_D3,
	QSIM_ARM64_D4,
	QSIM_ARM64_D5,
	QSIM_ARM64_D6,
	QSIM_ARM64_D7,
	QSIM_ARM64_D8,
	QSIM_ARM64_D9,
	QSIM_ARM64_D10,
	QSIM_ARM64_D11,
	QSIM_ARM64_D12,
	QSIM_ARM64_D13,
	QSIM_ARM64_D14,
	QSIM_ARM64_D15,
	QSIM_ARM64_D16,
	QSIM_ARM64_D17,
	QSIM_ARM64_D18,
	QSIM_ARM64_D19,
	QSIM_ARM64_D20,
	QSIM_ARM64_D21,
	QSIM_ARM64_D22,
	QSIM_ARM64_D23,
	QSIM_ARM64_D24,
	QSIM_ARM64_D25,
	QSIM_ARM64_D26,
	QSIM_ARM64_D27,
	QSIM_ARM64_D28,
	QSIM_ARM64_D29,
	QSIM_ARM64_D30,
	QSIM_ARM64_D31,
	QSIM_ARM64_H0,
	QSIM_ARM64_H1,
	QSIM_ARM64_H2,
	QSIM_ARM64_H3,
	QSIM_ARM64_H4,
	QSIM_ARM64_H5,
	QSIM_ARM64_H6,
	QSIM_ARM64_H7,
	QSIM_ARM64_H8,
	QSIM_ARM64_H9,
	QSIM_ARM64_H10,
	QSIM_ARM64_H11,
	QSIM_ARM64_H12,
	QSIM_ARM64_H13,
	QSIM_ARM64_H14,
	QSIM_ARM64_H15,
	QSIM_ARM64_H16,
	QSIM_ARM64_H17,
	QSIM_ARM64_H18,
	QSIM_ARM64_H19,
	QSIM_ARM64_H20,
	QSIM_ARM64_H21,
	QSIM_ARM64_H22,
	QSIM_ARM64_H23,
	QSIM_ARM64_H24,
	QSIM_ARM64_H25,
	QSIM_ARM64_H26,
	QSIM_ARM64_H27,
	QSIM_ARM64_H28,
	QSIM_ARM64_H29,
	QSIM_ARM64_H30,
	QSIM_ARM64_H31,
	QSIM_ARM64_Q0,
	QSIM_ARM64_Q1,
	QSIM_ARM64_Q2,
	QSIM_ARM64_Q3,
	QSIM_ARM64_Q4,
	QSIM_ARM64_Q5,
	QSIM_ARM64_Q6,
	QSIM_ARM64_Q7,
	QSIM_ARM64_Q8,
	QSIM_ARM64_Q9,
	QSIM_ARM64_Q10,
	QSIM_ARM64_Q11,
	QSIM_ARM64_Q12,
	QSIM_ARM64_Q13,
	QSIM_ARM64_Q14,
	QSIM_ARM64_Q15,
	QSIM_ARM64_Q16,
	QSIM_ARM64_Q17,
	QSIM_ARM64_Q18,
	QSIM_ARM64_Q19,
	QSIM_ARM64_Q20,
	QSIM_ARM64_Q21,
	QSIM_ARM64_Q22,
	QSIM_ARM64_Q23,
	QSIM_ARM64_Q24,
	QSIM_ARM64_Q25,
	QSIM_ARM64_Q26,
	QSIM_ARM64_Q27,
	QSIM_ARM64_Q28,
	QSIM_ARM64_Q29,
	QSIM_ARM64_Q30,
	QSIM_ARM64_Q31,
	QSIM_ARM64_S0,
	QSIM_ARM64_S1,
	QSIM_ARM64_S2,
	QSIM_ARM64_S3,
	QSIM_ARM64_S4,
	QSIM_ARM64_S5,
	QSIM_ARM64_S6,
	QSIM_ARM64_S7,
	QSIM_ARM64_S8,
	QSIM_ARM64_S9,
	QSIM_ARM64_S10,
	QSIM_ARM64_S11,
	QSIM_ARM64_S12,
	QSIM_ARM64_S13,
	QSIM_ARM64_S14,
	QSIM_ARM64_S15,
	QSIM_ARM64_S16,
	QSIM_ARM64_S17,
	QSIM_ARM64_S18,
	QSIM_ARM64_S19,
	QSIM_ARM64_S20,
	QSIM_ARM64_S21,
	QSIM_ARM64_S22,
	QSIM_ARM64_S23,
	QSIM_ARM64_S24,
	QSIM_ARM64_S25,
	QSIM_ARM64_S26,
	QSIM_ARM64_S27,
	QSIM_ARM64_S28,
	QSIM_ARM64_S29,
	QSIM_ARM64_S30,
	QSIM_ARM64_S31,
	QSIM_ARM64_W0,
	QSIM_ARM64_W1,
	QSIM_ARM64_W2,
	QSIM_ARM64_W3,
	QSIM_ARM64_W4,
	QSIM_ARM64_W5,
	QSIM_ARM64_W6,
	QSIM_ARM64_W7,
	QSIM_ARM64_W8,
	QSIM_ARM64_W9,
	QSIM_ARM64_W10,
	QSIM_ARM64_W11,
	QSIM_ARM64_W12,
	QSIM_ARM64_W13,
	QSIM_ARM64_W14,
	QSIM_ARM64_W15,
	QSIM_ARM64_W16,
	QSIM_ARM64_W17,
	QSIM_ARM64_W18,
	QSIM_ARM64_W19,
	QSIM_ARM64_W20,
	QSIM_ARM64_W21,
	QSIM_ARM64_W22,
	QSIM_ARM64_W23,
	QSIM_ARM64_W24,
	QSIM_ARM64_W25,
	QSIM_ARM64_W26,
	QSIM_ARM64_W27,
	QSIM_ARM64_W28,
	QSIM_ARM64_W29,
	QSIM_ARM64_W30,
	QSIM_ARM64_X0,
	QSIM_ARM64_X1,
	QSIM_ARM64_X2,
	QSIM_ARM64_X3,
	QSIM_ARM64_X4,
	QSIM_ARM64_X5,
	QSIM_ARM64_X6,
	QSIM_ARM64_X7,
	QSIM_ARM64_X8,
	QSIM_ARM64_X9,
	QSIM_ARM64_X10,
	QSIM_ARM64_X11,
	QSIM_ARM64_X12,
	QSIM_ARM64_X13,
	QSIM_ARM64_X14,
	QSIM_ARM64_X15,
	QSIM_ARM64_X16,
	QSIM_ARM64_X17,
	QSIM_ARM64_X18,
	QSIM_ARM64_X19,
	QSIM_ARM64_X20,
	QSIM_ARM64_X21,
	QSIM_ARM64_X22,
	QSIM_ARM64_X23,
	QSIM_ARM64_X24,
	QSIM_ARM64_X25,
	QSIM_ARM64_X26,
	QSIM_ARM64_X27,
	QSIM_ARM64_X28,

	QSIM_ARM64_V0,
	QSIM_ARM64_V1,
	QSIM_ARM64_V2,
	QSIM_ARM64_V3,
	QSIM_ARM64_V4,
	QSIM_ARM64_V5,
	QSIM_ARM64_V6,
	QSIM_ARM64_V7,
	QSIM_ARM64_V8,
	QSIM_ARM64_V9,
	QSIM_ARM64_V10,
	QSIM_ARM64_V11,
	QSIM_ARM64_V12,
	QSIM_ARM64_V13,
	QSIM_ARM64_V14,
	QSIM_ARM64_V15,
	QSIM_ARM64_V16,
	QSIM_ARM64_V17,
	QSIM_ARM64_V18,
	QSIM_ARM64_V19,
	QSIM_ARM64_V20,
	QSIM_ARM64_V21,
	QSIM_ARM64_V22,
	QSIM_ARM64_V23,
	QSIM_ARM64_V24,
	QSIM_ARM64_V25,
	QSIM_ARM64_V26,
	QSIM_ARM64_V27,
	QSIM_ARM64_V28,
	QSIM_ARM64_V29,
	QSIM_ARM64_V30,
	QSIM_ARM64_V31,

	QSIM_ARM64_ENDING,		// <-- mark the end of the list of registers

	//> alias registers

	QSIM_ARM64_IP1 = QSIM_ARM64_X16,
	QSIM_ARM64_IP0 = QSIM_ARM64_X17,
	QSIM_ARM64_FP = QSIM_ARM64_X29,
	QSIM_ARM64_LR = QSIM_ARM64_X30,
} qsim_arm64_reg;

static const char *a64_regs_str[] __attribute__((unused)) = {
	"ARM64_REG_INVALID",

	"ARM64_REG_X29",
	"ARM64_REG_X30",
	"ARM64_REG_NZCV",
	"ARM64_REG_SP",
	"ARM64_REG_WSP",
	"ARM64_REG_WZR",
	"ARM64_REG_XZR",
	"ARM64_REG_B0",
	"ARM64_REG_B1",
	"ARM64_REG_B2",
	"ARM64_REG_B3",
	"ARM64_REG_B4",
	"ARM64_REG_B5",
	"ARM64_REG_B6",
	"ARM64_REG_B7",
	"ARM64_REG_B8",
	"ARM64_REG_B9",
	"ARM64_REG_B10",
	"ARM64_REG_B11",
	"ARM64_REG_B12",
	"ARM64_REG_B13",
	"ARM64_REG_B14",
	"ARM64_REG_B15",
	"ARM64_REG_B16",
	"ARM64_REG_B17",
	"ARM64_REG_B18",
	"ARM64_REG_B19",
	"ARM64_REG_B20",
	"ARM64_REG_B21",
	"ARM64_REG_B22",
	"ARM64_REG_B23",
	"ARM64_REG_B24",
	"ARM64_REG_B25",
	"ARM64_REG_B26",
	"ARM64_REG_B27",
	"ARM64_REG_B28",
	"ARM64_REG_B29",
	"ARM64_REG_B30",
	"ARM64_REG_B31",
	"ARM64_REG_D0",
	"ARM64_REG_D1",
	"ARM64_REG_D2",
	"ARM64_REG_D3",
	"ARM64_REG_D4",
	"ARM64_REG_D5",
	"ARM64_REG_D6",
	"ARM64_REG_D7",
	"ARM64_REG_D8",
	"ARM64_REG_D9",
	"ARM64_REG_D10",
	"ARM64_REG_D11",
	"ARM64_REG_D12",
	"ARM64_REG_D13",
	"ARM64_REG_D14",
	"ARM64_REG_D15",
	"ARM64_REG_D16",
	"ARM64_REG_D17",
	"ARM64_REG_D18",
	"ARM64_REG_D19",
	"ARM64_REG_D20",
	"ARM64_REG_D21",
	"ARM64_REG_D22",
	"ARM64_REG_D23",
	"ARM64_REG_D24",
	"ARM64_REG_D25",
	"ARM64_REG_D26",
	"ARM64_REG_D27",
	"ARM64_REG_D28",
	"ARM64_REG_D29",
	"ARM64_REG_D30",
	"ARM64_REG_D31",
	"ARM64_REG_H0",
	"ARM64_REG_H1",
	"ARM64_REG_H2",
	"ARM64_REG_H3",
	"ARM64_REG_H4",
	"ARM64_REG_H5",
	"ARM64_REG_H6",
	"ARM64_REG_H7",
	"ARM64_REG_H8",
	"ARM64_REG_H9",
	"ARM64_REG_H10",
	"ARM64_REG_H11",
	"ARM64_REG_H12",
	"ARM64_REG_H13",
	"ARM64_REG_H14",
	"ARM64_REG_H15",
	"ARM64_REG_H16",
	"ARM64_REG_H17",
	"ARM64_REG_H18",
	"ARM64_REG_H19",
	"ARM64_REG_H20",
	"ARM64_REG_H21",
	"ARM64_REG_H22",
	"ARM64_REG_H23",
	"ARM64_REG_H24",
	"ARM64_REG_H25",
	"ARM64_REG_H26",
	"ARM64_REG_H27",
	"ARM64_REG_H28",
	"ARM64_REG_H29",
	"ARM64_REG_H30",
	"ARM64_REG_H31",
	"ARM64_REG_Q0",
	"ARM64_REG_Q1",
	"ARM64_REG_Q2",
	"ARM64_REG_Q3",
	"ARM64_REG_Q4",
	"ARM64_REG_Q5",
	"ARM64_REG_Q6",
	"ARM64_REG_Q7",
	"ARM64_REG_Q8",
	"ARM64_REG_Q9",
	"ARM64_REG_Q10",
	"ARM64_REG_Q11",
	"ARM64_REG_Q12",
	"ARM64_REG_Q13",
	"ARM64_REG_Q14",
	"ARM64_REG_Q15",
	"ARM64_REG_Q16",
	"ARM64_REG_Q17",
	"ARM64_REG_Q18",
	"ARM64_REG_Q19",
	"ARM64_REG_Q20",
	"ARM64_REG_Q21",
	"ARM64_REG_Q22",
	"ARM64_REG_Q23",
	"ARM64_REG_Q24",
	"ARM64_REG_Q25",
	"ARM64_REG_Q26",
	"ARM64_REG_Q27",
	"ARM64_REG_Q28",
	"ARM64_REG_Q29",
	"ARM64_REG_Q30",
	"ARM64_REG_Q31",
	"ARM64_REG_S0",
	"ARM64_REG_S1",
	"ARM64_REG_S2",
	"ARM64_REG_S3",
	"ARM64_REG_S4",
	"ARM64_REG_S5",
	"ARM64_REG_S6",
	"ARM64_REG_S7",
	"ARM64_REG_S8",
	"ARM64_REG_S9",
	"ARM64_REG_S10",
	"ARM64_REG_S11",
	"ARM64_REG_S12",
	"ARM64_REG_S13",
	"ARM64_REG_S14",
	"ARM64_REG_S15",
	"ARM64_REG_S16",
	"ARM64_REG_S17",
	"ARM64_REG_S18",
	"ARM64_REG_S19",
	"ARM64_REG_S20",
	"ARM64_REG_S21",
	"ARM64_REG_S22",
	"ARM64_REG_S23",
	"ARM64_REG_S24",
	"ARM64_REG_S25",
	"ARM64_REG_S26",
	"ARM64_REG_S27",
	"ARM64_REG_S28",
	"ARM64_REG_S29",
	"ARM64_REG_S30",
	"ARM64_REG_S31",
	"ARM64_REG_W0",
	"ARM64_REG_W1",
	"ARM64_REG_W2",
	"ARM64_REG_W3",
	"ARM64_REG_W4",
	"ARM64_REG_W5",
	"ARM64_REG_W6",
	"ARM64_REG_W7",
	"ARM64_REG_W8",
	"ARM64_REG_W9",
	"ARM64_REG_W10",
	"ARM64_REG_W11",
	"ARM64_REG_W12",
	"ARM64_REG_W13",
	"ARM64_REG_W14",
	"ARM64_REG_W15",
	"ARM64_REG_W16",
	"ARM64_REG_W17",
	"ARM64_REG_W18",
	"ARM64_REG_W19",
	"ARM64_REG_W20",
	"ARM64_REG_W21",
	"ARM64_REG_W22",
	"ARM64_REG_W23",
	"ARM64_REG_W24",
	"ARM64_REG_W25",
	"ARM64_REG_W26",
	"ARM64_REG_W27",
	"ARM64_REG_W28",
	"ARM64_REG_W29",
	"ARM64_REG_W30",
	"ARM64_REG_X0",
	"ARM64_REG_X1",
	"ARM64_REG_X2",
	"ARM64_REG_X3",
	"ARM64_REG_X4",
	"ARM64_REG_X5",
	"ARM64_REG_X6",
	"ARM64_REG_X7",
	"ARM64_REG_X8",
	"ARM64_REG_X9",
	"ARM64_REG_X10",
	"ARM64_REG_X11",
	"ARM64_REG_X12",
	"ARM64_REG_X13",
	"ARM64_REG_X14",
	"ARM64_REG_X15",
	"ARM64_REG_X16",
	"ARM64_REG_X17",
	"ARM64_REG_X18",
	"ARM64_REG_X19",
	"ARM64_REG_X20",
	"ARM64_REG_X21",
	"ARM64_REG_X22",
	"ARM64_REG_X23",
	"ARM64_REG_X24",
	"ARM64_REG_X25",
	"ARM64_REG_X26",
	"ARM64_REG_X27",
	"ARM64_REG_X28",

	"ARM64_REG_V0",
	"ARM64_REG_V1",
	"ARM64_REG_V2",
	"ARM64_REG_V3",
	"ARM64_REG_V4",
	"ARM64_REG_V5",
	"ARM64_REG_V6",
	"ARM64_REG_V7",
	"ARM64_REG_V8",
	"ARM64_REG_V9",
	"ARM64_REG_V10",
	"ARM64_REG_V11",
	"ARM64_REG_V12",
	"ARM64_REG_V13",
	"ARM64_REG_V14",
	"ARM64_REG_V15",
	"ARM64_REG_V16",
	"ARM64_REG_V17",
	"ARM64_REG_V18",
	"ARM64_REG_V19",
	"ARM64_REG_V20",
	"ARM64_REG_V21",
	"ARM64_REG_V22",
	"ARM64_REG_V23",
	"ARM64_REG_V24",
	"ARM64_REG_V25",
	"ARM64_REG_V26",
	"ARM64_REG_V27",
	"ARM64_REG_V28",
	"ARM64_REG_V29",
	"ARM64_REG_V30",
	"ARM64_REG_V31",

	"ARM64_REG_ENDING"		// <-- mark the end of the list of registers
};

#ifdef __cplusplus
}
#endif

#endif