diff --git a/apps/app_blink_k20.rs b/apps/app_blink_k20.rs index 27da4ece..cd8d2864 100644 --- a/apps/app_blink_k20.rs +++ b/apps/app_blink_k20.rs @@ -5,7 +5,6 @@ extern crate core; extern crate zinc; -use core::option::Some; use zinc::hal::k20::{pin, watchdog}; use zinc::hal::pin::GPIO; use zinc::hal::cortex_m4::systick; @@ -34,7 +33,7 @@ pub unsafe fn main() { watchdog::init(watchdog::Disabled); // Pins for MC HCK (http://www.mchck.org/) - let led1 = pin::Pin::new(pin::PortB, 16, pin::GPIO, Some(zinc::hal::pin::Out)); + let led1 = pin::GpioPin::new(pin::PortB, 16, zinc::hal::pin::Out); systick::setup(systick::ten_ms().unwrap_or(480000)); systick::enable(); diff --git a/src/zinc/hal/isr.rs b/src/zinc/hal/isr.rs index 0817fe41..4e6fea8c 100644 --- a/src/zinc/hal/isr.rs +++ b/src/zinc/hal/isr.rs @@ -29,6 +29,6 @@ extern crate core; #[path="lpc17xx/isr.rs"] pub mod isr_lpc17xx; #[cfg(mcu_k20)] -#[path="k20/isr.rs"] pub mod isr_k20; +#[path="k20/isr/mod.rs"] pub mod isr_k20; #[path="../util/lang_items.rs"] mod lang_items; diff --git a/src/zinc/hal/k20/iomem.ld b/src/zinc/hal/k20/iomem.ld index c8950426..d69cb156 100644 --- a/src/zinc/hal/k20/iomem.ld +++ b/src/zinc/hal/k20/iomem.ld @@ -70,8 +70,10 @@ PROVIDE(isr_port_d = isr_default_fault); PROVIDE(isr_port_e = isr_default_fault); PROVIDE(isr_soft = isr_default_fault); -# This originated from the Freescale K20 Sub-Family Reference Manual -# Document number K20P48M50SF0RM, Rev. 2 +/* + * This originated from the Freescale K20 Sub-Family Reference Manual + * Document number K20P48M50SF0RM, Rev. 2 + */ k20_iomem_PERIPH0 = 0x40000000; diff --git a/src/zinc/hal/k20/iomem_50.ld b/src/zinc/hal/k20/iomem_50.ld new file mode 100644 index 00000000..5a10150b --- /dev/null +++ b/src/zinc/hal/k20/iomem_50.ld @@ -0,0 +1,134 @@ +INCLUDE ./src/zinc/hal/cortex_m3/armmem.ld + +PROVIDE(isr_dma_0 = isr_default_fault); +PROVIDE(isr_dma_1 = isr_default_fault); +PROVIDE(isr_dma_2 = isr_default_fault); +PROVIDE(isr_dma_3 = isr_default_fault); +PROVIDE(isr_dma_err = isr_default_fault); +PROVIDE(isr_flash_complete = isr_default_fault); +PROVIDE(isr_flash_collision = isr_default_fault); +PROVIDE(isr_low_volt = isr_default_fault); +PROVIDE(isr_llwu = isr_default_fault); +PROVIDE(isr_wdt = isr_default_fault); +PROVIDE(isr_i2c_0 = isr_default_fault); +PROVIDE(isr_spi_0 = isr_default_fault); +PROVIDE(isr_i2s_0 = isr_default_fault); +PROVIDE(isr_i2s_1 = isr_default_fault); +PROVIDE(isr_uart_0_lon = isr_default_fault); +PROVIDE(isr_uart_0_stat = isr_default_fault); +PROVIDE(isr_uart_0_err = isr_default_fault); +PROVIDE(isr_uart_1_stat = isr_default_fault); +PROVIDE(isr_uart_1_err = isr_default_fault); +PROVIDE(isr_uart_2_stat = isr_default_fault); +PROVIDE(isr_uart_2_err = isr_default_fault); +PROVIDE(isr_adc_0 = isr_default_fault); +PROVIDE(isr_cmp_0 = isr_default_fault); +PROVIDE(isr_cmp_1 = isr_default_fault); +PROVIDE(isr_ftm_0 = isr_default_fault); +PROVIDE(isr_ftm_1 = isr_default_fault); +PROVIDE(ist_cmt = isr_default_fault); +PROVIDE(isr_rtc_alarm = isr_default_fault); +PROVIDE(isr_rtc_tick = isr_default_fault); +PROVIDE(isr_pit_0 = isr_default_fault); +PROVIDE(isr_pit_1 = isr_default_fault); +PROVIDE(isr_pit_2 = isr_default_fault); +PROVIDE(isr_pit_3 = isr_default_fault); +PROVIDE(isr_pdb = isr_default_fault); +PROVIDE(isr_usb = isr_default_fault); +PROVIDE(isr_usb_dcd = isr_default_fault); +PROVIDE(isr_tsi = isr_default_fault); +PROVIDE(isr_mcg = isr_default_fault); +PROVIDE(isr_lptimer = isr_default_fault); +PROVIDE(isr_port_a = isr_default_fault); +PROVIDE(isr_port_b = isr_default_fault); +PROVIDE(isr_port_c = isr_default_fault); +PROVIDE(isr_port_d = isr_default_fault); +PROVIDE(isr_port_e = isr_default_fault); +PROVIDE(isr_soft = isr_default_fault); + +/* + * This originated from the Freescale K20 Sub-Family Reference Manual + * Document number K20P48M50SF0RM, Rev. 2 + */ + +k20_iomem_PERIPH0 = 0x40000000; + +k20_iomem_CROSSBAR = 0x40004000; + +k20_iomem_DMACON = 0x40008000; +k20_iomem_DMATCD = 0x40009000; + +k20_iomem_FLASHCON = 0x4001F000; +k20_iomem_FLASH = 0x40020000; +k20_iomem_DMAMUX0 = 0x40021000; + +k20_iomem_CAN0 = 0x40024000; + +k20_iomem_SPI0 = 0x4002C000; +k20_iomem_SPI1 = 0x4002D000; +k20_iomem_I2S0 = 0x4002F000; + +k20_iomem_CRC = 0x40032000; + +k20_iomem_USBDCD = 0x40035000; +k20_iomem_PDB = 0x40036000; +k20_iomem_PIT = 0x40037000; +k20_iomem_FTM0 = 0x40038000; +k20_iomem_FTM1 = 0x40039000; + +k20_iomem_ADC0 = 0x4003B000; + +k20_iomem_RTC = 0x4003D000; +k20_iomem_VBAT = 0x4003E000; + +k20_iomem_LPTMR = 0x40040000; +k20_iomem_SYSREG = 0x40041000; + +k20_iomem_TSI = 0x40045000; + +k20_iomem_SIM = 0x40047000; +k20_iomem_PORTA = 0x40049000; +k20_iomem_PORTB = 0x4004A000; +k20_iomem_PORTC = 0x4004B000; +k20_iomem_PORTD = 0x4004C000; +k20_iomem_PORTE = 0x4004D000; + +k20_iomem_WDINT = 0x40052000; + +k20_iomem_WDEXT = 0x40061000; +k20_iomem_CMT = 0x40062000; + +k20_iomem_MCG = 0x40064000; +k20_iomem_OSC = 0x40065000; +k20_iomem_I2C0 = 0x40066000; +k20_iomem_I2C1 = 0x40067000; + +k20_iomem_UART0 = 0x4006A000; +k20_iomem_UART1 = 0x4006B000; +k20_iomem_UART2 = 0x4006C000; + +k20_iomem_USB = 0x40072000; +k20_iomem_CMP = 0x40073000; +k20_iomem_VREF = 0x40074000; + +k20_iomem_LLWU = 0x4007C000; +k20_iomem_PMC = 0x4007D000; +k20_iomem_SMC = 0x4007E000; +k20_iomem_RCM = 0x4007F000; + + +k20_iomem_PERIPH1 = 0x40080000; + +k20_iomem_FTM2 = 0x400B8000; + +k20_iomem_ADC1 = 0x400BB000; + +k20_iomem_DAC0 = 0x400CC000; + +k20_iomem_GPIOA = 0x400ff000; +k20_iomem_GPIOB = 0x400ff040; +k20_iomem_GPIOC = 0x400ff080; +k20_iomem_GPIOD = 0x400ff0C0; +k20_iomem_GPIOE = 0x400ff100; + +k20_iomem_WDOG = 0x40052000; diff --git a/src/zinc/hal/k20/iomem_72.ld b/src/zinc/hal/k20/iomem_72.ld new file mode 100644 index 00000000..85edf218 --- /dev/null +++ b/src/zinc/hal/k20/iomem_72.ld @@ -0,0 +1,153 @@ +INCLUDE ./src/zinc/hal/cortex_m3/armmem.ld + +PROVIDE(isr_dma_0 = isr_default_fault); +PROVIDE(isr_dma_1 = isr_default_fault); +PROVIDE(isr_dma_2 = isr_default_fault); +PROVIDE(isr_dma_3 = isr_default_fault); +PROVIDE(isr_dma_4 = isr_default_fault); +PROVIDE(isr_dma_5 = isr_default_fault); +PROVIDE(isr_dma_6 = isr_default_fault); +PROVIDE(isr_dma_7 = isr_default_fault); +PROVIDE(isr_dma_8 = isr_default_fault); +PROVIDE(isr_dma_9 = isr_default_fault); +PROVIDE(isr_dma_10 = isr_default_fault); +PROVIDE(isr_dma_11 = isr_default_fault); +PROVIDE(isr_dma_12 = isr_default_fault); +PROVIDE(isr_dma_13 = isr_default_fault); +PROVIDE(isr_dma_14 = isr_default_fault); +PROVIDE(isr_dma_15 = isr_default_fault); +PROVIDE(isr_dma_err = isr_default_fault); +PROVIDE(isr_flash_complete = isr_default_fault); +PROVIDE(isr_flash_collision = isr_default_fault); +PROVIDE(isr_low_volt = isr_default_fault); +PROVIDE(isr_llwu = isr_default_fault); +PROVIDE(isr_wdt = isr_default_fault); +PROVIDE(isr_i2c_0 = isr_default_fault); +PROVIDE(isr_i2c_1 = isr_default_fault); +PROVIDE(isr_spi_0 = isr_default_fault); +PROVIDE(isr_spi_1 = isr_default_fault); +PROVIDE(isr_can_0_msg = isr_default_fault); +PROVIDE(isr_can_0_bus = isr_default_fault); +PROVIDE(isr_can_0_err = isr_default_fault); +PROVIDE(isr_can_0_tx = isr_default_fault); +PROVIDE(isr_can_0_rx = isr_default_fault); +PROVIDE(isr_can_0_wake = isr_default_fault); +PROVIDE(isr_i2s_0_tx = isr_default_fault); +PROVIDE(isr_i2s_0_rx = isr_default_fault); +PROVIDE(isr_uart_0_lon = isr_default_fault); +PROVIDE(isr_uart_0_stat = isr_default_fault); +PROVIDE(isr_uart_0_err = isr_default_fault); +PROVIDE(isr_uart_1_stat = isr_default_fault); +PROVIDE(isr_uart_1_err = isr_default_fault); +PROVIDE(isr_uart_2_stat = isr_default_fault); +PROVIDE(isr_uart_2_err = isr_default_fault); +PROVIDE(isr_adc_0 = isr_default_fault); +PROVIDE(isr_adc_1 = isr_default_fault); +PROVIDE(isr_cmp_0 = isr_default_fault); +PROVIDE(isr_cmp_1 = isr_default_fault); +PROVIDE(isr_cmp_2 = isr_default_fault); +PROVIDE(isr_ftm_0 = isr_default_fault); +PROVIDE(isr_ftm_1 = isr_default_fault); +PROVIDE(isr_ftm_2 = isr_default_fault); +PROVIDE(ist_cmt = isr_default_fault); +PROVIDE(isr_rtc_alarm = isr_default_fault); +PROVIDE(isr_rtc_tick = isr_default_fault); +PROVIDE(isr_pit_0 = isr_default_fault); +PROVIDE(isr_pit_1 = isr_default_fault); +PROVIDE(isr_pit_2 = isr_default_fault); +PROVIDE(isr_pit_3 = isr_default_fault); +PROVIDE(isr_pdb = isr_default_fault); +PROVIDE(isr_usb = isr_default_fault); +PROVIDE(isr_usb_dcd = isr_default_fault); +PROVIDE(isr_dac_0 = isr_default_fault); +PROVIDE(isr_tsi = isr_default_fault); +PROVIDE(isr_mcg = isr_default_fault); +PROVIDE(isr_lptimer = isr_default_fault); +PROVIDE(isr_port_a = isr_default_fault); +PROVIDE(isr_port_b = isr_default_fault); +PROVIDE(isr_port_c = isr_default_fault); +PROVIDE(isr_port_d = isr_default_fault); +PROVIDE(isr_port_e = isr_default_fault); +PROVIDE(isr_soft = isr_default_fault); + +k20_iomem_PERIPH0 = 0x40000000; + +k20_iomem_CROSSBAR = 0x40004000; + +k20_iomem_DMACON = 0x40008000; +k20_iomem_DMATCD = 0x40009000; + +k20_iomem_FLASHCON = 0x4001F000; +k20_iomem_FLASH = 0x40020000; +k20_iomem_DMAMUX0 = 0x40021000; + +k20_iomem_CAN0 = 0x40024000; + +k20_iomem_SPI0 = 0x4002C000; +k20_iomem_SPI1 = 0x4002D000; +k20_iomem_I2S0 = 0x4002F000; + +k20_iomem_CRC = 0x40032000; + +k20_iomem_USBDCD = 0x40035000; +k20_iomem_PDB = 0x40036000; +k20_iomem_PIT = 0x40037000; +k20_iomem_FTM0 = 0x40038000; +k20_iomem_FTM1 = 0x40039000; + +k20_iomem_ADC0 = 0x4003B000; + +k20_iomem_RTC = 0x4003D000; +k20_iomem_VBAT = 0x4003E000; + +k20_iomem_LPTMR = 0x40040000; +k20_iomem_SYSREG = 0x40041000; + +k20_iomem_TSI = 0x40045000; + +k20_iomem_SIM = 0x40047000; +k20_iomem_PORTA = 0x40049000; +k20_iomem_PORTB = 0x4004A000; +k20_iomem_PORTC = 0x4004B000; +k20_iomem_PORTD = 0x4004C000; +k20_iomem_PORTE = 0x4004D000; + +k20_iomem_WDINT = 0x40052000; + +k20_iomem_WDEXT = 0x40061000; +k20_iomem_CMT = 0x40062000; + +k20_iomem_MCG = 0x40064000; +k20_iomem_OSC = 0x40065000; +k20_iomem_I2C0 = 0x40066000; +k20_iomem_I2C1 = 0x40067000; + +k20_iomem_UART0 = 0x4006A000; +k20_iomem_UART1 = 0x4006B000; +k20_iomem_UART2 = 0x4006C000; + +k20_iomem_USB = 0x40072000; +k20_iomem_CMP = 0x40073000; +k20_iomem_VREF = 0x40074000; + +k20_iomem_LLWU = 0x4007C000; +k20_iomem_PMC = 0x4007D000; +k20_iomem_SMC = 0x4007E000; +k20_iomem_RCM = 0x4007F000; + + +k20_iomem_PERIPH1 = 0x40080000; + +k20_iomem_FTM2 = 0x400B8000; + +k20_iomem_ADC1 = 0x400BB000; + +k20_iomem_DAC0 = 0x400CC000; + +k20_iomem_GPIOA = 0x400ff000; +k20_iomem_GPIOB = 0x400ff040; +k20_iomem_GPIOC = 0x400ff080; +k20_iomem_GPIOD = 0x400ff0C0; +k20_iomem_GPIOE = 0x400ff100; + +k20_iomem_WDOG = 0x40052000; diff --git a/src/zinc/hal/k20/isr.rs b/src/zinc/hal/k20/isr/k20_50.rs similarity index 67% rename from src/zinc/hal/k20/isr.rs rename to src/zinc/hal/k20/isr/k20_50.rs index dc19d252..97af7ecb 100644 --- a/src/zinc/hal/k20/isr.rs +++ b/src/zinc/hal/k20/isr/k20_50.rs @@ -21,18 +21,6 @@ extern { fn isr_dma_1(); fn isr_dma_2(); fn isr_dma_3(); - fn isr_dma_4(); - fn isr_dma_5(); - fn isr_dma_6(); - fn isr_dma_7(); - fn isr_dma_8(); - fn isr_dma_9(); - fn isr_dma_10(); - fn isr_dma_11(); - fn isr_dma_12(); - fn isr_dma_13(); - fn isr_dma_14(); - fn isr_dma_15(); fn isr_dma_err(); fn isr_flash_complete(); fn isr_flash_collision(); @@ -40,17 +28,9 @@ extern { fn isr_llwu(); fn isr_wdt(); fn isr_i2c_0(); - fn isr_i2c_1(); fn isr_spi_0(); - fn isr_spi_1(); - fn isr_can_0_msg(); - fn isr_can_0_bus(); - fn isr_can_0_err(); - fn isr_can_0_tx(); - fn isr_can_0_rx(); - fn isr_can_0_wake(); - fn isr_i2s_0_tx(); - fn isr_i2s_0_rx(); + fn isr_i2s_0(); + fn isr_i2s_1(); fn isr_uart_0_lon(); fn isr_uart_0_stat(); fn isr_uart_0_err(); @@ -59,13 +39,10 @@ extern { fn isr_uart_2_stat(); fn isr_uart_2_err(); fn isr_adc_0(); - fn isr_adc_1(); fn isr_cmp_0(); fn isr_cmp_1(); - fn isr_cmp_2(); fn isr_ftm_0(); fn isr_ftm_1(); - fn isr_ftm_2(); fn ist_cmt(); fn isr_rtc_alarm(); fn isr_rtc_tick(); @@ -76,7 +53,6 @@ extern { fn isr_pdb(); fn isr_usb(); fn isr_usb_dcd(); - fn isr_dac_0(); fn isr_tsi(); fn isr_mcg(); fn isr_lptimer(); @@ -89,7 +65,7 @@ extern { } #[allow(non_upper_case_globals)] -const ISRCount: uint = 95; +const ISRCount: uint = 46; #[link_section=".isr_vector_nvic"] #[allow(non_upper_case_globals)] @@ -99,18 +75,6 @@ pub static NVICVectors: [Option, ..ISRCount] = [ Some(isr_dma_1), Some(isr_dma_2), Some(isr_dma_3), - Some(isr_dma_4), - Some(isr_dma_5), - Some(isr_dma_6), - Some(isr_dma_7), - Some(isr_dma_8), - Some(isr_dma_9), - Some(isr_dma_10), - Some(isr_dma_11), - Some(isr_dma_12), - Some(isr_dma_13), - Some(isr_dma_14), - Some(isr_dma_15), Some(isr_dma_err), None, Some(isr_flash_complete), @@ -118,27 +82,10 @@ pub static NVICVectors: [Option, ..ISRCount] = [ Some(isr_low_volt), Some(isr_llwu), Some(isr_wdt), - None, Some(isr_i2c_0), - Some(isr_i2c_1), Some(isr_spi_0), - Some(isr_spi_1), - None, - Some(isr_can_0_msg), - Some(isr_can_0_bus), - Some(isr_can_0_err), - Some(isr_can_0_tx), - Some(isr_can_0_rx), - Some(isr_can_0_wake), - Some(isr_i2s_0_tx), - Some(isr_i2s_0_rx), - None, - None, - None, - None, - None, - None, - None, + Some(isr_i2s_0), + Some(isr_i2s_1), Some(isr_uart_0_lon), Some(isr_uart_0_stat), Some(isr_uart_0_err), @@ -146,20 +93,11 @@ pub static NVICVectors: [Option, ..ISRCount] = [ Some(isr_uart_1_err), Some(isr_uart_2_stat), Some(isr_uart_2_err), - None, - None, - None, - None, - None, - None, Some(isr_adc_0), - Some(isr_adc_1), Some(isr_cmp_0), Some(isr_cmp_1), - Some(isr_cmp_2), Some(isr_ftm_0), Some(isr_ftm_1), - Some(isr_ftm_2), Some(ist_cmt), Some(isr_rtc_alarm), Some(isr_rtc_tick), @@ -170,24 +108,13 @@ pub static NVICVectors: [Option, ..ISRCount] = [ Some(isr_pdb), Some(isr_usb), Some(isr_usb_dcd), - None, - None, - None, - None, - None, - None, - Some(isr_dac_0), - None, Some(isr_tsi), Some(isr_mcg), Some(isr_lptimer), - None, Some(isr_port_a), Some(isr_port_b), Some(isr_port_c), Some(isr_port_d), Some(isr_port_e), - None, - None, Some(isr_soft), ]; diff --git a/src/zinc/hal/k20/isr/k20_72.rs b/src/zinc/hal/k20/isr/k20_72.rs new file mode 100644 index 00000000..97af7ecb --- /dev/null +++ b/src/zinc/hal/k20/isr/k20_72.rs @@ -0,0 +1,120 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2014 Ben Gamari +// Based upon work by Ben Harris +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +use core::option::{Option, Some, None}; + +extern { + fn isr_dma_0(); + fn isr_dma_1(); + fn isr_dma_2(); + fn isr_dma_3(); + fn isr_dma_err(); + fn isr_flash_complete(); + fn isr_flash_collision(); + fn isr_low_volt(); + fn isr_llwu(); + fn isr_wdt(); + fn isr_i2c_0(); + fn isr_spi_0(); + fn isr_i2s_0(); + fn isr_i2s_1(); + fn isr_uart_0_lon(); + fn isr_uart_0_stat(); + fn isr_uart_0_err(); + fn isr_uart_1_stat(); + fn isr_uart_1_err(); + fn isr_uart_2_stat(); + fn isr_uart_2_err(); + fn isr_adc_0(); + fn isr_cmp_0(); + fn isr_cmp_1(); + fn isr_ftm_0(); + fn isr_ftm_1(); + fn ist_cmt(); + fn isr_rtc_alarm(); + fn isr_rtc_tick(); + fn isr_pit_0(); + fn isr_pit_1(); + fn isr_pit_2(); + fn isr_pit_3(); + fn isr_pdb(); + fn isr_usb(); + fn isr_usb_dcd(); + fn isr_tsi(); + fn isr_mcg(); + fn isr_lptimer(); + fn isr_port_a(); + fn isr_port_b(); + fn isr_port_c(); + fn isr_port_d(); + fn isr_port_e(); + fn isr_soft(); +} + +#[allow(non_upper_case_globals)] +const ISRCount: uint = 46; + +#[link_section=".isr_vector_nvic"] +#[allow(non_upper_case_globals)] +#[no_mangle] +pub static NVICVectors: [Option, ..ISRCount] = [ + Some(isr_dma_0), + Some(isr_dma_1), + Some(isr_dma_2), + Some(isr_dma_3), + Some(isr_dma_err), + None, + Some(isr_flash_complete), + Some(isr_flash_collision), + Some(isr_low_volt), + Some(isr_llwu), + Some(isr_wdt), + Some(isr_i2c_0), + Some(isr_spi_0), + Some(isr_i2s_0), + Some(isr_i2s_1), + Some(isr_uart_0_lon), + Some(isr_uart_0_stat), + Some(isr_uart_0_err), + Some(isr_uart_1_stat), + Some(isr_uart_1_err), + Some(isr_uart_2_stat), + Some(isr_uart_2_err), + Some(isr_adc_0), + Some(isr_cmp_0), + Some(isr_cmp_1), + Some(isr_ftm_0), + Some(isr_ftm_1), + Some(ist_cmt), + Some(isr_rtc_alarm), + Some(isr_rtc_tick), + Some(isr_pit_0), + Some(isr_pit_1), + Some(isr_pit_2), + Some(isr_pit_3), + Some(isr_pdb), + Some(isr_usb), + Some(isr_usb_dcd), + Some(isr_tsi), + Some(isr_mcg), + Some(isr_lptimer), + Some(isr_port_a), + Some(isr_port_b), + Some(isr_port_c), + Some(isr_port_d), + Some(isr_port_e), + Some(isr_soft), +]; diff --git a/src/zinc/hal/k20/isr/mod.rs b/src/zinc/hal/k20/isr/mod.rs new file mode 100644 index 00000000..967a83c2 --- /dev/null +++ b/src/zinc/hal/k20/isr/mod.rs @@ -0,0 +1,20 @@ +// Zinc, the bare metal stack for rust. +// Copyright 2014 Ben Gamari +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#[cfg(k20_72)] pub use hal::k20::isr::k20_72::*; +#[cfg(k20_50)] pub use hal::k20::isr::k20_50::*; + +#[cfg(k20_72)] mod k20_72; +#[cfg(k20_50)] mod k20_50; diff --git a/src/zinc/hal/k20/pin.rs b/src/zinc/hal/k20/pin.rs index 9c3c6c9f..217013e1 100644 --- a/src/zinc/hal/k20/pin.rs +++ b/src/zinc/hal/k20/pin.rs @@ -20,11 +20,8 @@ Some pins that could be configured here may be missing from actual MCU depending on the package. */ -use core::option::Option; - use super::sim; - /// A pin. #[allow(missing_doc)] pub struct Pin { @@ -79,21 +76,20 @@ pub enum SlewRate { } impl Pin { - /// Create and setup a Pin. + /// Create and setup a Pin in open-drain mode. pub fn new(port: Port, pin_index: u8, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>) -> Pin { + pull: PullConf, open_drain: bool) -> Pin { let pin = Pin { port: port, pin: pin_index, }; - pin.setup_regs(function, gpiodir, PullNone, - DriveStrengthHigh, SlewSlow, false, false); + pin.setup_regs(function, pull, DriveStrengthHigh, SlewSlow, + false, open_drain); pin } fn setup_regs(&self, function: Function, - gpiodir: Option<::hal::pin::GPIODirection>, pull: PullConf, drive_strength: DriveStrength, slew_rate: SlewRate, filter: bool, open_drain: bool) { // enable port clock @@ -121,20 +117,6 @@ impl Pin { .set_ode(open_drain) .set_dse(dse) .set_mux(function as u32); - - if function == GPIO { - (self as &::hal::pin::GPIO).set_direction(gpiodir.unwrap()); - } - } - - fn gpioreg(&self) -> &'static reg::GPIO { - match self.port { - PortA => ®::GPIOA, - PortB => ®::GPIOB, - PortC => ®::GPIOC, - PortD => ®::GPIOD, - PortE => ®::GPIOE, - } } fn pcr(&self) -> &'static reg::PORT_pcr { @@ -149,21 +131,51 @@ impl Pin { } } -impl ::hal::pin::GPIO for Pin { +/// A pin configured as a GPIO +pub struct GpioPin { + pin: Pin +} + +impl GpioPin { + /// Configure a `Pin` as a GPIO pin. + pub fn from_pin(pin: Pin, gpiodir: ::hal::pin::GPIODirection) -> GpioPin { + let pin = GpioPin {pin: pin}; + (&pin as &::hal::pin::GPIO).set_direction(gpiodir); + pin + } + + /// Create and setup a GPIO Pin. + pub fn new(port: Port, pin_index: u8, + gpiodir: ::hal::pin::GPIODirection) -> GpioPin { + GpioPin::from_pin(Pin::new(port, pin_index, GPIO, PullNone, false), gpiodir) + } + + fn gpioreg(&self) -> &'static reg::GPIO { + match self.pin.port { + PortA => ®::GPIOA, + PortB => ®::GPIOB, + PortC => ®::GPIOC, + PortD => ®::GPIOD, + PortE => ®::GPIOE, + } + } +} + +impl ::hal::pin::GPIO for GpioPin { /// Sets output GPIO value to high. fn set_high(&self) { - self.gpioreg().psor.set_ptso(self.pin as uint, true); + self.gpioreg().psor.set_ptso(self.pin.pin as uint, true); } /// Sets output GPIO value to low. fn set_low(&self) { - self.gpioreg().pcor.set_ptco(self.pin as uint, true); + self.gpioreg().pcor.set_ptco(self.pin.pin as uint, true); } /// Returns input GPIO level. fn level(&self) -> ::hal::pin::GPIOLevel { let reg = self.gpioreg(); - match reg.pdir.pdi(self.pin as uint) { + match reg.pdir.pdi(self.pin.pin as uint) { false => ::hal::pin::Low, _ => ::hal::pin::High, } @@ -176,7 +188,7 @@ impl ::hal::pin::GPIO for Pin { ::hal::pin::In => reg::INPUT, ::hal::pin::Out => reg::OUTPUT, }; - reg.pddr.set_pdd(self.pin as uint, val); + reg.pddr.set_pdd(self.pin.pin as uint, val); } }