From 831113c05ab4620c551806e26ba6963e50eec910 Mon Sep 17 00:00:00 2001 From: Dan Petrisko Date: Thu, 10 Oct 2024 22:28:11 -0700 Subject: [PATCH] Adding missing include to rv_plic template and regenerating output verilog Signed-off-by: Dan Petrisko --- hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl | 2 ++ hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv | 2 ++ 2 files changed, 4 insertions(+) diff --git a/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl b/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl index 6cd349beba748..8a562a6778570 100644 --- a/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl +++ b/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl @@ -14,6 +14,8 @@ // Verilog parameter // MAX_PRIO: Maximum value of interrupt priority +`include "prim_assert.sv" + module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #( parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // OpenTitan IP standardizes on level triggered interrupts, diff --git a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv index b2c4c8a2aedc8..c1a372d98149b 100644 --- a/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv +++ b/hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv @@ -14,6 +14,8 @@ // Verilog parameter // MAX_PRIO: Maximum value of interrupt priority +`include "prim_assert.sv" + module rv_plic import rv_plic_reg_pkg::*; #( parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}, // OpenTitan IP standardizes on level triggered interrupts,