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RISC-V 64-bit with 32-bit floating point extension support.

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RV64IF

⚠️ Note: This was a thesis that I never finished and it should be used for learning purposes only.

RISC-V 64-bit with 32-bit floating point extension support, in-order, 5-stage pipeline, with tournament (hybrid) branch prediction (bimodal + gshare), described in Combining Branch Predictors by Scott McFarling.