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Differential_csvco_5stage.cir.out
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Differential_csvco_5stage.cir.out
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* Generated for: PrimeSim
* Design library name: th_analog_circuits
* Design cell name: th_differential_csvco_5stage
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Wed Feb 23 09:08:28 2022
.global gnd!
********************************************************************************
* Library : th_analog_circuits
* Cell : th_differential_inverter
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt th_differential_inverter vdd vgn vgp vin+ vin- vout+ vout- gnd_1
xm1 vout- vin- vdd vgp p105 w=0.1u l=0.03u nf=1 m=1
xm0 vout+ vin+ vdd vgp p105 w=0.1u l=0.03u nf=1 m=1
xm3 vout- vin- gnd_1 vgn n105 w=0.1u l=0.03u nf=1 m=1
xm2 vout+ vin+ gnd_1 vgn n105 w=0.1u l=0.03u nf=1 m=1
.ends th_differential_inverter
********************************************************************************
* Library : th_analog_circuits
* Cell : th_buffer
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
.subckt th_buffer vdd gnd_1 in out
xm1 out net16 vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm0 net16 in vdd vdd p105 w=0.1u l=0.03u nf=1 m=1
xm3 out net16 gnd_1 gnd_1 n105 w=0.1u l=0.03u nf=1 m=1
xm2 net16 in gnd_1 gnd_1 n105 w=0.1u l=0.03u nf=1 m=1
.ends th_buffer
********************************************************************************
* Library : th_analog_circuits
* Cell : th_differential_csvco_5stage
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm11 net39 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm9 net25 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm7 net5 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm6 net11 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm5 net15 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm0 net6 net43 gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm10 net38 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xm8 net24 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xm4 net4 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xm3 net10 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xm2 net14 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xm1 net6 net6 net47 net47 p105 w=0.1u l=0.03u nf=1 m=1
xi14 net38 gnd! net47 net44 net45 net3 net2 net39 th_differential_inverter
xi0 net24 gnd! net47 net30 net31 net45 net44 net25 th_differential_inverter
xi7 net4 gnd! net47 net8 net9 net31 net30 net5 th_differential_inverter
xi6 net10 gnd! net47 net12 net13 net9 net8 net11 th_differential_inverter
xi5 net14 gnd! net47 net3 net2 net13 net12 net15 th_differential_inverter
v9 net43 gnd! dc='vctrl'
v8 net47 gnd! dc='vsupp'
xi13 net47 gnd! net2 out- th_buffer
xi12 net47 gnd! net3 out+ th_buffer
.tran '10p' '2n' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(out+) v(out-)
.temp 25
.ic v(net3)=0 v(net2)=0
.option primesim_output=wdf
.option parhier = LOCAL
.end