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Merge pull request #200 from tudorsiminic/patch-1
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Fix typo effects -> affects
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angrave authored Dec 18, 2023
2 parents 7187355 + 99a0102 commit d9a14b5
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2 changes: 1 addition & 1 deletion background/background.tex
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Expand Up @@ -57,7 +57,7 @@ \subsection{Caching}
\begin{enumerate}
\item Race Conditions! If a value is stored in two different processor caches, then that value should be accessed by a single thread.
\item Speed. With a cache, your program may look faster mysteriously. Just assume that reads and writes that either happened recently or are next to each other in memory are fast.
\item Side effects. Every read or write effects the cache state. While most of the time this doesn't help or hurt, it is important to know. Check the Intel programmer guide on the lock prefix for more information.
\item Side effects. Every read or write affects the cache state. While most of the time this doesn't help or hurt, it is important to know. Check the Intel programmer guide on the lock prefix for more information.
\end{enumerate}

\subsection{Interrupts}
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