diff --git a/IGC/VectorCompiler/include/vc/InternalIntrinsics/InternalIntrinsics.h b/IGC/VectorCompiler/include/vc/InternalIntrinsics/InternalIntrinsics.h
index ad2f80958400..6d09a9133693 100644
--- a/IGC/VectorCompiler/include/vc/InternalIntrinsics/InternalIntrinsics.h
+++ b/IGC/VectorCompiler/include/vc/InternalIntrinsics/InternalIntrinsics.h
@@ -147,6 +147,8 @@ unsigned getMemoryVectorSizePerLane(const llvm::Instruction *I);
 unsigned getMemorySimdWidth(const llvm::Instruction *I);
 unsigned getMemoryRegisterElementSize(const llvm::Instruction *I);
 
+int getMemorySurfaceOperandIndex(unsigned IID);
+
 int getMemoryCacheControlOperandIndex(unsigned IID);
 
 inline int getMemoryCacheControlOperandIndex(const llvm::Value *V) {
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXPromoteStatefulToBindless.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXPromoteStatefulToBindless.cpp
index fc21d9100a5f..9375a723ed04 100644
--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXPromoteStatefulToBindless.cpp
+++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXPromoteStatefulToBindless.cpp
@@ -238,16 +238,6 @@ static int getSurfaceOperandNo(unsigned Id) {
   case genx_oword_st:
     return 0;
 
-  case vc::InternalIntrinsic::lsc_atomic_bti:
-  case vc::InternalIntrinsic::lsc_load_bti:
-  case vc::InternalIntrinsic::lsc_prefetch_bti:
-  case vc::InternalIntrinsic::lsc_store_bti:
-  case vc::InternalIntrinsic::lsc_load_quad_bti:
-  case vc::InternalIntrinsic::lsc_prefetch_quad_bti:
-  case vc::InternalIntrinsic::lsc_store_quad_bti:
-    return 5;
-
-
   default:
     return -1;
   }
diff --git a/IGC/VectorCompiler/lib/InternalIntrinsics/InternalIntrinsics.cpp b/IGC/VectorCompiler/lib/InternalIntrinsics/InternalIntrinsics.cpp
index bb118d3490f6..ae69b20d9579 100644
--- a/IGC/VectorCompiler/lib/InternalIntrinsics/InternalIntrinsics.cpp
+++ b/IGC/VectorCompiler/lib/InternalIntrinsics/InternalIntrinsics.cpp
@@ -975,3 +975,27 @@ int InternalIntrinsic::getMemoryCacheControlOperandIndex(unsigned IID) {
 
   return 4;
 }
+
+int InternalIntrinsic::getMemorySurfaceOperandIndex(unsigned IID) {
+  switch (IID) {
+  case vc::InternalIntrinsic::lsc_atomic_bti:
+  case vc::InternalIntrinsic::lsc_load_bti:
+  case vc::InternalIntrinsic::lsc_prefetch_bti:
+  case vc::InternalIntrinsic::lsc_store_bti:
+  case vc::InternalIntrinsic::lsc_load_quad_bti:
+  case vc::InternalIntrinsic::lsc_prefetch_quad_bti:
+  case vc::InternalIntrinsic::lsc_store_quad_bti:
+    return 5;
+  case vc::InternalIntrinsic::lsc_load_2d_tgm_bti:
+  case vc::InternalIntrinsic::lsc_store_2d_tgm_bti:
+    return 1;
+  case vc::InternalIntrinsic::lsc_load_quad_tgm:
+  case vc::InternalIntrinsic::lsc_store_quad_tgm:
+  case vc::InternalIntrinsic::lsc_prefetch_quad_tgm:
+    return 3;
+  default:
+    break;
+  }
+
+  return -1;
+}