diff --git a/IGC/VectorCompiler/test/CMABI/debug-bool.ll b/IGC/VectorCompiler/test/CMABI/debug-bool.ll index c5e45c4da012..6bf0c97f7c8f 100644 --- a/IGC/VectorCompiler/test/CMABI/debug-bool.ll +++ b/IGC/VectorCompiler/test/CMABI/debug-bool.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; CMABI ; ------------------------------------------------ @@ -20,7 +21,8 @@ ; CHECK: void @llvm.dbg.value(metadata <2 x i1> [[VAL1_V:%[A-z0-9]*]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i1 [[VAL2_V:%[A-z0-9]*]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC:![0-9]*]] ; CHECK: [[VAL3_V:%[A-z0-9]*]] = {{.*}}, !dbg [[VAL3_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata <2 x i1>* [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata <2 x i1>* [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] ; CHECK: [[VAL4_V:%[A-z0-9]*]] = {{.*}}, !dbg [[VAL4_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata <2 x i1> [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] diff --git a/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_implicit.ll b/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_implicit.ll index 9840244d26c8..2d834b0bf9dc 100644 --- a/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_implicit.ll +++ b/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_implicit.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" @@ -16,7 +17,8 @@ target triple = "spir64-unknown-unknown" ; CHECK-LABEL: @K1 ; CHECK-SAME: (i32 %0, <3 x i16> %__arg_llvm.genx.local.id16, i64 %privBase) ; CHECK: [[K1_ALLOCA:%[^ ]+]] = alloca <3 x i16> -; CHECK: call void @llvm.dbg.declare(metadata <3 x i16>* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK-TYPED-PTRS: call void @llvm.dbg.declare(metadata <3 x i16>* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK-OPAQUE-PTRS: call void @llvm.dbg.declare(metadata ptr [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] ; CHECK-DAG: ![[#K1_SP:]] = distinct !DISubprogram(name: "K1", ; CHECK-DAG: ![[#K1VAR]] = !DILocalVariable(name: "__llvm_genx_local_id16", scope: ![[#K1_SP]], file: ![[#]], type: ![[#K1VAR_TYPE:]], flags: DIFlagArtificial) ; CHECK-DAG: ![[#K1VAR_TYPE]] = !DICompositeType(tag: DW_TAG_array_type, baseType: ![[#K1VAR_BASE_TYPE:]], size: 48, flags: DIFlagVector, elements: ![[#K1VAR_ELEMENTS:]]) diff --git a/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_localized.ll b/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_localized.ll index 79c887f40787..3c7437547812 100644 --- a/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_localized.ll +++ b/IGC/VectorCompiler/test/CMABI/debuginfo_kernel_localized.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" @@ -16,7 +17,8 @@ target triple = "spir64-unknown-unknown" ; CHECK-LABEL: @K1 ; CHECK-SAME: (i32 %0, i64 %privBase) ; CHECK: [[K1_ALLOCA:%[^ ]+]] = alloca i32 -; CHECK: call void @llvm.dbg.declare(metadata i32* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK-TYPED-PTRS: call void @llvm.dbg.declare(metadata i32* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK-OPAQUE-PTRS: call void @llvm.dbg.declare(metadata ptr [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] ; CHECK-DAG: ![[#K1_SP:]] = distinct !DISubprogram(name: "K1", ; CHECK-DAG: ![[#K1VAR]] = !DILocalVariable(name: "x", scope: ![[#K1_SP]], file: ![[#]], type: ![[#TYPE:]], flags: DIFlagArtificial) ; CHECK-DAG: ![[#TYPE]] = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) diff --git a/IGC/VectorCompiler/test/CMABI/debuginfo_stackcall_global.ll b/IGC/VectorCompiler/test/CMABI/debuginfo_stackcall_global.ll index d54c17ded6aa..31d5264ff189 100644 --- a/IGC/VectorCompiler/test/CMABI/debuginfo_stackcall_global.ll +++ b/IGC/VectorCompiler/test/CMABI/debuginfo_stackcall_global.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --check-prefix=CHECK_S1 %s -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --check-prefix=CHECK_K1 %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK_S1,CHECK_S1-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK_S1,CHECK_S1-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK_K1,CHECK_K1-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK_K1,CHECK_K1-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" @@ -17,7 +19,8 @@ target triple = "spir64-unknown-unknown" ; CHECK_S1-LABEL: @S1 ; CHECK_S1-SAME: (i32 %0, i32 %x.in) ; CHECK_S1: [[S1_ALLOCA:%[^ ]+]] = alloca i32 -; CHECK_S1: call void @llvm.dbg.declare(metadata i32* [[S1_ALLOCA]], metadata ![[#S1VAR:]], metadata !DIExpression()), !dbg ![[#S1LOC:]] +; CHECK_S1-TYPED-PTRS: call void @llvm.dbg.declare(metadata i32* [[S1_ALLOCA]], metadata ![[#S1VAR:]], metadata !DIExpression()), !dbg ![[#S1LOC:]] +; CHECK_S1-OPAQUE-PTRS: call void @llvm.dbg.declare(metadata ptr [[S1_ALLOCA]], metadata ![[#S1VAR:]], metadata !DIExpression()), !dbg ![[#S1LOC:]] ; CHECK_S1-DAG: ![[#S1_SP:]] = distinct !DISubprogram(name: "S1", ; CHECK_S1-DAG: ![[#S1VAR]] = !DILocalVariable(name: "x", scope: ![[#S1_SP]], file: ![[#]], type: ![[#S1TYPE:]], flags: DIFlagArtificial) ; CHECK_S1-DAG: ![[#S1TYPE]] = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) @@ -31,7 +34,8 @@ define internal spir_func <8 x i32> @S1(i32 %0) #1 !dbg !17 { ; CHECK_K1-LABEL: @K1 ; CHECK_K1-SAME: (i32 %0, i64 %privBase) ; CHECK_K1: [[K1_ALLOCA:%[^ ]+]] = alloca i32 -; CHECK_K1: call void @llvm.dbg.declare(metadata i32* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK_K1-TYPED-PTRS: call void @llvm.dbg.declare(metadata i32* [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] +; CHECK_K1-OPAQUE-PTRS: call void @llvm.dbg.declare(metadata ptr [[K1_ALLOCA]], metadata ![[#K1VAR:]], metadata !DIExpression()), !dbg ![[#K1LOC:]] ; CHECK_K1-DAG: ![[#K1_SP:]] = distinct !DISubprogram(name: "K1", ; CHECK_K1-DAG: ![[#K1VAR]] = !DILocalVariable(name: "x", scope: ![[#K1_SP]], file: ![[#]], type: ![[#K1TYPE:]], flags: DIFlagArtificial) ; CHECK_K1-DAG: ![[#K1TYPE]] = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) diff --git a/IGC/VectorCompiler/test/CMABI/func_with_taken_addr.ll b/IGC/VectorCompiler/test/CMABI/func_with_taken_addr.ll index 961eb3a83198..19eee9b99003 100644 --- a/IGC/VectorCompiler/test/CMABI/func_with_taken_addr.ll +++ b/IGC/VectorCompiler/test/CMABI/func_with_taken_addr.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -15,8 +16,10 @@ define internal spir_func void @foo(<8 x i32>* %vector.ref) { ret void } ; COM: should stay the same -; CHECK: define internal spir_func void @foo(<8 x i32>* %vector.ref) { -; CHECK-NEXT: %vector.ld = load <8 x i32>, <8 x i32>* %vector.ref +; CHECK-TYPED-PTRS: define internal spir_func void @foo(<8 x i32>* %vector.ref) { +; CHECK-TYPED-PTRS-NEXT: %vector.ld = load <8 x i32>, <8 x i32>* %vector.ref +; CHECK-OPAQUE-PTRS: define internal spir_func void @foo(ptr %vector.ref) { +; CHECK-OPAQUE-PTRS-NEXT: %vector.ld = load <8 x i32>, ptr %vector.ref ; CHECK-NEXT: ret void ; CHECK-NEXT: } @@ -29,8 +32,10 @@ define dllexport void @kernel(i32 %val) { ; COM: should stay the same ; CHECK: define dllexport void @kernel(i32 %val) { ; CHECK-NEXT: %vec.alloca = alloca <8 x i32>, align 32 -; CHECK-NEXT: call spir_func void @foo(<8 x i32>* nonnull %vec.alloca) -; CHECK-NEXT: %indirect.user = ptrtoint void (<8 x i32>*)* @foo to i32 +; CHECK-TYPED-PTRS-NEXT: call spir_func void @foo(<8 x i32>* nonnull %vec.alloca) +; CHECK-TYPED-PTRS-NEXT: %indirect.user = ptrtoint void (<8 x i32>*)* @foo to i32 +; CHECK-OPAQUE-PTRS-NEXT: call spir_func void @foo(ptr nonnull %vec.alloca) +; CHECK-OPAQUE-PTRS-NEXT: %indirect.user = ptrtoint ptr @foo to i32 ; CHECK-NEXT: ret void ; CHECK-NEXT: } diff --git a/IGC/VectorCompiler/test/CMABI/global_without_align.ll b/IGC/VectorCompiler/test/CMABI/global_without_align.ll index bbfa137726db..7dea845c4da9 100644 --- a/IGC/VectorCompiler/test/CMABI/global_without_align.ll +++ b/IGC/VectorCompiler/test/CMABI/global_without_align.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -18,7 +19,8 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ; FIXME: Make 'align 1' an unconditional part of the check after LLVM 9-10 ; gets abolished. ; CHECK: %global.int.local = alloca i32{{(, align 1)?}} -; CHECK: store i32 0, i32* %global.int.local{{(, align 1)?}} +; CHECK-TYPED-PTRS: store i32 0, i32* %global.int.local{{(, align 1)?}} +; CHECK-OPAQUE-PTRS: store i32 0, ptr %global.int.local{{(, align 1)?}} define dllexport void @kernel(float %kernel.value) { %1 = load i32, i32* @global.int, align 4 ret void diff --git a/IGC/VectorCompiler/test/CMABI/linearization.ll b/IGC/VectorCompiler/test/CMABI/linearization.ll index e93f656b2d24..48caa9699ce3 100644 --- a/IGC/VectorCompiler/test/CMABI/linearization.ll +++ b/IGC/VectorCompiler/test/CMABI/linearization.ll @@ -1,16 +1,18 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" +; CHECK: define dllexport void @cmk_kmeans(i8 define dllexport void @cmk_kmeans(i1 zeroext %0, i64 %privBase) #0 { ret void } @@ -30,14 +32,8 @@ attributes #0 = { noinline nounwind "CMGenxMain" "oclrt"="1" } !1 = !{i32 1, i32 2} !2 = !{} !3 = !{i16 6, i16 14} -; CHECK: !4 = !{void -; CHECK-NOT: i1 -; CHECK-SAME: i8 !4 = !{void (i1, i64)* @cmk_kmeans, !"cmk_kmeans", !5, i32 0, i32 0, !6, !7, i32 0} !5 = !{i32 0, i32 96} !6 = !{i32 0} !7 = !{!"buffer_t read_write", !"buffer_t read_write", !"buffer_t read_write", !"", !""} -; CHECK: !8 = !{void -; CHECK-NOT: i1 -; CHECK-SAME: i8 !8 = !{void (i1, i64)* @cmk_kmeans, null, null, !2, null} diff --git a/IGC/VectorCompiler/test/GenXCFSimplification/debug.ll b/IGC/VectorCompiler/test/GenXCFSimplification/debug.ll index 9e431b02ddde..b680273cb74c 100644 --- a/IGC/VectorCompiler/test/GenXCFSimplification/debug.ll +++ b/IGC/VectorCompiler/test/GenXCFSimplification/debug.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXCFSimplification -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXCFSimplification -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXCFSimplification -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXCFSimplification ; ------------------------------------------------ @@ -23,7 +24,8 @@ ; CHECK: [[VAL3_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL3_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] ; CHECK: [[VAL4_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL4_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32* [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32* [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] ; CHECK: [[VAL5_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL5_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] ; CHECK: [[VAL6_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL6_LOC:![0-9]*]] diff --git a/IGC/VectorCompiler/test/GenXDetectPointerArg/integer.ll b/IGC/VectorCompiler/test/GenXDetectPointerArg/integer.ll index fae57273a3e9..324109cd24d8 100644 --- a/IGC/VectorCompiler/test/GenXDetectPointerArg/integer.ll +++ b/IGC/VectorCompiler/test/GenXDetectPointerArg/integer.ll @@ -6,7 +6,8 @@ ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS @data = internal global <8 x i64> undef, align 64, !spirv.Decorations !0 #0 @@ -39,7 +40,8 @@ attributes #3 = { nofree nounwind readonly "target-cpu"="XeHPC" } !llvm.module.flags = !{!20} ; CHECK: !genx.kernels = !{![[KERNEL:[0-9]+]]} -; CHECK: ![[KERNEL]] = !{void (i64, i64)* @kernel, !"kernel", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-TYPED-PTRS: ![[KERNEL]] = !{void (i64, i64)* @kernel, !"kernel", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-OPAQUE-PTRS: ![[KERNEL]] = !{ptr @kernel, !"kernel", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} ; CHECK: ![[NODE]] = !{!"svmptr_t", !""} !0 = !{!1, !2, !3, !4} diff --git a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-alloca.ll b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-alloca.ll index e87d9595db3f..15a627b3f67b 100644 --- a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-alloca.ll +++ b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-alloca.ll @@ -6,7 +6,8 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" @@ -54,7 +55,8 @@ attributes #3 = { "target-cpu"="XeHPC" } !genx.kernel.internal = !{!10} ; CHECK: !genx.kernels = !{![[KERNEL:[0-9]+]]} -; CHECK: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-TYPED-PTRS: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-OPAQUE-PTRS: ![[KERNEL]] = !{ptr @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} ; CHECK: ![[NODE]] = !{!"svmptr_t", !"svmptr_t", !"", !"", !"svmptr_t", !""} !0 = !{i32 0, i32 100000} diff --git a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array-indirect.ll b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array-indirect.ll index e69a6f78a941..ef27784a40c2 100644 --- a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array-indirect.ll +++ b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array-indirect.ll @@ -6,7 +6,8 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" @@ -62,7 +63,8 @@ attributes #2 = { "target-cpu"="XeHPC" } !genx.kernel.internal = !{!10} ; CHECK: !genx.kernels = !{![[KERNEL:[0-9]+]]} -; CHECK: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, i64, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-TYPED-PTRS: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, i64, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-OPAQUE-PTRS: ![[KERNEL]] = !{ptr @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} ; CHECK: ![[NODE]] = !{!"svmptr_t", !"svmptr_t", !"", !"", !"svmptr_t", !"svmptr_t", !"svmptr_t", !""} !0 = !{i32 0, i32 100000} diff --git a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array.ll b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array.ll index d7982be920a7..6b8c2426208e 100644 --- a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array.ll +++ b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct-array.ll @@ -6,7 +6,8 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" @@ -59,7 +60,8 @@ attributes #2 = { "target-cpu"="XeHPC" } !genx.kernel.internal = !{!10} ; CHECK: !genx.kernels = !{![[KERNEL:[0-9]+]]} -; CHECK: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, i64, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-TYPED-PTRS: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, i64, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-OPAQUE-PTRS: ![[KERNEL]] = !{ptr @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} ; CHECK: ![[NODE]] = !{!"svmptr_t", !"svmptr_t", !"", !"", !"", !"", !"svmptr_t", !""} !0 = !{i32 0, i32 100000} diff --git a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct.ll b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct.ll index e28bf4b27a47..6c083e198883 100644 --- a/IGC/VectorCompiler/test/GenXDetectPointerArg/struct.ll +++ b/IGC/VectorCompiler/test/GenXDetectPointerArg/struct.ll @@ -6,7 +6,8 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXDetectPointerArg -march=genx64 -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" @@ -42,7 +43,8 @@ attributes #3 = { "target-cpu"="XeHPC" } !genx.kernel.internal = !{!10} ; CHECK: !genx.kernels = !{![[KERNEL:[0-9]+]]} -; CHECK: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-TYPED-PTRS: ![[KERNEL]] = !{void (%struct.state*, i32 addrspace(1)*, i64, i8, i64, float)* @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} +; CHECK-OPAQUE-PTRS: ![[KERNEL]] = !{ptr @foo, !"foo", !{{[0-9]+}}, i32 0, !{{[0-9]+}}, !{{[0-9]+}}, ![[NODE:[0-9]+]], i32 0} ; CHECK: ![[NODE]] = !{!"svmptr_t", !"svmptr_t", !"", !"", !"svmptr_t", !""} !0 = !{i32 0, i32 100000} diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop32.ll b/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop32.ll index 804b2e13aff6..6a9141c3c88b 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop32.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop32.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXGEPLowering ; ------------------------------------------------ @@ -28,7 +29,8 @@ ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] ; CHECK: [[VAL3_V:%[A-z0-9]*]] = add{{.*}}, !dbg [[VAL3_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata i32* [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] +; CHECK-TYPED-PTRS-DAG: void @llvm.dbg.value(metadata i32* [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] +; CHECK-OPAQUE-PTRS-DAG: void @llvm.dbg.value(metadata ptr [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] ; CHECK-DAG: [[VAL4_V]] = {{.*}}, !dbg [[VAL4_LOC]] target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32" diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop64.ll b/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop64.ll index 6dbb274209a0..f6ec49df6963 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop64.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/debug-loop64.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXGEPLowering ; ------------------------------------------------ @@ -27,7 +28,8 @@ ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] ; CHECK: [[VAL3_V:%[A-z0-9]*]] = add{{.*}}, !dbg [[VAL3_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata i32* [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] +; CHECK-TYPED-PTRS-DAG: void @llvm.dbg.value(metadata i32* [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] +; CHECK-OPAQUE-PTRS-DAG: void @llvm.dbg.value(metadata ptr [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] ; CHECK-DAG: [[VAL4_V]] = {{.*}}, !dbg [[VAL4_LOC]] target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32" diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/debug.ll b/IGC/VectorCompiler/test/GenXGEPLowering/debug.ll index a949a865a1c5..28de0c2874f8 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/debug.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/debug.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXGEPLowering ; ------------------------------------------------ @@ -21,21 +22,26 @@ ; CHECK: void @test_lowergep{{.*}} !dbg [[SCOPE:![0-9]*]] ; CHECK: entry: ; CHECK: [[VAL1_V:%[A-z0-9]*]] = addrspacecast{{.*}}, !dbg [[VAL1_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i8 addrspace(4)* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i8 addrspace(4)* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr addrspace(4) [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] ; CHECK: [[VAL2_V:%[A-z0-9]*]] = ptrtoint{{.*}}, !dbg [[VAL2_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i8 [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] ; ; CHECK: geps: -; CHECK-DAG: void @llvm.dbg.value(metadata <4 x float>* [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] -; CHECK-DAG: [[VAL4_V]] = {{.*}}, !dbg [[VAL4_LOC]] +; CHECK: [[VAL4_V:%[A-z0-9.]*]] = inttoptr{{.*}}, !dbg [[VAL4_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata <4 x float>* [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] ; CHECK: [[VAL5_V:%[A-z0-9]*]] = load{{.*}}, !dbg [[VAL5_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata <4 x float> [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] ; CHECK: [[VAL6_V:%[A-z0-9]*]] = inttoptr{{.*}}, !dbg [[VAL6_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32* [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata i32* [[VAL7_V:%[A-z0-9.]*]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC:![0-9]*]] -; CHECK-DAG: [[VAL7_V]] = {{.*}}, !dbg [[VAL7_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata <4 x i32*> [[VAL9_V:%[A-z0-9.]*]], metadata [[VAL9_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL9_LOC:![0-9]*]] -; CHECK-DAG: [[VAL9_V]] = {{.*}}, !dbg [[VAL9_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32* [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] +; CHECK: [[VAL7_V:%[A-z0-9.]*]] = inttoptr{{.*}}, !dbg [[VAL7_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32* [[VAL7_V]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL7_V]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC]] +; CHECK: [[VAL9_V:%[A-z0-9.]*]] = inttoptr{{.*}}, !dbg [[VAL9_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata <4 x i32*> [[VAL9_V]], metadata [[VAL9_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL9_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata <4 x ptr> [[VAL9_V]], metadata [[VAL9_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL9_LOC]] %struct._test = type { i32, <4 x float>, [2 x i64] } diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/fold-ptrtoint.ll b/IGC/VectorCompiler/test/GenXGEPLowering/fold-ptrtoint.ll index 61b5b04a0378..a30efd7e1adb 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/fold-ptrtoint.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/fold-ptrtoint.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-p3:32:32-i64:64-n8:16:32:64" @@ -18,7 +19,8 @@ declare <32 x double> @llvm.vc.internal.lsc.load.ugm.v32f64.v32i1.v32i64(<32 x i define <32 x i32> @test_fold_cast(i8 addrspace(1)* align 8 %a) { entry: %bitcast = bitcast i8 addrspace(1)* %a to double addrspace(1)* - ; CHECK: %pti = ptrtoint i8 addrspace(1)* %a to i64 + ; CHECK-TYPED-PTRS: %pti = ptrtoint i8 addrspace(1)* %a to i64 + ; CHECK-OPAQUE-PTRS: %pti = ptrtoint ptr addrspace(1) %a to i64 %pti = ptrtoint double addrspace(1)* %bitcast to i64 %res = call <32 x i32> @llvm.vc.internal.lsc.load.ugm.v32i32.v1i1.i64(<1 x i1> , i8 3, i8 3, i8 7, i8 0, i8 0, i64 0, i64 %pti, i16 1, i32 0, <32 x i32> undef) ret <32 x i32> %res @@ -38,11 +40,12 @@ entry: define <32 x i32> @test_fold_cast_gep_pti(i8 addrspace(1)* align 8 %a) { entry: %bitcast = bitcast i8 addrspace(1)* %a to double addrspace(1)* - ; CHECK: [[PTI:%[^ ]+]] = ptrtoint i8 addrspace(1)* %a to i64 + ; CHECK-TYPED-PTRS: [[PTI:%[^ ]+]] = ptrtoint i8 addrspace(1)* %a to i64 + ; CHECK-OPAQUE-PTRS: [[PTI:%[^ ]+]] = ptrtoint ptr addrspace(1) %a to i64 ; CHECK: [[ADD:%[^ ]+]] = add i64 [[PTI]], 1024 %gep = getelementptr double, double addrspace(1)* %bitcast, i32 128 %pti = ptrtoint double addrspace(1)* %gep to i64 - ; CHECL: %res = call <32 x i32> @llvm.vc.internal.lsc.load.ugm.v32i32.v1i1.i64(<1 x i1> , i8 3, i8 3, i8 7, i8 0, i8 0, i64 0, i64 [[ADD]], i16 1, i32 0, <32 x i32> undef) + ; CHECK: %res = call <32 x i32> @llvm.vc.internal.lsc.load.ugm.v32i32.v1i1.i64(<1 x i1> , i8 3, i8 3, i8 7, i8 0, i8 0, i64 0, i64 [[ADD]], i16 1, i32 0, <32 x i32> undef) %res = call <32 x i32> @llvm.vc.internal.lsc.load.ugm.v32i32.v1i1.i64(<1 x i1> , i8 3, i8 3, i8 7, i8 0, i8 0, i64 0, i64 %pti, i16 1, i32 0, <32 x i32> undef) ret <32 x i32> %res } @@ -51,7 +54,8 @@ entry: define <32 x double> @test_fold_ascastp42p3_vector(<32 x i1> %mask, <32 x double addrspace(4)*> %a) { entry: %ascast = addrspacecast <32 x double addrspace(4)*> %a to <32 x double addrspace(3)*> - ; CHECK: %pti = ptrtoint <32 x double addrspace(3)*> %ascast to <32 x i32> + ; CHECK-TYPED-PTRS: %pti = ptrtoint <32 x double addrspace(3)*> %ascast to <32 x i32> + ; CHECK-OPAQUE-PTRS: %pti = ptrtoint <32 x ptr addrspace(3)> %ascast to <32 x i32> %pti = ptrtoint <32 x double addrspace(3)*> %ascast to <32 x i32> %res = call <32 x double> @llvm.vc.internal.lsc.load.slm.v32f64.v32i1.v32i32(<32 x i1> %mask, i8 2, i8 4, i8 1, i8 0, i8 0, i32 0, <32 x i32> %pti, i16 1, i32 0, <32 x double> undef) ret <32 x double> %res @@ -61,7 +65,8 @@ entry: define <32 x double> @test_fold_ascastp42p1_vector(<32 x i1> %mask, <32 x double addrspace(4)*> %a) { entry: %ascast = addrspacecast <32 x double addrspace(4)*> %a to <32 x double addrspace(1)*> - ; CHECK: %pti = ptrtoint <32 x double addrspace(4)*> %a to <32 x i64> + ; CHECK-TYPED-PTRS: %pti = ptrtoint <32 x double addrspace(4)*> %a to <32 x i64> + ; CHECK-OPAQUE-PTRS: %pti = ptrtoint <32 x ptr addrspace(4)> %a to <32 x i64> %pti = ptrtoint <32 x double addrspace(1)*> %ascast to <32 x i64> %res = call <32 x double> @llvm.vc.internal.lsc.load.ugm.v32f64.v32i1.v32i64(<32 x i1> %mask, i8 3, i8 4, i8 1, i8 0, i8 0, i64 0, <32 x i64> %pti, i16 1, i32 0, <32 x double> undef) ret <32 x double> %res @@ -71,7 +76,8 @@ entry: define <32 x double> @test_fold_cast_vector(<32 x i1> %mask, <32 x i8 addrspace(1)*> %a) { entry: %bitcast = bitcast <32 x i8 addrspace(1)*> %a to <32 x double addrspace(1)*> - ; CHECK: %pti = ptrtoint <32 x i8 addrspace(1)*> %a to <32 x i64> + ; CHECK-TYPED-PTRS: %pti = ptrtoint <32 x i8 addrspace(1)*> %a to <32 x i64> + ; CHECK-OPAQUE-PTRS: %pti = ptrtoint <32 x ptr addrspace(1)> %a to <32 x i64> %pti = ptrtoint <32 x double addrspace(1)*> %bitcast to <32 x i64> %res = call <32 x double> @llvm.vc.internal.lsc.load.ugm.v32f64.v32i1.v32i64(<32 x i1> %mask, i8 3, i8 4, i8 1, i8 0, i8 0, i64 0, <32 x i64> %pti, i16 1, i32 0, <32 x double> undef) ret <32 x double> %res @@ -111,7 +117,8 @@ define i64 @test_bitcast_vector_to_scalar(<1 x i8*> %vptr) { %ptr = bitcast <1 x i8*> %vptr to i8* %gep = getelementptr i8, i8* %ptr, i32 123 %addr = ptrtoint i8* %gep to i64 - ; CHECK: [[PTI:%[^ ]+]] = ptrtoint i8* %ptr to i64 + ; CHECK-TYPED-PTRS: [[PTI:%[^ ]+]] = ptrtoint i8* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[PTI:%[^ ]+]] = ptrtoint ptr %ptr to i64 ; CHECK: [[ADD:%[^ ]+]] = add i64 [[PTI]], 123 ; CHECK: ret i64 [[ADD]] ret i64 %addr diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector.ll b/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector.ll index d30da188fe2f..607d8be329f5 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector.ll @@ -1,19 +1,21 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s - +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS define void @test8.v16i64(<16 x i64*> %arg, <16 x i64> %offset) { %arrayidx = getelementptr i64, <16 x i64*> %arg, <16 x i64> %offset -; CHECK: [[V1:%.*]] = ptrtoint <16 x i64*> %arg to <16 x i64> +; CHECK-TYPED-PTRS: [[V1:%.*]] = ptrtoint <16 x i64*> %arg to <16 x i64> +; CHECK-OPAQUE-PTRS: [[V1:%.*]] = ptrtoint <16 x ptr> %arg to <16 x i64> ; CHECK-NEXT: [[V2:%.*]] = shl <16 x i64> %offset, ; CHECK-NEXT: [[V3:%.*]] = add <16 x i64> [[V1]], [[V2]] -; CHECK-NEXT: [[V4:%.*]] = inttoptr <16 x i64> [[V3]] to <16 x i64*> +; CHECK-TYPED-PTRS-NEXT: [[V4:%.*]] = inttoptr <16 x i64> [[V3]] to <16 x i64*> +; CHECK-OPAQUE-PTRS-NEXT: [[V4:%.*]] = inttoptr <16 x i64> [[V3]] to <16 x ptr> ret void } diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector2.ll b/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector2.ll index c0abc307a0e0..850a30bed1d8 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector2.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/geplower-vector2.ll @@ -1,19 +1,22 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS %struct.st = type { i32, <4 x float>, [2 x i64] } define void @test_lowergep(<2 x %struct.st*> %arg) { %1 = getelementptr %struct.st, <2 x %struct.st*> %arg, <2 x i32> , <2 x i32> -; CHECK: [[V1:%.*]] = ptrtoint <2 x %struct.st*> %arg to <2 x i64> +; CHECK-TYPED-PTRS: [[V1:%.*]] = ptrtoint <2 x %struct.st*> %arg to <2 x i64> +; CHECK-OPAQUE-PTRS: [[V1:%.*]] = ptrtoint <2 x ptr> %arg to <2 x i64> ; CHECK-NEXT: [[V2:%.*]] = add <2 x i64> [[V1]], ; CHECK-NEXT: [[V3:%.*]] = add <2 x i64> [[V2]], -; CHECK-NEXT: [[V4:%.*]] = inttoptr <2 x i64> [[V3]] to <2 x <4 x float>*> +; CHECK-TYPED-PTRS-NEXT: [[V4:%.*]] = inttoptr <2 x i64> [[V3]] to <2 x <4 x float>*> +; CHECK-OPAQUE-PTRS-NEXT: [[V4:%.*]] = inttoptr <2 x i64> [[V3]] to <2 x ptr> ret void } diff --git a/IGC/VectorCompiler/test/GenXGEPLowering/geplower2.ll b/IGC/VectorCompiler/test/GenXGEPLowering/geplower2.ll index e3c30b47cfbd..c8e3d1087c18 100644 --- a/IGC/VectorCompiler/test/GenXGEPLowering/geplower2.ll +++ b/IGC/VectorCompiler/test/GenXGEPLowering/geplower2.ll @@ -1,21 +1,24 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGEPLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS %struct.a = type { [5 x [16 x double]] } define dllexport spir_kernel void @test_lowergep([5 x %struct.a]* %a, i64 %b, i64 %c) { %1 = getelementptr [5 x %struct.a], [5 x %struct.a]* %a, i64 0, i64 %b, i32 0, i64 %c, i64 0 -; CHECK: [[V1:%.*]] = ptrtoint [5 x %struct.a]* %a to i64 +; CHECK-TYPED-PTRS: [[V1:%.*]] = ptrtoint [5 x %struct.a]* %a to i64 +; CHECK-OPAQUE-PTRS: [[V1:%.*]] = ptrtoint ptr %a to i64 ; CHECK-NEXT: [[V2:%.*]] = mul i64 %b, 640 ; CHECK-NEXT: [[V3:%.*]] = add i64 [[V1]], %2 ; CHECK-NEXT: [[V4:%.*]] = shl i64 %c, 7 ; CHECK-NEXT: [[V5:%.*]] = add i64 [[V3]], %4 -; CHECK-NEXT: [[V6:%.*]] = inttoptr i64 [[V5]] to double* +; CHECK-TYPED-PTRS-NEXT: [[V6:%.*]] = inttoptr i64 [[V5]] to double* +; CHECK-OPAQUE-PTRS-NEXT: [[V6:%.*]] = inttoptr i64 [[V5]] to ptr ret void } diff --git a/IGC/VectorCompiler/test/GenXIMadPostLegalization/no_move_if_gv_clobbering.ll b/IGC/VectorCompiler/test/GenXIMadPostLegalization/no_move_if_gv_clobbering.ll index 50f44b022369..5abd11e916ee 100644 --- a/IGC/VectorCompiler/test/GenXIMadPostLegalization/no_move_if_gv_clobbering.ll +++ b/IGC/VectorCompiler/test/GenXIMadPostLegalization/no_move_if_gv_clobbering.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXIMadLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXIMadLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXIMadLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXIMadPostLegalization ; ------------------------------------------------ @@ -66,8 +67,10 @@ entry: %call4.i.i.i.esimd = call <32 x double> @llvm.genx.wrregionf.v32f64.f64.i16.i1(<32 x double> %call.i.i.i123.esimd69, double %mad18, i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true) store volatile <32 x double> %call4.i.i.i.esimd, <32 x double>* @_ZL1A %call.i.i.i.i170.esimd73 = load volatile <32 x double>, <32 x double>* @_ZL1A -; CHECK: store volatile <32 x double> %call4.i.i.i.esimd, <32 x double>* @_ZL1A -; CHECK-NEXT: %call.i.i.i.i170.esimd73 = load volatile <32 x double>, <32 x double>* @_ZL1A +; CHECK-TYPED-PTRS: store volatile <32 x double> %call4.i.i.i.esimd, <32 x double>* @_ZL1A +; CHECK-TYPED-PTRS-NEXT: %call.i.i.i.i170.esimd73 = load volatile <32 x double>, <32 x double>* @_ZL1A +; CHECK-OPAQUE-PTRS: store volatile <32 x double> %call4.i.i.i.esimd, ptr @_ZL1A +; CHECK-OPAQUE-PTRS-NEXT: %call.i.i.i.i170.esimd73 = load volatile <32 x double>, ptr @_ZL1A ; CHECK-NOT: %vecext.i1.regioncollapsed[[POST_BALING_CLONE_IDX0:[0-9]+]] = tail call double @llvm.genx.rdregionf.f64.v32f64.i16(<32 x double> %call.i.i.i123.esimd69, i32 0, i32 1, i32 1, i16 0, i32 undef) ; CHECK-NOT: %mul25 = fmul double %vecext.i1.regioncollapsed[[POST_BALING_CLONE_IDX0:[0-9]+]], %mul17 ; CHECK-NOT: %vecext.i1503.regioncollapsed[[POST_BALING_CLONE_IDX1:[0-9]+]] = tail call double @llvm.genx.rdregionf.f64.v32f64.i16(<32 x double> %call.i.i.i123.esimd69, i32 0, i32 1, i32 1, i16 8, i32 undef) diff --git a/IGC/VectorCompiler/test/GenXLegalization/gvload_clone_per_gstore_bale_split.ll b/IGC/VectorCompiler/test/GenXLegalization/gvload_clone_per_gstore_bale_split.ll index b76fc5e67a1b..47499f1292fe 100644 --- a/IGC/VectorCompiler/test/GenXLegalization/gvload_clone_per_gstore_bale_split.ll +++ b/IGC/VectorCompiler/test/GenXLegalization/gvload_clone_per_gstore_bale_split.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLegalization -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ; ------------------------------------------------ ; GenXLegalization @@ -21,7 +22,8 @@ target triple = "genx64-unknown-unknown" define internal spir_func void @test_gvload_clone_per_split1() { %gvload1 = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 %add = add <64 x i16> %gvload1, zeroinitializer -; CHECK: %add.gvload_use_split_clone = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 +; CHECK-TYPED-PTRS: %add.gvload_use_split_clone = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 +; CHECK-OPAQUE-PTRS: %add.gvload_use_split_clone = load volatile <64 x i16>, ptr @g_global1, align 128 ; CHECK: %add.gvload_use_split_clone.split32 = call <32 x i16> @llvm.genx.rdregioni.v32i16.v64i16.i16(<64 x i16> %add.gvload_use_split_clone, i32 32, i32 32, i32 1, i16 64, i32 undef) ; CHECK: %add.split32 = add <32 x i16> %add.gvload_use_split_clone.split32, zeroinitializer store volatile <64 x i16> %add, <64 x i16>* @g_global1, align 128 @@ -32,7 +34,8 @@ define internal spir_func void @test_gvload_clone_per_split2() { %gvload1 = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 %gvload2 = load volatile <64 x i16>, <64 x i16>* @g_global2, align 128 %add = add <64 x i16> %gvload1, %gvload2 -; CHECK: %add.gvload_use_split_clone = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 +; CHECK-TYPED-PTRS: %add.gvload_use_split_clone = load volatile <64 x i16>, <64 x i16>* @g_global1, align 128 +; CHECK-OPAQUE-PTRS: %add.gvload_use_split_clone = load volatile <64 x i16>, ptr @g_global1, align 128 ; CHECK-NEXT: %add.gvload_use_split_clone.split32 = call <32 x i16> @llvm.genx.rdregioni.v32i16.v64i16.i16(<64 x i16> %add.gvload_use_split_clone, i32 32, i32 32, i32 1, i16 64, i32 undef) ; CHECK-NEXT: %gvload2.split32 = call <32 x i16> @llvm.genx.rdregioni.v32i16.v64i16.i16(<64 x i16> %gvload2, i32 32, i32 32, i32 1, i16 64, i32 undef) ; CHECK-NEXT: %add.split32 = add <32 x i16> %add.gvload_use_split_clone.split32, %gvload2.split32 diff --git a/IGC/VectorCompiler/test/GenXLegalizeGVLoadUses/mem2reg_gv_clobbering_avoidance.ll b/IGC/VectorCompiler/test/GenXLegalizeGVLoadUses/mem2reg_gv_clobbering_avoidance.ll index c75273dfcd5a..5e7b0dc03cb8 100644 --- a/IGC/VectorCompiler/test/GenXLegalizeGVLoadUses/mem2reg_gv_clobbering_avoidance.ll +++ b/IGC/VectorCompiler/test/GenXLegalizeGVLoadUses/mem2reg_gv_clobbering_avoidance.ll @@ -1,6 +1,6 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; @@ -23,11 +23,15 @@ ; use(L) ;================================================= ; -; RUN: %opt %use_old_pass_manager% -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ -; RUN: FileCheck --check-prefix=UNFIXED %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ +; RUN: FileCheck %s --check-prefixes=UNFIXED,UNFIXED-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ +; RUN: FileCheck %s --check-prefixes=UNFIXED,UNFIXED-OPAQUE-PTRS ; -; RUN: %opt %use_old_pass_manager% -GenXLegalizeGVLoadUses -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ -; RUN: FileCheck --check-prefix=FIXED %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLegalizeGVLoadUses -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ +; RUN: FileCheck %s --check-prefixes=FIXED,FIXED-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLegalizeGVLoadUses -mem2reg -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | \ +; RUN: FileCheck %s --check-prefixes=FIXED,FIXED-OPAQUE-PTRS target datalayout = "e-p:64:64-p3:32:32-p6:32:32-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown" @@ -50,14 +54,18 @@ define spir_kernel void @test() #1 { } ; FIXED: define spir_kernel void @test() -; FIXED: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(<1 x double>* @left2) +; FIXED-TYPED-PTRS: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(<1 x double>* @left2) +; FIXED-OPAQUE-PTRS: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(ptr @left2) ; FIXED: %gload47.i._gvload_legalized_rdr = call <1 x double> @llvm.genx.rdregionf.v1f64.v1f64.i16(<1 x double> %gload47.i, i32 0, i32 1, i32 1, i16 0, i32 undef) -; FIXED: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, <1 x double>* @left2) +; FIXED-TYPED-PTRS: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, <1 x double>* @left2) +; FIXED-OPAQUE-PTRS: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, ptr @left2) ; FIXED: %rdr39.i = call <1 x double> @llvm.genx.rdregionf.v1f64.v1f64.i16(<1 x double> %gload47.i._gvload_legalized_rdr, i32 0, i32 1, i32 0, i16 0, i32 0) ; UNFIXED: define spir_kernel void @test() -; UNFIXED: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(<1 x double>* @left2) -; UNFIXED: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, <1 x double>* @left2) +; UNFIXED-TYPED-PTRS: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(<1 x double>* @left2) +; UNFIXED-TYPED-PTRS: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, <1 x double>* @left2) +; UNFIXED-OPAQUE-PTRS: %gload47.i = call <1 x double> @llvm.genx.vload.v1f64.p0v1f64(ptr @left2) +; UNFIXED-OPAQUE-PTRS: call void @llvm.genx.vstore.v1f64.p0v1f64(<1 x double> zeroinitializer, ptr @left2) ; UNFIXED: %rdr39.i = call <1 x double> @llvm.genx.rdregionf.v1f64.v1f64.i16(<1 x double> %gload47.i, i32 0, i32 1, i32 0, i16 0, i32 0) attributes #0 = { "genx_volatile" } diff --git a/IGC/VectorCompiler/test/GenXNumbering/debug.ll b/IGC/VectorCompiler/test/GenXNumbering/debug.ll index 1bb36d3a5970..e52c207a833f 100644 --- a/IGC/VectorCompiler/test/GenXNumbering/debug.ll +++ b/IGC/VectorCompiler/test/GenXNumbering/debug.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXNumberingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXNumberingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXNumberingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXNumbering ; ------------------------------------------------ @@ -22,7 +23,8 @@ ; CHECK: [[VAL1_V:%[A-z0-9]*]] = {{.*}}, !dbg [[VAL1_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] ; CHECK: [[VAL2_V:%[A-z0-9]*]] = {{.*}}, !dbg [[VAL2_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32* [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32* [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] ; CHECK: call void @test_func{{.*}}, !dbg [[CALL1_LOC:![0-9]*]] define dllexport void @test_kernel(i32* %a) #0 !dbg !6 { diff --git a/IGC/VectorCompiler/test/GenXRegionCollapsing/aggregate_collapsing.ll b/IGC/VectorCompiler/test/GenXRegionCollapsing/aggregate_collapsing.ll index e84fb30bdf2e..73dca5b31345 100644 --- a/IGC/VectorCompiler/test/GenXRegionCollapsing/aggregate_collapsing.ll +++ b/IGC/VectorCompiler/test/GenXRegionCollapsing/aggregate_collapsing.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXRegionCollapsing \ -; RUN: -march=genx64 -mcpu=Gen9 -mtriple=spir64 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXRegionCollapsing \ +; RUN: -march=genx64 -mcpu=Gen9 -mtriple=spir64 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXRegionCollapsing \ +; RUN: -march=genx64 -mcpu=Gen9 -mtriple=spir64 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ModuleID = 'bugpoint-reduced-simplified.bc' source_filename = "the_file.ll" @@ -20,12 +22,13 @@ target triple = "genx64-unknown-unknown" ; COM: the check that collapsing succesfully operates on aggregate types ; CHECK-LABEL: @wobble -; CHECK-NEXT: [[TOPTR:%[^ ]+]] = inttoptr <1 x i64> %arg to <1 x %struct.hoge addrspace(4)*> -; CHECK-NEXT: [[RECAST:%[^ ]+]] = bitcast <1 x %struct.hoge addrspace(4)*> [[TOPTR]] to %struct.hoge addrspace(4)* -; CHECK-NEXT: [[BITCAST:%[^ ]+]] = bitcast %struct.hoge addrspace(4)* [[RECAST]] to %struct.bar addrspace(4)* -; CHECK-NEXT: [[RDREGION:%[^ ]+]] = bitcast %struct.bar addrspace(4)* [[BITCAST]] to <1 x %struct.bar addrspace(4)*> -; CHECK-NEXT: [[ICAST:%[^ ]+]] = ptrtoint <1 x %struct.bar addrspace(4)*> [[RDREGION]] to <1 x i64> -; CHECK-NEXT: call void @llvm.genx.svm.scatter.v1i1.v1i64.v1i64(<1 x i1> , i32 0, <1 x i64> undef, <1 x i64> [[ICAST]]) +; CHECK-TYPED-PTRS-NEXT: [[TOPTR:%[^ ]+]] = inttoptr <1 x i64> %arg to <1 x %struct.hoge addrspace(4)*> +; CHECK-TYPED-PTRS-NEXT: [[RECAST:%[^ ]+]] = bitcast <1 x %struct.hoge addrspace(4)*> [[TOPTR]] to %struct.hoge addrspace(4)* +; CHECK-TYPED-PTRS-NEXT: [[BITCAST:%[^ ]+]] = bitcast %struct.hoge addrspace(4)* [[RECAST]] to %struct.bar addrspace(4)* +; CHECK-TYPED-PTRS-NEXT: [[RDREGION:%[^ ]+]] = bitcast %struct.bar addrspace(4)* [[BITCAST]] to <1 x %struct.bar addrspace(4)*> +; CHECK-TYPED-PTRS-NEXT: [[ICAST:%[^ ]+]] = ptrtoint <1 x %struct.bar addrspace(4)*> [[RDREGION]] to <1 x i64> +; CHECK-TYPED-PTRS-NEXT: call void @llvm.genx.svm.scatter.v1i1.v1i64.v1i64(<1 x i1> , i32 0, <1 x i64> undef, <1 x i64> [[ICAST]]) +; CHECK-OPAQUE-PTRS-NEXT: call void @llvm.genx.svm.scatter.v1i1.v1i64.v1i64(<1 x i1> , i32 0, <1 x i64> undef, <1 x i64> %arg) define internal spir_func void @wobble(<1 x i64> %arg) #0 { %tmp = inttoptr <1 x i64> %arg to <1 x %struct.hoge addrspace(4)*> diff --git a/IGC/VectorCompiler/test/GenXSLMResolution/simple.ll b/IGC/VectorCompiler/test/GenXSLMResolution/simple.ll index 31fbd111b0bb..ecf044f3a8a2 100644 --- a/IGC/VectorCompiler/test/GenXSLMResolution/simple.ll +++ b/IGC/VectorCompiler/test/GenXSLMResolution/simple.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022-2023 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -17,16 +18,20 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" define dllexport spir_kernel void @kernel() #0 { - ; CHECK: %load_i1 = load i1, i1 addrspace(3)* inttoptr (i32 26 to i1 addrspace(3)*) + ; CHECK-TYPED-PTRS: %load_i1 = load i1, i1 addrspace(3)* inttoptr (i32 26 to i1 addrspace(3)*) + ; CHECK-OPAQUE-PTRS: %load_i1 = load i1, ptr addrspace(3) inttoptr (i32 26 to ptr addrspace(3)) %load_i1 = load i1, i1 addrspace(3)* @slm_i1 - ; CHECK: %load_v2i8 = load <2 x i8>, <2 x i8> addrspace(3)* inttoptr (i32 24 to <2 x i8> addrspace(3)*), + ; CHECK-TYPED-PTRS: %load_v2i8 = load <2 x i8>, <2 x i8> addrspace(3)* inttoptr (i32 24 to <2 x i8> addrspace(3)*), + ; CHECK-OPAQUE-PTRS: %load_v2i8 = load <2 x i8>, ptr addrspace(3) inttoptr (i32 24 to ptr addrspace(3)), %load_v2i8 = load <2 x i8>, <2 x i8> addrspace(3)* @slm_v2i8 - ; CHECK: %load_struct_i64i8 = load { i64, i8 }, { i64, i8 } addrspace(3)* inttoptr (i32 8 to { i64, i8 } addrspace(3)*) + ; CHECK-TYPED-PTRS: %load_struct_i64i8 = load { i64, i8 }, { i64, i8 } addrspace(3)* inttoptr (i32 8 to { i64, i8 } addrspace(3)*) + ; CHECK-OPAQUE-PTRS: %load_struct_i64i8 = load { i64, i8 }, ptr addrspace(3) inttoptr (i32 8 to ptr addrspace(3)) %load_struct_i64i8 = load { i64, i8 }, { i64, i8 } addrspace(3)* @slm_struct_i64i8 - ; CHECK: %load_struct_align = load { i1 }, { i1 } addrspace(3)* inttoptr (i32 268435456 to { i1 } addrspace(3)*) + ; CHECK-TYPED-PTRS: %load_struct_align = load { i1 }, { i1 } addrspace(3)* inttoptr (i32 268435456 to { i1 } addrspace(3)*) + ; CHECK-OPAQUE-PTRS: %load_struct_align = load { i1 }, ptr addrspace(3) inttoptr (i32 268435456 to ptr addrspace(3)) %load_struct_align = load { i1 }, { i1 } addrspace(3)* @slm_struct_align ret void } @@ -36,7 +41,8 @@ attributes #0 = { noinline nounwind "CMGenxMain" } !genx.kernels = !{!0} !genx.kernel.internal = !{!3} -; CHECK: !{{[[:digit:]]}} = !{void ()* @kernel, !"kernel", !{{[[:digit:]]}}, i32 27, !{{[[:digit:]]}}, !{{[[:digit:]]}}, !{{[[:digit:]]}}, i32 0} +; CHECK-TYPED-PTRS: !{{[[:digit:]]}} = !{void ()* @kernel, !"kernel", !{{[[:digit:]]}}, i32 27, !{{[[:digit:]]}}, !{{[[:digit:]]}}, !{{[[:digit:]]}}, i32 0} +; CHECK-OPAQUE-PTRS: !{{[[:digit:]]}} = !{ptr @kernel, !"kernel", !{{[[:digit:]]}}, i32 27, !{{[[:digit:]]}}, !{{[[:digit:]]}}, !{{[[:digit:]]}}, i32 0} !0 = !{void ()* @kernel, !"kernel", !1, i32 0, !1, !1, !2, i32 0} !1 = !{} !2 = !{!""} diff --git a/IGC/VectorCompiler/test/GenXSLMResolution/slm-init.ll b/IGC/VectorCompiler/test/GenXSLMResolution/slm-init.ll index d58e4c6623db..11ff23462b0a 100644 --- a/IGC/VectorCompiler/test/GenXSLMResolution/slm-init.ll +++ b/IGC/VectorCompiler/test/GenXSLMResolution/slm-init.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022-2023 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXSLMResolution -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS declare void @llvm.genx.slm.init(i32) @@ -19,7 +20,8 @@ define dllexport spir_kernel void @kernel() { !genx.kernels = !{!0} !genx.kernel.internal = !{!2} -; CHECK: !0 = !{void ()* @kernel, !"kernel", !1, i32 12345, !1, !1, !1, i32 0} +; CHECK-TYPED-PTRS: !0 = !{void ()* @kernel, !"kernel", !1, i32 12345, !1, !1, !1, i32 0} +; CHECK-OPAQUE-PTRS: !0 = !{ptr @kernel, !"kernel", !1, i32 12345, !1, !1, !1, i32 0} !0 = !{void ()* @kernel, !"kernel", !1, i32 1234, !1, !1, !1, i32 0} !1 = !{} !2 = !{void ()* @kernel, !1, !1, !1, !1} diff --git a/IGC/VectorCompiler/test/GenXSimdCFRegion/cm_loop.ll b/IGC/VectorCompiler/test/GenXSimdCFRegion/cm_loop.ll index b0e4f5eed63f..c41c3e61af1a 100644 --- a/IGC/VectorCompiler/test/GenXSimdCFRegion/cm_loop.ll +++ b/IGC/VectorCompiler/test/GenXSimdCFRegion/cm_loop.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -simdcf-region -simdcf-skip-search-preds \ -; RUN: -simdcf-rm-loop-mask -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -simdcf-region -simdcf-skip-search-preds \ +; RUN: -simdcf-rm-loop-mask -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -simdcf-region -simdcf-skip-search-preds \ +; RUN: -simdcf-rm-loop-mask -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXSimdCFRegion ; ------------------------------------------------ @@ -30,7 +32,8 @@ entry: ; CHECK-SAME: i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, ; CHECK-SAME: i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, ; CHECK-SAME: i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, -; CHECK-SAME: <32 x i1>* %[[EM]] +; CHECK-TYPED-PTRS-SAME: <32 x i1>* %[[EM]] +; CHECK-OPAQUE-PTRS-SAME: ptr %[[EM]] br label %while.cond ; CHECK: while.cond: @@ -40,19 +43,22 @@ while.cond: ; preds = %while.body, %entry %out.0 = phi <32 x i32> [ , %entry ], [ %merge29, %while.body ] %cmp18 = icmp ne <32 x i16> %mask.0, zeroinitializer -; CHECK: %[[PRED_1:.*]] = load <32 x i1>, <32 x i1>* %[[EM]] +; CHECK-TYPED-PTRS: %[[PRED_1:.*]] = load <32 x i1>, <32 x i1>* %[[EM]] +; CHECK-OPAQUE-PTRS: %[[PRED_1:.*]] = load <32 x i1>, ptr %[[EM]] %allany = tail call i1 @llvm.genx.any.v32i1(<32 x i1> %cmp18) ; CHECK: %[[GOTO_PRE:.*]] = tail call {{.*}} @llvm.genx.simdcf.goto ; CHECK: %[[EM_TO_STORE:.*]] = extractvalue { <32 x i1>, <32 x i1>, i1 } %[[GOTO_PRE]], 0 -; CHECK: store <32 x i1> %[[EM_TO_STORE]], <32 x i1>* %[[EM]], align 4 +; CHECK-TYPED-PTRS: store <32 x i1> %[[EM_TO_STORE]], <32 x i1>* %[[EM]], align 4 +; CHECK-OPAQUE-PTRS: store <32 x i1> %[[EM_TO_STORE]], ptr %[[EM]], align 4 br i1 %allany, label %while.body, label %while.end ; CHECK: while.body: while.body: ; preds = %while.cond ; COM: Here apply SIMD CF and change predicate from loop-predicate to execution mask -; CHECK: %[[EM_BODY:.*]] = load <32 x i1>, <32 x i1>* %[[EM]] +; CHECK-TYPED-PTRS: %[[EM_BODY:.*]] = load <32 x i1>, <32 x i1>* %[[EM]] +; CHECK-OPAQUE-PTRS: %[[EM_BODY:.*]] = load <32 x i1>, ptr %[[EM]] %.not = icmp eq <32 x i16> %mask.0, zeroinitializer ; CHECK-NOT: %{{.*}} = icmp eq <32 x i16> %mul21 = mul <32 x i32> %random.0, diff --git a/IGC/VectorCompiler/test/GenXSimdCFRegion/if-else.ll b/IGC/VectorCompiler/test/GenXSimdCFRegion/if-else.ll index 6ad9868e7ab8..1e6e50139a26 100644 --- a/IGC/VectorCompiler/test/GenXSimdCFRegion/if-else.ll +++ b/IGC/VectorCompiler/test/GenXSimdCFRegion/if-else.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -simdcf-region -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -simdcf-region -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -simdcf-region -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXSimdCFRegion ; ------------------------------------------------ @@ -30,9 +31,11 @@ if.entry: ; CHECK: [[IF_AFTER_ENTRY:[A-z0-9.]*]]: ; CHECK: %[[GOTO:[A-z0-9.]*]] = tail call { <32 x i1>, <16 x i1>, i1 } @llvm.genx.simdcf.goto ; CHECK: %[[BASIC_EM:[A-z0-9.]*]] = extractvalue { <32 x i1>, <16 x i1>, i1 } %[[GOTO]], 0 -; CHECK-DAG: store <32 x i1> %[[BASIC_EM]], <32 x i1>* %[[EM_ALLOCA]] +; CHECK-TYPED-PTRS-DAG: store <32 x i1> %[[BASIC_EM]], <32 x i1>* %[[EM_ALLOCA]] +; CHECK-OPAQUE-PTRS-DAG: store <32 x i1> %[[BASIC_EM]], ptr %[[EM_ALLOCA]] ; CHECK: %[[BASIC_RM:[A-z0-9.]*]] = extractvalue { <32 x i1>, <16 x i1>, i1 } %[[GOTO]], 1 -; CHECK-DAG: store <16 x i1> %[[BASIC_RM]], <16 x i1>* %[[RM_ALLOCA]] +; CHECK-TYPED-PTRS-DAG: store <16 x i1> %[[BASIC_RM]], <16 x i1>* %[[RM_ALLOCA]] +; CHECK-OPAQUE-PTRS-DAG: store <16 x i1> %[[BASIC_RM]], ptr %[[RM_ALLOCA]] ; CHECK: %[[BASIC_COND:[A-z0-9.]*]] = extractvalue { <32 x i1>, <16 x i1>, i1 } %[[GOTO]], 2 ; CHECK: br i1 %[[BASIC_COND]], label %[[AFTERTHEN:[A-z0-9.]*]], label %[[IF_THEN:[A-z0-9.]*]] diff --git a/IGC/VectorCompiler/test/GenXSimplify/gv_clobbering.ll b/IGC/VectorCompiler/test/GenXSimplify/gv_clobbering.ll index 6f811dc1358b..977233c61764 100644 --- a/IGC/VectorCompiler/test/GenXSimplify/gv_clobbering.ll +++ b/IGC/VectorCompiler/test/GenXSimplify/gv_clobbering.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | \ -; RUN: FileCheck --check-prefix=FIXED %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | \ +; RUN: FileCheck --check-prefixes=FIXED,FIXED-TYPED-PTRS %s +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | \ +; RUN: FileCheck --check-prefixes=FIXED,FIXED-OPAQUE-PTRS %s target datalayout = "e-p:64:64-p3:32:32-p6:32:32-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown" @@ -28,9 +30,11 @@ define spir_kernel void @wavefront_pth_3_atomic_noflag_r63_s2d_group__double_8_8 } ; FIXED: define spir_kernel void @wavefront_pth_3_atomic_noflag_r63_s2d_group__double_8_8_16() #2 { -; FIXED: %gload47.i = call <8 x double> @llvm.genx.vload.v8f64.p0v8f64(<8 x double>* @left2) +; FIXED-TYPED-PTRS: %gload47.i = call <8 x double> @llvm.genx.vload.v8f64.p0v8f64(<8 x double>* @left2) +; FIXED-OPAQUE-PTRS: %gload47.i = call <8 x double> @llvm.genx.vload.v8f64.p0v8f64(ptr @left2) ; FIXED: %gload47.i._gvload_legalized_rdr = call <8 x double> @llvm.genx.rdregionf.v8f64.v8f64.i16(<8 x double> %gload47.i, i32 0, i32 0, i32 1, i16 0, i32 0) -; FIXED: call void @llvm.genx.vstore.v8f64.p0v8f64(<8 x double> zeroinitializer, <8 x double>* @left2) +; FIXED-TYPED-PTRS: call void @llvm.genx.vstore.v8f64.p0v8f64(<8 x double> zeroinitializer, <8 x double>* @left2) +; FIXED-OPAQUE-PTRS: call void @llvm.genx.vstore.v8f64.p0v8f64(<8 x double> zeroinitializer, ptr @left2) ; FIXED-NOT: %rdr39.i = call <1 x double> @llvm.genx.rdregionf.v1f64.v8f64.i16(<8 x double> %gload47.i, i32 0, i32 0, i32 0, i16 0, i32 0) attributes #0 = { "genx_volatile" } diff --git a/IGC/VectorCompiler/test/GenXSimplify/ptr_constant_fold.ll b/IGC/VectorCompiler/test/GenXSimplify/ptr_constant_fold.ll index 873ec2a98ceb..d7fd77cffe33 100644 --- a/IGC/VectorCompiler/test/GenXSimplify/ptr_constant_fold.ll +++ b/IGC/VectorCompiler/test/GenXSimplify/ptr_constant_fold.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -genx-simplify -mcpu=Gen9 -march=genx64 -mtriple=spir64 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ;; Test constant folding of pointers -- that pass do not fails and ;; correctly handles pointer size. @@ -16,7 +17,8 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ;; wrr <2 x i8*>, (8)<0;1,0>, i8 *null -> zeroinitializer define <2 x i8*> @test_const_wrr_ptr() { ; CHECK-LABEL: @test_const_wrr_ptr( -; CHECK-NEXT: ret <2 x i8*> zeroinitializer +; CHECK-TYPED-PTRS-NEXT: ret <2 x i8*> zeroinitializer +; CHECK-OPAQUE-PTRS-NEXT: ret <2 x ptr> zeroinitializer %x = call <2 x i8*> @llvm.genx.wrregioni.v2p0i8.p0i8.i16.i1(<2 x i8*> , i8* null, i32 0, i32 1, i32 0, i16 8, i32 0, i1 true) ret <2 x i8*> %x } @@ -24,7 +26,8 @@ define <2 x i8*> @test_const_wrr_ptr() { ;; rdr <2 x i8*>, (8)<0;1,0> -> <2 x i8*> zeroinitializer define <2 x i8*> @test_const_rdr_ptr_vec_broadcast() { ; CHECK-LABEL: @test_const_rdr_ptr_vec_broadcast( -; CHECK-NEXT: ret <2 x i8*> zeroinitializer +; CHECK-TYPED-PTRS-NEXT: ret <2 x i8*> zeroinitializer +; CHECK-OPAQUE-PTRS-NEXT: ret <2 x ptr> zeroinitializer %x = call <2 x i8*> @llvm.genx.rdregioni.v2p0i8.v2p0i8.i16(<2 x i8*> , i32 0, i32 1, i32 0, i16 8, i32 0) ret <2 x i8*> %x } diff --git a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/addc.ll b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/addc.ll index 1a40a785d0c1..d6ef822cb9fa 100644 --- a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/addc.ll +++ b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/addc.ll @@ -1,14 +1,17 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ ; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ -; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXTranslateSPIRVBuiltins ; ------------------------------------------------ @@ -19,11 +22,15 @@ ; CHECK: [[ADDC:%[^ ]*]] = call { <16 x i32>, <16 x i32> } @llvm.genx.addc.v16i32.v16i32(<16 x i32> {{.*}}, <16 x i32> {{.*}}) ; CHECK: [[ADDC_C:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[ADDC]], 0 ; CHECK: [[ADDC_RES:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[ADDC]], 1 -; CHECK: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair{{.*}} to <16 x i32> -; CHECK: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32>{{.*}} [[PTR_CAST]], i32 0 -; CHECK: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32>{{.*}} [[PTR_CAST]], i32 1 -; CHECK: store <16 x i32> [[ADDC_RES]], <16 x i32>{{.*}} [[PTR_RES]], align 64 -; CHECK: store <16 x i32> [[ADDC_C]], <16 x i32>{{.*}} [[PTR_C]], align 64 +; CHECK-TYPED-PTRS: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair addrspace(4)* {{.*}} to <16 x i32> addrspace(4)* +; CHECK-TYPED-PTRS: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 0 +; CHECK-TYPED-PTRS: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 1 +; CHECK-TYPED-PTRS: store <16 x i32> [[ADDC_RES]], <16 x i32> addrspace(4)* [[PTR_RES]], align 64 +; CHECK-TYPED-PTRS: store <16 x i32> [[ADDC_C]], <16 x i32> addrspace(4)* [[PTR_C]], align 64 +; CHECK-OPAQUE-PTRS: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 0 +; CHECK-OPAQUE-PTRS: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 1 +; CHECK-OPAQUE-PTRS: store <16 x i32> [[ADDC_RES]], ptr addrspace(4) [[PTR_RES]], align 64 +; CHECK-OPAQUE-PTRS: store <16 x i32> [[ADDC_C]], ptr addrspace(4) [[PTR_C]], align 64 ; Function Attrs: nounwind define dllexport spir_kernel void @test() #0 { diff --git a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert.ll b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert.ll index 364d0a016727..17cd3e95ba05 100644 --- a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert.ll +++ b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert.ll @@ -1,14 +1,17 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ ; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ -; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXTranslateSPIRVBuiltins ; ------------------------------------------------ @@ -21,12 +24,17 @@ declare spir_func i64 @_Z33__spirv_BuiltInGlobalInvocationIdi(i32) #2 define spir_func void @__assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3) { %5 = call spir_func i64 @_Z33__spirv_BuiltInGlobalInvocationIdi(i32 0) #3 ; Multi-call must be handled -; CHECK: [[ARG1:%[^ ]*]] = addrspacecast [31 x i8] addrspace(2)* %0 to i8 addrspace(4)* -; CHECK: [[ARG2:%[^ ]*]] = addrspacecast [11 x i8] addrspace(2)* %1 to i8 addrspace(4)* -; CHECK: [[ARG3:%[^ ]*]] = addrspacecast [56 x i8] addrspace(2)* %3 to i8 addrspace(4)* -; CHECK: call spir_func void @__devicelib_assert_fail(i8 addrspace(4)* [[ARG1]], i8 addrspace(4)* [[ARG2]], i32 %2, i8 addrspace(4)* [[ARG3]] +; CHECK-TYPED-PTRS: [[ARG1:%[^ ]*]] = addrspacecast [31 x i8] addrspace(2)* %0 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: [[ARG2:%[^ ]*]] = addrspacecast [11 x i8] addrspace(2)* %1 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: [[ARG3:%[^ ]*]] = addrspacecast [56 x i8] addrspace(2)* %3 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: call spir_func void @__devicelib_assert_fail(i8 addrspace(4)* [[ARG1]], i8 addrspace(4)* [[ARG2]], i32 %2, i8 addrspace(4)* [[ARG3]] +; CHECK-OPAQUE-PTRS: [[ARG1:%[^ ]*]] = addrspacecast ptr addrspace(2) %0 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: [[ARG2:%[^ ]*]] = addrspacecast ptr addrspace(2) %1 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: [[ARG3:%[^ ]*]] = addrspacecast ptr addrspace(2) %3 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: call spir_func void @__devicelib_assert_fail(ptr addrspace(4) [[ARG1]], ptr addrspace(4) [[ARG2]], i32 %2, ptr addrspace(4) [[ARG3]] call spir_func void @__devicelib_assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5) #1 -; CHECK: void @__devicelib_assert_fail(i8 addrspace(4)*{{.*}}, i8 addrspace(4)*{{.*}}, i32{{.*}}, i8 addrspace(4)* +; CHECK-TYPED-PTRS: void @__devicelib_assert_fail(i8 addrspace(4)*{{.*}}, i8 addrspace(4)*{{.*}}, i32{{.*}}, i8 addrspace(4)* +; CHECK-OPAQUE-PTRS: void @__devicelib_assert_fail(ptr addrspace(4){{.*}}, ptr addrspace(4){{.*}}, i32{{.*}}, ptr addrspace(4) call spir_func void @__devicelib_assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5) #1 ret void } @@ -40,4 +48,4 @@ define spir_func void @__devicelib_assert_fail([31 x i8] addrspace(2)* %0, [11 x } attributes #2 = { mustprogress nofree nosync nounwind readnone willreturn } -attributes #3 = { nounwind readnone willreturn } \ No newline at end of file +attributes #3 = { nounwind readnone willreturn } diff --git a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert_decl.ll b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert_decl.ll index 1ddc79236a26..e60ce16eb9bf 100644 --- a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert_decl.ll +++ b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/assert_decl.ll @@ -1,14 +1,17 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ ; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ -; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXTranslateSPIRVBuiltins ; ------------------------------------------------ @@ -21,12 +24,17 @@ declare spir_func i64 @_Z33__spirv_BuiltInGlobalInvocationIdi(i32) #2 define spir_func void @__assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3) { %5 = call spir_func i64 @_Z33__spirv_BuiltInGlobalInvocationIdi(i32 0) #3 ; Multi-call must be handled -; CHECK: [[ARG1:%[^ ]*]] = addrspacecast [31 x i8] addrspace(2)* %0 to i8 addrspace(4)* -; CHECK: [[ARG2:%[^ ]*]] = addrspacecast [11 x i8] addrspace(2)* %1 to i8 addrspace(4)* -; CHECK: [[ARG3:%[^ ]*]] = addrspacecast [56 x i8] addrspace(2)* %3 to i8 addrspace(4)* -; CHECK: call spir_func void @__devicelib_assert_fail(i8 addrspace(4)* [[ARG1]], i8 addrspace(4)* [[ARG2]], i32 %2, i8 addrspace(4)* [[ARG3]] +; CHECK-TYPED-PTRS: [[ARG1:%[^ ]*]] = addrspacecast [31 x i8] addrspace(2)* %0 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: [[ARG2:%[^ ]*]] = addrspacecast [11 x i8] addrspace(2)* %1 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: [[ARG3:%[^ ]*]] = addrspacecast [56 x i8] addrspace(2)* %3 to i8 addrspace(4)* +; CHECK-TYPED-PTRS: call spir_func void @__devicelib_assert_fail(i8 addrspace(4)* [[ARG1]], i8 addrspace(4)* [[ARG2]], i32 %2, i8 addrspace(4)* [[ARG3]] +; CHECK-OPAQUE-PTRS: [[ARG1:%[^ ]*]] = addrspacecast ptr addrspace(2) %0 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: [[ARG2:%[^ ]*]] = addrspacecast ptr addrspace(2) %1 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: [[ARG3:%[^ ]*]] = addrspacecast ptr addrspace(2) %3 to ptr addrspace(4) +; CHECK-OPAQUE-PTRS: call spir_func void @__devicelib_assert_fail(ptr addrspace(4) [[ARG1]], ptr addrspace(4) [[ARG2]], i32 %2, ptr addrspace(4) [[ARG3]] call spir_func void @__devicelib_assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5) #1 -; CHECK: void @__devicelib_assert_fail(i8 addrspace(4)*{{.*}}, i8 addrspace(4)*{{.*}}, i32{{.*}}, i8 addrspace(4)* +; CHECK-TYPED-PTRS: void @__devicelib_assert_fail(i8 addrspace(4)*{{.*}}, i8 addrspace(4)*{{.*}}, i32{{.*}}, i8 addrspace(4)* +; CHECK-OPAQUE-PTRS: void @__devicelib_assert_fail(ptr addrspace(4){{.*}}, ptr addrspace(4){{.*}}, i32{{.*}}, ptr addrspace(4) call spir_func void @__devicelib_assert_fail([31 x i8] addrspace(2)* %0, [11 x i8] addrspace(2)* %1, i32 %2, [56 x i8] addrspace(2)* %3, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5, i64 %5) #1 ret void } diff --git a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/atomic_fminmax.ll b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/atomic_fminmax.ll index bcf31c9b1b9d..d054915a3839 100644 --- a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/atomic_fminmax.ll +++ b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/atomic_fminmax.ll @@ -6,16 +6,19 @@ ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXTranslateSPIRVBuiltins -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS declare spir_func float @_Z21__spirv_AtomicFMinEXTPU3AS4fiif(float addrspace(4)*, i32, i32, float) #0 declare spir_func float @_Z21__spirv_AtomicFMaxEXTPU3AS4fiif(float addrspace(4)*, i32, i32, float) #0 define spir_func void @foo(float addrspace(4)* %Ptr, float %Value) { - ; CHECK: %res.fmin = call float @llvm.vc.internal.atomic.fmin.f32.p4f32.f32(float addrspace(4)* %Ptr, i32 4, i32 16, float %Value) + ; CHECK-TYPED-PTRS: %res.fmin = call float @llvm.vc.internal.atomic.fmin.f32.p4f32.f32(float addrspace(4)* %Ptr, i32 4, i32 16, float %Value) + ; CHECK-OPAQUE-PTRS: %res.fmin = call float @llvm.vc.internal.atomic.fmin.f32.p4.f32(ptr addrspace(4) %Ptr, i32 4, i32 16, float %Value) %res.fmin = call spir_func float @_Z21__spirv_AtomicFMinEXTPU3AS4fiif(float addrspace(4)* %Ptr, i32 4, i32 16, float %Value) #0 - ; CHECK: %res.fmax = call float @llvm.vc.internal.atomic.fmax.f32.p4f32.f32(float addrspace(4)* %Ptr, i32 1, i32 8, float %Value) + ; CHECK-TYPED-PTRS: %res.fmax = call float @llvm.vc.internal.atomic.fmax.f32.p4f32.f32(float addrspace(4)* %Ptr, i32 1, i32 8, float %Value) + ; CHECK-OPAQUE-PTRS: %res.fmax = call float @llvm.vc.internal.atomic.fmax.f32.p4.f32(ptr addrspace(4) %Ptr, i32 1, i32 8, float %Value) %res.fmax = call spir_func float @_Z21__spirv_AtomicFMaxEXTPU3AS4fiif(float addrspace(4)* %Ptr, i32 1, i32 8, float %Value) #0 ret void } diff --git a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/subb.ll b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/subb.ll index 96ef410e21f3..ea4c844c4faa 100644 --- a/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/subb.ll +++ b/IGC/VectorCompiler/test/GenXTranslateSPIRVBuiltins/subb.ll @@ -1,14 +1,17 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ ; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ -; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXTranslateSPIRVBuiltins \ +; RUN: -vc-spirv-builtins-bif-path=%VC_SPIRV_OCL_BIF% -march=genx64 \ +; RUN: -mtriple=spir64-unknown-unknown -mcpu=XeHPC -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXTranslateSPIRVBuiltins ; ------------------------------------------------ @@ -19,11 +22,15 @@ ; CHECK: [[SUBB:%[^ ]*]] = call { <16 x i32>, <16 x i32> } @llvm.genx.subb.v16i32.v16i32(<16 x i32> {{.*}}, <16 x i32> {{.*}}) ; CHECK: [[SUBB_C:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[SUBB]], 0 ; CHECK: [[SUBB_RES:%[^ ]*]] = extractvalue { <16 x i32>, <16 x i32> } [[SUBB]], 1 -; CHECK: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair{{.*}} to <16 x i32> -; CHECK: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32>{{.*}} [[PTR_CAST]], i32 0 -; CHECK: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32>{{.*}} [[PTR_CAST]], i32 1 -; CHECK: store <16 x i32> [[SUBB_RES]], <16 x i32>{{.*}} [[PTR_RES]], align 64 -; CHECK: store <16 x i32> [[SUBB_C]], <16 x i32>{{.*}} [[PTR_C]], align 64 +; CHECK-TYPED-PTRS: [[PTR_CAST:%[^ ]*]] = bitcast %struct_pair addrspace(4)* {{.*}} to <16 x i32> addrspace(4)* +; CHECK-TYPED-PTRS: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 0 +; CHECK-TYPED-PTRS: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, <16 x i32> addrspace(4)* [[PTR_CAST]], i32 1 +; CHECK-TYPED-PTRS: store <16 x i32> [[SUBB_RES]], <16 x i32> addrspace(4)* [[PTR_RES]], align 64 +; CHECK-TYPED-PTRS: store <16 x i32> [[SUBB_C]], <16 x i32> addrspace(4)* [[PTR_C]], align 64 +; CHECK-OPAQUE-PTRS: [[PTR_RES:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 0 +; CHECK-OPAQUE-PTRS: [[PTR_C:%[^ ]*]] = getelementptr <16 x i32>, ptr addrspace(4) {{.*}}, i32 1 +; CHECK-OPAQUE-PTRS: store <16 x i32> [[SUBB_RES]], ptr addrspace(4) [[PTR_RES]], align 64 +; CHECK-OPAQUE-PTRS: store <16 x i32> [[SUBB_C]], ptr addrspace(4) [[PTR_C]], align 64 ; Function Attrs: nounwind define dllexport spir_kernel void @test() #0 { diff --git a/IGC/VectorCompiler/test/GenXUnbaling/debug-process-phi.ll b/IGC/VectorCompiler/test/GenXUnbaling/debug-process-phi.ll index 87a31c9e6b52..5607ca65fb4f 100644 --- a/IGC/VectorCompiler/test/GenXUnbaling/debug-process-phi.ll +++ b/IGC/VectorCompiler/test/GenXUnbaling/debug-process-phi.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXModule -GenXUnbalingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXModule -GenXUnbalingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXModule -GenXUnbalingWrapper -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXUnbaling ; ------------------------------------------------ @@ -32,7 +33,8 @@ ; CHECK-DAG: [[VAL5_V]] = {{.*}}, !dbg [[VAL5_LOC]] ; CHECK-DAG: void @llvm.dbg.value(metadata i32 [[VAL6_V:%[A-z0-9]*]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC:![0-9]*]] ; CHECK-DAG: [[VAL6_V]] = {{.*}}, !dbg [[VAL6_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata <4 x i32>* [[VAL7_V:%[A-z0-9]*]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC:![0-9]*]] +; CHECK-TYPED-PTRS-DAG: void @llvm.dbg.value(metadata <4 x i32>* [[VAL7_V:%[A-z0-9]*]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC:![0-9]*]] +; CHECK-OPAQUE-PTRS-DAG: void @llvm.dbg.value(metadata ptr [[VAL7_V:%[A-z0-9]*]], metadata [[VAL7_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL7_LOC:![0-9]*]] ; CHECK-DAG: [[VAL7_V]] = {{.*}}, !dbg [[VAL7_LOC]] ; CHECK-DAG: void @llvm.dbg.value(metadata <4 x i32> [[VAL8_V:%[A-z0-9]*]], metadata [[VAL8_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL8_LOC:![0-9]*]] ; CHECK-DAG: [[VAL8_V]] = {{.*}}, !dbg [[VAL8_LOC]] diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/all_in.ll b/IGC/VectorCompiler/test/GlobalValueLowering/all_in.ll index 941f7bd55d15..008e3e3aea41 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/all_in.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/all_in.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -26,36 +27,54 @@ define dllexport void @simple_array() { %struct.outer* %ptr.vec ; COM: lower global variables -; CHECK-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_a) -; CHECK-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to [8 x i32]* -; CHECK-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_b) -; CHECK-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to [8 x i32]* -; CHECK-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_c) -; CHECK-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_a) +; CHECK-TYPED-PTRS-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_b) +; CHECK-TYPED-PTRS-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_c) +; CHECK-TYPED-PTRS-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to [8 x i32]* +; CHECK-OPAQUE-PTRS-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_a) +; CHECK-OPAQUE-PTRS-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to ptr +; CHECK-OPAQUE-PTRS-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_b) +; CHECK-OPAQUE-PTRS-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to ptr +; CHECK-OPAQUE-PTRS-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_c) +; CHECK-OPAQUE-PTRS-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to ptr ; COM: lower GEP -; CHECK-DAG: %[[GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %array_a.lowered, i32 0, i64 3 +; CHECK-TYPED-PTRS-DAG: %[[GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %array_a.lowered, i32 0, i64 3 +; CHECK-OPAQUE-PTRS-DAG: %[[GEP:[^ ]+]] = getelementptr inbounds [8 x i32], ptr %array_a.lowered, i32 0, i64 3 ; COM: lower inner struct -; CHECK-DAG: %[[INN_ST_HALF:[^ ]+]] = insertvalue %struct.inner undef, [8 x i32]* %array_a.lowered, 0 -; CHECK-DAG: %[[INN_ST_GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %array_a.lowered, i32 0, i64 5 -; CHECK-DAG: %[[INN_ST:[^ ]+]] = insertvalue %struct.inner %[[INN_ST_HALF]], i32* %[[INN_ST_GEP]], 1 +; CHECK-TYPED-PTRS-DAG: %[[INN_ST_HALF:[^ ]+]] = insertvalue %struct.inner undef, [8 x i32]* %array_a.lowered, 0 +; CHECK-TYPED-PTRS-DAG: %[[INN_ST_GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %array_a.lowered, i32 0, i64 5 +; CHECK-TYPED-PTRS-DAG: %[[INN_ST:[^ ]+]] = insertvalue %struct.inner %[[INN_ST_HALF]], i32* %[[INN_ST_GEP]], 1 +; CHECK-OPAQUE-PTRS-DAG: %[[INN_ST_HALF:[^ ]+]] = insertvalue %struct.inner undef, ptr %array_a.lowered, 0 +; CHECK-OPAQUE-PTRS-DAG: %[[INN_ST_GEP:[^ ]+]] = getelementptr inbounds [8 x i32], ptr %array_a.lowered, i32 0, i64 5 +; CHECK-OPAQUE-PTRS-DAG: %[[INN_ST:[^ ]+]] = insertvalue %struct.inner %[[INN_ST_HALF]], ptr %[[INN_ST_GEP]], 1 ; COM: lower array -; CHECK-DAG: %[[ARR_HALF:[^ ]+]] = insertvalue [2 x [8 x i32]*] undef, [8 x i32]* %array_b.lowered, 0 -; CHECK-DAG: %[[ARR:[^ ]+]] = insertvalue [2 x [8 x i32]*] %[[ARR_HALF]], [8 x i32]* %array_c.lowered, 1 +; CHECK-TYPED-PTRS-DAG: %[[ARR_HALF:[^ ]+]] = insertvalue [2 x [8 x i32]*] undef, [8 x i32]* %array_b.lowered, 0 +; CHECK-TYPED-PTRS-DAG: %[[ARR:[^ ]+]] = insertvalue [2 x [8 x i32]*] %[[ARR_HALF]], [8 x i32]* %array_c.lowered, 1 +; CHECK-OPAQUE-PTRS-DAG: %[[ARR_HALF:[^ ]+]] = insertvalue [2 x ptr] undef, ptr %array_b.lowered, 0 +; CHECK-OPAQUE-PTRS-DAG: %[[ARR:[^ ]+]] = insertvalue [2 x ptr] %[[ARR_HALF]], ptr %array_c.lowered, 1 ; COM: lower vector -; CHECK-DAG: %[[VEC_HALF:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_c.lowered, i64 0 -; CHECK-DAG: %[[VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[VEC_HALF]], [8 x i32]* %array_a.lowered, i64 1 +; CHECK-TYPED-PTRS-DAG: %[[VEC_HALF:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_c.lowered, i64 0 +; CHECK-TYPED-PTRS-DAG: %[[VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[VEC_HALF]], [8 x i32]* %array_a.lowered, i64 1 +; CHECK-OPAQUE-PTRS-DAG: %[[VEC_HALF:[^ ]+]] = insertelement <2 x ptr> undef, ptr %array_c.lowered, i64 0 +; CHECK-OPAQUE-PTRS-DAG: %[[VEC:[^ ]+]] = insertelement <2 x ptr> %[[VEC_HALF]], ptr %array_a.lowered, i64 1 ; COM: lower outer struct -; CHECK-DAG: %[[OUT_ST_GEP:[^ ]+]] = insertvalue %struct.outer { i32 23, i32* undef, %struct.inner undef, [2 x [8 x i32]*] undef, <2 x [8 x i32]*> undef }, i32* %[[GEP]], 1 +; CHECK-TYPED-PTRS-DAG: %[[OUT_ST_GEP:[^ ]+]] = insertvalue %struct.outer { i32 23, i32* undef, %struct.inner undef, [2 x [8 x i32]*] undef, <2 x [8 x i32]*> undef }, i32* %[[GEP]], 1 +; CHECK-OPAQUE-PTRS-DAG: %[[OUT_ST_GEP:[^ ]+]] = insertvalue %struct.outer { i32 23, ptr undef, %struct.inner undef, [2 x ptr] undef, <2 x ptr> undef }, ptr %[[GEP]], 1 ; CHECK-DAG: %[[OUT_ST_INN_ST:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_GEP]], %struct.inner %[[INN_ST]], 2 -; CHECK-DAG: %[[OUT_ST_ARR:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_INN_ST]], [2 x [8 x i32]*] %[[ARR]], 3 -; CHECK-DAG: %[[OUT_ST:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_ARR]], <2 x [8 x i32]*> %[[VEC]], 4 +; CHECK-TYPED-PTRS-DAG: %[[OUT_ST_ARR:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_INN_ST]], [2 x [8 x i32]*] %[[ARR]], 3 +; CHECK-TYPED-PTRS-DAG: %[[OUT_ST:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_ARR]], <2 x [8 x i32]*> %[[VEC]], 4 +; CHECK-OPAQUE-PTRS-DAG: %[[OUT_ST_ARR:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_INN_ST]], [2 x ptr] %[[ARR]], 3 +; CHECK-OPAQUE-PTRS-DAG: %[[OUT_ST:[^ ]+]] = insertvalue %struct.outer %[[OUT_ST_ARR]], <2 x ptr> %[[VEC]], 4 -; CHECK: store %struct.outer %[[OUT_ST]], %struct.outer* %ptr.vec +; CHECK-TYPED-PTRS: store %struct.outer %[[OUT_ST]], %struct.outer* %ptr.vec +; CHECK-OPAQUE-PTRS: store %struct.outer %[[OUT_ST]], ptr %ptr.vec ret void } diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/const_expr.ll b/IGC/VectorCompiler/test/GlobalValueLowering/const_expr.ll index 6a24c3a77a01..b6f5754627b6 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/const_expr.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/const_expr.ll @@ -1,31 +1,39 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @simple_global_array = internal global [8 x i32] [i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49], align 4 define dllexport void @simple_array(i64 %provided.offset) { -; CHECK: %simple_global_array.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @simple_global_array) -; CHECK: %simple_global_array.lowered = inttoptr i64 %simple_global_array.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS: %simple_global_array.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @simple_global_array) +; CHECK-TYPED-PTRS: %simple_global_array.lowered = inttoptr i64 %simple_global_array.gaddr to [8 x i32]* +; CHECK-OPAQUE-PTRS: %simple_global_array.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @simple_global_array) +; CHECK-OPAQUE-PTRS: %simple_global_array.lowered = inttoptr i64 %simple_global_array.gaddr to ptr ; COM: bitcast didn't survive IRReader, it was transformed into GEP at the very beginning. Because no one wants you to test bitcast. -; CHECK-DAG: %[[BC_CASE_CONST:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i32 0 -; CHECK-DAG: %[[BC_GEP_CASE_CONST:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i64 3 -; CHECK-DAG: %[[P2I_BC_GEP_CASE_CONST_GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i64 5 -; CHECK-DAG: %[[P2I_BC_GEP_CASE_CONST:[^ ]+]] = ptrtoint i32* %[[P2I_BC_GEP_CASE_CONST_GEP]] to i64 +; CHECK-TYPED-PTRS-DAG: %[[BC_CASE_CONST:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i32 0 +; CHECK-TYPED-PTRS-DAG: %[[BC_GEP_CASE_CONST:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i64 3 +; CHECK-TYPED-PTRS-DAG: %[[P2I_BC_GEP_CASE_CONST_GEP:[^ ]+]] = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.lowered, i32 0, i64 5 +; CHECK-TYPED-PTRS-DAG: %[[P2I_BC_GEP_CASE_CONST:[^ ]+]] = ptrtoint i32* %[[P2I_BC_GEP_CASE_CONST_GEP]] to i64 +; CHECK-OPAQUE-PTRS-DAG: %[[BC_GEP_CASE_CONST:[^ ]+]] = getelementptr inbounds i32, ptr %simple_global_array.lowered, i64 3 +; CHECK-OPAQUE-PTRS-DAG: %[[P2I_BC_GEP_CASE_CONST_GEP:[^ ]+]] = getelementptr inbounds i32, ptr %simple_global_array.lowered, i64 5 +; CHECK-OPAQUE-PTRS-DAG: %[[P2I_BC_GEP_CASE_CONST:[^ ]+]] = ptrtoint ptr %[[P2I_BC_GEP_CASE_CONST_GEP]] to i64 %bc.case = getelementptr inbounds i32, i32* bitcast ([8 x i32]* @simple_global_array to i32*), i64 %provided.offset -; CHECK: %bc.case = getelementptr inbounds i32, i32* %[[BC_CASE_CONST]], i64 %provided.offset +; CHECK-TYPED-PTRS: %bc.case = getelementptr inbounds i32, i32* %[[BC_CASE_CONST]], i64 %provided.offset +; CHECK-OPAQUE-PTRS: %bc.case = getelementptr inbounds i32, ptr %simple_global_array.lowered, i64 %provided.offset %gep.bc.case = ptrtoint i32* getelementptr inbounds (i32, i32* bitcast ([8 x i32]* @simple_global_array to i32*), i64 3) to i64 -; CHECK: %gep.bc.case = ptrtoint i32* %[[BC_GEP_CASE_CONST]] to i64 +; CHECK-TYPED-PTRS: %gep.bc.case = ptrtoint i32* %[[BC_GEP_CASE_CONST]] to i64 +; CHECK-OPAQUE-PTRS: %gep.bc.case = ptrtoint ptr %[[BC_GEP_CASE_CONST]] to i64 %p2i.gep.bc.case = add i64 ptrtoint (i32* getelementptr inbounds (i32, i32* bitcast ([8 x i32]* @simple_global_array to i32*), i64 5) to i64), 1 ; CHECK: %p2i.gep.bc.case = add i64 %[[P2I_BC_GEP_CASE_CONST]], 1 diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/debug.ll b/IGC/VectorCompiler/test/GlobalValueLowering/debug.ll index 6baaec24a4de..3e9e77dfe7c2 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/debug.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/debug.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; ------------------------------------------------ ; GenXGlobalValueLowering ; ------------------------------------------------ @@ -16,17 +17,22 @@ ; Debug MD for this test was created with debugify pass. ; CHECK: void @test_gvlower{{.*}} !dbg [[SCOPE:![0-9]*]] -; CHECK: [[VAL1_V:%[A-z0-9.]*]] = load i32 addrspace(1)*{{.*}}, !dbg [[VAL1_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32 addrspace(1)* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK-TYPED-PTRS: [[VAL1_V:%[A-z0-9.]*]] = load i32 addrspace(1)*{{.*}}, !dbg [[VAL1_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32 addrspace(1)* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK-OPAQUE-PTRS: [[VAL1_V:%[A-z0-9.]*]] = load ptr addrspace(1){{.*}}, !dbg [[VAL1_LOC:![0-9]*]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr addrspace(1) [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] ; CHECK: [[VAL2_V:%[A-z0-9.]*]] = getelementptr {{.*}}, !dbg [[VAL2_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32 addrspace(1)* [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32 addrspace(1)* [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr addrspace(1) [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] ; CHECK: [[VAL3_V:%[A-z0-9.]*]] = call i32 {{.*}}, !dbg [[VAL3_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] ; CHECK: store i32 {{.*}}, !dbg [[STORE1_LOC:![0-9]*]] ; CHECK: [[VAL4_V:%[A-z0-9.]*]] = extractvalue {{.*}}, !dbg [[VAL4_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata [8 x i32]* [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata [8 x i32]* [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] ; CHECK: [[VAL5_V:%[A-z0-9.]*]] = getelementptr {{.*}}, !dbg [[VAL5_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i32* [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i32* [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] ; CHECK: [[VAL6_V:%[A-z0-9.]*]] = load {{.*}}, !dbg [[VAL6_LOC:![0-9]*]] ; CHECK: void @llvm.dbg.value(metadata i32 [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] ; CHECK: store i32 {{.*}}, !dbg [[STORE2_LOC:![0-9]*]] diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr.ll b/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr.ll index 7eef8753d3ec..dc50c8f1cdcf 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -21,13 +22,18 @@ define internal void @func_b() #1 { define dllexport void @simple(i1 %bool) { ; CHECK-LABEL: @simple ; COM: all the lowered function pointers are at the function entry -; CHECK-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_a) -; CHECK-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to void ()* -; CHECK-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_b) -; CHECK-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to void ()* +; CHECK-TYPED-PTRS-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_a) +; CHECK-TYPED-PTRS-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to void ()* +; CHECK-TYPED-PTRS-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_b) +; CHECK-TYPED-PTRS-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to void ()* +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @func_a) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to ptr +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @func_b) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to ptr %func.ptr = select i1 %bool, void ()* @func_a, void ()* @func_b -; CHECK: %func.ptr = select i1 %bool, void ()* %[[PTR_A]], void ()* %[[PTR_B]] +; CHECK-TYPED-PTRS: %func.ptr = select i1 %bool, void ()* %[[PTR_A]], void ()* %[[PTR_B]] +; CHECK-OPAQUE-PTRS: %func.ptr = select i1 %bool, ptr %[[PTR_A]], ptr %[[PTR_B]] call void %func.ptr() ; CHECK: call void %func.ptr() ret void @@ -35,12 +41,18 @@ define dllexport void @simple(i1 %bool) { define dllexport void @ispc_icmp(<4 x i64> %func.ptrs) { ; CHECK-LABEL: @ispc_icmp -; CHECK-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_a) -; CHECK-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to void ()* -; CHECK-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_b) -; CHECK-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to void ()* -; CHECK-DAG: %[[P2I_A:[^ ]+]] = ptrtoint void ()* %[[PTR_A]] to i64 -; CHECK-DAG: %[[P2I_B:[^ ]+]] = ptrtoint void ()* %[[PTR_B]] to i64 +; CHECK-TYPED-PTRS-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_a) +; CHECK-TYPED-PTRS-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to void ()* +; CHECK-TYPED-PTRS-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func_b) +; CHECK-TYPED-PTRS-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to void ()* +; CHECK-TYPED-PTRS-DAG: %[[P2I_A:[^ ]+]] = ptrtoint void ()* %[[PTR_A]] to i64 +; CHECK-TYPED-PTRS-DAG: %[[P2I_B:[^ ]+]] = ptrtoint void ()* %[[PTR_B]] to i64 +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_A:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @func_a) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_A:[^ ]+]] = inttoptr i64 %[[GADDR_A]] to ptr +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_B:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @func_b) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_B:[^ ]+]] = inttoptr i64 %[[GADDR_B]] to ptr +; CHECK-OPAQUE-PTRS-DAG: %[[P2I_A:[^ ]+]] = ptrtoint ptr %[[PTR_A]] to i64 +; CHECK-OPAQUE-PTRS-DAG: %[[P2I_B:[^ ]+]] = ptrtoint ptr %[[PTR_B]] to i64 ; CHECK-DAG: %[[VEC_0:[^ ]+]] = insertelement <4 x i64> undef, i64 %[[P2I_A]], i64 0 ; CHECK-DAG: %[[VEC_1:[^ ]+]] = insertelement <4 x i64> %[[VEC_0]], i64 %[[P2I_B]], i64 1 ; CHECK-DAG: %[[VEC_2:[^ ]+]] = insertelement <4 x i64> %[[VEC_1]], i64 %[[P2I_A]], i64 2 diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr_and_global.ll b/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr_and_global.ll index 12d083fd8981..d0dad8441175 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr_and_global.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/func_ptr_and_global.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck --enable-var-scope %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -19,15 +20,21 @@ define internal void @func() #1 { define dllexport void @simple(void ()** %func.ptr.ptr, i32** %global.ptr.ptr) { ; CHECK-LABEL: @simple ; COM: all the lowered function pointers are at the function entry -; CHECK-DAG: %[[GADDR_FUNC:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func) -; CHECK-DAG: %[[PTR_FUNC:[^ ]+]] = inttoptr i64 %[[GADDR_FUNC]] to void ()* -; CHECK-DAG: %[[GADDR_GLOBAL:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0i32(i32* @global) -; CHECK-DAG: %[[PTR_GLOBAL:[^ ]+]] = inttoptr i64 %[[GADDR_GLOBAL]] to i32* +; CHECK-TYPED-PTRS-DAG: %[[GADDR_FUNC:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0f_isVoidf(void ()* @func) +; CHECK-TYPED-PTRS-DAG: %[[PTR_FUNC:[^ ]+]] = inttoptr i64 %[[GADDR_FUNC]] to void ()* +; CHECK-TYPED-PTRS-DAG: %[[GADDR_GLOBAL:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0i32(i32* @global) +; CHECK-TYPED-PTRS-DAG: %[[PTR_GLOBAL:[^ ]+]] = inttoptr i64 %[[GADDR_GLOBAL]] to i32* +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_FUNC:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @func) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_FUNC:[^ ]+]] = inttoptr i64 %[[GADDR_FUNC]] to ptr +; CHECK-OPAQUE-PTRS-DAG: %[[GADDR_GLOBAL:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @global) +; CHECK-OPAQUE-PTRS-DAG: %[[PTR_GLOBAL:[^ ]+]] = inttoptr i64 %[[GADDR_GLOBAL]] to ptr store void ()* @func, void ()** %func.ptr.ptr, align 8 -; CHECK: store void ()* %[[PTR_FUNC]], void ()** %func.ptr.ptr, align 8 +; CHECK-TYPED-PTRS: store void ()* %[[PTR_FUNC]], void ()** %func.ptr.ptr, align 8 +; CHECK-OPAQUE-PTRS: store ptr %[[PTR_FUNC]], ptr %func.ptr.ptr, align 8 store i32* @global, i32** %global.ptr.ptr, align 8 -; CHECK: store i32* %[[PTR_GLOBAL]], i32** %global.ptr.ptr, align 8 +; CHECK-TYPED-PTRS: store i32* %[[PTR_GLOBAL]], i32** %global.ptr.ptr, align 8 +; CHECK-OPAQUE-PTRS: store ptr %[[PTR_GLOBAL]], ptr %global.ptr.ptr, align 8 ret void } diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/multi_func.ll b/IGC/VectorCompiler/test/GlobalValueLowering/multi_func.ll index 1c103e06bb87..d755d4b337e3 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/multi_func.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/multi_func.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -17,8 +18,10 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ; CHECK-LABEL: define dllexport spir_kernel void @multi_func define dllexport spir_kernel void @multi_func(i64 %provided.offset) #1 { ; COM: all the lowered globals are at the function entry -; CHECK-DAG: %[[KERN_ALL_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_all) -; CHECK-DAG: %[[KERN_FOO_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_foo) +; CHECK-TYPED-PTRS-DAG: %[[KERN_ALL_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_all) +; CHECK-TYPED-PTRS-DAG: %[[KERN_FOO_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_foo) +; CHECK-OPAQUE-PTRS-DAG: %[[KERN_ALL_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_all) +; CHECK-OPAQUE-PTRS-DAG: %[[KERN_FOO_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_foo) %all.ptrtoint = ptrtoint [8 x i32]* @array_all to i64 %all.user = add i64 %all.ptrtoint, 3 @@ -35,7 +38,8 @@ define dllexport spir_kernel void @multi_func(i64 %provided.offset) #1 { ; CHECK-LABEL: define internal spir_func void @foo define internal spir_func void @foo(i64 %provided.offset) { -; CHECK: %array_foo.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_foo) +; CHECK-TYPED-PTRS: %array_foo.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_foo) +; CHECK-OPAQUE-PTRS: %array_foo.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_foo) %foo.ptrtoint = ptrtoint [8 x i32]* @array_foo to i64 %foo.user = add i64 %foo.ptrtoint, 7 @@ -46,7 +50,8 @@ define internal spir_func void @foo(i64 %provided.offset) { ; CHECK-LABEL: define internal spir_func void @bar define internal spir_func void @bar(i64 %provided.offset) { -; CHECK: %[[BAR_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_bar) +; CHECK-TYPED-PTRS: %[[BAR_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_bar) +; CHECK-OPAQUE-PTRS: %[[BAR_GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_bar) %bar.ptrtoint = ptrtoint [8 x i32]* @array_bar to i64 %bar.user = add i64 %bar.ptrtoint, 9 diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/nested_const.ll b/IGC/VectorCompiler/test/GlobalValueLowering/nested_const.ll index 83330ea8fe96..678914857abb 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/nested_const.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/nested_const.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -22,29 +23,45 @@ define dllexport void @simple_array() { [3 x <2 x [8 x i32]*>]* %ptr.vec ; COM: lower global variables -; CHECK-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_a) -; CHECK-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to [8 x i32]* -; CHECK-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_b) -; CHECK-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to [8 x i32]* -; CHECK-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_c) -; CHECK-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_a) +; CHECK-TYPED-PTRS-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_b) +; CHECK-TYPED-PTRS-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to [8 x i32]* +; CHECK-TYPED-PTRS-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @array_c) +; CHECK-TYPED-PTRS-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to [8 x i32]* +; CHECK-OPAQUE-PTRS-DAG: %array_a.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_a) +; CHECK-OPAQUE-PTRS-DAG: %array_a.lowered = inttoptr i64 %array_a.gaddr to ptr +; CHECK-OPAQUE-PTRS-DAG: %array_b.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_b) +; CHECK-OPAQUE-PTRS-DAG: %array_b.lowered = inttoptr i64 %array_b.gaddr to ptr +; CHECK-OPAQUE-PTRS-DAG: %array_c.gaddr = call i64 @llvm.genx.gaddr.i64.p0(ptr @array_c) +; CHECK-OPAQUE-PTRS-DAG: %array_c.lowered = inttoptr i64 %array_c.gaddr to ptr ; COM: lower vectors -; CHECK-DAG: %[[ZER_VEC_A:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_a.lowered, i64 0 -; CHECK-DAG: %[[ZER_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[ZER_VEC_A]], [8 x i32]* %array_b.lowered, i64 1 +; CHECK-TYPED-PTRS-DAG: %[[ZER_VEC_A:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_a.lowered, i64 0 +; CHECK-TYPED-PTRS-DAG: %[[ZER_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[ZER_VEC_A]], [8 x i32]* %array_b.lowered, i64 1 +; CHECK-OPAQUE-PTRS-DAG: %[[ZER_VEC_A:[^ ]+]] = insertelement <2 x ptr> undef, ptr %array_a.lowered, i64 0 +; CHECK-OPAQUE-PTRS-DAG: %[[ZER_VEC:[^ ]+]] = insertelement <2 x ptr> %[[ZER_VEC_A]], ptr %array_b.lowered, i64 1 ; COM: this [[FST_VEC_A]] can be potentially avoided as [[ZER_VEC_A]] is the same -; CHECK-DAG: %[[FST_VEC_B:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_b.lowered, i64 0 -; CHECK-DAG: %[[FST_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[FST_VEC_B:[^ ]+]], [8 x i32]* %array_c.lowered, i64 1 +; CHECK-TYPED-PTRS-DAG: %[[FST_VEC_B:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_b.lowered, i64 0 +; CHECK-TYPED-PTRS-DAG: %[[FST_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[FST_VEC_B:[^ ]+]], [8 x i32]* %array_c.lowered, i64 1 +; CHECK-OPAQUE-PTRS-DAG: %[[FST_VEC_B:[^ ]+]] = insertelement <2 x ptr> undef, ptr %array_b.lowered, i64 0 +; CHECK-OPAQUE-PTRS-DAG: %[[FST_VEC:[^ ]+]] = insertelement <2 x ptr> %[[FST_VEC_B:[^ ]+]], ptr %array_c.lowered, i64 1 -; CHECK-DAG: %[[SND_VEC_C:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_c.lowered, i64 0 -; CHECK-DAG: %[[SND_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[SND_VEC_C]], [8 x i32]* %array_a.lowered, i64 1 +; CHECK-TYPED-PTRS-DAG: %[[SND_VEC_C:[^ ]+]] = insertelement <2 x [8 x i32]*> undef, [8 x i32]* %array_c.lowered, i64 0 +; CHECK-TYPED-PTRS-DAG: %[[SND_VEC:[^ ]+]] = insertelement <2 x [8 x i32]*> %[[SND_VEC_C]], [8 x i32]* %array_a.lowered, i64 1 +; CHECK-OPAQUE-PTRS-DAG: %[[SND_VEC_C:[^ ]+]] = insertelement <2 x ptr> undef, ptr %array_c.lowered, i64 0 +; CHECK-OPAQUE-PTRS-DAG: %[[SND_VEC:[^ ]+]] = insertelement <2 x ptr> %[[SND_VEC_C]], ptr %array_a.lowered, i64 1 ; COM: lower array -; CHECK-DAG: %[[ARR_ZER_VEC:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] undef, <2 x [8 x i32]*> %[[ZER_VEC]], 0 -; CHECK-DAG: %[[ARR_FST_VEC:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] %[[ARR_ZER_VEC]], <2 x [8 x i32]*> %[[FST_VEC]], 1 -; CHECK: %[[ARR:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] %[[ARR_FST_VEC]], <2 x [8 x i32]*> %[[SND_VEC]], 2 +; CHECK-TYPED-PTRS-DAG: %[[ARR_ZER_VEC:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] undef, <2 x [8 x i32]*> %[[ZER_VEC]], 0 +; CHECK-TYPED-PTRS-DAG: %[[ARR_FST_VEC:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] %[[ARR_ZER_VEC]], <2 x [8 x i32]*> %[[FST_VEC]], 1 +; CHECK-TYPED-PTRS: %[[ARR:[^ ]+]] = insertvalue [3 x <2 x [8 x i32]*>] %[[ARR_FST_VEC]], <2 x [8 x i32]*> %[[SND_VEC]], 2 +; CHECK-OPAQUE-PTRS-DAG: %[[ARR_ZER_VEC:[^ ]+]] = insertvalue [3 x <2 x ptr>] undef, <2 x ptr> %[[ZER_VEC]], 0 +; CHECK-OPAQUE-PTRS-DAG: %[[ARR_FST_VEC:[^ ]+]] = insertvalue [3 x <2 x ptr>] %[[ARR_ZER_VEC]], <2 x ptr> %[[FST_VEC]], 1 +; CHECK-OPAQUE-PTRS: %[[ARR:[^ ]+]] = insertvalue [3 x <2 x ptr>] %[[ARR_FST_VEC]], <2 x ptr> %[[SND_VEC]], 2 -; CHECK: store [3 x <2 x [8 x i32]*>] %[[ARR]], [3 x <2 x [8 x i32]*>]* %ptr.vec +; CHECK-TYPED-PTRS: store [3 x <2 x [8 x i32]*>] %[[ARR]], [3 x <2 x [8 x i32]*>]* %ptr.vec +; CHECK-OPAQUE-PTRS: store [3 x <2 x ptr>] %[[ARR]], ptr %ptr.vec ret void } diff --git a/IGC/VectorCompiler/test/GlobalValueLowering/simple_cases.ll b/IGC/VectorCompiler/test/GlobalValueLowering/simple_cases.ll index 46ea2a6c728c..c745b887f74e 100644 --- a/IGC/VectorCompiler/test/GlobalValueLowering/simple_cases.ll +++ b/IGC/VectorCompiler/test/GlobalValueLowering/simple_cases.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXGlobalValueLowering -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -14,16 +15,20 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" define dllexport void @simple_array(i64 %provided.offset) { ; COM: all the lowered globals are at the function entry -; CHECK: %[[GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @simple_global_array) -; CHECK: %[[INTTOPTR:[^ ]+]] = inttoptr i64 %[[GADDR]] to [8 x i32]* +; CHECK-TYPED-PTRS: %[[GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0a8i32([8 x i32]* @simple_global_array) +; CHECK-TYPED-PTRS: %[[INTTOPTR:[^ ]+]] = inttoptr i64 %[[GADDR]] to [8 x i32]* +; CHECK-OPAQUE-PTRS: %[[GADDR:[^ ]+]] = call i64 @llvm.genx.gaddr.i64.p0(ptr @simple_global_array) +; CHECK-OPAQUE-PTRS: %[[INTTOPTR:[^ ]+]] = inttoptr i64 %[[GADDR]] to ptr %ptrtoint.case = ptrtoint [8 x i32]* @simple_global_array to i64 ; COM: optimized out -; CHECK-NOT: %ptrtoint.case = ptrtoint [8 x i32]* @simple_global_array to i64 +; CHECK-TYPED-PTRS-NOT: %ptrtoint.case = ptrtoint [8 x i32]* @simple_global_array to i64 +; CHECK-OPAQUE-PTRS-NOT: %ptrtoint.case = ptrtoint ptr @simple_global_array to i64 %ptrtoint.case.user = add i64 %ptrtoint.case, 3 ; CHECK: %ptrtoint.case.user = add i64 %[[GADDR]], 3 %gep.case = getelementptr inbounds [8 x i32], [8 x i32]* @simple_global_array, i64 0, i64 %provided.offset -; CHECK: %gep.case = getelementptr inbounds [8 x i32], [8 x i32]* %[[INTTOPTR]], i64 0, i64 %provided.offset +; CHECK-TYPED-PTRS: %gep.case = getelementptr inbounds [8 x i32], [8 x i32]* %[[INTTOPTR]], i64 0, i64 %provided.offset +; CHECK-OPAQUE-PTRS: %gep.case = getelementptr inbounds [8 x i32], ptr %[[INTTOPTR]], i64 0, i64 %provided.offset ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/const_expr.ll b/IGC/VectorCompiler/test/GlobalsLocalization/const_expr.ll index e0b31c23f1e6..7694f74bdc55 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/const_expr.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/const_expr.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -15,11 +16,13 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" define dllexport void @const_expr() { ; CHECK: %[[ALLOCA:[^ ]+]] = alloca <256 x i8>, align 256 -; CHECK: store <256 x i8> zeroinitializer, <256 x i8>* %[[ALLOCA]] +; CHECK-TYPED-PTRS: store <256 x i8> zeroinitializer, <256 x i8>* %[[ALLOCA]] +; CHECK-OPAQUE-PTRS: store <256 x i8> zeroinitializer, ptr %[[ALLOCA]] %ld = load <64 x i32>, <64 x i32>* bitcast (<256 x i8>* @gvec to <64 x i32>*), align 256 -; CHECK: %[[BC:[^ ]+]] = bitcast <256 x i8>* %[[ALLOCA]] to <64 x i32>* -; CHECK: %ld = load <64 x i32>, <64 x i32>* %[[BC]], align 256 +; CHECK-TYPED-PTRS: %[[BC:[^ ]+]] = bitcast <256 x i8>* %[[ALLOCA]] to <64 x i32>* +; CHECK-TYPED-PTRS: %ld = load <64 x i32>, <64 x i32>* %[[BC]], align 256 +; CHECK-OPAQUE-PTRS: %ld = load <64 x i32>, ptr %[[ALLOCA]], align 256 ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/extern_impl_params.ll b/IGC/VectorCompiler/test/GlobalsLocalization/extern_impl_params.ll index 1f25b9000117..012f94e23f4a 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/extern_impl_params.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/extern_impl_params.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" @@ -32,10 +33,12 @@ define dllexport spir_kernel void @loc_sz_overlap(i64 %privBase, <3 x i32> %__ar ; CHECK-NOT: alloca store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* @__imparg_llvm.genx.local.size -; CHECK: store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %__arg_llvm.genx.local.size, ptr %__imparg_llvm.genx.local.size.local call void @internal_loc_sz() -; CHECK: %__imparg_llvm.genx.local.size.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: %__imparg_llvm.genx.local.size.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: %__imparg_llvm.genx.local.size.val = load <3 x i32>, ptr %__imparg_llvm.genx.local.size.local ; CHECK: call {{.*}} @internal_loc_sz(<3 x i32> %__imparg_llvm.genx.local.size.val) call void @external_loc_size_loc_id() @@ -53,13 +56,17 @@ define spir_func void @external_loc_size_loc_id() #0 { %elsli.get.loc.sz = call <3 x i32> @get_loc_sz() store <3 x i16> %elsli.get.loc.id, <3 x i16>* @__imparg_llvm.genx.local.id16 store <3 x i32> %elsli.get.loc.sz, <3 x i32>* @__imparg_llvm.genx.local.size -; CHECK: store <3 x i16> %elsli.get.loc.id, <3 x i16>* %__imparg_llvm.genx.local.id16.local -; CHECK: store <3 x i32> %elsli.get.loc.sz, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: store <3 x i16> %elsli.get.loc.id, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: store <3 x i32> %elsli.get.loc.sz, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: store <3 x i16> %elsli.get.loc.id, ptr %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %elsli.get.loc.sz, ptr %__imparg_llvm.genx.local.size.local %elsli.loc.id = load <3 x i16>, <3 x i16>* @__imparg_llvm.genx.local.id16 %elsli.loc.sz = load <3 x i32>, <3 x i32>* @__imparg_llvm.genx.local.size -; CHECK: %elsli.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local -; CHECK: %elsli.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: %elsli.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: %elsli.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: %elsli.loc.id = load <3 x i16>, ptr %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: %elsli.loc.sz = load <3 x i32>, ptr %__imparg_llvm.genx.local.size.local ret void } @@ -84,15 +91,19 @@ define spir_func void @external_indir_use() #0 { %eiu.get.loc.sz = call <3 x i32> @get_loc_sz() store <3 x i16> %eiu.get.loc.id, <3 x i16>* @__imparg_llvm.genx.local.id16 store <3 x i32> %eiu.get.loc.sz, <3 x i32>* @__imparg_llvm.genx.local.size -; CHECK: store <3 x i16> %eiu.get.loc.id, <3 x i16>* %__imparg_llvm.genx.local.id16.local -; CHECK: store <3 x i32> %eiu.get.loc.sz, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: store <3 x i16> %eiu.get.loc.id, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: store <3 x i32> %eiu.get.loc.sz, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: store <3 x i16> %eiu.get.loc.id, ptr %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %eiu.get.loc.sz, ptr %__imparg_llvm.genx.local.size.local call void @internal_loc_sz() -; CHECK: %__imparg_llvm.genx.local.size.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: %__imparg_llvm.genx.local.size.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: %__imparg_llvm.genx.local.size.val = load <3 x i32>, ptr %__imparg_llvm.genx.local.size.local ; CHECK: call {{.*}} @internal_loc_sz(<3 x i32> %__imparg_llvm.genx.local.size.val) call void @internal_loc_id() -; CHECK: %__imparg_llvm.genx.local.id16.val = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: %__imparg_llvm.genx.local.id16.val = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: %__imparg_llvm.genx.local.id16.val = load <3 x i16>, ptr %__imparg_llvm.genx.local.id16.local ; CHECK: call {{.*}} @internal_loc_id(<3 x i16> %__imparg_llvm.genx.local.id16.val) ret void } @@ -106,14 +117,18 @@ define spir_func void @external_mixed_use() #0 { %emu.get.grp.cnt = call <3 x i32> @get_grp_cnt() store i64 %emu.get.printf.ptr, i64* @__imparg_llvm.vc.internal.print.buffer store <3 x i32> %emu.get.grp.cnt, <3 x i32>* @__imparg_llvm.genx.group.count -; CHECK: store i64 %emu.get.printf.ptr, i64* %__imparg_llvm.vc.internal.print.buffer.local -; CHECK: store <3 x i32> %emu.get.grp.cnt, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: store i64 %emu.get.printf.ptr, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-TYPED-PTRS: store <3 x i32> %emu.get.grp.cnt, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: store i64 %emu.get.printf.ptr, ptr %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %emu.get.grp.cnt, ptr %__imparg_llvm.genx.group.count.local %emu.printf.ptr = load i64, i64* @__imparg_llvm.vc.internal.print.buffer -; CHECK: %emu.printf.ptr = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-TYPED-PTRS: %emu.printf.ptr = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-OPAQUE-PTRS: %emu.printf.ptr = load i64, ptr %__imparg_llvm.vc.internal.print.buffer.local call void @internal_grp_cnt() -; CHECK: %__imparg_llvm.genx.group.count.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: %__imparg_llvm.genx.group.count.val = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: %__imparg_llvm.genx.group.count.val = load <3 x i32>, ptr %__imparg_llvm.genx.group.count.local ; CHECK: call {{.*}} @internal_grp_cnt(<3 x i32> %__imparg_llvm.genx.group.count.val) ret void } @@ -121,30 +136,36 @@ define spir_func void @external_mixed_use() #0 { define internal spir_func void @internal_loc_sz() #0 { ; CHECK-LABEL: define internal spir_func {{.*}} @internal_loc_sz(<3 x i32> %__imparg_llvm.genx.local.size.in) ; CHECK: %__imparg_llvm.genx.local.size.local = alloca <3 x i32> -; CHECK: store <3 x i32> %__imparg_llvm.genx.local.size.in, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: store <3 x i32> %__imparg_llvm.genx.local.size.in, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %__imparg_llvm.genx.local.size.in, ptr %__imparg_llvm.genx.local.size.local %ils.loc.sz = load <3 x i32>, <3 x i32>* @__imparg_llvm.genx.local.size -; CHECK: %ils.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: %ils.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: %ils.loc.sz = load <3 x i32>, ptr %__imparg_llvm.genx.local.size.local ret void } define internal spir_func void @internal_loc_id() #0 { ; CHECK-LABEL: define internal spir_func {{.*}} @internal_loc_id(<3 x i16> %__imparg_llvm.genx.local.id16.in) ; CHECK: %__imparg_llvm.genx.local.id16.local = alloca <3 x i16> -; CHECK: store <3 x i16> %__imparg_llvm.genx.local.id16.in, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: store <3 x i16> %__imparg_llvm.genx.local.id16.in, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: store <3 x i16> %__imparg_llvm.genx.local.id16.in, ptr %__imparg_llvm.genx.local.id16.local %ili.loc.id = load <3 x i16>, <3 x i16>* @__imparg_llvm.genx.local.id16 -; CHECK: %ili.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: %ili.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: %ili.loc.id = load <3 x i16>, ptr %__imparg_llvm.genx.local.id16.local ret void } define internal spir_func void @internal_grp_cnt() #0 { ; CHECK-LABEL: define internal spir_func {{.*}} @internal_grp_cnt(<3 x i32> %__imparg_llvm.genx.group.count.in) ; CHECK: %__imparg_llvm.genx.group.count.local = alloca <3 x i32> -; CHECK: store <3 x i32> %__imparg_llvm.genx.group.count.in, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: store <3 x i32> %__imparg_llvm.genx.group.count.in, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %__imparg_llvm.genx.group.count.in, ptr %__imparg_llvm.genx.group.count.local %igc.loc.id = load <3 x i32>, <3 x i32>* @__imparg_llvm.genx.group.count -; CHECK: %igc.loc.id = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: %igc.loc.id = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: %igc.loc.id = load <3 x i32>, ptr %__imparg_llvm.genx.group.count.local ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/func_with_taken_addr.ll b/IGC/VectorCompiler/test/GlobalsLocalization/func_with_taken_addr.ll index 5021d3911c7f..155c92862515 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/func_with_taken_addr.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/func_with_taken_addr.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -42,7 +43,8 @@ define internal spir_func void @indirect() { %indirect.get.ptr = call i64 @get_printf_ptr() store i64 %indirect.get.ptr, i64* @__imparg_llvm.vc.internal.print.buffer, align 8 %indirect.int.load = load i64, i64* @__imparg_llvm.vc.internal.print.buffer, align 8 -; CHECK: %indirect.int.load = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local, align 8 +; CHECK-TYPED-PTRS: %indirect.int.load = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local, align 8 +; CHECK-OPAQUE-PTRS: %indirect.int.load = load i64, ptr %__imparg_llvm.vc.internal.print.buffer.local, align 8 ret void } @@ -50,12 +52,15 @@ define internal spir_func void @indirect() { define dllexport spir_kernel void @foo_kernel() { ; CHECK-LABEL: define dllexport spir_kernel void @foo_kernel() { ; CHECK: %simple_const_float.local = alloca float, align 4 -; CHECK: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-TYPED-PTRS: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS: store float 4.200000e+01, ptr %simple_const_float.local ; CHECK: %simple_global_int.local = alloca i32, align 4 -; CHECK: store i32 42, i32* %simple_global_int.local +; CHECK-TYPED-PTRS: store i32 42, i32* %simple_global_int.local +; CHECK-OPAQUE-PTRS: store i32 42, ptr %simple_global_int.local %ret.val = call spir_func float @bar() ; COM: no need to store into a constant float -; CHECK-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-TYPED-PTRS-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS-NOT: store float %{{[^ ]+}}, ptr %simple_const_float.local %just.use = fadd float %ret.val, 1.000000e+00 %indirect.user = ptrtoint void ()* @indirect to i32 ret void diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/impl_params.ll b/IGC/VectorCompiler/test/GlobalsLocalization/impl_params.ll index 4d24161b6b0c..2f617278ac55 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/impl_params.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/impl_params.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "spir64-unknown-unknown" @@ -28,19 +29,27 @@ define dllexport spir_kernel void @direct(i64 %privBase, <3 x i16> %__arg_llvm.g store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* @__imparg_llvm.genx.local.size store i64 %__arg_llvm.vc.internal.print.buffer, i64* @__imparg_llvm.vc.internal.print.buffer store <3 x i32> %__arg_llvm.genx.group.count, <3 x i32>* @__imparg_llvm.genx.group.count -; CHECK: store <3 x i16> %__arg_llvm.genx.local.id16, <3 x i16>* %__imparg_llvm.genx.local.id16.local -; CHECK: store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* %__imparg_llvm.genx.local.size.local -; CHECK: store i64 %__arg_llvm.vc.internal.print.buffer, i64* %__imparg_llvm.vc.internal.print.buffer.local -; CHECK: store <3 x i32> %__arg_llvm.genx.group.count, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: store <3 x i16> %__arg_llvm.genx.local.id16, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: store <3 x i32> %__arg_llvm.genx.local.size, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: store i64 %__arg_llvm.vc.internal.print.buffer, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-TYPED-PTRS: store <3 x i32> %__arg_llvm.genx.group.count, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: store <3 x i16> %__arg_llvm.genx.local.id16, ptr %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %__arg_llvm.genx.local.size, ptr %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: store i64 %__arg_llvm.vc.internal.print.buffer, ptr %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-OPAQUE-PTRS: store <3 x i32> %__arg_llvm.genx.group.count, ptr %__imparg_llvm.genx.group.count.local %d.loc.id = load <3 x i16>, <3 x i16>* @__imparg_llvm.genx.local.id16 %d.loc.sz = load <3 x i32>, <3 x i32>* @__imparg_llvm.genx.local.size %d.grp.sz = load <3 x i32>, <3 x i32>* @__imparg_llvm.genx.group.count %d.print = load i64, i64* @__imparg_llvm.vc.internal.print.buffer -; CHECK: %d.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local -; CHECK: %d.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local -; CHECK: %d.grp.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local -; CHECK: %d.print = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-TYPED-PTRS: %d.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: %d.loc.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.local.size.local +; CHECK-TYPED-PTRS: %d.grp.sz = load <3 x i32>, <3 x i32>* %__imparg_llvm.genx.group.count.local +; CHECK-TYPED-PTRS: %d.print = load i64, i64* %__imparg_llvm.vc.internal.print.buffer.local +; CHECK-OPAQUE-PTRS: %d.loc.id = load <3 x i16>, ptr %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: %d.loc.sz = load <3 x i32>, ptr %__imparg_llvm.genx.local.size.local +; CHECK-OPAQUE-PTRS: %d.grp.sz = load <3 x i32>, ptr %__imparg_llvm.genx.group.count.local +; CHECK-OPAQUE-PTRS: %d.print = load i64, ptr %__imparg_llvm.vc.internal.print.buffer.local ret void } @@ -59,10 +68,12 @@ define dllexport spir_kernel void @indir(i64 %privBase, i64 %__arg_llvm.vc.inter define internal spir_func void @indir_func_1() #0 { ; CHECK: define internal spir_func {{.*}} @indir_func_1(<3 x i16> %__imparg_llvm.genx.local.id16.in) ; CHECK: %__imparg_llvm.genx.local.id16.local = alloca <3 x i16> -; CHECK: store <3 x i16> %__imparg_llvm.genx.local.id16.in, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: store <3 x i16> %__imparg_llvm.genx.local.id16.in, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: store <3 x i16> %__imparg_llvm.genx.local.id16.in, ptr %__imparg_llvm.genx.local.id16.local %i.1.loc.id = load <3 x i16>, <3 x i16>* @__imparg_llvm.genx.local.id16 -; CHECK: %i.1.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-TYPED-PTRS: %i.1.loc.id = load <3 x i16>, <3 x i16>* %__imparg_llvm.genx.local.id16.local +; CHECK-OPAQUE-PTRS: %i.1.loc.id = load <3 x i16>, ptr %__imparg_llvm.genx.local.id16.local ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/mixed.ll b/IGC/VectorCompiler/test/GlobalsLocalization/mixed.ll index e1851ed8de8b..2747e2b93ec9 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/mixed.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/mixed.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -40,17 +41,23 @@ define dllexport void @simple_partial(i64 %provided_offset) { ; CHECK-DAG: %[[ALLOCA_VEC_A:[^ ]+]] = alloca <32 x i8> %gep.int.a = getelementptr inbounds i16, i16* @global.int.a, i64 0 -; CHECK: %gep.int.a = getelementptr inbounds i16, i16* %[[ALLOCA_INT_A]], i64 0 +; CHECK-TYPED-PTRS: %gep.int.a = getelementptr inbounds i16, i16* %[[ALLOCA_INT_A]], i64 0 +; CHECK-OPAQUE-PTRS: %gep.int.a = getelementptr inbounds i16, ptr %[[ALLOCA_INT_A]], i64 0 %gep.int.b = getelementptr inbounds i32, i32* @global.int.b, i64 0 -; CHECK-NEXT: %gep.int.b = getelementptr inbounds i32, i32* %[[ALLOCA_INT_B]], i64 0 +; CHECK-TYPED-PTRS-NEXT: %gep.int.b = getelementptr inbounds i32, i32* %[[ALLOCA_INT_B]], i64 0 +; CHECK-OPAQUE-PTRS-NEXT: %gep.int.b = getelementptr inbounds i32, ptr %[[ALLOCA_INT_B]], i64 0 %gep.arr.a = getelementptr inbounds [8 x i8], [8 x i8]* @global.arr.a, i64 0, i64 %provided_offset -; CHECK-NEXT: %gep.arr.a = getelementptr inbounds [8 x i8], [8 x i8]* %[[ALLOCA_ARR_A]], i64 0, i64 %provided_offset +; CHECK-TYPED-PTRS-NEXT: %gep.arr.a = getelementptr inbounds [8 x i8], [8 x i8]* %[[ALLOCA_ARR_A]], i64 0, i64 %provided_offset +; CHECK-OPAQUE-PTRS-NEXT: %gep.arr.a = getelementptr inbounds [8 x i8], ptr %[[ALLOCA_ARR_A]], i64 0, i64 %provided_offset %gep.arr.b = getelementptr inbounds [16 x i8], [16 x i8]* @global.arr.b, i64 0, i64 %provided_offset -; CHECK-NEXT: %gep.arr.b = getelementptr inbounds [16 x i8], [16 x i8]* %[[ALLOCA_ARR_B]], i64 0, i64 %provided_offset +; CHECK-TYPED-PTRS-NEXT: %gep.arr.b = getelementptr inbounds [16 x i8], [16 x i8]* %[[ALLOCA_ARR_B]], i64 0, i64 %provided_offset +; CHECK-OPAQUE-PTRS-NEXT: %gep.arr.b = getelementptr inbounds [16 x i8], ptr %[[ALLOCA_ARR_B]], i64 0, i64 %provided_offset %ld.vec.a = load <32 x i8>, <32 x i8>* @global.vec.a -; CHECK-NEXT: %ld.vec.a = load <32 x i8>, <32 x i8>* %[[ALLOCA_VEC_A]] +; CHECK-TYPED-PTRS-NEXT: %ld.vec.a = load <32 x i8>, <32 x i8>* %[[ALLOCA_VEC_A]] +; CHECK-OPAQUE-PTRS-NEXT: %ld.vec.a = load <32 x i8>, ptr %[[ALLOCA_VEC_A]] %ld.vec.c = call <16 x i8> @llvm.genx.vload.v15i8.p0v15i8(<16 x i8>* @volatile.vec.c) -; CHECK: %ld.vec.c = call <16 x i8> @llvm.genx.vload.v15i8.p0v15i8(<16 x i8>* @volatile.vec.c) +; CHECK-TYPED-PTRS: %ld.vec.c = call <16 x i8> @llvm.genx.vload.v15i8.p0v15i8(<16 x i8>* @volatile.vec.c) +; CHECK-OPAQUE-PTRS: %ld.vec.c = call <16 x i8> @llvm.genx.vload.v15i8.p0v15i8(ptr @volatile.vec.c) ; CHECK-NOT: @global.int.a ; CHECK-NOT: @global.int.b ; CHECK-NOT: @global.arr.a diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array.ll b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array.ll index 5f913ace60db..26d3f198a3b7 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -18,11 +19,14 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ; Function Attrs: noinline nounwind define dllexport void @simple_array(i64 %provided_offset) { ; CHECK: %simple_global_array.local = alloca [8 x i32], align 4 -; CHECK-NEXT: store [8 x i32] [i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49], [8 x i32]* %simple_global_array.local +; CHECK-TYPED-PTRS-NEXT: store [8 x i32] [i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49], [8 x i32]* %simple_global_array.local +; CHECK-OPAQUE-PTRS-NEXT: store [8 x i32] [i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49], ptr %simple_global_array.local %ptr = getelementptr inbounds [8 x i32], [8 x i32]* @simple_global_array, i64 0, i64 %provided_offset -; CHECK-NEXT: %ptr = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.local, i64 0, i64 %provided_offset +; CHECK-TYPED-PTRS-NEXT: %ptr = getelementptr inbounds [8 x i32], [8 x i32]* %simple_global_array.local, i64 0, i64 %provided_offset +; CHECK-OPAQUE-PTRS-NEXT: %ptr = getelementptr inbounds [8 x i32], ptr %simple_global_array.local, i64 0, i64 %provided_offset %val = load i32, i32* %ptr, align 4 -; CHECK-NEXT: %val = load i32, i32* %ptr, align 4 +; CHECK-TYPED-PTRS-NEXT: %val = load i32, i32* %ptr, align 4 +; CHECK-OPAQUE-PTRS-NEXT: %val = load i32, ptr %ptr, align 4 ; CHECK-NOT: @simple_global_array ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace.ll b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace.ll index ccc034dca781..4c3cd6e21d85 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -17,11 +18,14 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ; Function Attrs: noinline nounwind define dllexport void @simple_array(i64 %provided_offset) { %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided_offset -; CHECK: %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided_offset +; CHECK-TYPED-PTRS: %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided_offset +; CHECK-OPAQUE-PTRS: %ptr = getelementptr inbounds [8 x i32], ptr addrspace(2) @simple_global_array, i64 0, i64 %provided_offset %ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* -; CHECK: %ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* +; CHECK-TYPED-PTRS: %ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* +; CHECK-OPAQUE-PTRS: %ptr.cast = bitcast ptr addrspace(2) %ptr to ptr addrspace(2) %val = load i8, i8 addrspace(2)* %ptr.cast, align 4 -; CHECK: %val = load i8, i8 addrspace(2)* %ptr.cast, align 4 +; CHECK-TYPED-PTRS: %val = load i8, i8 addrspace(2)* %ptr.cast, align 4 +; CHECK-OPAQUE-PTRS: %val = load i8, ptr addrspace(2) %ptr.cast, align 4 %val.use = add i8 %val, 1 ; CHECK: %val.use = add i8 %val, 1 ret void diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace_nested_ifs.ll b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace_nested_ifs.ll index dd9381419d66..7c7acf1b4452 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace_nested_ifs.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/simple_array_addrspace_nested_ifs.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -18,47 +19,55 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" define dllexport void @simple_array(i64 %provided.offset) { entry: %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided.offset -; CHECK: %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided.offset +; CHECK-TYPED-PTRS: %ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %provided.offset +; CHECK-OPAQUE-PTRS: %ptr = getelementptr inbounds [8 x i32], ptr addrspace(2) @simple_global_array, i64 0, i64 %provided.offset %level.0.cmp = icmp slt i64 %provided.offset, 4 br i1 %level.0.cmp, label %level.1.less.4, label %level.1.greater.equal.4 level.1.less.4: ; preds = %entry %level.1.ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* -; CHECK-DAG: %level.1.ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* +; CHECK-TYPED-PTRS-DAG: %level.1.ptr.cast = bitcast i32 addrspace(2)* %ptr to i8 addrspace(2)* +; CHECK-OPAQUE-PTRS-DAG: %level.1.ptr.cast = bitcast ptr addrspace(2) %ptr to ptr addrspace(2) %level.1.less.4.cmp = icmp slt i64 %provided.offset, -1 br i1 %level.1.less.4.cmp, label %level.2.less.min.1, label %level.2.greater.equal.min.1 level.2.less.min.1: ; preds = %level.1.less.4 %level.2.val = load i8, i8 addrspace(2)* %level.1.ptr.cast, align 4 -; CHECK-DAG: %level.2.val = load i8, i8 addrspace(2)* %level.1.ptr.cast, align 4 +; CHECK-TYPED-PTRS-DAG: %level.2.val = load i8, i8 addrspace(2)* %level.1.ptr.cast, align 4 +; CHECK-OPAQUE-PTRS-DAG: %level.2.val = load i8, ptr addrspace(2) %level.1.ptr.cast, align 4 %level.2.val.use = add i8 %level.2.val, 1 ; CHECK-DAG: %level.2.val.use = add i8 %level.2.val, 1 br label %exit level.2.greater.equal.min.1: ; preds = %level.1.less.4 %level.2.ptr.cast.back = bitcast i8 addrspace(2)* %level.1.ptr.cast to i32 addrspace(2)* -; CHECK-DAG: %level.2.ptr.cast.back = bitcast i8 addrspace(2)* %level.1.ptr.cast to i32 addrspace(2)* +; CHECK-TYPED-PTRS-DAG: %level.2.ptr.cast.back = bitcast i8 addrspace(2)* %level.1.ptr.cast to i32 addrspace(2)* +; CHECK-OPAQUE-PTRS-DAG: %level.2.ptr.cast.back = bitcast ptr addrspace(2) %level.1.ptr.cast to ptr addrspace(2) br label %exit level.1.greater.equal.4: ; preds = %entry %shifted.offset = add nsw i64 %provided.offset, -1 %level.1.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %shifted.offset -; CHECK-DAG: %level.1.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %shifted.offset +; CHECK-TYPED-PTRS-DAG: %level.1.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %shifted.offset +; CHECK-OPAQUE-PTRS-DAG: %level.1.ptr = getelementptr inbounds [8 x i32], ptr addrspace(2) @simple_global_array, i64 0, i64 %shifted.offset %level.1.greater.equal.4.cmp = icmp sgt i64 %provided.offset, 7 br i1 %level.1.greater.equal.4.cmp, label %level.2.greater.7, label %level.2.less.equal.7 level.2.less.equal.7: ; preds = %level.1.greater.equal.4 %level.2.less.equal.7.val = load i32, i32 addrspace(2)* %level.1.ptr, align 4 -; CHECK-DAG: %level.2.less.equal.7.val = load i32, i32 addrspace(2)* %level.1.ptr, align 4 +; CHECK-TYPED-PTRS-DAG: %level.2.less.equal.7.val = load i32, i32 addrspace(2)* %level.1.ptr, align 4 +; CHECK-OPAQUE-PTRS-DAG: %level.2.less.equal.7.val = load i32, ptr addrspace(2) %level.1.ptr, align 4 %level.2.less.equal.7.val.use = add i32 %level.2.less.equal.7.val, 1 ; CHECK-DAG: %level.2.less.equal.7.val.use = add i32 %level.2.less.equal.7.val, 1 br label %exit level.2.greater.7: ; preds = %level.1.greater.equal.4 %level.2.greater.7.ptr.cast = bitcast i32 addrspace(2)* %level.1.ptr to i8 addrspace(2)* -; CHECK-DAG: %level.2.greater.7.ptr.cast = bitcast i32 addrspace(2)* %level.1.ptr to i8 addrspace(2)* +; CHECK-TYPED-PTRS-DAG: %level.2.greater.7.ptr.cast = bitcast i32 addrspace(2)* %level.1.ptr to i8 addrspace(2)* +; CHECK-OPAQUE-PTRS-DAG: %level.2.greater.7.ptr.cast = bitcast ptr addrspace(2) %level.1.ptr to ptr addrspace(2) %level.2.greater.7.val = load i8, i8 addrspace(2)* %level.2.greater.7.ptr.cast, align 4 -; CHEKC-DAG: %level.2.greater.7.val = load i8, i8 addrspace(2)* %level.2.greater.7.ptr.cast, align 4 +; CHECK-TYPED-PTRS-DAG: %level.2.greater.7.val = load i8, i8 addrspace(2)* %level.2.greater.7.ptr.cast, align 4 +; CHECK-OPAQUE-PTRS-DAG: %level.2.greater.7.val = load i8, ptr addrspace(2) %level.2.greater.7.ptr.cast, align 4 %level.2.greater.7.val.use = add i8 %level.2.greater.7.val, 1 ; CHECK-DAG: %level.2.greater.7.val.use = add i8 %level.2.greater.7.val, 1 br label %exit diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_composite_addrspace.ll b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_composite_addrspace.ll index a0f958c88b76..768f4271a08e 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_composite_addrspace.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_composite_addrspace.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -18,7 +19,8 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" define internal spir_func i32 @bar(i64 %passed.offset) { ; CHECK: define internal spir_func i32 @bar(i64 %passed.offset) { %elem.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %passed.offset -; CHECK: %elem.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %passed.offset +; CHECK-TYPED-PTRS: %elem.ptr = getelementptr inbounds [8 x i32], [8 x i32] addrspace(2)* @simple_global_array, i64 0, i64 %passed.offset +; CHECK-OPAQUE-PTRS: %elem.ptr = getelementptr inbounds [8 x i32], ptr addrspace(2) @simple_global_array, i64 0, i64 %passed.offset %elem = load i32, i32 addrspace(2)* %elem.ptr, align 4 ret i32 %elem } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite.ll b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite.ll index e87ead04ab70..ba9c23b40a77 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -29,12 +30,15 @@ define internal spir_func float @bar() { ; Function Attrs: noinline nounwind define dllexport void @foo_kernel() { ; CHECK: %simple_const_float.local = alloca float, align 4 -; CHECK: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-TYPED-PTRS: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS: store float 4.200000e+01, ptr %simple_const_float.local ; CHECK: %simple_global_int.local = alloca i32, align 4 -; CHECK: store i32 42, i32* %simple_global_int.local +; CHECK-TYPED-PTRS: store i32 42, i32* %simple_global_int.local +; CHECK-OPAQUE-PTRS: store i32 42, ptr %simple_global_int.local %ret.val = call spir_func float @bar() ; COM: no need to store into a constant float -; CHECK-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-TYPED-PTRS-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS-NOT: store float %{{[^ ]+}}, ptr %simple_const_float.local %just.use = fadd float %ret.val, 1.000000e+00 ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite_addrspace.ll b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite_addrspace.ll index 7f61b2be9cb9..d0dcff23e957 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite_addrspace.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/subroutine_noncomposite_addrspace.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -29,10 +30,12 @@ define internal spir_func float @bar() { ; Function Attrs: noinline nounwind define dllexport void @foo_kernel() { ; CHECK: %simple_const_float.local = alloca float, align 4 -; CHECK: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-TYPED-PTRS: store float 4.200000e+01, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS: store float 4.200000e+01, ptr %simple_const_float.local %ret.val = call spir_func float @bar() ; COM: no need to store into a constant float -; CHECK-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-TYPED-PTRS-NOT: store float %{{[^ ]+}}, float* %simple_const_float.local +; CHECK-OPAQUE-PTRS-NOT: store float %{{[^ ]+}}, ptr %simple_const_float.local %just.use = fadd float %ret.val, 1.000000e+00 ret void } diff --git a/IGC/VectorCompiler/test/GlobalsLocalization/vector_of_pointers.ll b/IGC/VectorCompiler/test/GlobalsLocalization/vector_of_pointers.ll index b6c364695917..ad50a7e45fe7 100644 --- a/IGC/VectorCompiler/test/GlobalsLocalization/vector_of_pointers.ll +++ b/IGC/VectorCompiler/test/GlobalsLocalization/vector_of_pointers.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -cmabi -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -21,15 +22,20 @@ declare void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float>, <8 x float*>, i32 i ; Function Attrs: noinline nounwind define dllexport void @simple_case(<8 x i64> %offsets) { ; CHECK: %[[SIMPLE_ALLOCA:[^ ]+]] = alloca [210 x i32] -; CHECK-NEXT: store [210 x i32] zeroinitializer, [210 x i32]* %[[SIMPLE_ALLOCA]] +; CHECK-TYPED-PTRS-NEXT: store [210 x i32] zeroinitializer, [210 x i32]* %[[SIMPLE_ALLOCA]] +; CHECK-OPAQUE-PTRS-NEXT: store [210 x i32] zeroinitializer, ptr %[[SIMPLE_ALLOCA]] %gep = getelementptr [210 x i32], [210 x i32]* @table, <8 x i64> zeroinitializer, <8 x i64> %offsets -; CHECK-NEXT: %gep = getelementptr [210 x i32], [210 x i32]* %[[SIMPLE_ALLOCA]], <8 x i64> zeroinitializer, <8 x i64> %offsets +; CHECK-TYPED-PTRS-NEXT: %gep = getelementptr [210 x i32], [210 x i32]* %[[SIMPLE_ALLOCA]], <8 x i64> zeroinitializer, <8 x i64> %offsets +; CHECK-OPAQUE-PTRS-NEXT: %gep = getelementptr [210 x i32], ptr %[[SIMPLE_ALLOCA]], <8 x i64> zeroinitializer, <8 x i64> %offsets %bc = bitcast <8 x i32*> %gep to <8 x float*> -; CHECK-NEXT: %bc = bitcast <8 x i32*> %gep to <8 x float*> +; CHECK-TYPED-PTRS-NEXT: %bc = bitcast <8 x i32*> %gep to <8 x float*> +; CHECK-OPAQUE-PTRS-NEXT: %bc = bitcast <8 x ptr> %gep to <8 x ptr> %val = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %bc, i32 4, <8 x i1> , <8 x float> undef) -; CHECK-NEXT: %val = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %bc, i32 4, <8 x i1> , <8 x float> undef) +; CHECK-TYPED-PTRS-NEXT: %val = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %bc, i32 4, <8 x i1> , <8 x float> undef) +; CHECK-OPAQUE-PTRS-NEXT: %val = call <8 x float> @llvm.masked.gather.v8f32.v8p0(<8 x ptr> %bc, i32 4, <8 x i1> , <8 x float> undef) call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %bc, i32 4, <8 x i1> ) -; CHECK-NEXT: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %bc, i32 4, <8 x i1> ) +; CHECK-TYPED-PTRS-NEXT: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> %val, <8 x float*> %bc, i32 4, <8 x i1> ) +; CHECK-OPAQUE-PTRS-NEXT: call void @llvm.masked.scatter.v8f32.v8p0(<8 x float> %val, <8 x ptr> %bc, i32 4, <8 x i1> ) %user = fadd <8 x float> %val, zeroinitializer ; CHECK-NEXT: %user = fadd <8 x float> %val, zeroinitializer ; CHECK-NOT: @table diff --git a/IGC/VectorCompiler/test/JumpTable/basic.ll b/IGC/VectorCompiler/test/JumpTable/basic.ll index e0b54fb0b0fa..c666bdbb9ec9 100644 --- a/IGC/VectorCompiler/test/JumpTable/basic.ll +++ b/IGC/VectorCompiler/test/JumpTable/basic.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2020-2021 Intel Corporation +; Copyright (C) 2020-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXLowerJmpTableSwitch -march=genx64 -mtriple=spir64-unknown-unknown \ -; RUN: -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLowerJmpTableSwitch -march=genx64 -mtriple=spir64-unknown-unknown \ +; RUN: -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLowerJmpTableSwitch -march=genx64 -mtriple=spir64-unknown-unknown \ +; RUN: -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS ; CHECK: [[JTCOND:%.new.jt.cond]] = sub i32 %2, 1 ; CHECK-NEXT: [[JTDEFAULT:%.jt.default]] = icmp ule i32 [[JTCOND]], 4 @@ -16,7 +18,8 @@ ; CHECK-LABEL: .jt: ; CHECK: [[JTIDX:%switch.jt]] = ; CHECK-SAME: @llvm.vc.internal.jump.table -; CHECK-NEXT: indirectbr i8* [[JTIDX]] +; CHECK-TYPED-PTRS-NEXT: indirectbr i8* [[JTIDX]] +; CHECK-OPAQUE-PTRS-NEXT: indirectbr ptr [[JTIDX]] define dllexport spir_kernel void @foo(i32* %0) { %2 = load i32, i32* %0 diff --git a/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv.ll b/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv.ll index 619ae7364602..337683d609dc 100644 --- a/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv.ll +++ b/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv.ll @@ -1,6 +1,6 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; @@ -9,7 +9,8 @@ ; This is a test for vc-function-control option also available ; as IGC_FunctionControl environment -; RUN: %opt %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -24,7 +25,8 @@ define dllexport void @kernel() { %kernel.vec.ref = alloca <8 x i32>, align 32 call spir_func void @foo(<8 x i32>* nonnull %kernel.vec.ref) -; CHECK: call spir_func void @foo(<8 x i32>* nonnull %kernel.vec.ref) +; CHECK-TYPED-PTRS: call spir_func void @foo(<8 x i32>* nonnull %kernel.vec.ref) +; CHECK-OPAQUE-PTRS: call spir_func void @foo(ptr nonnull %kernel.vec.ref) ; CHECK: CMStackCall ret void diff --git a/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv_new.ll b/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv_new.ll index 6d21aea692b4..6b20b642e7ac 100644 --- a/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv_new.ll +++ b/IGC/VectorCompiler/test/LinkageCorruptor/stackcall_conv_new.ll @@ -1,6 +1,6 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; @@ -9,12 +9,14 @@ ; This is a test for vc-function-control option also available ; as IGC_FunctionControl environment -; RUN: %opt %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -save-stack-call-linkage=true -mcpu=Gen9 -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -save-stack-call-linkage=true -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLinkageCorruptor -march=genx64 -vc-function-control=stackcall -save-stack-call-linkage=true -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" -; CHECK: define spir_func void @foo(<8 x i32>* %vec.ref) [[ATTR:#[0-9]+]] { +; CHECK-TYPED-PTRS: define spir_func void @foo(<8 x i32>* %vec.ref) [[ATTR:#[0-9]+]] { +; CHECK-OPAQUE-PTRS: define spir_func void @foo(ptr %vec.ref) [[ATTR:#[0-9]+]] { define spir_func void @foo(<8 x i32>* %vec.ref) #0 { %vec.ref.ld = load <8 x i32>, <8 x i32>* %vec.ref ret void @@ -25,7 +27,8 @@ define dllexport void @kernel() { call spir_func void @foo(<8 x i32>* nonnull %kernel.vec.ref) ; CHECK: call spir_func void @foo -; CHECK-SAME: <8 x i32>* nonnull +; CHECK-TYPED-PTRS-SAME: <8 x i32>* nonnull +; CHECK-OPAQUE-PTRS-SAME: ptr nonnull ret void } diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/alloca-store.ll b/IGC/VectorCompiler/test/LoadStoreLowering/alloca-store.ll index 40bc5e83a8df..b558b1add271 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/alloca-store.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/alloca-store.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS target datalayout = "e-p:64:64-i64:64-n8:16:32" @@ -20,7 +21,8 @@ define void @test(float* %RET) { %ipt = inttoptr i64 %pti to <8 x i16>* store <8 x i16> , <8 x i16>* %ipt -; CHECK: [[ADDR:%.*]] = ptrtoint <8 x i16>* %ipt to i64 +; CHECK-TYPED-PTRS: [[ADDR:%.*]] = ptrtoint <8 x i16>* %ipt to i64 +; CHECK-OPAQUE-PTRS: [[ADDR:%.*]] = ptrtoint ptr %ipt to i64 ; CHECK: call void @llvm.genx.svm.block.st.i64.v8i16(i64 [[ADDR]], <8 x i16> ) ret void } diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-global.ll b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-global.ll index c2b0865f6a51..0a6cb2f89553 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-global.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-global.ll @@ -6,13 +6,15 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS declare float @llvm.vc.internal.atomic.fmin.f32.p1f32.f32(float addrspace(1)*, i32, i32, float) #0 declare float @llvm.vc.internal.atomic.fmax.f32.p1f32.f32(float addrspace(1)*, i32, i32, float) #0 define float @fmin_float(float addrspace(1)* %ptr, float %arg) { - ; CHECK: [[FMIN_ADDR:%[^ ]+]] = ptrtoint float addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[FMIN_ADDR:%[^ ]+]] = ptrtoint float addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[FMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[FMIN_VADDR:%[^ ]+]] = bitcast i64 [[FMIN_ADDR]] to <1 x i64> ; CHECK: [[FMIN_VDATA:%[^ ]+]] = bitcast float %arg to <1 x float> ; CHECK: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 2) @@ -24,7 +26,8 @@ define float @fmin_float(float addrspace(1)* %ptr, float %arg) { } define float @fmax_float(float addrspace(1)* %ptr, float %arg) { - ; CHECK: [[FMAX_ADDR:%[^ ]+]] = ptrtoint float addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[FMAX_ADDR:%[^ ]+]] = ptrtoint float addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[FMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[FMAX_VADDR:%[^ ]+]] = bitcast i64 [[FMAX_ADDR]] to <1 x i64> ; CHECK: [[FMAX_VDATA:%[^ ]+]] = bitcast float %arg to <1 x float> ; CHECK-NOT: call void @llvm.genx.lsc.fence diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-local.ll b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-local.ll index d8b920bab12e..670d7fb94af9 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-local.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-float-local.ll @@ -6,13 +6,15 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS declare float @llvm.vc.internal.atomic.fmin.f32.p3f32.f32(float addrspace(3)*, i32, i32, float) #0 declare float @llvm.vc.internal.atomic.fmax.f32.p3f32.f32(float addrspace(3)*, i32, i32, float) #0 define float @fmin_float(float addrspace(3)* %ptr, float %arg) { - ; CHECK: [[FMIN_ADDR:%[^ ]+]] = ptrtoint float addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[FMIN_ADDR:%[^ ]+]] = ptrtoint float addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[FMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[FMIN_VADDR:%[^ ]+]] = bitcast i32 [[FMIN_ADDR]] to <1 x i32> ; CHECK: [[FMIN_VDATA:%[^ ]+]] = bitcast float %arg to <1 x float> ; CHECK: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -24,7 +26,8 @@ define float @fmin_float(float addrspace(3)* %ptr, float %arg) { } define float @fmax_float(float addrspace(3)* %ptr, float %arg) { - ; CHECK: [[FMAX_ADDR:%[^ ]+]] = ptrtoint float addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[FMAX_ADDR:%[^ ]+]] = ptrtoint float addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[FMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[FMAX_VADDR:%[^ ]+]] = bitcast i32 [[FMAX_ADDR]] to <1 x i32> ; CHECK: [[FMAX_VDATA:%[^ ]+]] = bitcast float %arg to <1 x float> ; CHECK: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int16-global.ll b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int16-global.ll index d0b50f94a85c..b7fdc32a7886 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int16-global.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int16-global.ll @@ -6,10 +6,12 @@ ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS define i16 @inc_i16(i16 addrspace(1)* %ptr) { - ; CHECK-LSC: [[INC_ADDR:%[^ ]+]] = ptrtoint i16 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint i16 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[INC_VADDR:%[^ ]+]] = bitcast i64 [[INC_ADDR]] to <1 x i64> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) ; CHECK-LSC: [[INC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 8, i8 3, i8 6, <2 x i8> zeroinitializer, i64 0, <1 x i64> [[INC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) @@ -21,7 +23,8 @@ define i16 @inc_i16(i16 addrspace(1)* %ptr) { } define i16 @dec_i16(i16 addrspace(1)* %ptr) { - ; CHECK-LSC: [[DEC_ADDR:%[^ ]+]] = ptrtoint i16 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint i16 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[DEC_VADDR:%[^ ]+]] = bitcast i64 [[DEC_ADDR]] to <1 x i64> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) ; CHECK-LSC: [[DEC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 9, i8 3, i8 6, <2 x i8> zeroinitializer, i64 0, <1 x i64> [[DEC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-global.ll b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-global.ll index 7c0f486aa08a..c4b38dad8743 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-global.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-global.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -23,12 +25,14 @@ target triple = "genx64-unknown-unknown" ; Address space 1 (global) operations are lowered into svm/stateless intrinsics define i32 @load_i32(i32 addrspace(1)* %ptr) { - ; CHECK: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[LOAD_VADDR:%[^ ]+]] = bitcast i64 [[LOAD_ADDR]] to <1 x i64> ; CHECK: [[LOAD_VDATA:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.or.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[LOAD_VADDR]], <1 x i32> zeroinitializer, <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[LOAD_VDATA]] to i32 - ; CHECK-LSC: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[LOAD_VADDR:%[^ ]+]] = bitcast i64 [[LOAD_ADDR]] to <1 x i64> ; CHECK-LSC: [[LOAD_VDATA:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 10, i8 3, i8 3, <2 x i8> zeroinitializer, i64 0, <1 x i64> [[LOAD_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 2) @@ -38,12 +42,14 @@ define i32 @load_i32(i32 addrspace(1)* %ptr) { } define void @store_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[STORE_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[STORE_VADDR:%[^ ]+]] = bitcast i64 [[STORE_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: call <1 x i32> @llvm.genx.svm.atomic.xchg.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[STORE_VADDR]], <1 x i32> [[STORE_VDATA]], <1 x i32> undef) - ; CHECK-LSC: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[STORE_VADDR:%[^ ]+]] = bitcast i64 [[STORE_ADDR]] to <1 x i64> ; CHECK-LSC: [[STORE_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 2) @@ -53,12 +59,14 @@ define void @store_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @xchg_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[XCHG_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[XCHG_VADDR:%[^ ]+]] = bitcast i64 [[XCHG_ADDR]] to <1 x i64> ; CHECK: [[XCHG_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.xchg.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[XCHG_VADDR]], <1 x i32> [[XCHG_VDATA]], <1 x i32> undef) ; CHECK: %res = bitcast <1 x i32> [[XCHG_VRES]] to i32 - ; CHECK-LSC: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[XCHG_VADDR:%[^ ]+]] = bitcast i64 [[XCHG_ADDR]] to <1 x i64> ; CHECK-LSC: [[XCHG_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: [[XCHG_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 11, i8 3, i8 3, <2 x i8> , i64 0, <1 x i64> [[XCHG_VADDR]], i16 1, i32 0, <1 x i32> [[XCHG_VDATA]], <1 x i32> undef, <1 x i32> undef) @@ -68,14 +76,16 @@ define i32 @xchg_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @add_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[ADD_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[ADD_VADDR:%[^ ]+]] = bitcast i64 [[ADD_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[ADD_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.add.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[ADD_VADDR]], <1 x i32> [[ADD_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[ADD_VRES]] to i32 - ; CHECK-LSC: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[ADD_VADDR:%[^ ]+]] = bitcast i64 [[ADD_ADDR]] to <1 x i64> ; CHECK-LSC: [[ADD_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -87,13 +97,15 @@ define i32 @add_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @inc_i32(i32 addrspace(1)* %ptr) { - ; CHECK: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[INC_VADDR:%[^ ]+]] = bitcast i64 [[INC_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[INC_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.inc.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[INC_VADDR]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[INC_VRES]] to i32 - ; CHECK-LSC: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[INC_VADDR:%[^ ]+]] = bitcast i64 [[INC_ADDR]] to <1 x i64> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) ; CHECK-LSC: [[INC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 8, i8 3, i8 3, <2 x i8> zeroinitializer, i64 0, <1 x i64> [[INC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) @@ -104,14 +116,16 @@ define i32 @inc_i32(i32 addrspace(1)* %ptr) { } define i32 @sub_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[SUB_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[SUB_VADDR:%[^ ]+]] = bitcast i64 [[SUB_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[SUB_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.sub.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[SUB_VADDR]], <1 x i32> [[SUB_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[SUB_VRES]] to i32 - ; CHECK-LSC: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[SUB_VADDR:%[^ ]+]] = bitcast i64 [[SUB_ADDR]] to <1 x i64> ; CHECK-LSC: [[SUB_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -123,13 +137,15 @@ define i32 @sub_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @dec_i32(i32 addrspace(1)* %ptr) { - ; CHECK: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[DEC_VADDR:%[^ ]+]] = bitcast i64 [[DEC_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[DEC_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.dec.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[DEC_VADDR]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[DEC_VRES]] to i32 - ; CHECK-LSC: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[DEC_VADDR:%[^ ]+]] = bitcast i64 [[DEC_ADDR]] to <1 x i64> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) ; CHECK-LSC: [[DEC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.ugm.v1i32.v1i1.v2i8.v1i64(<1 x i1> , i8 9, i8 3, i8 3, <2 x i8> zeroinitializer, i64 0, <1 x i64> [[DEC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) @@ -140,14 +156,16 @@ define i32 @dec_i32(i32 addrspace(1)* %ptr) { } define i32 @and_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[AND_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[AND_VADDR:%[^ ]+]] = bitcast i64 [[AND_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[AND_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.and.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[AND_VADDR]], <1 x i32> [[AND_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[AND_VRES]] to i32 - ; CHECK-LSC: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[AND_VADDR:%[^ ]+]] = bitcast i64 [[AND_ADDR]] to <1 x i64> ; CHECK-LSC: [[AND_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 4) @@ -159,14 +177,16 @@ define i32 @and_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @or_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[OR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[OR_VADDR:%[^ ]+]] = bitcast i64 [[OR_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[OR_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.or.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[OR_VADDR]], <1 x i32> [[OR_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[OR_VRES]] to i32 - ; CHECK-LSC: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[OR_VADDR:%[^ ]+]] = bitcast i64 [[OR_ADDR]] to <1 x i64> ; CHECK-LSC: [[OR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -178,14 +198,16 @@ define i32 @or_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @xor_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[XOR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[XOR_VADDR:%[^ ]+]] = bitcast i64 [[XOR_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[XOR_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.xor.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[XOR_VADDR]], <1 x i32> [[XOR_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[XOR_VRES]] to i32 - ; CHECK-LSC: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[XOR_VADDR:%[^ ]+]] = bitcast i64 [[XOR_ADDR]] to <1 x i64> ; CHECK-LSC: [[XOR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -197,14 +219,16 @@ define i32 @xor_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @max_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[MAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[MAX_VADDR:%[^ ]+]] = bitcast i64 [[MAX_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[MAX_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.imax.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[MAX_VADDR]], <1 x i32> [[MAX_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[MAX_VRES]] to i32 - ; CHECK-LSC: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[MAX_VADDR:%[^ ]+]] = bitcast i64 [[MAX_ADDR]] to <1 x i64> ; CHECK-LSC: [[MAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -216,14 +240,16 @@ define i32 @max_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @min_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[MIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[MIN_VADDR:%[^ ]+]] = bitcast i64 [[MIN_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[MIN_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.imin.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[MIN_VADDR]], <1 x i32> [[MIN_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[MIN_VRES]] to i32 - ; CHECK-LSC: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[MIN_VADDR:%[^ ]+]] = bitcast i64 [[MIN_ADDR]] to <1 x i64> ; CHECK-LSC: [[MIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -235,14 +261,16 @@ define i32 @min_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @umax_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[UMAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[UMAX_VADDR:%[^ ]+]] = bitcast i64 [[UMAX_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[UMAX_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.max.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[UMAX_VADDR]], <1 x i32> [[UMAX_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[UMAX_VRES]] to i32 - ; CHECK-LSC: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[UMAX_VADDR:%[^ ]+]] = bitcast i64 [[UMAX_ADDR]] to <1 x i64> ; CHECK-LSC: [[UMAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -254,14 +282,16 @@ define i32 @umax_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @umin_i32(i32 addrspace(1)* %ptr, i32 %arg) { - ; CHECK: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[UMIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[UMIN_VADDR:%[^ ]+]] = bitcast i64 [[UMIN_ADDR]] to <1 x i64> ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: [[UMIN_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.svm.atomic.min.v1i32.v1i1.v1i64(<1 x i1> , <1 x i64> [[UMIN_VADDR]], <1 x i32> [[UMIN_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 1) ; CHECK: %res = bitcast <1 x i32> [[UMIN_VRES]] to i32 - ; CHECK-LSC: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[UMIN_VADDR:%[^ ]+]] = bitcast i64 [[UMIN_ADDR]] to <1 x i64> ; CHECK-LSC: [[UMIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 0, i8 0, i8 0) @@ -273,7 +303,8 @@ define i32 @umin_i32(i32 addrspace(1)* %ptr, i32 %arg) { } define i32 @cmpxchg_i32(i32 addrspace(1)* %ptr, i32 %cmp, i32 %arg) { - ; CHECK: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-TYPED-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-OPAQUE-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK: [[CAS_VARG:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[CAS_VCMP:%[^ ]+]] = bitcast i32 %cmp to <1 x i32> ; CHECK: [[CAS_VADDR:%[^ ]+]] = bitcast i64 [[CAS_ADDR]] to <1 x i64> @@ -284,7 +315,8 @@ define i32 @cmpxchg_i32(i32 addrspace(1)* %ptr, i32 %cmp, i32 %arg) { ; CHECK: [[CAS_CMP:%[^ ]+]] = icmp eq i32 [[CAS_VAL]], %cmp ; CHECK: [[CAS_INS:%[^ ]+]] = insertvalue { i32, i1 } undef, i32 [[CAS_VAL]], 0 ; CHECK: %res = insertvalue { i32, i1 } [[CAS_INS]], i1 [[CAS_CMP]], 1 - ; CHECK-LSC: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-TYPED-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(1)* %ptr to i64 + ; CHECK-LSC-OPAQUE-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(1) %ptr to i64 ; CHECK-LSC: [[CAS_VADDR:%[^ ]+]] = bitcast i64 [[CAS_ADDR]] to <1 x i64> ; CHECK-LSC: [[CAS_VCMP:%[^ ]+]] = bitcast i32 %cmp to <1 x i32> ; CHECK-LSC: [[CAS_VARG:%[^ ]+]] = bitcast i32 %arg to <1 x i32> diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-local.ll b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-local.ll index 2212a41412c3..7d68b3b4e13b 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-local.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/atomic-int32-local.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -23,12 +25,14 @@ target triple = "genx64-unknown-unknown" ; Address space 1 (global) operations are lowered into dword/slm intrinsics define i32 @load_i32(i32 addrspace(3)* %ptr) { - ; CHECK: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[LOAD_VADDR:%[^ ]+]] = bitcast i32 [[LOAD_ADDR]] to <1 x i32> ; CHECK: [[LOAD_VDATA:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.or.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[LOAD_VADDR]], <1 x i32> zeroinitializer, <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[LOAD_VDATA]] to i32 - ; CHECK-LSC: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[LOAD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[LOAD_VADDR:%[^ ]+]] = bitcast i32 [[LOAD_ADDR]] to <1 x i32> ; CHECK-LSC: [[LOAD_VDATA:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.slm.v1i32.v1i1.v2i8.v1i32(<1 x i1> , i8 10, i8 2, i8 3, <2 x i8> zeroinitializer, i32 0, <1 x i32> [[LOAD_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 2) @@ -38,12 +42,14 @@ define i32 @load_i32(i32 addrspace(3)* %ptr) { } define void @store_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[STORE_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[STORE_VADDR:%[^ ]+]] = bitcast i32 [[STORE_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: call <1 x i32> @llvm.genx.dword.atomic.xchg.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[STORE_VADDR]], <1 x i32> [[STORE_VDATA]], <1 x i32> undef) - ; CHECK-LSC: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[STORE_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[STORE_VADDR:%[^ ]+]] = bitcast i32 [[STORE_ADDR]] to <1 x i32> ; CHECK-LSC: [[STORE_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 2) @@ -53,12 +59,14 @@ define void @store_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @xchg_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[XCHG_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[XCHG_VADDR:%[^ ]+]] = bitcast i32 [[XCHG_ADDR]] to <1 x i32> ; CHECK: [[XCHG_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.xchg.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[XCHG_VADDR]], <1 x i32> [[XCHG_VDATA]], <1 x i32> undef) ; CHECK: %res = bitcast <1 x i32> [[XCHG_VRES]] to i32 - ; CHECK-LSC: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[XCHG_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[XCHG_VADDR:%[^ ]+]] = bitcast i32 [[XCHG_ADDR]] to <1 x i32> ; CHECK-LSC: [[XCHG_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: [[XCHG_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.slm.v1i32.v1i1.v2i8.v1i32(<1 x i1> , i8 11, i8 2, i8 3, <2 x i8> zeroinitializer, i32 0, <1 x i32> [[XCHG_VADDR]], i16 1, i32 0, <1 x i32> [[XCHG_VDATA]], <1 x i32> undef, <1 x i32> undef) @@ -68,14 +76,16 @@ define i32 @xchg_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @add_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[ADD_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[ADD_VADDR:%[^ ]+]] = bitcast i32 [[ADD_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[ADD_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.add.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[ADD_VADDR]], <1 x i32> [[ADD_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[ADD_VRES]] to i32 - ; CHECK-LSC: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[ADD_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[ADD_VADDR:%[^ ]+]] = bitcast i32 [[ADD_ADDR]] to <1 x i32> ; CHECK-LSC: [[ADD_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -87,13 +97,15 @@ define i32 @add_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @inc_i32(i32 addrspace(3)* %ptr) { - ; CHECK: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[INC_VADDR:%[^ ]+]] = bitcast i32 [[INC_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[INC_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.inc.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[INC_VADDR]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[INC_VRES]] to i32 - ; CHECK-LSC: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[INC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[INC_VADDR:%[^ ]+]] = bitcast i32 [[INC_ADDR]] to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) ; CHECK-LSC: [[INC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.slm.v1i32.v1i1.v2i8.v1i32(<1 x i1> , i8 8, i8 2, i8 3, <2 x i8> zeroinitializer, i32 0, <1 x i32> [[INC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) @@ -104,14 +116,16 @@ define i32 @inc_i32(i32 addrspace(3)* %ptr) { } define i32 @sub_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[SUB_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[SUB_VADDR:%[^ ]+]] = bitcast i32 [[SUB_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[SUB_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.sub.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[SUB_VADDR]], <1 x i32> [[SUB_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[SUB_VRES]] to i32 - ; CHECK-LSC: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[SUB_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[SUB_VADDR:%[^ ]+]] = bitcast i32 [[SUB_ADDR]] to <1 x i32> ; CHECK-LSC: [[SUB_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -123,13 +137,15 @@ define i32 @sub_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @dec_i32(i32 addrspace(3)* %ptr) { - ; CHECK: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[DEC_VADDR:%[^ ]+]] = bitcast i32 [[DEC_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[DEC_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.dec.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[DEC_VADDR]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[DEC_VRES]] to i32 - ; CHECK-LSC: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[DEC_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[DEC_VADDR:%[^ ]+]] = bitcast i32 [[DEC_ADDR]] to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) ; CHECK-LSC: [[DEC_VRES:%[^ ]+]] = call <1 x i32> @llvm.vc.internal.lsc.atomic.slm.v1i32.v1i1.v2i8.v1i32(<1 x i1> , i8 9, i8 2, i8 3, <2 x i8> zeroinitializer, i32 0, <1 x i32> [[DEC_VADDR]], i16 1, i32 0, <1 x i32> undef, <1 x i32> undef, <1 x i32> undef) @@ -140,14 +156,16 @@ define i32 @dec_i32(i32 addrspace(3)* %ptr) { } define i32 @and_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[AND_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[AND_VADDR:%[^ ]+]] = bitcast i32 [[AND_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[AND_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.and.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[AND_VADDR]], <1 x i32> [[AND_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[AND_VRES]] to i32 - ; CHECK-LSC: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[AND_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[AND_VADDR:%[^ ]+]] = bitcast i32 [[AND_ADDR]] to <1 x i32> ; CHECK-LSC: [[AND_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 4) @@ -159,14 +177,16 @@ define i32 @and_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @or_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[OR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[OR_VADDR:%[^ ]+]] = bitcast i32 [[OR_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[OR_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.or.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[OR_VADDR]], <1 x i32> [[OR_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[OR_VRES]] to i32 - ; CHECK-LSC: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[OR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[OR_VADDR:%[^ ]+]] = bitcast i32 [[OR_ADDR]] to <1 x i32> ; CHECK-LSC: [[OR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -178,14 +198,16 @@ define i32 @or_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @xor_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[XOR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[XOR_VADDR:%[^ ]+]] = bitcast i32 [[XOR_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[XOR_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.xor.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[XOR_VADDR]], <1 x i32> [[XOR_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[XOR_VRES]] to i32 - ; CHECK-LSC: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[XOR_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[XOR_VADDR:%[^ ]+]] = bitcast i32 [[XOR_ADDR]] to <1 x i32> ; CHECK-LSC: [[XOR_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -197,14 +219,16 @@ define i32 @xor_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @max_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[MAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[MAX_VADDR:%[^ ]+]] = bitcast i32 [[MAX_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[MAX_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.imax.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[MAX_VADDR]], <1 x i32> [[MAX_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[MAX_VRES]] to i32 - ; CHECK-LSC: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[MAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[MAX_VADDR:%[^ ]+]] = bitcast i32 [[MAX_ADDR]] to <1 x i32> ; CHECK-LSC: [[MAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -216,14 +240,16 @@ define i32 @max_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @min_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[MIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[MIN_VADDR:%[^ ]+]] = bitcast i32 [[MIN_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[MIN_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.imin.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[MIN_VADDR]], <1 x i32> [[MIN_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[MIN_VRES]] to i32 - ; CHECK-LSC: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[MIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[MIN_VADDR:%[^ ]+]] = bitcast i32 [[MIN_ADDR]] to <1 x i32> ; CHECK-LSC: [[MIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -235,14 +261,16 @@ define i32 @min_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @umax_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[UMAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[UMAX_VADDR:%[^ ]+]] = bitcast i32 [[UMAX_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[UMAX_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.max.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[UMAX_VADDR]], <1 x i32> [[UMAX_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[UMAX_VRES]] to i32 - ; CHECK-LSC: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[UMAX_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[UMAX_VADDR:%[^ ]+]] = bitcast i32 [[UMAX_ADDR]] to <1 x i32> ; CHECK-LSC: [[UMAX_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -254,14 +282,16 @@ define i32 @umax_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @umin_i32(i32 addrspace(3)* %ptr, i32 %arg) { - ; CHECK: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[UMIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[UMIN_VADDR:%[^ ]+]] = bitcast i32 [[UMIN_ADDR]] to <1 x i32> ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: [[UMIN_VRES:%[^ ]+]] = call <1 x i32> @llvm.genx.dword.atomic.min.v1i32.v1i1.v1i32(<1 x i1> , i32 254, <1 x i32> [[UMIN_VADDR]], <1 x i32> [[UMIN_VDATA]], <1 x i32> undef) ; CHECK: call void @llvm.genx.fence(i8 33) ; CHECK: %res = bitcast <1 x i32> [[UMIN_VRES]] to i32 - ; CHECK-LSC: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[UMIN_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[UMIN_VADDR:%[^ ]+]] = bitcast i32 [[UMIN_ADDR]] to <1 x i32> ; CHECK-LSC: [[UMIN_VDATA:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK-LSC: call void @llvm.genx.lsc.fence.i1(i1 true, i8 3, i8 0, i8 0) @@ -273,7 +303,8 @@ define i32 @umin_i32(i32 addrspace(3)* %ptr, i32 %arg) { } define i32 @cmpxchg_i32(i32 addrspace(3)* %ptr, i32 %cmp, i32 %arg) { - ; CHECK: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-TYPED-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-OPAQUE-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK: [[CAS_VARG:%[^ ]+]] = bitcast i32 %arg to <1 x i32> ; CHECK: [[CAS_VCMP:%[^ ]+]] = bitcast i32 %cmp to <1 x i32> ; CHECK: [[CAS_VADDR:%[^ ]+]] = bitcast i32 [[CAS_ADDR]] to <1 x i32> @@ -284,7 +315,8 @@ define i32 @cmpxchg_i32(i32 addrspace(3)* %ptr, i32 %cmp, i32 %arg) { ; CHECK: [[CAS_CMP:%[^ ]+]] = icmp eq i32 [[CAS_VAL]], %cmp ; CHECK: [[CAS_INS:%[^ ]+]] = insertvalue { i32, i1 } undef, i32 [[CAS_VAL]], 0 ; CHECK: %res = insertvalue { i32, i1 } [[CAS_INS]], i1 [[CAS_CMP]], 1 - ; CHECK-LSC: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-TYPED-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint i32 addrspace(3)* %ptr to i32 + ; CHECK-LSC-OPAQUE-PTRS: [[CAS_ADDR:%[^ ]+]] = ptrtoint ptr addrspace(3) %ptr to i32 ; CHECK-LSC: [[CAS_VADDR:%[^ ]+]] = bitcast i32 [[CAS_ADDR]] to <1 x i32> ; CHECK-LSC: [[CAS_VCMP:%[^ ]+]] = bitcast i32 %cmp to <1 x i32> ; CHECK-LSC: [[CAS_VARG:%[^ ]+]] = bitcast i32 %arg to <1 x i32> diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/debug.ll b/IGC/VectorCompiler/test/LoadStoreLowering/debug.ll index 7e627166f12d..6cd4b0ece1cb 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/debug.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/debug.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2022-2023 Intel Corporation +; Copyright (C) 2022-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s -; RUN: %opt %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s -check-prefix=STRICT +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=STRICT +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLoadStoreLowering -enable-ldst-lowering=true -mattr=+ocl_runtime -march=genx64 -mtriple=spir64-unknown-unknown -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=STRICT ; ------------------------------------------------ ; GenXLoadStoreLowering ; ------------------------------------------------ @@ -18,23 +20,28 @@ ; CHECK: void @test_lowerloadstore{{.*}} !dbg [[SCOPE:![0-9]*]] ; CHECK: bbi16: -; CHECK: [[VAL1_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL1_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i16* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata i16 [[VAL2_V:%[A-z0-9.]*]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC:![0-9]*]] -; CHECK-DAG: [[VAL2_V]] = {{.*}}, !dbg [[VAL2_LOC]] -; CHECK-DAG: scatter{{.*}}, !dbg [[STORE1_LOC:![0-9]*]] +; CHECK: [[VAL1_V:%[A-z0-9.]*]] = inttoptr {{.*}}, !dbg [[VAL1_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i16* [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL1_V]], metadata [[VAL1_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL1_LOC]] +; CHECK: bitcast +; CHECK: [[VAL2_V:%[A-z0-9.]*]] = bitcast {{.*}}, !dbg [[VAL2_LOC:![0-9]*]] +; CHECK: void @llvm.dbg.value(metadata i16 [[VAL2_V]], metadata [[VAL2_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL2_LOC]] +; CHECK: scatter{{.*}}, !dbg [[STORE1_LOC:![0-9]*]] ; CHECK: bbi64: -; CHECK: [[VAL3_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL3_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata i64* [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata i64 [[VAL4_V:%[A-z0-9.]*]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC:![0-9]*]] -; CHECK-DAG: [[VAL4_V]] = {{.*}}, !dbg [[VAL4_LOC]] -; CHECK-DAG: scatter{{.*}}, !dbg [[STORE2_LOC:![0-9]*]] +; CHECK: [[VAL3_V:%[A-z0-9.]*]] = inttoptr {{.*}}, !dbg [[VAL3_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata i64* [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL3_V]], metadata [[VAL3_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL3_LOC]] +; CHECK: [[VAL4_V:%[A-z0-9.]*]] = bitcast {{.*}}, !dbg [[VAL4_LOC:![0-9]*]] +; CHECK: void @llvm.dbg.value(metadata i64 [[VAL4_V]], metadata [[VAL4_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL4_LOC]] +; CHECK: scatter{{.*}}, !dbg [[STORE2_LOC:![0-9]*]] ; CHECK: bbfptr: -; CHECK: [[VAL5_V:%[A-z0-9.]*]] = {{.*}}, !dbg [[VAL5_LOC:![0-9]*]] -; CHECK: void @llvm.dbg.value(metadata void (i32*)** [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] -; CHECK-DAG: void @llvm.dbg.value(metadata void (i32*)* [[VAL6_V:%[A-z0-9.]*]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC:![0-9]*]] -; CHECK-DAG: [[VAL6_V]] = {{.*}}, !dbg [[VAL6_LOC]] -; CHECK-DAG: scatter{{.*}}, !dbg [[STORE3_LOC:![0-9]*]] +; CHECK: [[VAL5_V:%[A-z0-9.]*]] = inttoptr {{.*}}, !dbg [[VAL5_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata void (i32*)** [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL5_V]], metadata [[VAL5_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL5_LOC]] +; CHECK: [[VAL6_V:%[A-z0-9.]*]] = bitcast {{.*}}, !dbg [[VAL6_LOC:![0-9]*]] +; CHECK-TYPED-PTRS: void @llvm.dbg.value(metadata void (i32*)* [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] +; CHECK-OPAQUE-PTRS: void @llvm.dbg.value(metadata ptr [[VAL6_V]], metadata [[VAL6_MD:![0-9]*]], metadata !DIExpression()), !dbg [[VAL6_LOC]] +; CHECK: scatter{{.*}}, !dbg [[STORE3_LOC:![0-9]*]] ; ; STRICT: bbi16: ; STRICT: , !dbg [[VAL1_LOC:![0-9]*]] diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/funcptr.ll b/IGC/VectorCompiler/test/LoadStoreLowering/funcptr.ll index 32f1f4bcd37f..433401db11ac 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/funcptr.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/funcptr.ll @@ -1,13 +1,15 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2021-2023 Intel Corporation +; Copyright (C) 2021-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -18,11 +20,15 @@ target datalayout = "e-p:64:64-i64:64-n8:16:32" ; CHECK-LABEL: foo ; CHECK: %[[GATHER:.*]] = call <1 x i64> @llvm.genx.svm.gather.v1i64.v1i1.v1i64(<1 x i1> , i32 0, <1 x i64> undef, <1 x i64> undef) -; CHECK: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x float (i8 addrspace(1)*, float)*> -; CHECK: bitcast <1 x float (i8 addrspace(1)*, float)*> %[[INTPTR]] to float (i8 addrspace(1)*, float)* +; CHECK-TYPED-PTRS: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x float (i8 addrspace(1)*, float)*> +; CHECK-TYPED-PTRS: bitcast <1 x float (i8 addrspace(1)*, float)*> %[[INTPTR]] to float (i8 addrspace(1)*, float)* +; CHECK-OPAQUE-PTRS: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x ptr> +; CHECK-OPAQUE-PTRS: bitcast <1 x ptr> %[[INTPTR]] to ptr ; CHECK-LSC: %[[GATHER:.*]] = call <1 x i64> @llvm.vc.internal.lsc.load.ugm.v1i64.v1i1.v2i8.i64(<1 x i1> , i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, i64 undef, i16 1, i32 0, <1 x i64> undef) -; CHECK-LSC: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x float (i8 addrspace(1)*, float)*> -; CHECK-LSC: bitcast <1 x float (i8 addrspace(1)*, float)*> %[[INTPTR]] to float (i8 addrspace(1)*, float)* +; CHECK-LSC-TYPED-PTRS: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x float (i8 addrspace(1)*, float)*> +; CHECK-LSC-TYPED-PTRS: bitcast <1 x float (i8 addrspace(1)*, float)*> %[[INTPTR]] to float (i8 addrspace(1)*, float)* +; CHECK-LSC-OPAQUE-PTRS: %[[INTPTR:.*]] = inttoptr <1 x i64> %[[GATHER]] to <1 x ptr> +; CHECK-LSC-OPAQUE-PTRS: bitcast <1 x ptr> %[[INTPTR]] to ptr define void @foo() { %1 = load float (i8 addrspace(1)*, float)*, float (i8 addrspace(1)*, float)* addrspace(1)* undef, align 8 diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/gather-global.ll b/IGC/VectorCompiler/test/LoadStoreLowering/gather-global.ll index 34c599c1b7db..aa3c0bfba97c 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/gather-global.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/gather-global.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -35,12 +37,14 @@ declare <8 x i8*> @llvm.masked.gather.v8p0i8.v8p1p0i8(<8 x i8* addrspace(1)*>, i define <8 x i8> @test_i8(<8 x i8 addrspace(1)*> %pi8, <8 x i1> %mask, <8 x i8> %passthru) { ; CHECK-DAG: [[PASSTHRU8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> ; CHECK-DAG: [[CAST8:[^ ]+]] = bitcast <8 x i32> [[PASSTHRU8]] to <32 x i8> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi8 to <8 x i64> ; CHECK: [[DATA8:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR8]], <32 x i8> [[CAST8]]) ; CHECK: [[LCAST8:[^ ]+]] = bitcast <32 x i8> [[DATA8]] to <8 x i32> ; CHECK: %res = trunc <8 x i32> [[LCAST8]] to <8 x i8> ; CHECK-LSC-DAG: [[PASSTHRU8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi8 to <8 x i64> ; CHECK-LSC: [[DATA8:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 5, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR8]], i16 1, i32 0, <8 x i32> [[PASSTHRU8]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA8]] to <8 x i8> %res = call <8 x i8> @llvm.masked.gather.v8i8.v8p1i8(<8 x i8 addrspace(1)*> %pi8, i32 1, <8 x i1> %mask, <8 x i8> %passthru) @@ -50,12 +54,14 @@ define <8 x i8> @test_i8(<8 x i8 addrspace(1)*> %pi8, <8 x i1> %mask, <8 x i8> % define <8 x i16> @test_i16(<8 x i16 addrspace(1)*> %pi16, <8 x i1> %mask, <8 x i16> %passthru) { ; CHECK-DAG: [[PASSTHRU16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> ; CHECK-DAG: [[CAST16:[^ ]+]] = bitcast <8 x i32> [[PASSTHRU16]] to <32 x i8> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK: [[DATA16:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 1, <8 x i64> [[ADDR16]], <32 x i8> [[CAST16]]) ; CHECK: [[LCAST16:[^ ]+]] = bitcast <32 x i8> [[DATA16]] to <8 x i32> ; CHECK: %res = trunc <8 x i32> [[LCAST16]] to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRU16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK-LSC: [[DATA16:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR16]], i16 1, i32 0, <8 x i32> [[PASSTHRU16]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA16]] to <8 x i16> %res = call <8 x i16> @llvm.masked.gather.v8i16.v8p1i16(<8 x i16 addrspace(1)*> %pi16, i32 2, <8 x i1> %mask, <8 x i16> %passthru) @@ -63,18 +69,22 @@ define <8 x i16> @test_i16(<8 x i16 addrspace(1)*> %pi16, <8 x i1> %mask, <8 x i } define <8 x i32> @test_i32(<8 x i32 addrspace(1)*> %pi32, <8 x i1> %mask, <8 x i32> %passthru) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK: %res = call <8 x i32> @llvm.genx.svm.gather.v8i32.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR32]], <8 x i32> %passthru) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK-LSC: %res = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i32> %passthru) %res = call <8 x i32> @llvm.masked.gather.v8i32.v8p1i32(<8 x i32 addrspace(1)*> %pi32, i32 4, <8 x i1> %mask, <8 x i32> %passthru) ret <8 x i32> %res } define <8 x i64> @test_i64(<8 x i64 addrspace(1)*> %pi64, <8 x i1> %mask, <8 x i64> %passthru) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK: %res = call <8 x i64> @llvm.genx.svm.gather.v8i64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR64]], <8 x i64> %passthru) -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK-LSC: %res = call <8 x i64> @llvm.vc.internal.lsc.load.ugm.v8i64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i64> %passthru) %res = call <8 x i64> @llvm.masked.gather.v8i64.v8p1i64(<8 x i64 addrspace(1)*> %pi64, i32 8, <8 x i1> %mask, <8 x i64> %passthru) ret <8 x i64> %res @@ -84,14 +94,16 @@ define <8 x half> @test_f16(<8 x half addrspace(1)*> %pi16, <8 x i1> %mask, <8 x ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK-DAG: [[PASSTHRUH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> ; CHECK-DAG: [[CASTI:[^ ]+]] = bitcast <8 x i32> [[PASSTHRUH]] to <32 x i8> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK: [[DATAH:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 1, <8 x i64> [[ADDRH]], <32 x i8> [[CASTI]]) ; CHECK: [[LCASTH:[^ ]+]] = bitcast <32 x i8> [[DATAH]] to <8 x i32> ; CHECK: [[TRUNC:[^ ]+]] = trunc <8 x i32> [[LCASTH]] to <8 x i16> ; CHECK: %res = bitcast <8 x i16> [[TRUNC]] to <8 x half> ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRUH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK-LSC: [[DATAH:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRH]], i16 1, i32 0, <8 x i32> [[PASSTHRUH]]) ; CHECK-LSC: [[TRUNC:[^ ]+]] = trunc <8 x i32> [[DATAH]] to <8 x i16> ; CHECK-LSC: %res = bitcast <8 x i16> [[TRUNC]] to <8 x half> @@ -100,32 +112,42 @@ define <8 x half> @test_f16(<8 x half addrspace(1)*> %pi16, <8 x i1> %mask, <8 x } define <8 x float> @test_f32(<8 x float addrspace(1)*> %pi32, <8 x i1> %mask, <8 x float> %passthru) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK: %res = call <8 x float> @llvm.genx.svm.gather.v8f32.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRF]], <8 x float> %passthru) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK-LSC: %res = call <8 x float> @llvm.vc.internal.lsc.load.ugm.v8f32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRF]], i16 1, i32 0, <8 x float> %passthru) %res = call <8 x float> @llvm.masked.gather.v8f32.v8p1f32(<8 x float addrspace(1)*> %pi32, i32 4, <8 x i1> %mask, <8 x float> %passthru) ret <8 x float> %res } define <8 x double> @test_f64(<8 x double addrspace(1)*> %pi64, <8 x i1> %mask, <8 x double> %passthru) { -; CHECK: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK: %res = call <8 x double> @llvm.genx.svm.gather.v8f64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRD]], <8 x double> %passthru) -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK-LSC: %res = call <8 x double> @llvm.vc.internal.lsc.load.ugm.v8f64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRD]], i16 1, i32 0, <8 x double> %passthru) %res = call <8 x double> @llvm.masked.gather.v8f64.v8p1f64(<8 x double addrspace(1)*> %pi64, i32 8, <8 x i1> %mask, <8 x double> %passthru) ret <8 x double> %res } define <8 x i8*> @test_ptr(<8 x i8* addrspace(1)*> %pptr, <8 x i1> %mask, <8 x i8*> %passthru) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pptr to <8 x i64> ; CHECK: [[DATAP:[^ ]+]] = call <8 x i64> @llvm.genx.svm.gather.v8i64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRP]], <8 x i64> [[PTI]]) -; CHECK: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-TYPED-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x ptr> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pptr to <8 x i64> ; CHECK-LSC: [[DATAP:[^ ]+]] = call <8 x i64> @llvm.vc.internal.lsc.load.ugm.v8i64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) -; CHECK-LSC: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-TYPED-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x ptr> %res = call <8 x i8*> @llvm.masked.gather.v8p0i8.v8p1p0i8(<8 x i8* addrspace(1)*> %pptr, i32 8, <8 x i1> %mask, <8 x i8*> %passthru) ret <8 x i8*> %res } diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/gather-local.ll b/IGC/VectorCompiler/test/LoadStoreLowering/gather-local.ll index c3a4b1ea35dc..3f9aa07be1a1 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/gather-local.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/gather-local.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -34,11 +36,13 @@ declare <8 x i8*> @llvm.masked.gather.v8p0i8.v8p3p0i8(<8 x i8* addrspace(3)*>, i define <8 x i8> @test_i8(<8 x i8 addrspace(3)*> %pi8, <8 x i1> %mask, <8 x i8> %passthru) { ; CHECK: [[ZEXT8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> -; CHECK: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi8 to <8 x i32> ; CHECK: [[LOAD8:[^ ]+]] = call <8 x i32> @llvm.genx.gather.scaled.v8i32.v8i1.v8i32(<8 x i1> %mask, i32 0, i16 0, i32 254, i32 0, <8 x i32> [[ADDR8]], <8 x i32> [[ZEXT8]]) ; CHECK: %res = trunc <8 x i32> [[LOAD8]] to <8 x i8> ; CHECK-LSC-DAG: [[PASSTHRU8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi8 to <8 x i32> ; CHECK-LSC: [[DATA8:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.slm.v8i32.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 5, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR8]], i16 1, i32 0, <8 x i32> [[PASSTHRU8]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA8]] to <8 x i8> %res = call <8 x i8> @llvm.masked.gather.v8i8.v8p3i8(<8 x i8 addrspace(3)*> %pi8, i32 1, <8 x i1> %mask, <8 x i8> %passthru) @@ -47,11 +51,13 @@ define <8 x i8> @test_i8(<8 x i8 addrspace(3)*> %pi8, <8 x i1> %mask, <8 x i8> % define <8 x i16> @test_i16(<8 x i16 addrspace(3)*> %pi16, <8 x i1> %mask, <8 x i16> %passthru) { ; CHECK: [[ZEXT16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> -; CHECK: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK: [[LOAD16:[^ ]+]] = call <8 x i32> @llvm.genx.gather.scaled.v8i32.v8i1.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 254, i32 0, <8 x i32> [[ADDR16]], <8 x i32> [[ZEXT16]]) ; CHECK: %res = trunc <8 x i32> [[LOAD16]] to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRU16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK-LSC: [[DATA16:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.slm.v8i32.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR16]], i16 1, i32 0, <8 x i32> [[PASSTHRU16]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA16]] to <8 x i16> %res = call <8 x i16> @llvm.masked.gather.v8i16.v8p3i16(<8 x i16 addrspace(3)*> %pi16, i32 2, <8 x i1> %mask, <8 x i16> %passthru) @@ -59,22 +65,26 @@ define <8 x i16> @test_i16(<8 x i16 addrspace(3)*> %pi16, <8 x i1> %mask, <8 x i } define <8 x i32> @test_i32(<8 x i32 addrspace(3)*> %pi32, <8 x i1> %mask, <8 x i32> %passthru) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK: %res = call <8 x i32> @llvm.genx.gather.scaled.v8i32.v8i1.v8i32(<8 x i1> %mask, i32 2, i16 0, i32 254, i32 0, <8 x i32> [[ADDR32]], <8 x i32> %passthru) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK-LSC: %res = call <8 x i32> @llvm.vc.internal.lsc.load.slm.v8i32.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR32]], i16 1, i32 0, <8 x i32> %passthru) %res = call <8 x i32> @llvm.masked.gather.v8i32.v8p3i32(<8 x i32 addrspace(3)*> %pi32, i32 4, <8 x i1> %mask, <8 x i32> %passthru) ret <8 x i32> %res } define <8 x i64> @test_i64(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i64> %passthru) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK: [[CAST64:[^ ]+]] = bitcast <8 x i64> %passthru to <16 x i32> ; CHECK: [[STOA64:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CAST64]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: [[LOAD64:[^ ]+]] = call <16 x i32> @llvm.genx.gather4.scaled.v16i32.v8i1.v8i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDR64]], <16 x i32> [[STOA64]]) ; CHECK: [[ATOS64:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[LOAD64]], i32 1, i32 2, i32 8, i16 0, i32 undef) ; CHECK: %res = bitcast <16 x i32> [[ATOS64]] to <8 x i64> -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: %res = call <8 x i64> @llvm.vc.internal.lsc.load.slm.v8i64.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR32]], i16 1, i32 0, <8 x i64> %passthru) %res = call <8 x i64> @llvm.masked.gather.v8i64.v8p3i64(<8 x i64 addrspace(3)*> %pi64, i32 8, <8 x i1> %mask, <8 x i64> %passthru) ret <8 x i64> %res @@ -83,13 +93,15 @@ define <8 x i64> @test_i64(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i define <8 x half> @test_f16(<8 x half addrspace(3)*> %pi16, <8 x i1> %mask, <8 x half> %passthru) { ; CHECK: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK: [[ZEXTH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK: [[LOADH:[^ ]+]] = call <8 x i32> @llvm.genx.gather.scaled.v8i32.v8i1.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 254, i32 0, <8 x i32> [[ADDRH]], <8 x i32> [[ZEXTH]]) ; CHECK: %5 = trunc <8 x i32> %4 to <8 x i16> ; CHECK: %res = bitcast <8 x i16> %5 to <8 x half> ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRUH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK-LSC: [[DATAH:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.slm.v8i32.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRH]], i16 1, i32 0, <8 x i32> [[PASSTHRUH]]) ; CHECK-LSC: [[TRUNC:[^ ]+]] = trunc <8 x i32> [[DATAH]] to <8 x i16> ; CHECK-LSC: %res = bitcast <8 x i16> [[TRUNC]] to <8 x half> @@ -98,46 +110,57 @@ define <8 x half> @test_f16(<8 x half addrspace(3)*> %pi16, <8 x i1> %mask, <8 x } define <8 x float> @test_f32(<8 x float addrspace(3)*> %pi32, <8 x i1> %mask, <8 x float> %passthru) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK: %res = call <8 x float> @llvm.genx.gather.scaled.v8f32.v8i1.v8i32(<8 x i1> %mask, i32 2, i16 0, i32 254, i32 0, <8 x i32> [[ADDRF]], <8 x float> %passthru) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK-LSC: %res = call <8 x float> @llvm.vc.internal.lsc.load.slm.v8f32.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRF]], i16 1, i32 0, <8 x float> %passthru) %res = call <8 x float> @llvm.masked.gather.v8f32.v8p3f32(<8 x float addrspace(3)*> %pi32, i32 4, <8 x i1> %mask, <8 x float> %passthru) ret <8 x float> %res } define <8 x double> @test_f64(<8 x double addrspace(3)*> %pi64, <8 x i1> %mask, <8 x double> %passthru) { -; CHECK: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK: [[CASTD:[^ ]+]] = bitcast <8 x double> %passthru to <16 x i32> ; CHECK: [[STOAD:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTD]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: [[LOADD:[^ ]+]] = call <16 x i32> @llvm.genx.gather4.scaled.v16i32.v8i1.v8i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDRD]], <16 x i32> [[STOAD]]) ; CHECK: [[ATOSD:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[LOADD]], i32 1, i32 2, i32 8, i16 0, i32 undef) ; CHECK: %res = bitcast <16 x i32> [[ATOSD]] to <8 x double> -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: %res = call <8 x double> @llvm.vc.internal.lsc.load.slm.v8f64.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRD]], i16 1, i32 0, <8 x double> %passthru) %res = call <8 x double> @llvm.masked.gather.v8f64.v8p3f64(<8 x double addrspace(3)*> %pi64, i32 8, <8 x i1> %mask, <8 x double> %passthru) ret <8 x double> %res } define <8 x i8*> @test_ptr(<8 x i8* addrspace(3)*> %pptr, <8 x i1> %mask, <8 x i8*> %passthru) { -; CHECK: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-TYPED-PTRS: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-OPAQUE-PTRS: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pptr to <8 x i32> ; CHECK: [[CASTP:[^ ]+]] = bitcast <8 x i64> [[PTI]] to <16 x i32> ; CHECK: [[STOAP:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTP]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: [[LOADP:[^ ]+]] = call <16 x i32> @llvm.genx.gather4.scaled.v16i32.v8i1.v8i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDRP]], <16 x i32> [[STOAP]]) ; CHECK: [[ATOSP:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[LOADP]], i32 1, i32 2, i32 8, i16 0, i32 undef) ; CHECK: [[ITP:[^ ]+]] = bitcast <16 x i32> [[ATOSP]] to <8 x i64> -; CHECK: %res = inttoptr <8 x i64> [[ITP]] to <8 x i8*> -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-TYPED-PTRS: %res = inttoptr <8 x i64> [[ITP]] to <8 x i8*> +; CHECK-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[ITP]] to <8 x ptr> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pptr to <8 x i32> ; CHECK-LSC: [[DATAP:[^ ]+]] = call <8 x i64> @llvm.vc.internal.lsc.load.slm.v8i64.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) -; CHECK-LSC: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-TYPED-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x ptr> %res = call <8 x i8*> @llvm.masked.gather.v8p0i8.v8p3p0i8(<8 x i8* addrspace(3)*> %pptr, i32 8, <8 x i1> %mask, <8 x i8*> %passthru) ret <8 x i8*> %res } define <8 x i64> @test_i64_unaligned(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i64> %passthru) { -; CHECK: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK: [[CASTU64:[^ ]+]] = bitcast <8 x i64> %passthru to <16 x i32> ; CHECK: [[LOWU64:[^ ]+]] = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.i16(<16 x i32> [[CASTU64]], i32 2, i32 1, i32 0, i16 0, i32 undef) ; CHECK: [[HIGHU64:[^ ]+]] = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.i16(<16 x i32> [[CASTU64]], i32 2, i32 1, i32 0, i16 4, i32 undef) @@ -146,7 +169,8 @@ define <8 x i64> @test_i64_unaligned(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %ma ; CHECK: [[INSL64:[^ ]+]] = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.i16.i1(<16 x i32> undef, <8 x i32> [[LOADL64]], i32 2, i32 1, i32 0, i16 0, i32 undef, i1 true) ; CHECK: [[INSH64:[^ ]+]] = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.i16.i1(<16 x i32> %7, <8 x i32> [[LOADH64]], i32 2, i32 1, i32 0, i16 4, i32 undef, i1 true) ; CHECK: %res = bitcast <16 x i32> [[INSH64]] to <8 x i64> -; CHECK-LSC: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: %res = call <8 x i64> @llvm.vc.internal.lsc.load.slm.v8i64.v8i1.v2i8.v8i32(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRU64]], i16 1, i32 0, <8 x i64> %passthru) %res = call <8 x i64> @llvm.masked.gather.v8i64.v8p3i64(<8 x i64 addrspace(3)*> %pi64, i32 1, <8 x i1> %mask, <8 x i64> %passthru) ret <8 x i64> %res diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/gather-private.ll b/IGC/VectorCompiler/test/LoadStoreLowering/gather-private.ll index 6b04bef3f493..104017f5ad45 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/gather-private.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/gather-private.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -35,12 +37,14 @@ declare <8 x i8*> @llvm.masked.gather.v8p0i8.v8p0p0i8(<8 x i8**>, i32, <8 x i1>, define <8 x i8> @test_i8(<8 x i8*> %pi8, <8 x i1> %mask, <8 x i8> %passthru) { ; CHECK-DAG: [[PASSTHRU8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> ; CHECK-DAG: [[CAST8:[^ ]+]] = bitcast <8 x i32> [[PASSTHRU8]] to <32 x i8> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr> %pi8 to <8 x i64> ; CHECK: [[DATA8:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR8]], <32 x i8> [[CAST8]]) ; CHECK: [[LCAST8:[^ ]+]] = bitcast <32 x i8> [[DATA8]] to <8 x i32> ; CHECK: %res = trunc <8 x i32> [[LCAST8]] to <8 x i8> ; CHECK-LSC-DAG: [[PASSTHRU8:[^ ]+]] = zext <8 x i8> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr> %pi8 to <8 x i64> ; CHECK-LSC: [[DATA8:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 5, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR8]], i16 1, i32 0, <8 x i32> [[PASSTHRU8]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA8]] to <8 x i8> %res = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> %pi8, i32 1, <8 x i1> %mask, <8 x i8> %passthru) @@ -50,12 +54,14 @@ define <8 x i8> @test_i8(<8 x i8*> %pi8, <8 x i1> %mask, <8 x i8> %passthru) { define <8 x i16> @test_i16(<8 x i16*> %pi16, <8 x i1> %mask, <8 x i16> %passthru) { ; CHECK-DAG: [[PASSTHRU16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> ; CHECK-DAG: [[CAST16:[^ ]+]] = bitcast <8 x i32> [[PASSTHRU16]] to <32 x i8> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK: [[DATA16:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 1, <8 x i64> [[ADDR16]], <32 x i8> [[CAST16]]) ; CHECK: [[LCAST16:[^ ]+]] = bitcast <32 x i8> [[DATA16]] to <8 x i32> ; CHECK: %res = trunc <8 x i32> [[LCAST16]] to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRU16:[^ ]+]] = zext <8 x i16> %passthru to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK-LSC: [[DATA16:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR16]], i16 1, i32 0, <8 x i32> [[PASSTHRU16]]) ; CHECK-LSC: %res = trunc <8 x i32> [[DATA16]] to <8 x i16> %res = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %pi16, i32 2, <8 x i1> %mask, <8 x i16> %passthru) @@ -63,18 +69,22 @@ define <8 x i16> @test_i16(<8 x i16*> %pi16, <8 x i1> %mask, <8 x i16> %passthru } define <8 x i32> @test_i32(<8 x i32*> %pi32, <8 x i1> %mask, <8 x i32> %passthru) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK: %res = call <8 x i32> @llvm.genx.svm.gather.v8i32.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR32]], <8 x i32> %passthru) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK-LSC: %res = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i32> %passthru) %res = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> %pi32, i32 4, <8 x i1> %mask, <8 x i32> %passthru) ret <8 x i32> %res } define <8 x i64> @test_i64(<8 x i64*> %pi64, <8 x i1> %mask, <8 x i64> %passthru) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK: %res = call <8 x i64> @llvm.genx.svm.gather.v8i64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR64]], <8 x i64> %passthru) -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK-LSC: %res = call <8 x i64> @llvm.vc.internal.lsc.load.ugm.v8i64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i64> %passthru) %res = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %pi64, i32 8, <8 x i1> %mask, <8 x i64> %passthru) ret <8 x i64> %res @@ -84,14 +94,16 @@ define <8 x half> @test_f16(<8 x half*> %pi16, <8 x i1> %mask, <8 x half> %passt ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK-DAG: [[PASSTHRUH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> ; CHECK-DAG: [[CASTI:[^ ]+]] = bitcast <8 x i32> [[PASSTHRUH]] to <32 x i8> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK: [[DATAH:[^ ]+]] = call <32 x i8> @llvm.genx.svm.gather.v32i8.v8i1.v8i64(<8 x i1> %mask, i32 1, <8 x i64> [[ADDRH]], <32 x i8> [[CASTI]]) ; CHECK: [[LCASTH:[^ ]+]] = bitcast <32 x i8> [[DATAH]] to <8 x i32> ; CHECK: [[TRUNC:[^ ]+]] = trunc <8 x i32> [[LCASTH]] to <8 x i16> ; CHECK: %res = bitcast <8 x i16> [[TRUNC]] to <8 x half> ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %passthru to <8 x i16> ; CHECK-LSC-DAG: [[PASSTHRUH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK-LSC: [[DATAH:[^ ]+]] = call <8 x i32> @llvm.vc.internal.lsc.load.ugm.v8i32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRH]], i16 1, i32 0, <8 x i32> [[PASSTHRUH]]) ; CHECK-LSC: [[TRUNC:[^ ]+]] = trunc <8 x i32> [[DATAH]] to <8 x i16> ; CHECK-LSC: %res = bitcast <8 x i16> [[TRUNC]] to <8 x half> @@ -100,32 +112,42 @@ define <8 x half> @test_f16(<8 x half*> %pi16, <8 x i1> %mask, <8 x half> %passt } define <8 x float> @test_f32(<8 x float*> %pi32, <8 x i1> %mask, <8 x float> %passthru) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK: %res = call <8 x float> @llvm.genx.svm.gather.v8f32.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRF]], <8 x float> %passthru) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK-LSC: %res = call <8 x float> @llvm.vc.internal.lsc.load.ugm.v8f32.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRF]], i16 1, i32 0, <8 x float> %passthru) %res = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> %pi32, i32 4, <8 x i1> %mask, <8 x float> %passthru) ret <8 x float> %res } define <8 x double> @test_f64(<8 x double*> %pi64, <8 x i1> %mask, <8 x double> %passthru) { -; CHECK: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK: %res = call <8 x double> @llvm.genx.svm.gather.v8f64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRD]], <8 x double> %passthru) -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK-LSC: %res = call <8 x double> @llvm.vc.internal.lsc.load.ugm.v8f64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRD]], i16 1, i32 0, <8 x double> %passthru) %res = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> %pi64, i32 8, <8 x i1> %mask, <8 x double> %passthru) ret <8 x double> %res } define <8 x i8*> @test_ptr(<8 x i8**> %pptr, <8 x i1> %mask, <8 x i8*> %passthru) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr> %pptr to <8 x i64> ; CHECK: [[DATAP:[^ ]+]] = call <8 x i64> @llvm.genx.svm.gather.v8i64.v8i1.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRP]], <8 x i64> [[PTI]]) -; CHECK: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-TYPED-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x ptr> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %passthru to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %passthru to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr> %pptr to <8 x i64> ; CHECK-LSC: [[DATAP:[^ ]+]] = call <8 x i64> @llvm.vc.internal.lsc.load.ugm.v8i64.v8i1.v2i8.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) -; CHECK-LSC: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-TYPED-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x i8*> +; CHECK-LSC-OPAQUE-PTRS: %res = inttoptr <8 x i64> [[DATAP]] to <8 x ptr> %res = call <8 x i8*> @llvm.masked.gather.v8p0i8.v8p0p0i8(<8 x i8**> %pptr, i32 8, <8 x i1> %mask, <8 x i8*> %passthru) ret <8 x i8*> %res } diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global-a32.ll b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global-a32.ll index c941177ecb7e..0b9131365dfb 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global-a32.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global-a32.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -34,10 +36,12 @@ declare void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*>, <8 x i8* addrspace( define void @test_i8(<8 x i8 addrspace(6)*> %pi8, <8 x i1> %mask, <8 x i8> %data) { ; CHECK-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(6)*> %pi8 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(6)*> %pi8 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi8 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 0, i16 0, i32 255, i32 0, <8 x i32> [[ADDR8]], <8 x i32> [[DATA8]]) ; CHECK-LSC-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(6)*> %pi8 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(6)*> %pi8 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi8 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 5, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDR8]], i16 1, i32 0, <8 x i32> [[DATA8]]) call void @llvm.masked.scatter.v8p1i8.v8i8(<8 x i8> %data, <8 x i8 addrspace(6)*> %pi8, i32 1, <8 x i1> %mask) ret void @@ -45,30 +49,36 @@ define void @test_i8(<8 x i8 addrspace(6)*> %pi8, <8 x i1> %mask, <8 x i8> %data define void @test_i16(<8 x i16 addrspace(6)*> %pi16, <8 x i1> %mask, <8 x i16> %data) { ; CHECK-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(6)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(6)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi16 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 255, i32 0, <8 x i32> [[ADDR16]], <8 x i32> [[DATA16]]) ; CHECK-LSC-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(6)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(6)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi16 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDR16]], i16 1, i32 0, <8 x i32> [[DATA16]]) call void @llvm.masked.scatter.v8p1i16.v8i16(<8 x i16> %data, <8 x i16 addrspace(6)*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_i32(<8 x i32 addrspace(6)*> %pi32, <8 x i1> %mask, <8 x i32> %data) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(6)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(6)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi32 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 2, i16 0, i32 255, i32 0, <8 x i32> [[ADDR32]], <8 x i32> %data) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(6)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(6)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi32 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDR32]], i16 1, i32 0, <8 x i32> %data) call void @llvm.masked.scatter.v8p1i32.v8i32(<8 x i32> %data, <8 x i32 addrspace(6)*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_i64(<8 x i64 addrspace(6)*> %pi64, <8 x i1> %mask, <8 x i64> %data) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(6)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(6)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi64 to <8 x i32> ; CHECK: [[CAST64:[^ ]+]] = bitcast <8 x i64> %data to <16 x i32> ; CHECK: [[S2A64:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CAST64]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 255, i32 0, <8 x i32> [[ADDR64]], <16 x i32> [[S2A64]]) -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(6)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(6)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi64 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDR64]], i16 1, i32 0, <8 x i64> %data) call void @llvm.masked.scatter.v8p1i64.v8i64(<8 x i64> %data, <8 x i64 addrspace(6)*> %pi64, i32 8, <8 x i1> %mask) ret void @@ -77,44 +87,54 @@ define void @test_i64(<8 x i64 addrspace(6)*> %pi64, <8 x i1> %mask, <8 x i64> % define void @test_f16(<8 x half addrspace(6)*> %pi16, <8 x i1> %mask, <8 x half> %data) { ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(6)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(6)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi16 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 255, i32 0, <8 x i32> [[ADDRH]], <8 x i32> [[DATAH]]) ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-LSC-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(6)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(6)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi16 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDRH]], i16 1, i32 0, <8 x i32> [[DATAH]]) call void @llvm.masked.scatter.v8p1f16.v8f16(<8 x half> %data, <8 x half addrspace(6)*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_f32(<8 x float addrspace(6)*> %pi32, <8 x i1> %mask, <8 x float> %data) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(6)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(6)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi32 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8f32(<8 x i1> %mask, i32 2, i16 0, i32 255, i32 0, <8 x i32> [[ADDRF]], <8 x float> %data) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(6)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(6)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi32 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8f32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDRF]], i16 1, i32 0, <8 x float> %data) call void @llvm.masked.scatter.v8p1f32.v8f32(<8 x float> %data, <8 x float addrspace(6)*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_f64(<8 x double addrspace(6)*> %pi64, <8 x i1> %mask, <8 x double> %data) { -; CHECK-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(6)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(6)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi64 to <8 x i32> ; CHECK-DAG: [[CASTD:[^ ]+]] = bitcast <8 x double> %data to <16 x i32> ; CHECK-DAG: [[S2AD:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTD]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 255, i32 0, <8 x i32> [[ADDRD]], <16 x i32> [[S2AD]]) -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(6)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(6)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pi64 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8f64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDRD]], i16 1, i32 0, <8 x double> %data) call void @llvm.masked.scatter.v8p1f64.v8f64(<8 x double> %data, <8 x double addrspace(6)*> %pi64, i32 8, <8 x i1> %mask) ret void } define void @test_ptr(<8 x i8* addrspace(6)*> %pptr, <8 x i1> %mask, <8 x i8*> %data) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> ; CHECK-DAG: [[CASTP:[^ ]+]] = bitcast <8 x i64> [[PTI]] to <16 x i32> ; CHECK-DAG: [[S2AP:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTP]], i32 1, i32 8, i32 2, i16 0, i32 undef) -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(6)*> %pptr to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(6)*> %pptr to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pptr to <8 x i32> ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 255, i32 0, <8 x i32> [[ADDRP]], <16 x i32> [[S2AP]]) -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(6)*> %pptr to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(6)*> %pptr to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(6)> %pptr to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.bti.v8i1.v2i8.v8i32.v8i64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 255, <8 x i32> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) call void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*> %data, <8 x i8* addrspace(6)*> %pptr, i32 8, <8 x i1> %mask) ret void diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global.ll b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global.ll index 8ba893c58e6f..a53d91728170 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-global.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -35,10 +37,12 @@ declare void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*>, <8 x i8* addrspace( define void @test_i8(<8 x i8 addrspace(1)*> %pi8, <8 x i1> %mask, <8 x i8> %data) { ; CHECK-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> ; CHECK-DAG: [[CAST8:[^ ]+]] = bitcast <8 x i32> [[DATA8]] to <32 x i8> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi8 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR8]], <32 x i8> [[CAST8]]) ; CHECK-LSC-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(1)*> %pi8 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi8 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 5, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR8]], i16 1, i32 0, <8 x i32> [[DATA8]]) call void @llvm.masked.scatter.v8p1i8.v8i8(<8 x i8> %data, <8 x i8 addrspace(1)*> %pi8, i32 1, <8 x i1> %mask) ret void @@ -47,28 +51,34 @@ define void @test_i8(<8 x i8 addrspace(1)*> %pi8, <8 x i1> %mask, <8 x i8> %data define void @test_i16(<8 x i16 addrspace(1)*> %pi16, <8 x i1> %mask, <8 x i16> %data) { ; CHECK-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> ; CHECK-DAG: [[CAST16:[^ ]+]] = bitcast <8 x i32> [[DATA16]] to <32 x i8> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 1, <8 x i64> [[ADDR16]], <32 x i8> [[CAST16]]) ; CHECK-LSC-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR16]], i16 1, i32 0, <8 x i32> [[DATA16]]) call void @llvm.masked.scatter.v8p1i16.v8i16(<8 x i16> %data, <8 x i16 addrspace(1)*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_i32(<8 x i32 addrspace(1)*> %pi32, <8 x i1> %mask, <8 x i32> %data) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i32(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR32]], <8 x i32> %data) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i32> %data) call void @llvm.masked.scatter.v8p1i32.v8i32(<8 x i32> %data, <8 x i32 addrspace(1)*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_i64(<8 x i64 addrspace(1)*> %pi64, <8 x i1> %mask, <8 x i64> %data) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR64]], <8 x i64> %data) -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i64> %data) call void @llvm.masked.scatter.v8p1i64.v8i64(<8 x i64> %data, <8 x i64 addrspace(1)*> %pi64, i32 8, <8 x i1> %mask) ret void @@ -78,40 +88,50 @@ define void @test_f16(<8 x half addrspace(1)*> %pi16, <8 x i1> %mask, <8 x half> ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> ; CHECK-DAG: [[CAST2H:[^ ]+]] = bitcast <8 x i32> [[DATAH]] to <32 x i8> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 1, <8 x i64> [[ADDRH]], <32 x i8> [[CAST2H]]) ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-LSC-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(1)*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi16 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRH]], i16 1, i32 0, <8 x i32> [[DATAH]]) call void @llvm.masked.scatter.v8p1f16.v8f16(<8 x half> %data, <8 x half addrspace(1)*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_f32(<8 x float addrspace(1)*> %pi32, <8 x i1> %mask, <8 x float> %data) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8f32(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRF]], <8 x float> %data) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(1)*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi32 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8f32(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRF]], i16 1, i32 0, <8 x float> %data) call void @llvm.masked.scatter.v8p1f32.v8f32(<8 x float> %data, <8 x float addrspace(1)*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_f64(<8 x double addrspace(1)*> %pi64, <8 x i1> %mask, <8 x double> %data) { -; CHECK: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8f64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRD]], <8 x double> %data) -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(1)*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pi64 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8f64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRD]], i16 1, i32 0, <8 x double> %data) call void @llvm.masked.scatter.v8p1f64.v8f64(<8 x double> %data, <8 x double addrspace(1)*> %pi64, i32 8, <8 x i1> %mask) ret void } define void @test_ptr(<8 x i8* addrspace(1)*> %pptr, <8 x i1> %mask, <8 x i8*> %data) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pptr to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRP]], <8 x i64> [[PTI]]) -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(1)*> %pptr to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(1)> %pptr to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) call void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*> %data, <8 x i8* addrspace(1)*> %pptr, i32 8, <8 x i1> %mask) ret void diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-local.ll b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-local.ll index 6edf22cd9081..17d8e0a6b297 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-local.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-local.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -34,11 +36,13 @@ declare void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*>, <8 x i8* addrspace( define void @test_i8(<8 x i8 addrspace(3)*> %pi8, <8 x i1> %mask, <8 x i8> %data) { ; CHECK-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi8 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 0, i16 0, i32 254, i32 0, <8 x i32> [[ADDR8]], <8 x i32> [[DATA8]]) ; CHECK-SAME: !VCAlignment [[MDALIGN1:![0-9]+]] ; CHECK-LSC-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8 addrspace(3)*> %pi8 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi8 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 5, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR8]], i16 1, i32 0, <8 x i32> [[DATA8]]) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN1:![0-9]+]] call void @llvm.masked.scatter.v8p1i8.v8i8(<8 x i8> %data, <8 x i8 addrspace(3)*> %pi8, i32 1, <8 x i1> %mask) @@ -47,11 +51,13 @@ define void @test_i8(<8 x i8 addrspace(3)*> %pi8, <8 x i1> %mask, <8 x i8> %data define void @test_i16(<8 x i16 addrspace(3)*> %pi16, <8 x i1> %mask, <8 x i16> %data) { ; CHECK-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 254, i32 0, <8 x i32> [[ADDR16]], <8 x i32> [[DATA16]]) ; CHECK-SAME: !VCAlignment [[MDALIGN2:![0-9]+]] ; CHECK-LSC-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16 addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR16]], i16 1, i32 0, <8 x i32> [[DATA16]]) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN2:![0-9]+]] call void @llvm.masked.scatter.v8p1i16.v8i16(<8 x i16> %data, <8 x i16 addrspace(3)*> %pi16, i32 2, <8 x i1> %mask) @@ -59,10 +65,12 @@ define void @test_i16(<8 x i16 addrspace(3)*> %pi16, <8 x i1> %mask, <8 x i16> % } define void @test_i32(<8 x i32 addrspace(3)*> %pi32, <8 x i1> %mask, <8 x i32> %data) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 2, i16 0, i32 254, i32 0, <8 x i32> [[ADDR32]], <8 x i32> %data) ; CHECK-SAME: !VCAlignment [[MDALIGN4:![0-9]+]] -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32 addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR32]], i16 1, i32 0, <8 x i32> %data) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN4:![0-9]+]] call void @llvm.masked.scatter.v8p1i32.v8i32(<8 x i32> %data, <8 x i32 addrspace(3)*> %pi32, i32 4, <8 x i1> %mask) @@ -70,12 +78,14 @@ define void @test_i32(<8 x i32 addrspace(3)*> %pi32, <8 x i1> %mask, <8 x i32> % } define void @test_i64(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i64> %data) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK: [[CAST64:[^ ]+]] = bitcast <8 x i64> %data to <16 x i32> ; CHECK: [[S2A64:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CAST64]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDR64]], <16 x i32> [[S2A64]]) ; CHECK-SAME: !VCAlignment [[MDALIGN8:![0-9]+]] -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDR64]], i16 1, i32 0, <8 x i64> %data) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN8:![0-9]+]] call void @llvm.masked.scatter.v8p1i64.v8i64(<8 x i64> %data, <8 x i64 addrspace(3)*> %pi64, i32 8, <8 x i1> %mask) @@ -85,12 +95,14 @@ define void @test_i64(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i64> % define void @test_f16(<8 x half addrspace(3)*> %pi16, <8 x i1> %mask, <8 x half> %data) { ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 1, i16 0, i32 254, i32 0, <8 x i32> [[ADDRH]], <8 x i32> [[DATAH]]) ; CHECK-SAME: !VCAlignment [[MDALIGN2]] ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-LSC-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half addrspace(3)*> %pi16 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi16 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i32(<8 x i1> %mask, i8 2, i8 6, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRH]], i16 1, i32 0, <8 x i32> [[DATAH]]) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN2]] call void @llvm.masked.scatter.v8p1f16.v8f16(<8 x half> %data, <8 x half addrspace(3)*> %pi16, i32 2, <8 x i1> %mask) @@ -98,10 +110,12 @@ define void @test_f16(<8 x half addrspace(3)*> %pi16, <8 x i1> %mask, <8 x half> } define void @test_f32(<8 x float addrspace(3)*> %pi32, <8 x i1> %mask, <8 x float> %data) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8f32(<8 x i1> %mask, i32 2, i16 0, i32 254, i32 0, <8 x i32> [[ADDRF]], <8 x float> %data) ; CHECK-SAME: !VCAlignment [[MDALIGN4]] -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float addrspace(3)*> %pi32 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi32 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8f32(<8 x i1> %mask, i8 2, i8 3, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRF]], i16 1, i32 0, <8 x float> %data) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN4]] call void @llvm.masked.scatter.v8p1f32.v8f32(<8 x float> %data, <8 x float addrspace(3)*> %pi32, i32 4, <8 x i1> %mask) @@ -109,12 +123,14 @@ define void @test_f32(<8 x float addrspace(3)*> %pi32, <8 x i1> %mask, <8 x floa } define void @test_f64(<8 x double addrspace(3)*> %pi64, <8 x i1> %mask, <8 x double> %data) { -; CHECK-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-DAG: [[CASTD:[^ ]+]] = bitcast <8 x double> %data to <16 x i32> ; CHECK-DAG: [[S2AD:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTD]], i32 1, i32 8, i32 2, i16 0, i32 undef) ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDRD]], <16 x i32> [[S2AD]]) ; CHECK-SAME: !VCAlignment [[MDALIGN8]] -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8f64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRD]], i16 1, i32 0, <8 x double> %data) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN8]] call void @llvm.masked.scatter.v8p1f64.v8f64(<8 x double> %data, <8 x double addrspace(3)*> %pi64, i32 8, <8 x i1> %mask) @@ -122,14 +138,18 @@ define void @test_f64(<8 x double addrspace(3)*> %pi64, <8 x i1> %mask, <8 x dou } define void @test_ptr(<8 x i8* addrspace(3)*> %pptr, <8 x i1> %mask, <8 x i8*> %data) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> ; CHECK-DAG: [[CASTP:[^ ]+]] = bitcast <8 x i64> [[PTI]] to <16 x i32> ; CHECK-DAG: [[S2AP:[^ ]+]] = call <16 x i32> @llvm.genx.rdregioni.v16i32.v16i32.i16(<16 x i32> [[CASTP]], i32 1, i32 8, i32 2, i16 0, i32 undef) -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pptr to <8 x i32> ; CHECK: call void @llvm.genx.scatter4.scaled.v8i1.v8i32.v16i32(<8 x i1> %mask, i32 12, i16 0, i32 254, i32 0, <8 x i32> [[ADDRP]], <16 x i32> [[S2AP]]) ; CHECK-SAME: !VCAlignment [[MDALIGN8]] -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8* addrspace(3)*> %pptr to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pptr to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN8]] call void @llvm.masked.scatter.v8p1p0i8.v8p0i8(<8 x i8*> %data, <8 x i8* addrspace(3)*> %pptr, i32 8, <8 x i1> %mask) @@ -137,7 +157,8 @@ define void @test_ptr(<8 x i8* addrspace(3)*> %pptr, <8 x i1> %mask, <8 x i8*> % } define void @test_i64_unaligned(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, <8 x i64> %data) { -; CHECK: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-TYPED-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-OPAQUE-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK: [[CASTU64:[^ ]+]] = bitcast <8 x i64> %data to <16 x i32> ; CHECK: [[LOWU64:[^ ]+]] = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.i16(<16 x i32> [[CASTU64]], i32 2, i32 1, i32 0, i16 0, i32 undef) ; CHECK: [[HIGHU64:[^ ]+]] = call <8 x i32> @llvm.genx.rdregioni.v8i32.v16i32.i16(<16 x i32> [[CASTU64]], i32 2, i32 1, i32 0, i16 4, i32 undef) @@ -145,7 +166,8 @@ define void @test_i64_unaligned(<8 x i64 addrspace(3)*> %pi64, <8 x i1> %mask, < ; CHECK-SAME: !VCAlignment [[MDALIGN1]] ; CHECK: call void @llvm.genx.scatter.scaled.v8i1.v8i32.v8i32(<8 x i1> %mask, i32 2, i16 0, i32 254, i32 4, <8 x i32> [[ADDRU64]], <8 x i32> [[HIGHU64]]) ; CHECK-SAME: !VCAlignment [[MDALIGN1]] -; CHECK-LSC: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-TYPED-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x i64 addrspace(3)*> %pi64 to <8 x i32> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRU64:[^ ]+]] = ptrtoint <8 x ptr addrspace(3)> %pi64 to <8 x i32> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.slm.v8i1.v2i8.v8i32.v8i64(<8 x i1> %mask, i8 2, i8 4, i8 1, <2 x i8> zeroinitializer, i32 0, <8 x i32> [[ADDRU64]], i16 1, i32 0, <8 x i64> %data) ; CHECK-LSC-SAME: !VCAlignment [[MDALIGN1]] call void @llvm.masked.scatter.v8p1i64.v8i64(<8 x i64> %data, <8 x i64 addrspace(3)*> %pi64, i32 1, <8 x i1> %mask) diff --git a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-private.ll b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-private.ll index ada45e14ed01..7492e9f1e119 100644 --- a/IGC/VectorCompiler/test/LoadStoreLowering/scatter-private.ll +++ b/IGC/VectorCompiler/test/LoadStoreLowering/scatter-private.ll @@ -1,14 +1,16 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= ; -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck --check-prefix=CHECK-LSC %s +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS +; RUN: %opt_typed_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-TYPED-PTRS +; RUN: %opt_opaque_ptrs %use_old_pass_manager% -enable-debugify -GenXLoadStoreLowering -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -enable-ldst-lowering=true -mattr=+ocl_runtime -S < %s 2>&1 | FileCheck %s --check-prefixes=CHECK-LSC,CHECK-LSC-OPAQUE-PTRS ; ; CHECK-NOT: WARNING ; CHECK: CheckModuleDebugify: PASS @@ -35,10 +37,12 @@ declare void @llvm.masked.scatter.v8p0p0i8.v8p0i8(<8 x i8*>, <8 x i8**>, i32, <8 define void @test_i8(<8 x i8*> %pi8, <8 x i1> %mask, <8 x i8> %data) { ; CHECK-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> ; CHECK-DAG: [[CAST8:[^ ]+]] = bitcast <8 x i32> [[DATA8]] to <32 x i8> -; CHECK-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr> %pi8 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR8]], <32 x i8> [[CAST8]]) ; CHECK-LSC-DAG: [[DATA8:[^ ]+]] = zext <8 x i8> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x i8*> %pi8 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR8:[^ ]+]] = ptrtoint <8 x ptr> %pi8 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 5, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR8]], i16 1, i32 0, <8 x i32> [[DATA8]]) call void @llvm.masked.scatter.v8p0i8.v8i8(<8 x i8> %data, <8 x i8*> %pi8, i32 1, <8 x i1> %mask) ret void @@ -47,28 +51,34 @@ define void @test_i8(<8 x i8*> %pi8, <8 x i1> %mask, <8 x i8> %data) { define void @test_i16(<8 x i16*> %pi16, <8 x i1> %mask, <8 x i16> %data) { ; CHECK-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> ; CHECK-DAG: [[CAST16:[^ ]+]] = bitcast <8 x i32> [[DATA16]] to <32 x i8> -; CHECK-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 1, <8 x i64> [[ADDR16]], <32 x i8> [[CAST16]]) ; CHECK-LSC-DAG: [[DATA16:[^ ]+]] = zext <8 x i16> %data to <8 x i32> -; CHECK-LSC-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x i16*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDR16:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR16]], i16 1, i32 0, <8 x i32> [[DATA16]]) call void @llvm.masked.scatter.v8p0i16.v8i16(<8 x i16> %data, <8 x i16*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_i32(<8 x i32*> %pi32, <8 x i1> %mask, <8 x i32> %data) { -; CHECK: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i32(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR32]], <8 x i32> %data) -; CHECK-LSC: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x i32*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR32:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i32> %data) call void @llvm.masked.scatter.v8p0i32.v8i32(<8 x i32> %data, <8 x i32*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_i64(<8 x i64*> %pi64, <8 x i1> %mask, <8 x i64> %data) { -; CHECK: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDR64]], <8 x i64> %data) -; CHECK-LSC: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x i64*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDR64:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDR32]], i16 1, i32 0, <8 x i64> %data) call void @llvm.masked.scatter.v8p0i64.v8i64(<8 x i64> %data, <8 x i64*> %pi64, i32 8, <8 x i1> %mask) ret void @@ -78,40 +88,50 @@ define void @test_f16(<8 x half*> %pi16, <8 x i1> %mask, <8 x half> %data) { ; CHECK-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> ; CHECK-DAG: [[CAST2H:[^ ]+]] = bitcast <8 x i32> [[DATAH]] to <32 x i8> -; CHECK-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v32i8(<8 x i1> %mask, i32 1, <8 x i64> [[ADDRH]], <32 x i8> [[CAST2H]]) ; CHECK-LSC-DAG: [[CASTH:[^ ]+]] = bitcast <8 x half> %data to <8 x i16> ; CHECK-LSC-DAG: [[DATAH:[^ ]+]] = zext <8 x i16> [[CASTH]] to <8 x i32> -; CHECK-LSC-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x half*> %pi16 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRH:[^ ]+]] = ptrtoint <8 x ptr> %pi16 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i32(<8 x i1> %mask, i8 3, i8 6, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRH]], i16 1, i32 0, <8 x i32> [[DATAH]]) call void @llvm.masked.scatter.v8p0f16.v8f16(<8 x half> %data, <8 x half*> %pi16, i32 2, <8 x i1> %mask) ret void } define void @test_f32(<8 x float*> %pi32, <8 x i1> %mask, <8 x float> %data) { -; CHECK: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8f32(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRF]], <8 x float> %data) -; CHECK-LSC: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x float*> %pi32 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRF:[^ ]+]] = ptrtoint <8 x ptr> %pi32 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8f32(<8 x i1> %mask, i8 3, i8 3, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRF]], i16 1, i32 0, <8 x float> %data) call void @llvm.masked.scatter.v8p0f32.v8f32(<8 x float> %data, <8 x float*> %pi32, i32 4, <8 x i1> %mask) ret void } define void @test_f64(<8 x double*> %pi64, <8 x i1> %mask, <8 x double> %data) { -; CHECK: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8f64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRD]], <8 x double> %data) -; CHECK-LSC: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-LSC-TYPED-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x double*> %pi64 to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS: [[ADDRD:[^ ]+]] = ptrtoint <8 x ptr> %pi64 to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8f64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRD]], i16 1, i32 0, <8 x double> %data) call void @llvm.masked.scatter.v8p0f64.v8f64(<8 x double> %data, <8 x double*> %pi64, i32 8, <8 x i1> %mask) ret void } define void @test_ptr(<8 x i8**> %pptr, <8 x i1> %mask, <8 x i8*> %data) { -; CHECK-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr> %pptr to <8 x i64> ; CHECK: call void @llvm.genx.svm.scatter.v8i1.v8i64.v8i64(<8 x i1> %mask, i32 0, <8 x i64> [[ADDRP]], <8 x i64> [[PTI]]) -; CHECK-LSC-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> -; CHECK-LSC-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x i8*> %data to <8 x i64> +; CHECK-LSC-TYPED-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x i8**> %pptr to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[PTI:[^ ]+]] = ptrtoint <8 x ptr> %data to <8 x i64> +; CHECK-LSC-OPAQUE-PTRS-DAG: [[ADDRP:[^ ]+]] = ptrtoint <8 x ptr> %pptr to <8 x i64> ; CHECK-LSC: call void @llvm.vc.internal.lsc.store.ugm.v8i1.v2i8.v8i64.v8i64(<8 x i1> %mask, i8 3, i8 4, i8 1, <2 x i8> zeroinitializer, i64 0, <8 x i64> [[ADDRP]], i16 1, i32 0, <8 x i64> [[PTI]]) call void @llvm.masked.scatter.v8p0p0i8.v8p0i8(<8 x i8*> %data, <8 x i8**> %pptr, i32 8, <8 x i1> %mask) ret void