From e1259d56b97afd1ffc9485afdd655a64f3d87cc3 Mon Sep 17 00:00:00 2001 From: Maksim Shelegov Date: Mon, 5 Aug 2024 14:09:31 +0000 Subject: [PATCH] Enable legacy memory intrinsic translation by default . --- IGC/VectorCompiler/lib/GenXCodeGen/GenX.td | 5 +++++ IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp | 2 +- IGC/VectorCompiler/test/CisaBuilder/math_f16.ll | 3 ++- IGC/VectorCompiler/test/CisaBuilder/math_f32.ll | 3 ++- IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll | 5 ++++- IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll | 4 ++-- .../test/GenXLegacyToLscTranslator/gather-scatter.ll | 5 +++-- .../test/GenXLegacyToLscTranslator/gather4-scatter4.ll | 5 +++-- .../test/GenXLegacyToLscTranslator/media-block-ld.ll | 3 +-- .../test/GenXLegacyToLscTranslator/media-block-st.ll | 6 ++---- IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll | 5 +++-- 11 files changed, 28 insertions(+), 18 deletions(-) diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td index 13e6264e2b2a..13c91203695e 100644 --- a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td @@ -383,6 +383,7 @@ def : Proc<"XeHPG", [ FeatureMultiIndirectByteRegioning, FeatureSLM128K, FeatureThreadPayloadInMemory, + FeatureTransLegacy, ]>; def : Proc<"XeLPG", [ @@ -404,6 +405,7 @@ def : Proc<"XeLPG", [ FeatureMultiIndirectByteRegioning, FeatureSLM128K, FeatureThreadPayloadInMemory, + FeatureTransLegacy, ]>; def : Proc<"XeLPGPlus", [ @@ -425,6 +427,7 @@ def : Proc<"XeLPGPlus", [ FeatureMultiIndirectByteRegioning, FeatureSLM128K, FeatureThreadPayloadInMemory, + FeatureTransLegacy, ]>; def : Proc<"XeHPC", [ @@ -451,6 +454,7 @@ def : Proc<"XeHPC", [ FeatureSLM128K, FeatureSwitchjmp, FeatureThreadPayloadInMemory, + FeatureTransLegacy, ]>; def : Proc<"XeHPCVG", [ @@ -477,6 +481,7 @@ def : Proc<"XeHPCVG", [ FeatureSLM128K, FeatureSwitchjmp, FeatureThreadPayloadInMemory, + FeatureTransLegacy, ]>; def : Proc<"Xe2", [ diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp index ed4499999a46..98191987f807 100644 --- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp +++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp @@ -212,7 +212,7 @@ KernelArgBuilder::getOCLArgKind(ArrayRef Tokens, if (any_of(Tokens, getStrPred(OCLAttributes::Image2dArray))) return ArgKindType::Image2DArray; if (any_of(Tokens, getStrPred(OCLAttributes::Image2dMediaBlock))) { - if (ST.translateLegacyMessages()) + if (ST.translateMediaBlockMessages()) return ArgKindType::Image2D; return ArgKindType::Image2DMediaBlock; } diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll index 9bca67225793..8a3e64d01c1a 100644 --- a/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll +++ b/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll @@ -1,6 +1,6 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; @@ -14,6 +14,7 @@ ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;; +; CHECK: .decl {{V[^ ]+}} v_type=G type=hf num_elts=8 ; CHECK: .decl [[SRC:V[^ ]+]] v_type=G type=hf num_elts=8 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0> ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0> diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll index 031207f682c0..0e758f757393 100644 --- a/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll +++ b/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll @@ -1,6 +1,6 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; @@ -14,6 +14,7 @@ ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;; +; CHECK: .decl {{V[^ ]+}} v_type=G type=f num_elts=8 ; CHECK: .decl [[SRC:V[^ ]+]] v_type=G type=f num_elts=8 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0> ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0> diff --git a/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll b/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll index 9356ed0f1cf5..1ed39a9f9e63 100644 --- a/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll +++ b/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll @@ -14,19 +14,22 @@ ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;; +; CHECK: .decl [[SURF:V[^ ]+]] v_type=G type=d num_elts=1 align=dword ; CHECK: .decl [[TMC_1:V[^ ]+]] v_type=G type=q num_elts=1 align=qword ; CHECK: .decl [[TMC_2:V[^ ]+]] v_type=G type=q num_elts=1 align=qword ; CHECK: .decl [[RES:V[^ ]+]] v_type=G type=d num_elts=8 align=GRF +; CHECK: .decl [[ALIAS_SURF:V[^ ]+]] v_type=G type=ud num_elts=1 alias=<[[SURF]], 0> ; CHECK: .decl [[ALIAS_1:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_1]], 0> ; CHECK: .decl [[ALIAS_2:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_2]], 0> ; CHECK: .decl [[ALIAS_RES:V[^ ]+]] v_type=G type=q num_elts=4 alias=<[[RES]], 0> ; CHECK: .decl [[SURFACE:T[^ ]+]] v_type=T num_elts=1 +; CHECK: movs (M1, 1) [[ALIAS_SURF]](0,0)<1> [[SURFACE]](0) ; CHECK: mov (M1, 2) [[ALIAS_1]](0,0)<1> %tsc(0,0)<1;1,0> ; CHECK: mov (M1, 2) [[ALIAS_2]](0,0)<1> %tsc(0,0)<1;1,0> ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,0)<1> [[TMC_1]](0,0)<0;1,0> ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,1)<1> [[TMC_2]](0,0)<0;1,0> -; CHECK: oword_st (2) [[SURFACE]] 0x0:ud [[RES]] +; CHECK: lsc_store.ugm (M1, 1) bti([[SURF]])[{{V[^ ]+}}]:a32 [[RES]]:d32x8t ; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;; diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll index 54a6b453bcdc..1dfa7c876088 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll @@ -1,12 +1,12 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s +; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown" diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll index 9649bf27acd6..5490f278ef79 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s +; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \ +; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown" diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll index df67d8175b4b..69ce0c04a30a 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s +; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \ +; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown" diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll index 7ad46622f284..ea0f9ec43415 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll @@ -10,8 +10,7 @@ ; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \ -; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \ -; RUN: FileCheck --check-prefix=NOTYPED %s +; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck --check-prefix=NOTYPED %s ; COM: media.ld -> llvm.vc.internal.lsc.load.2d.tgm.bti diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll index 827c03f1aeb0..bfa570ebd6a5 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll @@ -7,12 +7,10 @@ ;============================ end_copyright_notice ============================= ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=Xe2 \ -; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \ -; RUN: FileCheck %s +; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \ -; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \ -; RUN: FileCheck --check-prefix=NOTYPED %s +; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck --check-prefix=NOTYPED %s ; COM: media.st -> llvm.genx.lsc.store2d.typed.bti diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll index bf452c3be25e..506d9c1fd1a8 100644 --- a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll +++ b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll @@ -1,12 +1,13 @@ ;=========================== begin_copyright_notice ============================ ; -; Copyright (C) 2023 Intel Corporation +; Copyright (C) 2023-2024 Intel Corporation ; ; SPDX-License-Identifier: MIT ; ;============================ end_copyright_notice ============================= -; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s +; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \ +; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s target datalayout = "e-p:64:64-i64:64-n8:16:32:64" target triple = "genx64-unknown-unknown"