From 1d8aaa494350c3c37ec98edc713570797209ef15 Mon Sep 17 00:00:00 2001 From: Alberto Cabrera Date: Tue, 9 Apr 2024 13:57:02 +0100 Subject: [PATCH] [SYCL][COMPAT] NVPTX nd_range_barrier seq_cst memory order --- sycl/doc/syclcompat/README.md | 4 ++-- sycl/include/syclcompat/util.hpp | 4 +--- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/sycl/doc/syclcompat/README.md b/sycl/doc/syclcompat/README.md index 45b48a3896d33..8b840a8eec0c3 100644 --- a/sycl/doc/syclcompat/README.md +++ b/sycl/doc/syclcompat/README.md @@ -1129,8 +1129,8 @@ spec, and so should be used with caution. namespace syclcompat { namespace experimental { - #if defined(__AMDGPU__) || defined(__NVPTX__) -// seq_cst currently not working with AMD and Nvidia Backends +#if defined(__AMDGPU__) +// seq_cst currently not working for AMD constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::acq_rel; #else constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::seq_cst; diff --git a/sycl/include/syclcompat/util.hpp b/sycl/include/syclcompat/util.hpp index f6b9ccf937d41..b644971465e4a 100644 --- a/sycl/include/syclcompat/util.hpp +++ b/sycl/include/syclcompat/util.hpp @@ -281,9 +281,7 @@ inline int get_sycl_language_version() { namespace experimental { -#if defined(__AMDGPU__) || defined(__NVPTX__) -// FIXME: https://github.com/intel/llvm/pull/12516 adds seq_cst support for the -// CUDA backend. +#if defined(__AMDGPU__) constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::acq_rel; #else constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::seq_cst;