diff --git a/buildbot/configure.py b/buildbot/configure.py index 344da7eed7a72..5a7fdd003a1de 100644 --- a/buildbot/configure.py +++ b/buildbot/configure.py @@ -64,7 +64,7 @@ def do_configure(args): sycl_enable_xpti_tracing = "ON" xpti_enable_werror = "OFF" - llvm_enable_zstd = "OFF" + llvm_enable_zstd = "ON" if sys.platform != "darwin": sycl_enabled_backends.append("level_zero") @@ -134,8 +134,6 @@ def do_configure(args): # For clang-format, clang-tidy and code coverage llvm_enable_projects += ";clang-tools-extra;compiler-rt" - # Build with zstd disabled on CI for now. - llvm_enable_zstd = "OFF" if sys.platform != "darwin": # libclc is required for CI validation libclc_enabled = True diff --git a/clang/include/clang/Driver/Action.h b/clang/include/clang/Driver/Action.h index 1128376aa75ec..56cd24b8f2ead 100644 --- a/clang/include/clang/Driver/Action.h +++ b/clang/include/clang/Driver/Action.h @@ -698,6 +698,14 @@ class OffloadWrapperJobAction : public JobAction { // Get the compilation step setting. bool getCompileStep() const { return CompileStep; } + // Set the individual wrapping setting. This is used to tell the wrapper job + // action that the wrapping (and subsequent compile step) should be done + // with for-each instead of using -batch. + void setWrapIndividualFiles() { WrapIndividualFiles = true; } + + // Get the individual wrapping setting. + bool getWrapIndividualFiles() const { return WrapIndividualFiles; } + // Set the offload kind for the current wrapping job action. Default usage // is to use the kind of the current toolchain. void setOffloadKind(OffloadKind SetKind) { Kind = SetKind; } @@ -707,6 +715,7 @@ class OffloadWrapperJobAction : public JobAction { private: bool CompileStep = true; + bool WrapIndividualFiles = false; OffloadKind Kind = OFK_None; }; diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index c751dff27a1e3..84c99041f7405 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -5536,9 +5536,58 @@ class OffloadingActionBuilder final { BundlingActions, types::TY_Object); if (auto *OWA = dyn_cast(DeviceAction)) OWA->setOffloadKind(Action::OFK_Host); + // The Backend compilation step performed here is being done for + // creating FPGA archives. The possible split binaries after + // sycl-post-link need to be individually wrapped as opposed to + // being passed into the clang-offload-wrapper via a table and + // using the -batch option - effectively creating a single + // binary. The resulting archive created from -fsycl-link should + // not contain the singular binary, but should be individual + // binaries to be consumed later by either the -fsycl-link=image + // device compilation step or being linked into the final exe. + // + // Typical compile flow: + // .bc + // | + // sycl-post-link -split=kernel + // | + // +--------+--------+ + // | | | + // split1 split2 split3 + // | | | + // llvm-spirv llvm-spirv llvm-spirv + // | | | + // ocloc ocloc ocloc + // | | | + // +--------+--------+ + // | + // clang-offload-wrapper -batch + // | + // .o + // + // Individual wrap compile flow: + // .bc + // | + // sycl-post-link -split=kernel + // | + // +--------+--------+ + // | | | + // split1 split2 split3 + // | | | + // llvm-spirv llvm-spirv llvm-spirv + // | | | + // ocloc ocloc ocloc + // | | | + // wrap wrap wrap + // | | | + // .o .o .o + // Action *CompiledDeviceAction = - C.MakeAction(WrapperItems, - types::TY_Object); + C.MakeAction(FPGAAOTAction, + types::TY_Tempfilelist); + if (auto *OWA = + dyn_cast(CompiledDeviceAction)) + OWA->setWrapIndividualFiles(); addDeps(CompiledDeviceAction, TC, BoundArch); } addDeps(DeviceAction, TC, BoundArch); @@ -5812,6 +5861,9 @@ class OffloadingActionBuilder final { }; Action *ExtractIRFilesAction = createExtractIRFilesAction(); + // Device binaries that are individually wrapped when creating an + // FPGA Archive. + ActionList FPGAArchiveWrapperInputs; if (IsNVPTX || IsAMDGCN) { JobAction *FinAction = @@ -5897,6 +5949,7 @@ class OffloadingActionBuilder final { FileTableTformJobAction::COL_CODE, FileTableTformJobAction::COL_CODE); WrapperInputs.push_back(ReplaceFilesAction); + FPGAArchiveWrapperInputs.push_back(BuildCodeAction); } if (SkipWrapper) { // Wrapper step not requested. @@ -5931,8 +5984,11 @@ class OffloadingActionBuilder final { if (auto *OWA = dyn_cast(DeviceAction)) OWA->setOffloadKind(Action::OFK_Host); Action *CompiledDeviceAction = - C.MakeAction(WrapperInputs, - types::TY_Object); + C.MakeAction( + FPGAArchiveWrapperInputs, types::TY_Tempfilelist); + if (auto *OWA = + dyn_cast(CompiledDeviceAction)) + OWA->setWrapIndividualFiles(); addDeps(CompiledDeviceAction, TC, nullptr); } addDeps(DeviceAction, TC, nullptr); diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 8b2d29c251437..8033cc490adec 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -10263,8 +10263,18 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA, const InputInfo &I = Inputs[0]; assert(I.isFilename() && "Invalid input."); - if (I.getType() == types::TY_Tempfiletable || - I.getType() == types::TY_Tempfilelist || IsEmbeddedIR) + // TODO: The embedded compilation step after the wrapping step restricts + // the ability to control the 'for each' methodology used when performing + // device code splitting. We set the individual wrap behavior when we know + // the wrapping and compile step should be done individually. Ideally this + // would be controlled at the JobAction creation, but we cannot do that + // until the compilation of the wrap is it's own JobAction. + bool IndividualWrapCompile = WrapperJob.getWrapIndividualFiles(); + const InputInfo TempOutput(types::TY_LLVM_BC, WrapperFileName, + WrapperFileName); + if (!IndividualWrapCompile && + (I.getType() == types::TY_Tempfiletable || + I.getType() == types::TY_Tempfilelist || IsEmbeddedIR)) // Input files are passed via the batch job file table. WrapperArgs.push_back(C.getArgs().MakeArgString("-batch")); WrapperArgs.push_back(C.getArgs().MakeArgString(I.getFilename())); @@ -10273,7 +10283,17 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA, JA, *this, ResponseFileSupport::None(), TCArgs.MakeArgString(getToolChain().GetProgramPath(getShortName())), WrapperArgs, std::nullopt); - C.addCommand(std::move(Cmd)); + + if (IndividualWrapCompile) { + // When wrapping FPGA device binaries for FPGA archives, create individual + // wrapped and compiled entries for the archive. + StringRef ParallelJobs = + C.getArgs().getLastArgValue(options::OPT_fsycl_max_parallel_jobs_EQ); + clang::driver::tools::SYCL::constructLLVMForeachCommand( + C, JA, std::move(Cmd), Inputs, TempOutput, this, "", "bc", + ParallelJobs); + } else + C.addCommand(std::move(Cmd)); if (WrapperCompileEnabled) { // TODO Use TC.SelectTool(). @@ -10296,9 +10316,19 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA, SmallString<128> ClangPath(C.getDriver().Dir); llvm::sys::path::append(ClangPath, "clang"); const char *Clang = C.getArgs().MakeArgString(ClangPath); - C.addCommand(std::make_unique(JA, *this, - ResponseFileSupport::None(), Clang, - ClangArgs, std::nullopt)); + auto PostWrapCompileCmd = + std::make_unique(JA, *this, ResponseFileSupport::None(), + Clang, ClangArgs, std::nullopt); + if (IndividualWrapCompile) { + StringRef ParallelJobs = C.getArgs().getLastArgValue( + options::OPT_fsycl_max_parallel_jobs_EQ); + InputInfoList Inputs; + Inputs.push_back(TempOutput); + clang::driver::tools::SYCL::constructLLVMForeachCommand( + C, JA, std::move(PostWrapCompileCmd), Inputs, Output, this, "", + "bc", ParallelJobs); + } else + C.addCommand(std::move(PostWrapCompileCmd)); } return; } // end of SYCL flavor of offload wrapper command creation diff --git a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp index cc42365cae65c..7556249df7c83 100644 --- a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp @@ -21,14 +21,17 @@ // CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-EARLY: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g" // CHK-FPGA-IMAGE: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" +// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "[[OUTPUT4]]" +// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]" // CHK-FPGA-LINK: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" -// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" -// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.o]]" "[[WRAPOUT]]" +// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]" +// CHK-FPGA-EARLY: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]" +// CHK-FPGA-EARLY: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]" // CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]" // CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]" // CHK-FPGA-IMAGE: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]" -// CHK-FPGA-EARLY: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "[[OBJOUTDEV]]" -// CHK-FPGA-IMAGE: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]"{{.*}} "[[WRAPWRAPOUT]]" +// CHK-FPGA-IMAGE: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]" /// -fintelfpga -fsycl-link clang-cl specific // RUN: touch %t.obj @@ -45,10 +48,13 @@ // CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" // CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-LINK-WIN: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "[[OUTPUT4]]" +// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]" // CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" -// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" -// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.obj]]" "[[WRAPOUT]]" -// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "[[OBJOUTDEV]]" {{.*}} "-OUT:libfoo.lib" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT2:.+\.obj]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAPOUT:.+\.bc]]" {{.*}} "-kind=host" "[[WRAPOUT2]]" +// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OUTDEV:.+\.obj]]" "[[WRAPWRAPOUT]]" +// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[OUTDEV]]" {{.*}} "-OUT:libfoo.lib" /// Check -fintelfpga -fsycl-link with an FPGA archive // Create the dummy archive @@ -71,26 +77,23 @@ // CHK-FPGA-LINK-LIB: clang{{.*}} "-o" "[[OUTPUT_O:.+\.o]]" "-x" "ir" "[[WRAPPED_AOCR_LIST_BC]]" // CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT2:.+\.aocr]]" "-unbundle" // CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g" +// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=sycl" "[[OUTPUT3]]" +// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPOUT]]" // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-IMAGE: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle" // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]" +// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" +// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]" // CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]" // CHK-FPGA-LINK-LIB-EARLY: llvm-foreach{{.*}} "--out-ext=aocr" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocr]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}}" "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g" // CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-EARLY: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle" // CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]" +// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" +// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]" // CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]" // CHK-FPGA-LINK-LIB: llvm-ar{{.*}} "cqL" {{.*}} "[[OUTPUT_O]]" - /// Check the warning's emission for conflicting emulation/hardware // RUN: touch %t-aocr.a // RUN: %clangxx -fintelfpga -fsycl-link=image -target x86_64-unknown-linux-gnu %t-aocr.a %s -Xshardware -### 2>&1 \ @@ -240,13 +243,13 @@ // CHK-FPGA-LINK-SRC: 15: file-table-tform, {14}, tempfilelist, (device-sycl) // CHK-FPGA-LINK-SRC: 16: llvm-spirv, {15}, tempfilelist, (device-sycl) // CHK-FPGA-LINK-SRC: 17: backend-compiler, {16}, fpga_aocr_emu, (device-sycl) -// CHK-FPGA-LINK-SRC: 18: file-table-tform, {14, 17}, tempfiletable, (device-sycl) -// CHK-FPGA-LINK-SRC: 19: clang-offload-wrapper, {18}, object, (device-sycl) -// CHK-FPGA-LINK-SRC: 20: offload, "device-sycl (spir64_fpga-unknown-unknown)" {19}, object -// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {18}, object, (device-sycl) +// CHK-FPGA-LINK-SRC: 18: clang-offload-wrapper, {17}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 19: offload, "device-sycl (spir64_fpga-unknown-unknown)" {18}, tempfilelist +// CHK-FPGA-LINK-SRC: 20: file-table-tform, {14, 17}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {20}, object, (device-sycl) // CHK-FPGA-LINK-SRC: 22: clang-offload-wrapper, {21}, object, (device-sycl) // CHK-FPGA-LINK-SRC: 23: offload, "device-sycl (spir64_fpga-unknown-unknown)" {22}, object -// CHK-FPGA-LINK-SRC: 24: linker, {12, 20, 23}, archive, (host-sycl) +// CHK-FPGA-LINK-SRC: 24: linker, {12, 19, 23}, archive, (host-sycl) /// Check for implied options with emulation (-g -O0) // RUN: %clang -### -target x86_64-unknown-linux-gnu -fintelfpga -g -O0 -Xs "-DFOO1 -DFOO2" %s 2>&1 \ diff --git a/clang/test/Driver/sycl-offload-intelfpga-link.cpp b/clang/test/Driver/sycl-offload-intelfpga-link.cpp index a92b47290893a..719b972581d30 100644 --- a/clang/test/Driver/sycl-offload-intelfpga-link.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga-link.cpp @@ -17,10 +17,18 @@ // CHK-FPGA-LINK: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" // CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-EARLY: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" -// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocx]]" "[[OUTPUT3]]" "-sycl" -// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" -// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.o]]" "[[WRAPOUT]]" -// CHK-FPGA-LINK: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "[[OBJOUTDEV]]" +// CHK-FPGA-IMAGE: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocx]]" "[[OUTPUT3]]" "-sycl" +// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "[[OUTPUT4]]" +// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]" +// CHK-FPGA-LINK: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]" +// CHK-FPGA-EARLY: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]" +// CHK-FPGA-EARLY: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]" +// CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]" +// CHK-FPGA-IMAGE: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]" +// CHK-FPGA-IMAGE: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]" // Output designation should not be used for unbundling step // RUN: touch %t.o @@ -48,10 +56,14 @@ // CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-O2" "-device-globals" "-properties" "-spec-const=emulation"{{.*}} "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" // CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" // CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" -// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT5:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" -// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" -// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.obj]]" "[[WRAPOUT]]" -// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "[[OBJOUTDEV]]" {{.*}} "-OUT:libfoo.lib" +// CHK-FPGA-LINK-WIN: aoc{{.*}} "-o" "[[OUTPUT4:.+\.aocr]]" "[[OUTPUT3]]" "-sycl" "-rtl" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "[[OUTPUT4]]" +// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]" +// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT2:.+\.obj]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]" +// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAPOUT:.+\.bc]]" {{.*}} "-kind=host" "[[WRAPOUT2]]" +// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OUTDEV:.+\.obj]]" "[[WRAPWRAPOUT]]" +// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[OUTDEV]]" {{.*}} "-OUT:libfoo.lib" /// Check -fintelfpga -fsycl-link with an FPGA archive // Create the dummy archive @@ -77,19 +89,15 @@ // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-IMAGE: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle" // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]" +// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" +// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]" // CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]" // CHK-FPGA-LINK-LIB-EARLY: llvm-foreach{{.*}} "--out-ext=aocr" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocr]]" "--out-replace=[[OUTPUT3]]" "--out-increment=a.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-rtl" "-output-report-folder=a.prj" "-g" // CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-EARLY: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle" // CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" -// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]" +// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]" +// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]" // CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]" // CHK-FPGA-LINK-LIB: llvm-ar{{.*}} "cqL" {{.*}} "[[OUTPUT_O]]" @@ -149,13 +157,13 @@ // CHK-FPGA-LINK-SRC: 15: file-table-tform, {14}, tempfilelist, (device-sycl) // CHK-FPGA-LINK-SRC: 16: llvm-spirv, {15}, tempfilelist, (device-sycl) // CHK-FPGA-LINK-SRC: 17: backend-compiler, {16}, fpga_aocr_emu, (device-sycl) -// CHK-FPGA-LINK-SRC: 18: file-table-tform, {14, 17}, tempfiletable, (device-sycl) -// CHK-FPGA-LINK-SRC: 19: clang-offload-wrapper, {18}, object, (device-sycl) -// CHK-FPGA-LINK-SRC: 20: offload, "device-sycl (spir64_fpga-unknown-unknown)" {19}, object -// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {18}, object, (device-sycl) +// CHK-FPGA-LINK-SRC: 18: clang-offload-wrapper, {17}, tempfilelist, (device-sycl) +// CHK-FPGA-LINK-SRC: 19: offload, "device-sycl (spir64_fpga-unknown-unknown)" {18}, tempfilelist +// CHK-FPGA-LINK-SRC: 20: file-table-tform, {14, 17}, tempfiletable, (device-sycl) +// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {20}, object, (device-sycl) // CHK-FPGA-LINK-SRC: 22: clang-offload-wrapper, {21}, object, (device-sycl) // CHK-FPGA-LINK-SRC: 23: offload, "device-sycl (spir64_fpga-unknown-unknown)" {22}, object -// CHK-FPGA-LINK-SRC: 24: linker, {12, 20, 23}, archive, (host-sycl) +// CHK-FPGA-LINK-SRC: 24: linker, {12, 19, 23}, archive, (host-sycl) /// -fintelfpga with AOCR library and additional object // RUN: touch %t2.o diff --git a/llvm/cmake/config-ix.cmake b/llvm/cmake/config-ix.cmake index 86f2bac7d23e8..03a532772cbfe 100644 --- a/llvm/cmake/config-ix.cmake +++ b/llvm/cmake/config-ix.cmake @@ -157,7 +157,14 @@ if(LLVM_ENABLE_ZSTD) find_package(zstd QUIET) endif() endif() + +# If LLVM_USE_STATIC_ZSTD is specified, make sure we enable zstd only if static +# libraries are found. +if(LLVM_USE_STATIC_ZSTD AND NOT TARGET zstd::libzstd_static) +set(LLVM_ENABLE_ZSTD OFF) +else() set(LLVM_ENABLE_ZSTD ${zstd_FOUND}) +endif() if(LLVM_ENABLE_LIBXML2) if(LLVM_ENABLE_LIBXML2 STREQUAL FORCE_ON) diff --git a/sycl/test-e2e/AOT/fpga-aoc-archive-split-per-kernel.cpp b/sycl/test-e2e/AOT/fpga-aoc-archive-split-per-kernel.cpp index eb43335df16e0..0e0c53d217c05 100644 --- a/sycl/test-e2e/AOT/fpga-aoc-archive-split-per-kernel.cpp +++ b/sycl/test-e2e/AOT/fpga-aoc-archive-split-per-kernel.cpp @@ -3,8 +3,6 @@ // REQUIRES: opencl-aot, accelerator -// XFAIL: * - // Remove any archives // RUN: rm -f %t_*.a diff --git a/sycl/test/e2e_test_requirements/no-xfail-without-tracker.cpp b/sycl/test/e2e_test_requirements/no-xfail-without-tracker.cpp index f36b3793b6d9f..3abbe2c6089fd 100644 --- a/sycl/test/e2e_test_requirements/no-xfail-without-tracker.cpp +++ b/sycl/test/e2e_test_requirements/no-xfail-without-tracker.cpp @@ -50,13 +50,12 @@ // tests to match the required format and in that case you should just update // (i.e. reduce) the number and the list below. // -// NUMBER-OF-XFAIL-WITHOUT-TRACKER: 157 +// NUMBER-OF-XFAIL-WITHOUT-TRACKER: 156 // // List of improperly XFAIL-ed tests. // Remove the CHECK once the test has been propely XFAIL-ed. // -// CHECK: AOT/fpga-aoc-archive-split-per-kernel.cpp -// CHECK-NEXT: AddressSanitizer/nullpointer/private_nullptr.cpp +// CHECK: AddressSanitizer/nullpointer/private_nullptr.cpp // CHECK-NEXT: Basic/accessor/accessor.cpp // CHECK-NEXT: Basic/aspects.cpp // CHECK-NEXT: Basic/buffer/reinterpret.cpp