From 49bffa5f8b790b6f180897b2a03840def645d8f0 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Thu, 13 Feb 2020 23:34:13 +0300 Subject: [PATCH 01/57] [clang-tidy] misc-no-recursion: a new check Summary: Recursion is a powerful tool, but like any tool without care it can be dangerous. For example, if the recursion is unbounded, you will eventually run out of stack and crash. You can of course track the recursion depth but if it is hardcoded, there can always be some other environment when that depth is too large, so said magic number would need to be env-dependent. But then your program's behavior is suddenly more env-dependent. Also, recursion, while it does not outright stop optimization, recursive calls are less great than normal calls, for example they hinder inlining. Recursion is banned in some coding guidelines: * SEI CERT DCL56-CPP. Avoid cycles during initialization of static objects * JPL 2.4 Do not use direct or indirect recursion. * I'd say it is frowned upon in LLVM, although not banned And is plain unsupported in some cases: * OpenCL 1.2, 6.9 Restrictions: i. Recursion is not supported. So there's clearly a lot of reasons why one might want to avoid recursion, and replace it with worklist handling. It would be great to have a enforcement for it though. This implements such a check. Here we detect both direct and indirect recursive calls, although since clang-tidy (unlike clang static analyzer) is CTU-unaware, if the recursion transcends a single standalone TU, we will naturally not find it :/ The algorithm is pretty straight-forward: 1. Build call-graph for the entire TU. For that, the existing `clang::CallGraph` is re-used, although it had to be modified to also track the location of the call. 2. Then, the hard problem: how do we detect recursion? Since we have a graph, let's just do the sane thing, and look for Strongly Connected Function Declarations - widely known as `SCC`. For that LLVM provides `llvm::scc_iterator`, which is internally an Tarjan's DFS algorithm, and is used throught LLVM, so this should be as performant as possible. 3. Now that we've got SCC's, we discard those that don't contain loops. Note that there may be more than one loop in SCC! 4. For each loopy SCC, we call out each function, and print a single example call graph that shows recursion -- it didn't seem worthwhile enumerating every possible loop in SCC, although i suppose it could be implemented. * To come up with that call graph cycle example, we start at first SCC node, see which callee of the node is within SCC (and is thus known to be in cycle), and recurse into it until we hit the callee that is already in call stack. Reviewers: JonasToth, aaron.ballman, ffrankies, Eugene.Zelenko, erichkeane, NoQ Reviewed By: aaron.ballman Subscribers: Charusso, Naghasan, bader, riccibruno, mgorny, Anastasia, xazax.hun, cfe-commits Tags: #llvm, #clang Differential Revision: https://reviews.llvm.org/D72362 --- .../clang-tidy/misc/CMakeLists.txt | 1 + .../clang-tidy/misc/MiscTidyModule.cpp | 2 + .../clang-tidy/misc/NoRecursionCheck.cpp | 276 ++++++++++++++++++ .../clang-tidy/misc/NoRecursionCheck.h | 42 +++ clang-tools-extra/docs/ReleaseNotes.rst | 5 + .../docs/clang-tidy/checks/list.rst | 1 + .../clang-tidy/checks/misc-no-recursion.rst | 18 ++ .../clang-tidy/checkers/misc-no-recursion.cpp | 179 ++++++++++++ 8 files changed, 524 insertions(+) create mode 100644 clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp create mode 100644 clang-tools-extra/clang-tidy/misc/NoRecursionCheck.h create mode 100644 clang-tools-extra/docs/clang-tidy/checks/misc-no-recursion.rst create mode 100644 clang-tools-extra/test/clang-tidy/checkers/misc-no-recursion.cpp diff --git a/clang-tools-extra/clang-tidy/misc/CMakeLists.txt b/clang-tools-extra/clang-tidy/misc/CMakeLists.txt index 3fc152148d6d6..7aa14d141fb1a 100644 --- a/clang-tools-extra/clang-tidy/misc/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/misc/CMakeLists.txt @@ -5,6 +5,7 @@ add_clang_library(clangTidyMiscModule MiscTidyModule.cpp MisplacedConstCheck.cpp NewDeleteOverloadsCheck.cpp + NoRecursionCheck.cpp NonCopyableObjects.cpp NonPrivateMemberVariablesInClassesCheck.cpp RedundantExpressionCheck.cpp diff --git a/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp b/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp index ba160d1dba38f..e06768c548bda 100644 --- a/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp @@ -12,6 +12,7 @@ #include "DefinitionsInHeadersCheck.h" #include "MisplacedConstCheck.h" #include "NewDeleteOverloadsCheck.h" +#include "NoRecursionCheck.h" #include "NonCopyableObjects.h" #include "NonPrivateMemberVariablesInClassesCheck.h" #include "RedundantExpressionCheck.h" @@ -35,6 +36,7 @@ class MiscModule : public ClangTidyModule { CheckFactories.registerCheck("misc-misplaced-const"); CheckFactories.registerCheck( "misc-new-delete-overloads"); + CheckFactories.registerCheck("misc-no-recursion"); CheckFactories.registerCheck( "misc-non-copyable-objects"); CheckFactories.registerCheck( diff --git a/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp b/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp new file mode 100644 index 0000000000000..cfbd6543e0866 --- /dev/null +++ b/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.cpp @@ -0,0 +1,276 @@ +//===--- NoRecursionCheck.cpp - clang-tidy --------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "NoRecursionCheck.h" +#include "clang/AST/ASTContext.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Analysis/CallGraph.h" +#include "llvm/ADT/DenseMapInfo.h" +#include "llvm/ADT/SCCIterator.h" + +using namespace clang::ast_matchers; + +namespace clang { +namespace tidy { +namespace misc { + +namespace { + +/// Much like SmallSet, with two differences: +/// 1. It can *only* be constructed from an ArrayRef<>. If the element count +/// is small, there is no copy and said storage *must* outlive us. +/// 2. it is immutable, the way it was constructed it will stay. +template class ImmutableSmallSet { + ArrayRef Vector; + llvm::DenseSet Set; + + static_assert(SmallSize <= 32, "N should be small"); + + bool isSmall() const { return Set.empty(); } + +public: + using size_type = size_t; + + ImmutableSmallSet() = delete; + ImmutableSmallSet(const ImmutableSmallSet &) = delete; + ImmutableSmallSet(ImmutableSmallSet &&) = delete; + T &operator=(const ImmutableSmallSet &) = delete; + T &operator=(ImmutableSmallSet &&) = delete; + + // WARNING: Storage *must* outlive us if we decide that the size is small. + ImmutableSmallSet(ArrayRef Storage) { + // Is size small-enough to just keep using the existing storage? + if (Storage.size() <= SmallSize) { + Vector = Storage; + return; + } + + // We've decided that it isn't performant to keep using vector. + // Let's migrate the data into Set. + Set.reserve(Storage.size()); + Set.insert(Storage.begin(), Storage.end()); + } + + /// count - Return 1 if the element is in the set, 0 otherwise. + size_type count(const T &V) const { + if (isSmall()) { + // Since the collection is small, just do a linear search. + return llvm::find(Vector, V) == Vector.end() ? 0 : 1; + } + + return Set.count(V); + } +}; + +/// Much like SmallSetVector, but with one difference: +/// when the size is \p SmallSize or less, when checking whether an element is +/// already in the set or not, we perform linear search over the vector, +/// but if the size is larger than \p SmallSize, we look in set. +/// FIXME: upstream this into SetVector/SmallSetVector itself. +template class SmartSmallSetVector { +public: + using size_type = size_t; + +private: + SmallVector Vector; + llvm::DenseSet Set; + + static_assert(SmallSize <= 32, "N should be small"); + + // Are we still using Vector for uniqness tracking? + bool isSmall() const { return Set.empty(); } + + // Will one more entry cause Vector to switch away from small-size storage? + bool entiretyOfVectorSmallSizeIsOccupied() const { + assert(isSmall() && Vector.size() <= SmallSize && + "Shouldn't ask if we have already [should have] migrated into Set."); + return Vector.size() == SmallSize; + } + + void populateSet() { + assert(Set.empty() && "Should not have already utilized the Set."); + // Magical growth factor prediction - to how many elements do we expect to + // sanely grow after switching away from small-size storage? + const size_t NewMaxElts = 4 * Vector.size(); + Vector.reserve(NewMaxElts); + Set.reserve(NewMaxElts); + Set.insert(Vector.begin(), Vector.end()); + } + + /// count - Return 1 if the element is in the set, 0 otherwise. + size_type count(const T &V) const { + if (isSmall()) { + // Since the collection is small, just do a linear search. + return llvm::find(Vector, V) == Vector.end() ? 0 : 1; + } + // Look-up in the Set. + return Set.count(V); + } + + bool setInsert(const T &V) { + if (count(V) != 0) + return false; // Already exists. + // Does not exist, Can/need to record it. + if (isSmall()) { // Are we still using Vector for uniqness tracking? + // Will one more entry fit within small-sized Vector? + if (!entiretyOfVectorSmallSizeIsOccupied()) + return true; // We'll insert into vector right afterwards anyway. + // Time to switch to Set. + populateSet(); + } + // Set time! + // Note that this must be after `populateSet()` might have been called. + bool SetInsertionSucceeded = Set.insert(V).second; + (void)SetInsertionSucceeded; + assert(SetInsertionSucceeded && "We did check that no such value existed"); + return true; + } + +public: + /// Insert a new element into the SmartSmallSetVector. + /// \returns true if the element was inserted into the SmartSmallSetVector. + bool insert(const T &X) { + bool result = setInsert(X); + if (result) + Vector.push_back(X); + return result; + } + + /// Clear the SmartSmallSetVector and return the underlying vector. + decltype(Vector) takeVector() { + Set.clear(); + return std::move(Vector); + } +}; + +constexpr unsigned SmallCallStackSize = 16; +constexpr unsigned SmallSCCSize = 32; + +using CallStackTy = + llvm::SmallVector; + +// In given SCC, find *some* call stack that will be cyclic. +// This will only find *one* such stack, it might not be the smallest one, +// and there may be other loops. +CallStackTy PathfindSomeCycle(ArrayRef SCC) { + // We'll need to be able to performantly look up whether some CallGraphNode + // is in SCC or not, so cache all the SCC elements in a set. + const ImmutableSmallSet SCCElts(SCC); + + // Is node N part if the current SCC? + auto NodeIsPartOfSCC = [&SCCElts](CallGraphNode *N) { + return SCCElts.count(N) != 0; + }; + + // Track the call stack that will cause a cycle. + SmartSmallSetVector + CallStackSet; + + // Arbitrairly take the first element of SCC as entry point. + CallGraphNode::CallRecord EntryNode(SCC.front(), /*CallExpr=*/nullptr); + // Continue recursing into subsequent callees that are part of this SCC, + // and are thus known to be part of the call graph loop, until loop forms. + CallGraphNode::CallRecord *Node = &EntryNode; + while (true) { + // Did we see this node before? + if (!CallStackSet.insert(*Node)) + break; // Cycle completed! Note that didn't insert the node into stack! + // Else, perform depth-first traversal: out of all callees, pick first one + // that is part of this SCC. This is not guaranteed to yield shortest cycle. + Node = llvm::find_if(Node->Callee->callees(), NodeIsPartOfSCC); + } + + // Note that we failed to insert the last node, that completes the cycle. + // But we really want to have it. So insert it manually into stack only. + CallStackTy CallStack = CallStackSet.takeVector(); + CallStack.emplace_back(*Node); + + return CallStack; +} + +} // namespace + +void NoRecursionCheck::registerMatchers(MatchFinder *Finder) { + Finder->addMatcher(translationUnitDecl().bind("TUDecl"), this); +} + +void NoRecursionCheck::handleSCC(ArrayRef SCC) { + assert(!SCC.empty() && "Empty SCC does not make sense."); + + // First of all, call out every stongly connected function. + for (CallGraphNode *N : SCC) { + Decl *D = N->getDecl(); + diag(D->getLocation(), "function %0 is within a recursive call chain") + << cast(D); + } + + // Now, SCC only tells us about strongly connected function declarations in + // the call graph. It doesn't *really* tell us about the cycles they form. + // And there may be more than one cycle in SCC. + // So let's form a call stack that eventually exposes *some* cycle. + const CallStackTy EventuallyCyclicCallStack = PathfindSomeCycle(SCC); + assert(!EventuallyCyclicCallStack.empty() && "We should've found the cycle"); + + // While last node of the call stack does cause a loop, due to the way we + // pathfind the cycle, the loop does not nessesairly begin at the first node + // of the call stack, so drop front nodes of the call stack until it does. + const auto CyclicCallStack = + ArrayRef(EventuallyCyclicCallStack) + .drop_until([LastNode = EventuallyCyclicCallStack.back()]( + CallGraphNode::CallRecord FrontNode) { + return FrontNode == LastNode; + }); + assert(CyclicCallStack.size() >= 2 && "Cycle requires at least 2 frames"); + + // Which function we decided to be the entry point that lead to the recursion? + Decl *CycleEntryFn = CyclicCallStack.front().Callee->getDecl(); + // And now, for ease of understanding, let's print the call sequence that + // forms the cycle in question. + diag(CycleEntryFn->getLocation(), + "example recursive call chain, starting from function %0", + DiagnosticIDs::Note) + << cast(CycleEntryFn); + for (int CurFrame = 1, NumFrames = CyclicCallStack.size(); + CurFrame != NumFrames; ++CurFrame) { + CallGraphNode::CallRecord PrevNode = CyclicCallStack[CurFrame - 1]; + CallGraphNode::CallRecord CurrNode = CyclicCallStack[CurFrame]; + + Decl *PrevDecl = PrevNode.Callee->getDecl(); + Decl *CurrDecl = CurrNode.Callee->getDecl(); + + diag(CurrNode.CallExpr->getBeginLoc(), + "Frame #%0: function %1 calls function %2 here:", DiagnosticIDs::Note) + << CurFrame << cast(PrevDecl) << cast(CurrDecl); + } + + diag(CyclicCallStack.back().CallExpr->getBeginLoc(), + "... which was the starting point of the recursive call chain; there " + "may be other cycles", + DiagnosticIDs::Note); +} + +void NoRecursionCheck::check(const MatchFinder::MatchResult &Result) { + // Build call graph for the entire translation unit. + const auto *TU = Result.Nodes.getNodeAs("TUDecl"); + CallGraph CG; + CG.addToCallGraph(const_cast(TU)); + + // Look for cycles in call graph, + // by looking for Strongly Connected Comonents (SCC's) + for (llvm::scc_iterator SCCI = llvm::scc_begin(&CG), + SCCE = llvm::scc_end(&CG); + SCCI != SCCE; ++SCCI) { + if (!SCCI.hasLoop()) // We only care about cycles, not standalone nodes. + continue; + handleSCC(*SCCI); + } +} + +} // namespace misc +} // namespace tidy +} // namespace clang diff --git a/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.h b/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.h new file mode 100644 index 0000000000000..c3a0d3e002c6c --- /dev/null +++ b/clang-tools-extra/clang-tidy/misc/NoRecursionCheck.h @@ -0,0 +1,42 @@ +//===--- NoRecursionCheck.h - clang-tidy ------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_NORECURSIONCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_NORECURSIONCHECK_H + +#include "../ClangTidyCheck.h" + +namespace clang { + +class CallGraphNode; + +namespace tidy { +namespace misc { + +/// Finds strongly connected functions (by analyzing call graph for SCC's +/// that are loops), diagnoses each function in the cycle, +/// and displays one example of possible call graph loop (recursion). +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/misc-no-recursion.html +class NoRecursionCheck : public ClangTidyCheck { +public: + NoRecursionCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context) {} + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + +private: + void handleSCC(ArrayRef SCC); +}; + +} // namespace misc +} // namespace tidy +} // namespace clang + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_NORECURSIONCHECK_H diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 7dfcd1a3c745f..dd30f66778a37 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -93,6 +93,11 @@ New checks Finds implementations of -dealloc in Objective-C categories. +- New :doc:`misc-no-recursion + ` check. + + Finds recursive functions and diagnoses them. + New check aliases ^^^^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index fb51e6f7a722d..ce4b20f8693f0 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -189,6 +189,7 @@ Clang-Tidy Checks `misc-definitions-in-headers `_, "Yes" `misc-misplaced-const `_, `misc-new-delete-overloads `_, + `misc-no-recursion `_, `misc-non-copyable-objects `_, `misc-non-private-member-variables-in-classes `_, `misc-redundant-expression `_, "Yes" diff --git a/clang-tools-extra/docs/clang-tidy/checks/misc-no-recursion.rst b/clang-tools-extra/docs/clang-tidy/checks/misc-no-recursion.rst new file mode 100644 index 0000000000000..dad6f74ef7f4d --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/misc-no-recursion.rst @@ -0,0 +1,18 @@ +.. title:: clang-tidy - misc-no-recursion + +misc-no-recursion +================= + +Finds strongly connected functions (by analyzing the call graph for +SCC's (Strongly Connected Components) that are loops), +diagnoses each function in the cycle, +and displays one example of a possible call graph loop (recursion). + +References: +* CERT C++ Coding Standard rule `DCL56-CPP. Avoid cycles during initialization of static objects `_. +* JPL Institutional Coding Standard for the C Programming Language (JPL DOCID D-60411) rule `2.4 Do not use direct or indirect recursion`. +* OpenCL Specification, Version 1.2 rule `6.9 Restrictions: i. Recursion is not supported. `_. + +Limitations: +* The check does not handle calls done through function pointers +* The check does not handle C++ destructors diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc-no-recursion.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc-no-recursion.cpp new file mode 100644 index 0000000000000..0cfacfe80cbe0 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc-no-recursion.cpp @@ -0,0 +1,179 @@ +// RUN: %check_clang_tidy %s misc-no-recursion %t + +// We don't have the definition of this function, +// so we can't tell anything about it.. +void external(); + +// This function is obviously not recursive. +void no_recursion() { +} + +// Since we don't know what `external()` does, +// we don't know if this is recursive or not. +void maybe_no_recursion() { + external(); +} + +// Function calls itself - obviously a recursion. +void endless_recursion() { + endless_recursion(); +} + +// CHECK-NOTES: :[[@LINE-4]]:6: warning: function 'endless_recursion' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-5]]:6: note: example recursive call chain, starting from function 'endless_recursion' +// CHECK-NOTES: :[[@LINE-5]]:3: note: Frame #1: function 'endless_recursion' calls function 'endless_recursion' here: +// CHECK-NOTES: :[[@LINE-6]]:3: note: ... which was the starting point of the recursive call chain; there may be other cycles + +bool external_oracle(); +bool another_external_oracle(); + +// Function calls itself if some external function said so - recursion. +void maybe_endless_recursion() { + if (external_oracle()) + maybe_endless_recursion(); +} + +// CHECK-NOTES: :[[@LINE-5]]:6: warning: function 'maybe_endless_recursion' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-6]]:6: note: example recursive call chain, starting from function 'maybe_endless_recursion' +// CHECK-NOTES: :[[@LINE-5]]:5: note: Frame #1: function 'maybe_endless_recursion' calls function 'maybe_endless_recursion' here: +// CHECK-NOTES: :[[@LINE-6]]:5: note: ... which was the starting point of the recursive call chain; there may be other cycles + +// Obviously-constrained recursion. +void recursive_countdown(unsigned x) { + if (x == 0) + return; + recursive_countdown(x - 1); +} + +// CHECK-NOTES: :[[@LINE-6]]:6: warning: function 'recursive_countdown' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-7]]:6: note: example recursive call chain, starting from function 'recursive_countdown' +// CHECK-NOTES: :[[@LINE-5]]:3: note: Frame #1: function 'recursive_countdown' calls function 'recursive_countdown' here: +// CHECK-NOTES: :[[@LINE-6]]:3: note: ... which was the starting point of the recursive call chain; there may be other cycles + +void indirect_recursion(); +void conditionally_executed() { + if (external_oracle()) + indirect_recursion(); +} +void indirect_recursion() { + if (external_oracle()) + conditionally_executed(); +} + +// CHECK-NOTES: :[[@LINE-10]]:6: warning: function 'indirect_recursion' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-10]]:6: warning: function 'conditionally_executed' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-12]]:6: note: example recursive call chain, starting from function 'indirect_recursion' +// CHECK-NOTES: :[[@LINE-6]]:5: note: Frame #1: function 'indirect_recursion' calls function 'conditionally_executed' here: +// CHECK-NOTES: :[[@LINE-11]]:5: note: Frame #2: function 'conditionally_executed' calls function 'indirect_recursion' here: +// CHECK-NOTES: :[[@LINE-12]]:5: note: ... which was the starting point of the recursive call chain; there may be other cycles + +void taint(); +void maybe_selfrecursion_with_two_backedges() { + if (external_oracle()) + maybe_selfrecursion_with_two_backedges(); + taint(); + if (another_external_oracle()) + maybe_selfrecursion_with_two_backedges(); +} + +// CHECK-NOTES: :[[@LINE-8]]:6: warning: function 'maybe_selfrecursion_with_two_backedges' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-9]]:6: note: example recursive call chain, starting from function 'maybe_selfrecursion_with_two_backedges' +// CHECK-NOTES: :[[@LINE-8]]:5: note: Frame #1: function 'maybe_selfrecursion_with_two_backedges' calls function 'maybe_selfrecursion_with_two_backedges' here: +// CHECK-NOTES: :[[@LINE-9]]:5: note: ... which was the starting point of the recursive call chain; there may be other cycles + +void indirect_recursion_with_alternatives(); +void conditionally_executed_choice_0() { + if (external_oracle()) + indirect_recursion_with_alternatives(); +} +void conditionally_executed_choice_1() { + if (external_oracle()) + indirect_recursion_with_alternatives(); +} +void indirect_recursion_with_alternatives() { + if (external_oracle()) + conditionally_executed_choice_0(); + else + conditionally_executed_choice_1(); +} + +// CHECK-NOTES: :[[@LINE-16]]:6: warning: function 'indirect_recursion_with_alternatives' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-16]]:6: warning: function 'conditionally_executed_choice_0' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-18]]:6: note: example recursive call chain, starting from function 'indirect_recursion_with_alternatives' +// CHECK-NOTES: :[[@LINE-8]]:5: note: Frame #1: function 'indirect_recursion_with_alternatives' calls function 'conditionally_executed_choice_0' here: +// CHECK-NOTES: :[[@LINE-17]]:5: note: Frame #2: function 'conditionally_executed_choice_0' calls function 'indirect_recursion_with_alternatives' here: +// CHECK-NOTES: :[[@LINE-18]]:5: note: ... which was the starting point of the recursive call chain; there may be other cycles +// CHECK-NOTES: :[[@LINE-17]]:6: warning: function 'conditionally_executed_choice_1' is within a recursive call chain [misc-no-recursion] + +static void indirect_recursion_with_depth2(); +static void conditionally_executed_depth1() { + if (external_oracle()) + indirect_recursion_with_depth2(); +} +static void conditionally_executed_depth0() { + if (external_oracle()) + conditionally_executed_depth1(); +} +void indirect_recursion_with_depth2() { + if (external_oracle()) + conditionally_executed_depth0(); +} + +// CHECK-NOTES: :[[@LINE-14]]:13: warning: function 'indirect_recursion_with_depth2' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-14]]:13: warning: function 'conditionally_executed_depth1' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-11]]:13: note: example recursive call chain, starting from function 'conditionally_executed_depth0' +// CHECK-NOTES: :[[@LINE-10]]:5: note: Frame #1: function 'conditionally_executed_depth0' calls function 'conditionally_executed_depth1' here: +// CHECK-NOTES: :[[@LINE-15]]:5: note: Frame #2: function 'conditionally_executed_depth1' calls function 'indirect_recursion_with_depth2' here: +// CHECK-NOTES: :[[@LINE-8]]:5: note: Frame #3: function 'indirect_recursion_with_depth2' calls function 'conditionally_executed_depth0' here: +// CHECK-NOTES: :[[@LINE-9]]:5: note: ... which was the starting point of the recursive call chain; there may be other cycles +// CHECK-NOTES: :[[@LINE-16]]:13: warning: function 'conditionally_executed_depth0' is within a recursive call chain [misc-no-recursion] + +int boo(); +void foo(int x = boo()) {} +void bar() { + foo(); + foo(); +} +int boo() { + bar(); + return 0; +} + +// CHECK-NOTES: :[[@LINE-11]]:5: warning: function 'boo' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-10]]:6: warning: function 'bar' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-13]]:5: note: example recursive call chain, starting from function 'boo' +// CHECK-NOTES: :[[@LINE-7]]:3: note: Frame #1: function 'boo' calls function 'bar' here: +// CHECK-NOTES: :[[@LINE-14]]:18: note: Frame #2: function 'bar' calls function 'boo' here: +// CHECK-NOTES: :[[@LINE-15]]:18: note: ... which was the starting point of the recursive call chain; there may be other cycles + +int recursion_through_function_ptr() { + auto *ptr = &recursion_through_function_ptr; + if (external_oracle()) + return ptr(); + return 0; +} + +int recursion_through_lambda() { + auto zz = []() { + if (external_oracle()) + return recursion_through_lambda(); + return 0; + }; + return zz(); +} + +// CHECK-NOTES: :[[@LINE-9]]:5: warning: function 'recursion_through_lambda' is within a recursive call chain [misc-no-recursion] +// CHECK-NOTES: :[[@LINE-9]]:13: note: example recursive call chain, starting from function 'operator()' +// CHECK-NOTES: :[[@LINE-8]]:14: note: Frame #1: function 'operator()' calls function 'recursion_through_lambda' here: +// CHECK-NOTES: :[[@LINE-6]]:10: note: Frame #2: function 'recursion_through_lambda' calls function 'operator()' here: +// CHECK-NOTES: :[[@LINE-7]]:10: note: ... which was the starting point of the recursive call chain; there may be other cycles +// CHECK-NOTES: :[[@LINE-13]]:13: warning: function 'operator()' is within a recursive call chain [misc-no-recursion] + +struct recursion_through_destructor { + ~recursion_through_destructor() { + if (external_oracle()) { + recursion_through_destructor variable; + // variable goes out of scope, it's destructor runs, and we are back here. + } + } +}; From 7ecf066e65d8d5970b2254c2674ad12ce3a76e31 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 13 Feb 2020 15:42:39 -0500 Subject: [PATCH 02/57] [OPENMP][DOCS]Fix misprint, NFC. --- clang/docs/OpenMPSupport.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/docs/OpenMPSupport.rst b/clang/docs/OpenMPSupport.rst index 98a4a324d67ce..91e1de61b456b 100644 --- a/clang/docs/OpenMPSupport.rst +++ b/clang/docs/OpenMPSupport.rst @@ -199,7 +199,7 @@ implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | clause: reverse_offload | :none:`unclaimed parts` | D52780 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -| device extension | clause: atomic_default_mem_orrder | :good:`done` | D53513 | +| device extension | clause: atomic_default_mem_order | :good:`done` | D53513 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | device extension | clause: dynamic_allocators | :none:`unclaimed parts` | D53079 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ From f888ae726280e3b173d323fd80ac7c3d93ad2026 Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Thu, 13 Feb 2020 20:43:19 +0000 Subject: [PATCH 03/57] [gn build] Port 49bffa5f8b7 --- .../gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn index a7a1abd0d41a4..fe00621e583a4 100644 --- a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn +++ b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/misc/BUILD.gn @@ -18,6 +18,7 @@ static_library("misc") { "MiscTidyModule.cpp", "MisplacedConstCheck.cpp", "NewDeleteOverloadsCheck.cpp", + "NoRecursionCheck.cpp", "NonCopyableObjects.cpp", "NonPrivateMemberVariablesInClassesCheck.cpp", "RedundantExpressionCheck.cpp", From f8b8a1ca8b6a82f28c96cbb1e3c2c136dc5b836b Mon Sep 17 00:00:00 2001 From: serge-sans-paille Date: Thu, 13 Feb 2020 21:48:56 +0100 Subject: [PATCH 04/57] Fix lit version test Looks like on some system, version is printed on stderr, on some it's on stdout... --- llvm/utils/lit/tests/version.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/lit/tests/version.py b/llvm/utils/lit/tests/version.py index 6d1d0fc5c794c..1d5e152ddd3b2 100644 --- a/llvm/utils/lit/tests/version.py +++ b/llvm/utils/lit/tests/version.py @@ -1,5 +1,5 @@ # Basic sanity check that --version works. # -# RUN: %{lit} --version | FileCheck %s +# RUN: %{lit} --version 2>&1 | FileCheck %s # # CHECK: lit {{[0-9]+\.[0-9]+\.[0-9]+[a-zA-Z0-9]*}} From e3548e23657d6c4988f815e9c87350f53e48e783 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Thu, 13 Feb 2020 12:50:54 -0800 Subject: [PATCH 05/57] Remove unnecessary typedef that GCC doesn't like --- clang/include/clang/AST/ParentMapContext.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/clang/include/clang/AST/ParentMapContext.h b/clang/include/clang/AST/ParentMapContext.h index 3ab55fb3d3095..be4d75df7b999 100644 --- a/clang/include/clang/AST/ParentMapContext.h +++ b/clang/include/clang/AST/ParentMapContext.h @@ -89,8 +89,6 @@ class TraversalKindScope { /// Container for either a single DynTypedNode or for an ArrayRef to /// DynTypedNode. For use with ParentMap. class DynTypedNodeList { - using DynTypedNode = DynTypedNode; - llvm::AlignedCharArrayUnion> Storage; bool IsSingleNode; From c6e8bfe7c9363129d98941373a94e22c226b4c08 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 13 Feb 2020 12:47:40 -0800 Subject: [PATCH 06/57] [llvm][TextAPI/MachO] Extend TBD_V4 unittest to verify writing Same as D73328 but for TBD_V4. One notable tidbit is that the swift abi version for swift 1 & 2 is emitted as a float which is considered invalid input. Differential revision: https://reviews.llvm.org/D73330 --- llvm/unittests/TextAPI/TextStubV4Tests.cpp | 92 +++++++++++++++++++++- 1 file changed, 90 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/TextAPI/TextStubV4Tests.cpp b/llvm/unittests/TextAPI/TextStubV4Tests.cpp index 3ffb66821814f..53e9bd9362c2f 100644 --- a/llvm/unittests/TextAPI/TextStubV4Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV4Tests.cpp @@ -33,6 +33,11 @@ inline bool operator==(const ExampleSymbol &LHS, const ExampleSymbol &RHS) { std::tie(RHS.Kind, RHS.Name, RHS.WeakDefined, RHS.ThreadLocalValue); } +inline std::string stripWhitespace(std::string s) { + s.erase(std::remove_if(s.begin(), s.end(), ::isspace), s.end()); + return s; +} + static ExampleSymbol TBDv4ExportedSymbols[] = { {SymbolKind::GlobalSymbol, "_symA", false, false}, {SymbolKind::GlobalSymbol, "_symAB", false, false}, @@ -255,13 +260,20 @@ TEST(TBDv4, MultipleTargets) { EXPECT_EQ(Platforms.size(), File->getPlatforms().size()); for (auto Platform : File->getPlatforms()) EXPECT_EQ(Platforms.count(Platform), 1U); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_multiple_targets), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, MultipleTargetsSameArch) { static const char tbd_targets_same_arch[] = "--- !tapi-tbd\n" "tbd-version: 4\n" - "targets: [ x86_64-maccatalyst, x86_64-tvos ]\n" + "targets: [ x86_64-tvos , x86_64-maccatalyst ]\n" "install-name: Test.dylib\n" "...\n"; @@ -277,13 +289,20 @@ TEST(TBDv4, MultipleTargetsSameArch) { EXPECT_EQ(Platforms.size(), File->getPlatforms().size()); for (auto Platform : File->getPlatforms()) EXPECT_EQ(Platforms.count(Platform), 1U); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_targets_same_arch), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, MultipleTargetsSamePlatform) { static const char tbd_multiple_targets_same_platform[] = "--- !tapi-tbd\n" "tbd-version: 4\n" - "targets: [ arm64-ios, armv7k-ios ]\n" + "targets: [ armv7k-ios , arm64-ios]\n" "install-name: Test.dylib\n" "...\n"; @@ -295,6 +314,13 @@ TEST(TBDv4, MultipleTargetsSamePlatform) { EXPECT_EQ(AK_arm64 | AK_armv7k, File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::iOS, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_multiple_targets_same_platform), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_maccatalyst) { @@ -313,6 +339,13 @@ TEST(TBDv4, Target_maccatalyst) { EXPECT_EQ(ArchitectureSet(AK_x86_64), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::macCatalyst, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_target_maccatalyst), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_x86_ios) { @@ -330,6 +363,13 @@ TEST(TBDv4, Target_x86_ios) { EXPECT_EQ(ArchitectureSet(AK_x86_64), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::iOS, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_target_x86_ios), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_arm_bridgeOS) { @@ -347,6 +387,13 @@ TEST(TBDv4, Target_arm_bridgeOS) { EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::bridgeOS, *File->getPlatforms().begin()); EXPECT_EQ(ArchitectureSet(AK_armv7k), File->getArchitectures()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_platform_bridgeos), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_x86_macos) { @@ -363,6 +410,12 @@ TEST(TBDv4, Target_x86_macos) { EXPECT_EQ(ArchitectureSet(AK_x86_64), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::macOS, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_x86_macos), stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_x86_ios_simulator) { @@ -380,6 +433,12 @@ TEST(TBDv4, Target_x86_ios_simulator) { EXPECT_EQ(ArchitectureSet(AK_x86_64), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::iOSSimulator, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_x86_ios_sim), stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_x86_tvos_simulator) { @@ -398,6 +457,12 @@ TEST(TBDv4, Target_x86_tvos_simulator) { EXPECT_EQ(ArchitectureSet(AK_x86_64), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::tvOSSimulator, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_x86_tvos_sim), stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Target_i386_watchos_simulator) { @@ -416,6 +481,13 @@ TEST(TBDv4, Target_i386_watchos_simulator) { EXPECT_EQ(ArchitectureSet(AK_i386), File->getArchitectures()); EXPECT_EQ(File->getPlatforms().size(), 1U); EXPECT_EQ(PlatformKind::watchOSSimulator, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_i386_watchos_sim), + stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Swift_1) { @@ -431,6 +503,8 @@ TEST(TBDv4, Swift_1) { auto File = std::move(Result.get()); EXPECT_EQ(FileType::TBD_V4, File->getFileType()); EXPECT_EQ(1U, File->getSwiftABIVersion()); + + // No writer test because we emit "swift-abi-version:1.0". } TEST(TBDv4, Swift_2) { @@ -446,6 +520,8 @@ TEST(TBDv4, Swift_2) { auto File = std::move(Result.get()); EXPECT_EQ(FileType::TBD_V4, File->getFileType()); EXPECT_EQ(2U, File->getSwiftABIVersion()); + + // No writer test because we emit "swift-abi-version:2.0". } TEST(TBDv4, Swift_5) { @@ -461,6 +537,12 @@ TEST(TBDv4, Swift_5) { auto File = std::move(Result.get()); EXPECT_EQ(FileType::TBD_V4, File->getFileType()); EXPECT_EQ(5U, File->getSwiftABIVersion()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_swift_5), stripWhitespace(Buffer.c_str())); } TEST(TBDv4, Swift_99) { @@ -476,6 +558,12 @@ TEST(TBDv4, Swift_99) { auto File = std::move(Result.get()); EXPECT_EQ(FileType::TBD_V4, File->getFileType()); EXPECT_EQ(99U, File->getSwiftABIVersion()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_swift_99), stripWhitespace(Buffer.c_str())); } TEST(TBDv4, InvalidArchitecture) { From 5810ed5186dcad03d4ae53abc103638462519f11 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 13 Feb 2020 12:51:19 -0800 Subject: [PATCH 07/57] [llvm][TextAPI/MachO] Extract common code into unittest helper (NFC) This extract common code between the 4 TBD formats in a header that can be shared. Differential revision: https://reviews.llvm.org/D73332 --- llvm/unittests/TextAPI/TextStubHelpers.h | 41 ++++++++++++++++++++ llvm/unittests/TextAPI/TextStubV1Tests.cpp | 18 +-------- llvm/unittests/TextAPI/TextStubV2Tests.cpp | 19 +-------- llvm/unittests/TextAPI/TextStubV3Tests.cpp | 25 +----------- llvm/unittests/TextAPI/TextStubV4Tests.cpp | 45 ++++++---------------- 5 files changed, 56 insertions(+), 92 deletions(-) create mode 100644 llvm/unittests/TextAPI/TextStubHelpers.h diff --git a/llvm/unittests/TextAPI/TextStubHelpers.h b/llvm/unittests/TextAPI/TextStubHelpers.h new file mode 100644 index 0000000000000..c33a45e87eb5e --- /dev/null +++ b/llvm/unittests/TextAPI/TextStubHelpers.h @@ -0,0 +1,41 @@ +//===-- TextStubHelpers.cpp -------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===-----------------------------------------------------------------------===/ + +#include "llvm/TextAPI/MachO/InterfaceFile.h" +#include +#include + +#ifndef TEXT_STUB_HELPERS_H +#define TEXT_STUB_HELPERS_H + +namespace llvm { +struct ExportedSymbol { + llvm::MachO::SymbolKind Kind; + std::string Name; + bool WeakDefined; + bool ThreadLocalValue; +}; + +using ExportedSymbolSeq = std::vector; +using UUIDs = std::vector>; + +inline bool operator<(const ExportedSymbol &LHS, const ExportedSymbol &RHS) { + return std::tie(LHS.Kind, LHS.Name) < std::tie(RHS.Kind, RHS.Name); +} + +inline bool operator==(const ExportedSymbol &LHS, const ExportedSymbol &RHS) { + return std::tie(LHS.Kind, LHS.Name, LHS.WeakDefined, LHS.ThreadLocalValue) == + std::tie(RHS.Kind, RHS.Name, RHS.WeakDefined, RHS.ThreadLocalValue); +} + +inline std::string stripWhitespace(std::string S) { + S.erase(std::remove_if(S.begin(), S.end(), ::isspace), S.end()); + return S; +} +} // namespace llvm +#endif diff --git a/llvm/unittests/TextAPI/TextStubV1Tests.cpp b/llvm/unittests/TextAPI/TextStubV1Tests.cpp index 68baac102dbf9..441db0ad629d5 100644 --- a/llvm/unittests/TextAPI/TextStubV1Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV1Tests.cpp @@ -6,6 +6,7 @@ // //===-----------------------------------------------------------------------===/ +#include "TextStubHelpers.h" #include "llvm/TextAPI/MachO/InterfaceFile.h" #include "llvm/TextAPI/MachO/TextAPIReader.h" #include "llvm/TextAPI/MachO/TextAPIWriter.h" @@ -16,23 +17,6 @@ using namespace llvm; using namespace llvm::MachO; -struct ExportedSymbol { - SymbolKind Kind; - std::string Name; - bool WeakDefined; - bool ThreadLocalValue; -}; -using ExportedSymbolSeq = std::vector; - -inline bool operator<(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name) < std::tie(rhs.Kind, rhs.Name); -} - -inline bool operator==(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name, lhs.WeakDefined, lhs.ThreadLocalValue) == - std::tie(rhs.Kind, rhs.Name, rhs.WeakDefined, rhs.ThreadLocalValue); -} - static ExportedSymbol TBDv1Symbols[] = { {SymbolKind::GlobalSymbol, "$ld$hide$os9.0$_sym1", false, false}, {SymbolKind::GlobalSymbol, "_sym1", false, false}, diff --git a/llvm/unittests/TextAPI/TextStubV2Tests.cpp b/llvm/unittests/TextAPI/TextStubV2Tests.cpp index 31de7fd2008ba..4864d8a95ccc8 100644 --- a/llvm/unittests/TextAPI/TextStubV2Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV2Tests.cpp @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===-----------------------------------------------------------------------===/ - +#include "TextStubHelpers.h" #include "llvm/TextAPI/MachO/InterfaceFile.h" #include "llvm/TextAPI/MachO/TextAPIReader.h" #include "llvm/TextAPI/MachO/TextAPIWriter.h" @@ -16,23 +16,6 @@ using namespace llvm; using namespace llvm::MachO; -struct ExportedSymbol { - SymbolKind Kind; - std::string Name; - bool WeakDefined; - bool ThreadLocalValue; -}; -using ExportedSymbolSeq = std::vector; - -inline bool operator<(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name) < std::tie(rhs.Kind, rhs.Name); -} - -inline bool operator==(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name, lhs.WeakDefined, lhs.ThreadLocalValue) == - std::tie(rhs.Kind, rhs.Name, rhs.WeakDefined, rhs.ThreadLocalValue); -} - static ExportedSymbol TBDv2Symbols[] = { {SymbolKind::GlobalSymbol, "$ld$hide$os9.0$_sym1", false, false}, {SymbolKind::GlobalSymbol, "_sym1", false, false}, diff --git a/llvm/unittests/TextAPI/TextStubV3Tests.cpp b/llvm/unittests/TextAPI/TextStubV3Tests.cpp index a9e54807cc85f..fe71fa5b2cf34 100644 --- a/llvm/unittests/TextAPI/TextStubV3Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV3Tests.cpp @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===-----------------------------------------------------------------------===/ - +#include "TextStubHelpers.h" #include "llvm/TextAPI/MachO/InterfaceFile.h" #include "llvm/TextAPI/MachO/TextAPIReader.h" #include "llvm/TextAPI/MachO/TextAPIWriter.h" @@ -16,29 +16,6 @@ using namespace llvm; using namespace llvm::MachO; -struct ExportedSymbol { - SymbolKind Kind; - std::string Name; - bool WeakDefined; - bool ThreadLocalValue; -}; -using ExportedSymbolSeq = std::vector; -using UUIDs = std::vector>; - -inline bool operator<(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name) < std::tie(rhs.Kind, rhs.Name); -} - -inline bool operator==(const ExportedSymbol &lhs, const ExportedSymbol &rhs) { - return std::tie(lhs.Kind, lhs.Name, lhs.WeakDefined, lhs.ThreadLocalValue) == - std::tie(rhs.Kind, rhs.Name, rhs.WeakDefined, rhs.ThreadLocalValue); -} - -inline std::string stripWhitespace(std::string s) { - s.erase(std::remove_if(s.begin(), s.end(), ::isspace), s.end()); - return s; -} - static ExportedSymbol TBDv3Symbols[] = { {SymbolKind::GlobalSymbol, "$ld$hide$os9.0$_sym1", false, false}, {SymbolKind::GlobalSymbol, "_sym1", false, false}, diff --git a/llvm/unittests/TextAPI/TextStubV4Tests.cpp b/llvm/unittests/TextAPI/TextStubV4Tests.cpp index 53e9bd9362c2f..07af8f20dea35 100644 --- a/llvm/unittests/TextAPI/TextStubV4Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV4Tests.cpp @@ -5,6 +5,8 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===-----------------------------------------------------------------------===/ + +#include "TextStubHelpers.h" #include "llvm/TextAPI/MachO/InterfaceFile.h" #include "llvm/TextAPI/MachO/TextAPIReader.h" #include "llvm/TextAPI/MachO/TextAPIWriter.h" @@ -15,40 +17,17 @@ using namespace llvm; using namespace llvm::MachO; -struct ExampleSymbol { - SymbolKind Kind; - std::string Name; - bool WeakDefined; - bool ThreadLocalValue; -}; -using ExampleSymbolSeq = std::vector; -using UUIDs = std::vector>; - -inline bool operator<(const ExampleSymbol &LHS, const ExampleSymbol &RHS) { - return std::tie(LHS.Kind, LHS.Name) < std::tie(RHS.Kind, RHS.Name); -} - -inline bool operator==(const ExampleSymbol &LHS, const ExampleSymbol &RHS) { - return std::tie(LHS.Kind, LHS.Name, LHS.WeakDefined, LHS.ThreadLocalValue) == - std::tie(RHS.Kind, RHS.Name, RHS.WeakDefined, RHS.ThreadLocalValue); -} - -inline std::string stripWhitespace(std::string s) { - s.erase(std::remove_if(s.begin(), s.end(), ::isspace), s.end()); - return s; -} - -static ExampleSymbol TBDv4ExportedSymbols[] = { +static ExportedSymbol TBDv4ExportedSymbols[] = { {SymbolKind::GlobalSymbol, "_symA", false, false}, {SymbolKind::GlobalSymbol, "_symAB", false, false}, {SymbolKind::GlobalSymbol, "_symB", false, false}, }; -static ExampleSymbol TBDv4ReexportedSymbols[] = { +static ExportedSymbol TBDv4ReexportedSymbols[] = { {SymbolKind::GlobalSymbol, "_symC", false, false}, }; -static ExampleSymbol TBDv4UndefinedSymbols[] = { +static ExportedSymbol TBDv4UndefinedSymbols[] = { {SymbolKind::GlobalSymbol, "_symD", false, false}, }; @@ -146,11 +125,11 @@ TEST(TBDv4, ReadFile) { EXPECT_EQ(1U, File->reexportedLibraries().size()); EXPECT_EQ(reexport, File->reexportedLibraries().front()); - ExampleSymbolSeq Exports, Reexports, Undefineds; - ExampleSymbol temp; + ExportedSymbolSeq Exports, Reexports, Undefineds; + ExportedSymbol temp; for (const auto *Sym : File->symbols()) { - temp = ExampleSymbol{Sym->getKind(), std::string(Sym->getName()), - Sym->isWeakDefined(), Sym->isThreadLocalValue()}; + temp = ExportedSymbol{Sym->getKind(), std::string(Sym->getName()), + Sym->isWeakDefined(), Sym->isThreadLocalValue()}; EXPECT_FALSE(Sym->isWeakReferenced()); if (Sym->isUndefined()) Undefineds.emplace_back(std::move(temp)); @@ -162,11 +141,11 @@ TEST(TBDv4, ReadFile) { llvm::sort(Reexports.begin(), Reexports.end()); llvm::sort(Undefineds.begin(), Undefineds.end()); - EXPECT_EQ(sizeof(TBDv4ExportedSymbols) / sizeof(ExampleSymbol), + EXPECT_EQ(sizeof(TBDv4ExportedSymbols) / sizeof(ExportedSymbol), Exports.size()); - EXPECT_EQ(sizeof(TBDv4ReexportedSymbols) / sizeof(ExampleSymbol), + EXPECT_EQ(sizeof(TBDv4ReexportedSymbols) / sizeof(ExportedSymbol), Reexports.size()); - EXPECT_EQ(sizeof(TBDv4UndefinedSymbols) / sizeof(ExampleSymbol), + EXPECT_EQ(sizeof(TBDv4UndefinedSymbols) / sizeof(ExportedSymbol), Undefineds.size()); EXPECT_TRUE(std::equal(Exports.begin(), Exports.end(), std::begin(TBDv4ExportedSymbols))); From 21695710cfa9a36256e9547155e2b9e0139f5c6a Mon Sep 17 00:00:00 2001 From: Kostya Kortchinsky Date: Thu, 13 Feb 2020 09:27:18 -0800 Subject: [PATCH 08/57] [scudo][standalone] Workaround for full regions on Android Summary: Due to Unity, we had to reduce our region sizes, but in some rare situations, some programs (mostly tests AFAICT) manage to fill up a region for a given size class. So this adds a workaround for that attempts to allocate the block from the immediately larger size class, wasting some memory but allowing the application to keep going. Reviewers: pcc, eugenis, cferris, hctim, morehouse Subscribers: #sanitizers, llvm-commits Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D74567 --- compiler-rt/lib/scudo/standalone/combined.h | 11 +++++ .../scudo/standalone/tests/combined_test.cpp | 49 ++++++++++++++++--- 2 files changed, 54 insertions(+), 6 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index bd78d79857ec9..e8390a7b44f16 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -267,6 +267,17 @@ class Allocator { bool UnlockRequired; auto *TSD = TSDRegistry.getTSDAndLock(&UnlockRequired); Block = TSD->Cache.allocate(ClassId); + // If the allocation failed, the most likely reason with a 64-bit primary + // is the region being full. In that event, retry once using the + // immediately larger class (except if the failing class was already the + // largest). This will waste some memory but will allow the application to + // not fail. + if (SCUDO_ANDROID) { + if (UNLIKELY(!Block)) { + if (ClassId < SizeClassMap::LargestClassId) + Block = TSD->Cache.allocate(++ClassId); + } + } if (UnlockRequired) TSD->unlock(); } else { diff --git a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp index 488dca91a3592..ce1b2824788da 100644 --- a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp @@ -344,20 +344,21 @@ TEST(ScudoCombinedTest, ThreadedCombined) { #endif } - struct DeathSizeClassConfig { static const scudo::uptr NumBits = 1; static const scudo::uptr MinSizeLog = 10; static const scudo::uptr MidSizeLog = 10; - static const scudo::uptr MaxSizeLog = 10; - static const scudo::u32 MaxNumCachedHint = 1; - static const scudo::uptr MaxBytesCachedLog = 10; + static const scudo::uptr MaxSizeLog = 11; + static const scudo::u32 MaxNumCachedHint = 4; + static const scudo::uptr MaxBytesCachedLog = 12; }; +static const scudo::uptr DeathRegionSizeLog = 20U; struct DeathConfig { - // Tiny allocator, its Primary only serves chunks of 1024 bytes. + // Tiny allocator, its Primary only serves chunks of two sizes. using DeathSizeClassMap = scudo::FixedSizeClassMap; - typedef scudo::SizeClassAllocator64 Primary; + typedef scudo::SizeClassAllocator64 + Primary; typedef scudo::MapAllocator Secondary; template using TSDRegistryT = scudo::TSDRegistrySharedT; }; @@ -415,3 +416,39 @@ TEST(ScudoCombinedTest, ReleaseToOS) { Allocator->releaseToOS(); } + +// Verify that when a region gets full, Android will still manage to +// fulfill the allocation through a larger size class. +TEST(ScudoCombinedTest, FullRegion) { + using AllocatorT = scudo::Allocator; + auto Deleter = [](AllocatorT *A) { + A->unmapTestOnly(); + delete A; + }; + std::unique_ptr Allocator(new AllocatorT, + Deleter); + Allocator->reset(); + + const scudo::uptr Size = 1000U; + const scudo::uptr MaxNumberOfChunks = + (1U << DeathRegionSizeLog) / + DeathConfig::DeathSizeClassMap::getSizeByClassId(1U); + void *P; + std::vector V; + scudo::uptr FailedAllocationsCount = 0; + for (scudo::uptr I = 0; I <= MaxNumberOfChunks; I++) { + P = Allocator->allocate(Size, Origin); + if (!P) + FailedAllocationsCount++; + else + V.push_back(P); + } + while (!V.empty()) { + Allocator->deallocate(V.back(), Origin); + V.pop_back(); + } + if (SCUDO_ANDROID) + EXPECT_EQ(FailedAllocationsCount, 0U); + else + EXPECT_GT(FailedAllocationsCount, 0U); +} From 1287977b9edd86a4983542b50a082dd0996ae67e Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Thu, 13 Feb 2020 13:04:51 -0800 Subject: [PATCH 09/57] Document third option to python synthetic type summary callback unconditionally; it was added to lldb five years ago and we don't need to qualify its availability. --- lldb/docs/use/variable.rst | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/lldb/docs/use/variable.rst b/lldb/docs/use/variable.rst index 4e3f25eb6a4a8..7915abf92d65c 100644 --- a/lldb/docs/use/variable.rst +++ b/lldb/docs/use/variable.rst @@ -651,7 +651,7 @@ class, as shown in this example: (lldb) type summary add -P Rectangle Enter your Python command(s). Type 'DONE' to end. - def function (valobj,internal_dict): + def function (valobj,internal_dict,options): height_val = valobj.GetChildMemberWithName('height') width_val = valobj.GetChildMemberWithName('width') height = height_val.GetValueAsUnsigned(0) @@ -698,6 +698,12 @@ that (yet) via this method call, and you must use ``GetChildAtIndex()`` querying it for the array items one by one. Also, handling custom formats is something you have to deal with on your own. +``options`` Python summary formatters can optionally define this +third argument, which is an object of type ``lldb.SBTypeSummaryOptions``, +allowing for a few customizations of the result. The decision to +adopt or not this third argument - and the meaning of options thereof +- is up to the individual formatter's writer. + Other than interactively typing a Python script there are two other ways for you to input a Python script as a summary: @@ -716,14 +722,6 @@ you to input a Python script as a summary: LLDB will emit a warning if it is unable to find the function you passed, but will still register the binding. -Starting in SVN r222593, Python summary formatters can optionally define a -third argument: options - -This is an object of type ``lldb.SBTypeSummaryOptions`` that can be passed into -the formatter, allowing for a few customizations of the result. The decision to -adopt or not this third argument - and the meaning of options thereof - is -within the individual formatters' writer. - Regular Expression Typenames ---------------------------- From 14d686309a1ac9cc41522b00da7a751db592ef6e Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Thu, 13 Feb 2020 13:06:44 -0800 Subject: [PATCH 10/57] Small reformat to avoid tripping up possible formatting. --- lldb/docs/use/variable.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lldb/docs/use/variable.rst b/lldb/docs/use/variable.rst index 7915abf92d65c..5b1fef7b06c34 100644 --- a/lldb/docs/use/variable.rst +++ b/lldb/docs/use/variable.rst @@ -701,8 +701,8 @@ something you have to deal with on your own. ``options`` Python summary formatters can optionally define this third argument, which is an object of type ``lldb.SBTypeSummaryOptions``, allowing for a few customizations of the result. The decision to -adopt or not this third argument - and the meaning of options thereof -- is up to the individual formatter's writer. +adopt or not this third argument - and the meaning of options +thereof - is up to the individual formatter's writer. Other than interactively typing a Python script there are two other ways for you to input a Python script as a summary: From ef7488ef205ceb018af463b82386f5ee6a365445 Mon Sep 17 00:00:00 2001 From: Kostya Kortchinsky Date: Thu, 13 Feb 2020 12:55:56 -0800 Subject: [PATCH 11/57] [GWP-ASan] Silence gcc error Summary: It complains about reaching the end of a non-void returning function. Reviewers: eugenis, hctim, morehouse Subscribers: #sanitizers, llvm-commits Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D74578 --- compiler-rt/lib/gwp_asan/platform_specific/utilities_posix.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/lib/gwp_asan/platform_specific/utilities_posix.cpp b/compiler-rt/lib/gwp_asan/platform_specific/utilities_posix.cpp index 45b19397b1a3c..0e60598967029 100644 --- a/compiler-rt/lib/gwp_asan/platform_specific/utilities_posix.cpp +++ b/compiler-rt/lib/gwp_asan/platform_specific/utilities_posix.cpp @@ -84,6 +84,7 @@ size_t rightAlignedAllocationSize(size_t RealAllocationSize, case AlignmentStrategy::DEFAULT: __builtin_unreachable(); } + __builtin_unreachable(); } } // namespace gwp_asan From fa0118e6e588fe303b08e7e06ba28ac1f8d50c68 Mon Sep 17 00:00:00 2001 From: Wawha Date: Thu, 13 Feb 2020 20:25:34 +0100 Subject: [PATCH 12/57] [clang-format] Add new option BeforeLambdaBody in Allman style. This option add a line break then a lambda is inside a function call. Reviewers : djasper, klimek, krasimir, MyDeveloperDay Reviewed By: MyDeveloperDay Differential Revision: https://reviews.llvm.org/D44609 --- clang/docs/ClangFormatStyleOptions.rst | 18 + clang/docs/ReleaseNotes.rst | 563 +++++++++++----------- clang/include/clang/Format/Format.h | 17 + clang/lib/Format/ContinuationIndenter.cpp | 36 +- clang/lib/Format/Format.cpp | 22 +- clang/lib/Format/TokenAnnotator.cpp | 71 ++- clang/unittests/Format/FormatTest.cpp | 240 +++++++++ 7 files changed, 680 insertions(+), 287 deletions(-) diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 0c515922e650b..50b4ff5d90105 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -968,6 +968,24 @@ the configuration (without a prefix: ``Auto``). } else { } + * ``bool BeforeLambdaBody`` Wrap lambda block. + + .. code-block:: c++ + + true: + connect( + []() + { + foo(); + bar(); + }); + + false: + connect([]() { + foo(); + bar(); + }); + * ``bool IndentBraces`` Indent the wrapped braces themselves. * ``bool SplitEmptyFunction`` If ``false``, empty function body can be put on a single line. diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index d24cd85673c67..e0a15f8d38a1e 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1,272 +1,291 @@ -======================================== -Clang 11.0.0 (In-Progress) Release Notes -======================================== - -.. contents:: - :local: - :depth: 2 - -Written by the `LLVM Team `_ - -.. warning:: - - These are in-progress notes for the upcoming Clang 11 release. - Release notes for previous releases can be found on - `the Download Page `_. - -Introduction -============ - -This document contains the release notes for the Clang C/C++/Objective-C -frontend, part of the LLVM Compiler Infrastructure, release 11.0.0. Here we -describe the status of Clang in some detail, including major -improvements from the previous release and new feature work. For the -general LLVM release notes, see `the LLVM -documentation `_. All LLVM -releases may be downloaded from the `LLVM releases web -site `_. - -For more information about Clang or LLVM, including information about the -latest release, please see the `Clang Web Site `_ or the -`LLVM Web Site `_. - -Note that if you are reading this file from a Git checkout or the -main Clang web page, this document applies to the *next* release, not -the current one. To see the release notes for a specific release, please -see the `releases page `_. - -What's New in Clang 11.0.0? -=========================== - -Some of the major new features and improvements to Clang are listed -here. Generic improvements to Clang as a whole or to its underlying -infrastructure are described first, followed by language-specific -sections with improvements to Clang's support for those languages. - -Major New Features ------------------- - -- ... - -Improvements to Clang's diagnostics -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ... - -Non-comprehensive list of changes in this release -------------------------------------------------- - - -New Compiler Flags ------------------- - - -- -fstack-clash-protection will provide a protection against the stack clash - attack for x86 architecture through automatic probing of each page of - allocated stack. - -Deprecated Compiler Flags -------------------------- - -The following options are deprecated and ignored. They will be removed in -future versions of Clang. - -- ... - -Modified Compiler Flags ------------------------ - - -New Pragmas in Clang --------------------- - -- ... - -Attribute Changes in Clang --------------------------- - -- ... - -Windows Support ---------------- - -C Language Changes in Clang ---------------------------- - -- ... - -C11 Feature Support -^^^^^^^^^^^^^^^^^^^ - -... - -C++ Language Changes in Clang ------------------------------ - -- Clang now implements a restriction on giving non-C-compatible anonymous - structs a typedef name for linkage purposes, as described in C++ committee - paper `P1766R1 `. This paper was adopted by the - C++ committee as a Defect Report resolution, so it is applied retroactively - to all C++ standard versions. This affects code such as: - - .. code-block:: c++ - - typedef struct { - int f() { return 0; } - } S; - - Previous versions of Clang rejected some constructs of this form - (specifically, where the linkage of the type happened to be computed - before the parser reached the typedef name); those cases are still rejected - in Clang 11. In addition, cases that previous versions of Clang did not - reject now produce an extension warning. This warning can be disabled with - the warning flag ``-Wno-non-c-typedef-for-linkage``. - - Affected code should be updated to provide a tag name for the anonymous - struct: - - .. code-block:: c++ - - struct S { - int f() { return 0; } - }; - - If the code is shared with a C compilation (for example, if the parts that - are not C-compatible are guarded with ``#ifdef __cplusplus``), the typedef - declaration should be retained, but a tag name should still be provided: - - .. code-block:: c++ - - typedef struct S { - int f() { return 0; } - } S; - -C++1z Feature Support -^^^^^^^^^^^^^^^^^^^^^ - -... - -Objective-C Language Changes in Clang -------------------------------------- - - -OpenCL C Language Changes in Clang ----------------------------------- - -... - -ABI Changes in Clang --------------------- - - -OpenMP Support in Clang ------------------------ - -- ... - -CUDA Support in Clang ---------------------- - -- ... - -Internal API Changes --------------------- - -These are major API changes that have happened since the 10.0.0 release of -Clang. If upgrading an external codebase that uses Clang as a library, -this section should help get you past the largest hurdles of upgrading. - - -Build System Changes --------------------- - -These are major changes to the build system that have happened since the 10.0.0 -release of Clang. Users of the build system should adjust accordingly. - -- ... - -AST Matchers ------------- - -- ... - -clang-format ------------- - - -- Option ``IndentCaseBlocks`` has been added to support treating the block - following a switch case label as a scope block which gets indented itself. - It helps avoid having the closing bracket align with the switch statement's - closing bracket (when ``IndentCaseLabels`` is ``false``). - -- Option ``ObjCBreakBeforeNestedBlockParam`` has been added to optionally apply - linebreaks for function arguments declarations before nested blocks. - - .. code-block:: c++ - - switch (fool) { vs. switch (fool) { - case 1: case 1: { - { bar(); - bar(); } break; - } default: { - break; plop(); - default: } - { } - plop(); - } - } - -- Option ``InsertTrailingCommas`` can be set to ``TCS_Wrapped`` to insert - trailing commas in container literals (arrays and objects) that wrap across - multiple lines. It is currently only available for JavaScript and disabled by - default (``TCS_None``). - -libclang --------- - -- ... - -Static Analyzer ---------------- - -- ... - -.. _release-notes-ubsan: - -Undefined Behavior Sanitizer (UBSan) ------------------------------------- - - -Core Analysis Improvements -========================== - -- ... - -New Issues Found -================ - -- ... - -Python Binding Changes ----------------------- - -The following methods have been added: - -- ... - -Significant Known Problems -========================== - -Additional Information -====================== - -A wide variety of additional information is available on the `Clang web -page `_. The web page contains versions of the -API documentation which are up-to-date with the Subversion version of -the source code. You can access versions of these documents specific to -this release by going into the "``clang/docs/``" directory in the Clang -tree. - -If you have any questions or comments about Clang, please feel free to -contact us via the `mailing -list `_. +======================================== +Clang 11.0.0 (In-Progress) Release Notes +======================================== + +.. contents:: + :local: + :depth: 2 + +Written by the `LLVM Team `_ + +.. warning:: + + These are in-progress notes for the upcoming Clang 11 release. + Release notes for previous releases can be found on + `the Download Page `_. + +Introduction +============ + +This document contains the release notes for the Clang C/C++/Objective-C +frontend, part of the LLVM Compiler Infrastructure, release 11.0.0. Here we +describe the status of Clang in some detail, including major +improvements from the previous release and new feature work. For the +general LLVM release notes, see `the LLVM +documentation `_. All LLVM +releases may be downloaded from the `LLVM releases web +site `_. + +For more information about Clang or LLVM, including information about the +latest release, please see the `Clang Web Site `_ or the +`LLVM Web Site `_. + +Note that if you are reading this file from a Git checkout or the +main Clang web page, this document applies to the *next* release, not +the current one. To see the release notes for a specific release, please +see the `releases page `_. + +What's New in Clang 11.0.0? +=========================== + +Some of the major new features and improvements to Clang are listed +here. Generic improvements to Clang as a whole or to its underlying +infrastructure are described first, followed by language-specific +sections with improvements to Clang's support for those languages. + +Major New Features +------------------ + +- ... + +Improvements to Clang's diagnostics +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- ... + +Non-comprehensive list of changes in this release +------------------------------------------------- + + +New Compiler Flags +------------------ + + +- -fstack-clash-protection will provide a protection against the stack clash + attack for x86 architecture through automatic probing of each page of + allocated stack. + +Deprecated Compiler Flags +------------------------- + +The following options are deprecated and ignored. They will be removed in +future versions of Clang. + +- ... + +Modified Compiler Flags +----------------------- + + +New Pragmas in Clang +-------------------- + +- ... + +Attribute Changes in Clang +-------------------------- + +- ... + +Windows Support +--------------- + +C Language Changes in Clang +--------------------------- + +- ... + +C11 Feature Support +^^^^^^^^^^^^^^^^^^^ + +... + +C++ Language Changes in Clang +----------------------------- + +- Clang now implements a restriction on giving non-C-compatible anonymous + structs a typedef name for linkage purposes, as described in C++ committee + paper `P1766R1 `. This paper was adopted by the + C++ committee as a Defect Report resolution, so it is applied retroactively + to all C++ standard versions. This affects code such as: + + .. code-block:: c++ + + typedef struct { + int f() { return 0; } + } S; + + Previous versions of Clang rejected some constructs of this form + (specifically, where the linkage of the type happened to be computed + before the parser reached the typedef name); those cases are still rejected + in Clang 11. In addition, cases that previous versions of Clang did not + reject now produce an extension warning. This warning can be disabled with + the warning flag ``-Wno-non-c-typedef-for-linkage``. + + Affected code should be updated to provide a tag name for the anonymous + struct: + + .. code-block:: c++ + + struct S { + int f() { return 0; } + }; + + If the code is shared with a C compilation (for example, if the parts that + are not C-compatible are guarded with ``#ifdef __cplusplus``), the typedef + declaration should be retained, but a tag name should still be provided: + + .. code-block:: c++ + + typedef struct S { + int f() { return 0; } + } S; + +C++1z Feature Support +^^^^^^^^^^^^^^^^^^^^^ + +... + +Objective-C Language Changes in Clang +------------------------------------- + + +OpenCL C Language Changes in Clang +---------------------------------- + +... + +ABI Changes in Clang +-------------------- + + +OpenMP Support in Clang +----------------------- + +- ... + +CUDA Support in Clang +--------------------- + +- ... + +Internal API Changes +-------------------- + +These are major API changes that have happened since the 10.0.0 release of +Clang. If upgrading an external codebase that uses Clang as a library, +this section should help get you past the largest hurdles of upgrading. + + +Build System Changes +-------------------- + +These are major changes to the build system that have happened since the 10.0.0 +release of Clang. Users of the build system should adjust accordingly. + +- ... + +AST Matchers +------------ + +- ... + +clang-format +------------ + + +- Option ``IndentCaseBlocks`` has been added to support treating the block + following a switch case label as a scope block which gets indented itself. + It helps avoid having the closing bracket align with the switch statement's + closing bracket (when ``IndentCaseLabels`` is ``false``). + +- Option ``ObjCBreakBeforeNestedBlockParam`` has been added to optionally apply + linebreaks for function arguments declarations before nested blocks. + + .. code-block:: c++ + + switch (fool) { vs. switch (fool) { + case 1: case 1: { + { bar(); + bar(); } break; + } default: { + break; plop(); + default: } + { } + plop(); + } + } + +- Option ``InsertTrailingCommas`` can be set to ``TCS_Wrapped`` to insert + trailing commas in container literals (arrays and objects) that wrap across + multiple lines. It is currently only available for JavaScript and disabled by + default (``TCS_None``). + +- Option ``BraceWrapping.BeforeLambdaBody`` has been added to manage lambda + line break inside function parameter call in Allman style. + + .. code-block:: c++ + + true: + connect( + []() + { + foo(); + bar(); + }); + + false: + connect([]() { + foo(); + bar(); + }); + +libclang +-------- + +- ... + +Static Analyzer +--------------- + +- ... + +.. _release-notes-ubsan: + +Undefined Behavior Sanitizer (UBSan) +------------------------------------ + + +Core Analysis Improvements +========================== + +- ... + +New Issues Found +================ + +- ... + +Python Binding Changes +---------------------- + +The following methods have been added: + +- ... + +Significant Known Problems +========================== + +Additional Information +====================== + +A wide variety of additional information is available on the `Clang web +page `_. The web page contains versions of the +API documentation which are up-to-date with the Subversion version of +the source code. You can access versions of these documents specific to +this release by going into the "``clang/docs/``" directory in the Clang +tree. + +If you have any questions or comments about Clang, please feel free to +contact us via the `mailing +list `_. diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 82afaa721ed9a..d4f76c87c14ea 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -992,6 +992,23 @@ struct FormatStyle { /// } /// \endcode bool BeforeElse; + /// Wrap lambda block. + /// \code + /// true: + /// connect( + /// []() + /// { + /// foo(); + /// bar(); + /// }); + /// + /// false: + /// connect([]() { + /// foo(); + /// bar(); + /// }); + /// \endcode + bool BeforeLambdaBody; /// Indent the wrapped braces themselves. bool IndentBraces; /// If ``false``, empty function body can be put on a single line. diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index e3c9f7ce5f0cb..a08f5a3df864d 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -329,6 +329,11 @@ bool ContinuationIndenter::canBreak(const LineState &State) { bool ContinuationIndenter::mustBreak(const LineState &State) { const FormatToken &Current = *State.NextToken; const FormatToken &Previous = *Current.Previous; + if (Style.BraceWrapping.BeforeLambdaBody && Current.CanBreakBefore && + Current.is(TT_LambdaLBrace)) { + auto LambdaBodyLength = getLengthToMatchingParen(Current, State.Stack); + return (LambdaBodyLength > getColumnLimit(State)); + } if (Current.MustBreakBefore || Current.is(TT_InlineASMColon)) return true; if (State.Stack.back().BreakBeforeClosingBrace && @@ -1081,6 +1086,18 @@ unsigned ContinuationIndenter::getNewLineColumn(const LineState &State) { return State.Stack.back().Indent; } +static bool hasNestedBlockInlined(const FormatToken *Previous, + const FormatToken &Current, + const FormatStyle &Style) { + if (Previous->isNot(tok::l_paren)) + return true; + if (Previous->ParameterCount > 1) + return true; + + // Also a nested block if contains a lambda inside function with 1 parameter + return (Style.BraceWrapping.BeforeLambdaBody && Current.is(TT_LambdaLSquare)); +} + unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, bool DryRun, bool Newline) { assert(State.Stack.size()); @@ -1183,8 +1200,7 @@ unsigned ContinuationIndenter::moveStateToNextToken(LineState &State, Previous->isOneOf(TT_BinaryOperator, TT_ConditionalExpr)) && !Previous->isOneOf(TT_DictLiteral, TT_ObjCMethodExpr)) { State.Stack.back().NestedBlockInlined = - !Newline && - (Previous->isNot(tok::l_paren) || Previous->ParameterCount > 1); + !Newline && hasNestedBlockInlined(Previous, Current, Style); } moveStatePastFakeLParens(State, Newline); @@ -1421,7 +1437,21 @@ void ContinuationIndenter::moveStatePastScopeOpener(LineState &State, ParenState(&Current, NewIndent, LastSpace, AvoidBinPacking, NoLineBreak)); State.Stack.back().NestedBlockIndent = NestedBlockIndent; State.Stack.back().BreakBeforeParameter = BreakBeforeParameter; - State.Stack.back().HasMultipleNestedBlocks = Current.BlockParameterCount > 1; + State.Stack.back().HasMultipleNestedBlocks = (Current.BlockParameterCount > 1); + + if (Style.BraceWrapping.BeforeLambdaBody && + Current.Next != nullptr && Current.Tok.is(tok::l_paren)) { + // Search for any parameter that is a lambda + FormatToken const *next = Current.Next; + while (next != nullptr) { + if (next->is(TT_LambdaLSquare)) { + State.Stack.back().HasMultipleNestedBlocks = true; + break; + } + next = next->Next; + } + } + State.Stack.back().IsInsideObjCArrayLiteral = Current.is(TT_ArrayInitializerLSquare) && Current.Previous && Current.Previous->is(tok::at); diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 83e95982aa447..031312bd16d86 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -581,6 +581,7 @@ template <> struct MappingTraits { IO.mapOptional("AfterExternBlock", Wrapping.AfterExternBlock); IO.mapOptional("BeforeCatch", Wrapping.BeforeCatch); IO.mapOptional("BeforeElse", Wrapping.BeforeElse); + IO.mapOptional("BeforeLambdaBody", Wrapping.BeforeLambdaBody); IO.mapOptional("IndentBraces", Wrapping.IndentBraces); IO.mapOptional("SplitEmptyFunction", Wrapping.SplitEmptyFunction); IO.mapOptional("SplitEmptyRecord", Wrapping.SplitEmptyRecord); @@ -668,8 +669,8 @@ static FormatStyle expandPresets(const FormatStyle &Style) { false, false, false, false, false, false, false, false, false, - false, true, true, - true}; + false, false, true, + true, true}; switch (Style.BreakBeforeBraces) { case FormatStyle::BS_Linux: Expanded.BraceWrapping.AfterClass = true; @@ -717,14 +718,15 @@ static FormatStyle expandPresets(const FormatStyle &Style) { Expanded.BraceWrapping.AfterExternBlock = true; Expanded.BraceWrapping.BeforeCatch = true; Expanded.BraceWrapping.BeforeElse = true; + Expanded.BraceWrapping.BeforeLambdaBody = true; break; case FormatStyle::BS_GNU: - Expanded.BraceWrapping = {true, true, FormatStyle::BWACS_Always, - true, true, true, - true, true, true, - true, true, true, - true, true, true, - true}; + Expanded.BraceWrapping = {true, true, FormatStyle::BWACS_Always, + true, true, true, + true, true, true, + true, true, true, + false, true, true, + true, true}; break; case FormatStyle::BS_WebKit: Expanded.BraceWrapping.AfterFunction = true; @@ -768,8 +770,8 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { false, false, false, false, false, false, false, false, false, - false, true, true, - true}; + false, false, true, + true, true}; LLVMStyle.BreakAfterJavaFieldAnnotations = false; LLVMStyle.BreakConstructorInitializers = FormatStyle::BCIS_BeforeColon; LLVMStyle.BreakInheritanceList = FormatStyle::BILS_BeforeColon; diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 1c15859e5786a..42963ca105a95 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -3122,6 +3122,56 @@ static bool isAllmanBrace(const FormatToken &Tok) { !Tok.isOneOf(TT_ObjCBlockLBrace, TT_LambdaLBrace, TT_DictLiteral); } +// Returns 'true' if 'Tok' is an function argument. +static bool IsFunctionArgument(const FormatToken &Tok) { + return Tok.MatchingParen && Tok.MatchingParen->Next && + Tok.MatchingParen->Next->isOneOf(tok::comma, tok::r_paren); +} + +static bool +isItAnEmptyLambdaAllowed(const FormatToken &Tok, + FormatStyle::ShortLambdaStyle ShortLambdaOption) { + return Tok.Children.empty() && ShortLambdaOption != FormatStyle::SLS_None; +} + +static bool +isItAInlineLambdaAllowed(const FormatToken &Tok, + FormatStyle::ShortLambdaStyle ShortLambdaOption) { + return (ShortLambdaOption == FormatStyle::SLS_Inline && + IsFunctionArgument(Tok)) || + (ShortLambdaOption == FormatStyle::SLS_All); +} + +static bool isOneChildWithoutMustBreakBefore(const FormatToken &Tok) { + if (Tok.Children.size() != 1) + return false; + FormatToken *curElt = Tok.Children[0]->First; + while (curElt) { + if (curElt->MustBreakBefore) + return false; + curElt = curElt->Next; + } + return true; +} +static bool +isAllmanLambdaBrace(const FormatToken &Tok) { + return (Tok.is(tok::l_brace) && Tok.BlockKind == BK_Block && + !Tok.isOneOf(TT_ObjCBlockLBrace, TT_DictLiteral)); +} + +static bool +isAllmanBraceIncludedBreakableLambda(const FormatToken &Tok, + FormatStyle::ShortLambdaStyle ShortLambdaOption) { + if (!isAllmanLambdaBrace(Tok)) + return false; + + if (isItAnEmptyLambdaAllowed(Tok, ShortLambdaOption)) + return false; + + return !isItAInlineLambdaAllowed(Tok, ShortLambdaOption) || + !isOneChildWithoutMustBreakBefore(Tok); +} + bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, const FormatToken &Right) { const FormatToken &Left = *Right.Previous; @@ -3257,6 +3307,14 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, } if (Right.is(TT_InlineASMBrace)) return Right.HasUnescapedNewline; + + auto ShortLambdaOption = Style.AllowShortLambdasOnASingleLine; + if (Style.BraceWrapping.BeforeLambdaBody && + (isAllmanBraceIncludedBreakableLambda(Left, ShortLambdaOption) || + isAllmanBraceIncludedBreakableLambda(Right, ShortLambdaOption))) { + return true; + } + if (isAllmanBrace(Left) || isAllmanBrace(Right)) return (Line.startsWith(tok::kw_enum) && Style.BraceWrapping.AfterEnum) || (Line.startsWith(tok::kw_typedef, tok::kw_enum) && @@ -3268,8 +3326,7 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, return true; if (Left.is(TT_LambdaLBrace)) { - if (Left.MatchingParen && Left.MatchingParen->Next && - Left.MatchingParen->Next->isOneOf(tok::comma, tok::r_paren) && + if (IsFunctionArgument(Left) && Style.AllowShortLambdasOnASingleLine == FormatStyle::SLS_Inline) return false; @@ -3667,11 +3724,21 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, if ((Left.is(TT_AttributeSquare) && Right.is(tok::l_square)) || (Left.is(tok::r_square) && Right.is(TT_AttributeSquare))) return false; + + auto ShortLambdaOption = Style.AllowShortLambdasOnASingleLine; + if (Style.BraceWrapping.BeforeLambdaBody) { + if (isAllmanLambdaBrace(Left)) + return !isItAnEmptyLambdaAllowed(Left, ShortLambdaOption); + if (isAllmanLambdaBrace(Right)) + return !isItAnEmptyLambdaAllowed(Right, ShortLambdaOption); + } + return Left.isOneOf(tok::comma, tok::coloncolon, tok::semi, tok::l_brace, tok::kw_class, tok::kw_struct, tok::comment) || Right.isMemberAccess() || Right.isOneOf(TT_TrailingReturnArrow, TT_LambdaArrow, tok::lessless, tok::colon, tok::l_square, tok::at) || + (Style.BraceWrapping.BeforeLambdaBody && Right.is(tok::l_brace)) || (Left.is(tok::r_paren) && Right.isOneOf(tok::identifier, tok::kw_const)) || (Left.is(tok::l_paren) && !Right.is(tok::r_paren)) || diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index ea064305091a0..f00c980cb7151 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -12673,6 +12673,7 @@ TEST_F(FormatTest, ParsesConfigurationBools) { CHECK_PARSE_NESTED_BOOL(BraceWrapping, AfterExternBlock); CHECK_PARSE_NESTED_BOOL(BraceWrapping, BeforeCatch); CHECK_PARSE_NESTED_BOOL(BraceWrapping, BeforeElse); + CHECK_PARSE_NESTED_BOOL(BraceWrapping, BeforeLambdaBody); CHECK_PARSE_NESTED_BOOL(BraceWrapping, IndentBraces); CHECK_PARSE_NESTED_BOOL(BraceWrapping, SplitEmptyFunction); CHECK_PARSE_NESTED_BOOL(BraceWrapping, SplitEmptyRecord); @@ -13962,6 +13963,245 @@ TEST_F(FormatTest, FormatsLambdas) { "function([]() { return b; }, a)", MergeInline); verifyFormat("function(a, []() { return b; })", "function(a, []() { return b; })", MergeInline); + + // Check option "BraceWrapping.BeforeLambdaBody" and different state of + // AllowShortLambdasOnASingleLine + FormatStyle LLVMWithBeforeLambdaBody = getLLVMStyle(); + LLVMWithBeforeLambdaBody.BreakBeforeBraces = FormatStyle::BS_Custom; + LLVMWithBeforeLambdaBody.BraceWrapping.BeforeLambdaBody = true; + LLVMWithBeforeLambdaBody.AllowShortLambdasOnASingleLine = + FormatStyle::ShortLambdaStyle::SLS_None; + verifyFormat("FctWithOneNestedLambdaInline_SLS_None(\n" + " []()\n" + " {\n" + " return 17;\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdaEmpty_SLS_None(\n" + " []()\n" + " {\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("auto fct_SLS_None = []()\n" + "{\n" + " return 17;\n" + "};", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_None(\n" + " []()\n" + " {\n" + " return Call(\n" + " []()\n" + " {\n" + " return 17;\n" + " });\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("void Fct()\n" + "{\n" + " return {[]()\n" + " {\n" + " return 17;\n" + " }};\n" + "}", + LLVMWithBeforeLambdaBody); + + LLVMWithBeforeLambdaBody.AllowShortLambdasOnASingleLine = + FormatStyle::ShortLambdaStyle::SLS_Empty; + verifyFormat("FctWithOneNestedLambdaInline_SLS_Empty(\n" + " []()\n" + " {\n" + " return 17;\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdaEmpty_SLS_Empty([]() {});", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdaEmptyInsideAVeryVeryVeryVeryVeryVeryVeryL" + "ongFunctionName_SLS_Empty(\n" + " []() {});", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithMultipleParams_SLS_Empty(A, B,\n" + " []()\n" + " {\n" + " return 17;\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("auto fct_SLS_Empty = []()\n" + "{\n" + " return 17;\n" + "};", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_Empty(\n" + " []()\n" + " {\n" + " return Call([]() {});\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_Empty(A,\n" + " []()\n" + " {\n" + " return Call([]() {});\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_Empty(\n" + " []()\n" + " {\n" + " return HereAVeryLongLine(ThatWillBeFormatted, OnMultipleLine,\n" + " AndShouldNotBeConsiderAsInline,\n" + " LambdaBodyMustBeBreak);\n" + " });", + LLVMWithBeforeLambdaBody); + + LLVMWithBeforeLambdaBody.AllowShortLambdasOnASingleLine = + FormatStyle::ShortLambdaStyle::SLS_Inline; + verifyFormat("FctWithOneNestedLambdaInline_SLS_Inline([]() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdaEmpty_SLS_Inline([]() {});", + LLVMWithBeforeLambdaBody); + verifyFormat("auto fct_SLS_Inline = []()\n" + "{\n" + " return 17;\n" + "};", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_Inline([]() { return Call([]() { return " + "17; }); });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_Inline(\n" + " []()\n" + " {\n" + " return HereAVeryLongLine(ThatWillBeFormatted, OnMultipleLine,\n" + " AndShouldNotBeConsiderAsInline,\n" + " LambdaBodyMustBeBreak);\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithMultipleParams_SLS_Inline(" + "VeryLongParameterThatShouldAskToBeOnMultiLine,\n" + " []() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithMultipleParams_SLS_Inline(FirstParam, []() { return 17; });", + LLVMWithBeforeLambdaBody); + + LLVMWithBeforeLambdaBody.AllowShortLambdasOnASingleLine = + FormatStyle::ShortLambdaStyle::SLS_All; + verifyFormat("FctWithOneNestedLambdaInline_SLS_All([]() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdaEmpty_SLS_All([]() {});", + LLVMWithBeforeLambdaBody); + verifyFormat("auto fct_SLS_All = []() { return 17; };", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneParam_SLS_All(\n" + " []()\n" + " {\n" + " // A cool function...\n" + " return 43;\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithMultipleParams_SLS_All(" + "VeryLongParameterThatShouldAskToBeOnMultiLine,\n" + " []() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithMultipleParams_SLS_All(A, []() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithMultipleParams_SLS_All(A, B, []() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_All(\n" + " []()\n" + " {\n" + " return HereAVeryLongLine(ThatWillBeFormatted, OnMultipleLine,\n" + " AndShouldNotBeConsiderAsInline,\n" + " LambdaBodyMustBeBreak);\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "auto fct_SLS_All = []()\n" + "{\n" + " return HereAVeryLongLine(ThatWillBeFormatted, OnMultipleLine,\n" + " AndShouldNotBeConsiderAsInline,\n" + " LambdaBodyMustBeBreak);\n" + "};", + LLVMWithBeforeLambdaBody); + LLVMWithBeforeLambdaBody.BinPackParameters = false; + verifyFormat("FctAllOnSameLine_SLS_All([]() { return S; }, Fst, Second);", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_All([]() { return SomeValueNotSoLong; },\n" + " FirstParam,\n" + " SecondParam,\n" + " ThirdParam,\n" + " FourthParam);", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithLongLineInLambda_SLS_All(\n" + " []() { return " + "SomeValueVeryVeryVeryVeryVeryVeryVeryVeryVeryLong; },\n" + " FirstParam,\n" + " SecondParam,\n" + " ThirdParam,\n" + " FourthParam);", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_All(FirstParam,\n" + " SecondParam,\n" + " ThirdParam,\n" + " FourthParam,\n" + " []() { return SomeValueNotSoLong; });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithLongLineInLambda_SLS_All(\n" + " []()\n" + " {\n" + " return " + "HereAVeryLongLineThatWillBeFormattedOnMultipleLineAndShouldNotB" + "eConsiderAsInline;\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "FctWithLongLineInLambda_SLS_All(\n" + " []()\n" + " {\n" + " return HereAVeryLongLine(ThatWillBeFormatted, OnMultipleLine,\n" + " AndShouldNotBeConsiderAsInline,\n" + " LambdaBodyMustBeBreak);\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithTwoParams_SLS_All(\n" + " []()\n" + " {\n" + " // A cool function...\n" + " return 43;\n" + " },\n" + " 87);", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithTwoParams_SLS_All([]() { return 43; }, 87);", + LLVMWithBeforeLambdaBody); + verifyFormat("FctWithOneNestedLambdas_SLS_All([]() { return 17; });", + LLVMWithBeforeLambdaBody); + verifyFormat( + "TwoNestedLambdas_SLS_All([]() { return Call([]() { return 17; }); });", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_All([]() { return Call([]() { return 17; " + "}); }, x);", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_All(\n" + " []()\n" + " {\n" + " // A cool function...\n" + " return Call([]() { return 17; });\n" + " });", + LLVMWithBeforeLambdaBody); + verifyFormat("TwoNestedLambdas_SLS_All(\n" + " []()\n" + " {\n" + " return Call(\n" + " []()\n" + " {\n" + " // A cool function...\n" + " return 17;\n" + " });\n" + " });", + LLVMWithBeforeLambdaBody); } TEST_F(FormatTest, EmptyLinesInLambdas) { From e252293d0629066225228596a9ef9d397513eb99 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Fri, 7 Feb 2020 15:01:34 -0800 Subject: [PATCH 13/57] [WebAssembly] Add cbrt function signatures Summary: Fixes a crash in the backend where optimizations produce calls to the cbrt runtime functions. Fixes PR 44227. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74259 --- .../WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp | 3 +++ llvm/test/CodeGen/WebAssembly/libcalls.ll | 6 ++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp index 1ad7720e9db9a..6456026f4ba74 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp @@ -178,6 +178,9 @@ struct RuntimeLibcallSignatureTable { Table[RTLIB::SQRT_F32] = f32_func_f32; Table[RTLIB::SQRT_F64] = f64_func_f64; Table[RTLIB::SQRT_F128] = func_iPTR_i64_i64; + Table[RTLIB::CBRT_F32] = f32_func_f32; + Table[RTLIB::CBRT_F64] = f64_func_f64; + Table[RTLIB::CBRT_F128] = func_iPTR_i64_i64; Table[RTLIB::LOG_F32] = f32_func_f32; Table[RTLIB::LOG_F64] = f64_func_f64; Table[RTLIB::LOG_F128] = func_iPTR_i64_i64; diff --git a/llvm/test/CodeGen/WebAssembly/libcalls.ll b/llvm/test/CodeGen/WebAssembly/libcalls.ll index 37929fe8cf64c..db1ab5c98884b 100644 --- a/llvm/test/CodeGen/WebAssembly/libcalls.ll +++ b/llvm/test/CodeGen/WebAssembly/libcalls.ll @@ -73,9 +73,11 @@ define i32 @f64libcalls(double %x, double %y, i32 %z) { %e = call double @llvm.log.f64(double %d) ; CHECK: f64.call $push{{[0-9]}}=, exp %f = call double @llvm.exp.f64(double %e) + ; CHECK: f64.call $push{{[0-9]}}=, cbrt + %g = call fast double @llvm.pow.f64(double %f, double 0x3FD5555555555555) ; CHECK: i32.call $push{{[0-9]}}=, lround - %g = call i32 @llvm.lround(double %f) - ret i32 %g + %h = call i32 @llvm.lround(double %g) + ret i32 %h } ; fcmp ord and unord (RTLIB::O_F32 / RTLIB::UO_F32 etc) are a special case (see From 0dce409cee17811c725749d651df89ad62dd38bb Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 13:10:49 -0800 Subject: [PATCH 14/57] [AsmPrinter] De-capitalize Emit{Function,BasicBlock]* and Emit{Start,End}OfAsmFile --- llvm/include/llvm/CodeGen/AsmPrinter.h | 22 +++++------ llvm/include/llvm/CodeGen/SelectionDAGISel.h | 2 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 28 +++++++------- .../SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 14 +++---- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 20 +++++----- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 12 +++--- llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 12 +++--- llvm/lib/Target/ARM/ARMAsmPrinter.h | 10 ++--- .../Target/Hexagon/HexagonISelDAGToDAG.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h | 2 +- llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp | 2 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 14 +++---- llvm/lib/Target/Mips/MipsAsmPrinter.h | 12 +++--- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 10 ++--- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h | 8 ++-- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 38 +++++++++---------- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 4 +- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZAsmPrinter.h | 2 +- .../WebAssembly/WebAssemblyAsmPrinter.cpp | 6 +-- .../WebAssembly/WebAssemblyAsmPrinter.h | 4 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 10 ++--- llvm/lib/Target/X86/X86AsmPrinter.h | 12 +++--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 +- llvm/lib/Target/XCore/XCoreAsmPrinter.cpp | 12 +++--- 27 files changed, 134 insertions(+), 134 deletions(-) diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 7d2034f88d36a..1df889f5722b5 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -319,7 +319,7 @@ class AsmPrinter : public MachineFunctionPass { /// Emit the specified function out to the OutStreamer. bool runOnMachineFunction(MachineFunction &MF) override { SetupMachineFunction(MF); - EmitFunctionBody(); + emitFunctionBody(); return false; } @@ -332,7 +332,7 @@ class AsmPrinter : public MachineFunctionPass { virtual void SetupMachineFunction(MachineFunction &MF); /// This method emits the body and trailer for a function. - void EmitFunctionBody(); + void emitFunctionBody(); void emitCFIInstruction(const MachineInstr &MI); @@ -406,28 +406,28 @@ class AsmPrinter : public MachineFunctionPass { /// This virtual method can be overridden by targets that want to emit /// something at the start of their file. - virtual void EmitStartOfAsmFile(Module &) {} + virtual void emitStartOfAsmFile(Module &) {} /// This virtual method can be overridden by targets that want to emit /// something at the end of their file. - virtual void EmitEndOfAsmFile(Module &) {} + virtual void emitEndOfAsmFile(Module &) {} /// Targets can override this to emit stuff before the first basic block in /// the function. - virtual void EmitFunctionBodyStart() {} + virtual void emitFunctionBodyStart() {} /// Targets can override this to emit stuff after the last basic block in the /// function. - virtual void EmitFunctionBodyEnd() {} + virtual void emitFunctionBodyEnd() {} /// Targets can override this to emit stuff at the start of a basic block. /// By default, this method prints the label for the specified /// MachineBasicBlock, an alignment (if present) and a comment describing it /// if appropriate. - virtual void EmitBasicBlockStart(const MachineBasicBlock &MBB); + virtual void emitBasicBlockStart(const MachineBasicBlock &MBB); /// Targets can override this to emit stuff at the end of a basic block. - virtual void EmitBasicBlockEnd(const MachineBasicBlock &MBB); + virtual void emitBasicBlockEnd(const MachineBasicBlock &MBB); /// Targets should implement this to emit instructions. virtual void EmitInstruction(const MachineInstr *) { @@ -437,9 +437,9 @@ class AsmPrinter : public MachineFunctionPass { /// Return the symbol for the specified constant pool entry. virtual MCSymbol *GetCPISymbol(unsigned CPID) const; - virtual void EmitFunctionEntryLabel(); + virtual void emitFunctionEntryLabel(); - virtual void EmitFunctionDescriptor() { + virtual void emitFunctionDescriptor() { llvm_unreachable("Function descriptor is target-specific."); } @@ -678,7 +678,7 @@ class AsmPrinter : public MachineFunctionPass { mutable unsigned Counter = ~0U; /// This method emits the header for the current function. - virtual void EmitFunctionHeader(); + virtual void emitFunctionHeader(); /// Emit a blob of inline asm to the output streamer. void diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h index 9874d782c7824..52c3e0c6148af 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h @@ -78,7 +78,7 @@ class SelectionDAGISel : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; - virtual void EmitFunctionEntryCode() {} + virtual void emitFunctionEntryCode() {} /// PreprocessISelDAG - This hook allows targets to hack on the graph before /// instruction selection starts. diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index ec0eb497bfa86..f81a291846546 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -280,7 +280,7 @@ bool AsmPrinter::doInitialization(Module &M) { OutStreamer->EmitVersionForTarget(Target, M.getSDKVersion()); // Allow the target to emit any magic that it wants at the start of the file. - EmitStartOfAsmFile(M); + emitStartOfAsmFile(M); // Very minimal debug info. It is ignored if we emit actual debug info. If we // don't, this at least helps the user find where a global came from. @@ -670,7 +670,7 @@ void AsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { /// EmitFunctionHeader - This method emits the header for the current /// function. -void AsmPrinter::EmitFunctionHeader() { +void AsmPrinter::emitFunctionHeader() { const Function &F = MF->getFunction(); if (isVerbose()) @@ -750,11 +750,11 @@ void AsmPrinter::EmitFunctionHeader() { // the AIX target. The PowerPC 64-bit V1 ELF target also uses function // descriptors and should be converted to use this hook as well. if (MAI->needsFunctionDescriptors()) - EmitFunctionDescriptor(); + emitFunctionDescriptor(); // Emit the CurrentFnSym. This is a virtual function to allow targets to do // their wild and crazy things as required. - EmitFunctionEntryLabel(); + emitFunctionEntryLabel(); if (CurrentFnBegin) { if (MAI->useAssignmentForEHBegin()) { @@ -781,7 +781,7 @@ void AsmPrinter::EmitFunctionHeader() { /// EmitFunctionEntryLabel - Emit the label that is the entrypoint for the /// function. This can be overridden by targets as required to do custom stuff. -void AsmPrinter::EmitFunctionEntryLabel() { +void AsmPrinter::emitFunctionEntryLabel() { CurrentFnSym->redefineIfPossible(); // The function label could have already been emitted if two symbols end up @@ -1066,11 +1066,11 @@ static bool needFuncLabelsForEHOrDebugInfo(const MachineFunction &MF, /// EmitFunctionBody - This method emits the body and trailer for a /// function. -void AsmPrinter::EmitFunctionBody() { - EmitFunctionHeader(); +void AsmPrinter::emitFunctionBody() { + emitFunctionHeader(); // Emit target-specific gunk before the function body. - EmitFunctionBodyStart(); + emitFunctionBodyStart(); bool ShouldPrintDebugScopes = MMI->hasDebugInfo(); @@ -1097,7 +1097,7 @@ void AsmPrinter::EmitFunctionBody() { int NumInstsInFunction = 0; for (auto &MBB : *MF) { // Print a label for the basic block. - EmitBasicBlockStart(MBB); + emitBasicBlockStart(MBB); for (auto &MI : MBB) { // Print the assembly for the instruction. if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() && @@ -1175,7 +1175,7 @@ void AsmPrinter::EmitFunctionBody() { } } - EmitBasicBlockEnd(MBB); + emitBasicBlockEnd(MBB); } EmittedInsts += NumInstsInFunction; @@ -1220,7 +1220,7 @@ void AsmPrinter::EmitFunctionBody() { } // Emit target-specific gunk after the function body. - EmitFunctionBodyEnd(); + emitFunctionBodyEnd(); if (needFuncLabelsForEHOrDebugInfo(*MF, MMI) || MAI->hasDotTypeDotSizeDirective()) { @@ -1682,7 +1682,7 @@ bool AsmPrinter::doFinalization(Module &M) { // Allow the target to emit any magic that it wants at the end of the file, // after everything else has gone out. - EmitEndOfAsmFile(M); + emitEndOfAsmFile(M); MMI = nullptr; @@ -2981,7 +2981,7 @@ static void emitBasicBlockLoopComments(const MachineBasicBlock &MBB, /// EmitBasicBlockStart - This method prints the label for the specified /// MachineBasicBlock, an alignment (if present) and a comment describing /// it if appropriate. -void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) { +void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { // End the previous funclet and start a new one. if (MBB.isEHFuncletEntry()) { for (const HandlerInfo &HI : Handlers) { @@ -3041,7 +3041,7 @@ void AsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) { } } -void AsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) {} +void AsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) {} void AsmPrinter::EmitVisibility(MCSymbol *Sym, unsigned Visibility, bool IsDefinition) const { diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 0da07b60fe5e7..dab8637515668 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -9982,7 +9982,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) { } // Finally, if the target has anything special to do, allow it to do so. - EmitFunctionEntryCode(); + emitFunctionEntryCode(); } /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index 6da089d1859a3..3a2a912180ccb 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -84,7 +84,7 @@ class AArch64AsmPrinter : public AsmPrinter { return MCInstLowering.lowerOperand(MO, MCOp); } - void EmitStartOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; void EmitJumpTableInfo() override; void emitJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned JTI); @@ -139,7 +139,7 @@ class AArch64AsmPrinter : public AsmPrinter { } // Emit the rest of the function body. - EmitFunctionBody(); + emitFunctionBody(); // Emit the XRay table for this function. emitXRayTable(); @@ -162,10 +162,10 @@ class AArch64AsmPrinter : public AsmPrinter { void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); - void EmitFunctionBodyEnd() override; + void emitFunctionBodyEnd() override; MCSymbol *GetCPISymbol(unsigned CPID) const override; - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; AArch64FunctionInfo *AArch64FI = nullptr; @@ -182,7 +182,7 @@ class AArch64AsmPrinter : public AsmPrinter { } // end anonymous namespace -void AArch64AsmPrinter::EmitStartOfAsmFile(Module &M) { +void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) { if (!TM.getTargetTriple().isOSBinFormatELF()) return; @@ -518,7 +518,7 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { } } -void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) { +void AArch64AsmPrinter::emitEndOfAsmFile(Module &M) { EmitHwasanMemaccessSymbols(M); const Triple &TT = TM.getTargetTriple(); @@ -548,7 +548,7 @@ void AArch64AsmPrinter::EmitLOHs() { } } -void AArch64AsmPrinter::EmitFunctionBodyEnd() { +void AArch64AsmPrinter::emitFunctionBodyEnd() { if (!AArch64FI->getLOHRelated().empty()) EmitLOHs(); } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 7eb8fb8f5d13b..7669bce410996 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -112,7 +112,7 @@ AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const { return static_cast(OutStreamer->getTargetStreamer()); } -void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) { +void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) { if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) { std::string ExpectedTarget; raw_string_ostream ExpectedTargetOS(ExpectedTarget); @@ -144,7 +144,7 @@ void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) { Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU"); } -void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) { +void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) { // Following code requires TargetStreamer to be present. if (!getTargetStreamer()) return; @@ -180,7 +180,7 @@ bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough( return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64); } -void AMDGPUAsmPrinter::EmitFunctionBodyStart() { +void AMDGPUAsmPrinter::emitFunctionBodyStart() { const SIMachineFunctionInfo &MFI = *MF->getInfo(); if (!MFI.isEntryFunction()) return; @@ -199,7 +199,7 @@ void AMDGPUAsmPrinter::EmitFunctionBodyStart() { HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo); } -void AMDGPUAsmPrinter::EmitFunctionBodyEnd() { +void AMDGPUAsmPrinter::emitFunctionBodyEnd() { const SIMachineFunctionInfo &MFI = *MF->getInfo(); if (!MFI.isEntryFunction()) return; @@ -239,10 +239,10 @@ void AMDGPUAsmPrinter::EmitFunctionBodyEnd() { Streamer.PopSection(); } -void AMDGPUAsmPrinter::EmitFunctionEntryLabel() { +void AMDGPUAsmPrinter::emitFunctionEntryLabel() { if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) && TM.getTargetTriple().getOS() == Triple::AMDHSA) { - AsmPrinter::EmitFunctionEntryLabel(); + AsmPrinter::emitFunctionEntryLabel(); return; } @@ -261,10 +261,10 @@ void AMDGPUAsmPrinter::EmitFunctionEntryLabel() { HexLines.push_back(""); } - AsmPrinter::EmitFunctionEntryLabel(); + AsmPrinter::emitFunctionEntryLabel(); } -void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) { +void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) { // Write a line for the basic block label if it is not only fallthrough. DisasmLines.push_back( @@ -273,7 +273,7 @@ void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) { DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size()); HexLines.push_back(""); } - AsmPrinter::EmitBasicBlockStart(MBB); + AsmPrinter::emitBasicBlockStart(MBB); } void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { @@ -460,7 +460,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) { HexLines.clear(); DisasmLineMaxLen = 0; - EmitFunctionBody(); + emitFunctionBody(); if (isVerbose()) { MCSectionELF *CommentSection = diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index c50c19a4609c6..08725399b1a69 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -123,19 +123,19 @@ class AMDGPUAsmPrinter final : public AsmPrinter { /// Implemented in AMDGPUMCInstLower.cpp void EmitInstruction(const MachineInstr *MI) override; - void EmitFunctionBodyStart() override; + void emitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitFunctionBodyEnd() override; - void EmitFunctionEntryLabel() override; + void emitFunctionEntryLabel() override; - void EmitBasicBlockStart(const MachineBasicBlock &MBB) override; + void emitBasicBlockStart(const MachineBasicBlock &MBB) override; void EmitGlobalVariable(const GlobalVariable *GV) override; - void EmitStartOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; bool isBlockOnlyReachableByFallthrough( const MachineBasicBlock *MBB) const override; diff --git a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp index ed23c8ea814b4..1342f0fd6678e 100644 --- a/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp @@ -115,7 +115,7 @@ bool R600AsmPrinter::runOnMachineFunction(MachineFunction &MF) { EmitProgramInfoR600(MF); - EmitFunctionBody(); + emitFunctionBody(); if (isVerbose()) { MCSectionELF *CommentSection = diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 14d40188f1d6c..dd0db72c7c77c 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -57,7 +57,7 @@ ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM, : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), AFI(nullptr), MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {} -void ARMAsmPrinter::EmitFunctionBodyEnd() { +void ARMAsmPrinter::emitFunctionBodyEnd() { // Make sure to terminate any constant pools that were at the end // of the function. if (!InConstantPool) @@ -66,7 +66,7 @@ void ARMAsmPrinter::EmitFunctionBodyEnd() { OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); } -void ARMAsmPrinter::EmitFunctionEntryLabel() { +void ARMAsmPrinter::emitFunctionEntryLabel() { if (AFI->isThumbFunction()) { OutStreamer->EmitAssemblerFlag(MCAF_Code16); OutStreamer->EmitThumbFunc(CurrentFnSym); @@ -158,7 +158,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { } // Emit the rest of the function body. - EmitFunctionBody(); + emitFunctionBody(); // Emit the XRay table for this function. emitXRayTable(); @@ -471,7 +471,7 @@ void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, } } -void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { +void ARMAsmPrinter::emitStartOfAsmFile(Module &M) { const Triple &TT = TM.getTargetTriple(); // Use unified assembler syntax. OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified); @@ -511,7 +511,7 @@ emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, } -void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { +void ARMAsmPrinter::emitEndOfAsmFile(Module &M) { const Triple &TT = TM.getTargetTriple(); if (TT.isOSBinFormatMachO()) { // All darwin targets use mach-o. @@ -570,7 +570,7 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { } //===----------------------------------------------------------------------===// -// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile() +// Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile() // FIXME: // The following seem like one-off assembler flags, but they actually need // to appear in the .ARM.attributes section in ELF. diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h index a4b37fa2331f6..22016dedf2f20 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.h +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h @@ -93,10 +93,10 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { void EmitConstantPool() override { // we emit constant pools customly! } - void EmitFunctionBodyEnd() override; - void EmitFunctionEntryLabel() override; - void EmitStartOfAsmFile(Module &M) override; - void EmitEndOfAsmFile(Module &M) override; + void emitFunctionBodyEnd() override; + void emitFunctionEntryLabel() override; + void emitStartOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void EmitXXStructor(const DataLayout &DL, const Constant *CV) override; void EmitGlobalVariable(const GlobalVariable *GV) override; @@ -117,7 +117,7 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { private: void EmitSled(const MachineInstr &MI, SledKind Kind); - // Helpers for EmitStartOfAsmFile() and EmitEndOfAsmFile() + // Helpers for emitStartOfAsmFile() and emitEndOfAsmFile() void emitAttributes(); // Generic helper used to emit e.g. ARMv5 mul pseudos diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 8632250fa7f56..e220a0765e2d5 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1275,7 +1275,7 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { } } -void HexagonDAGToDAGISel::EmitFunctionEntryCode() { +void HexagonDAGToDAGISel::emitFunctionEntryCode() { auto &HST = MF->getSubtarget(); auto &HFI = *HST.getFrameLowering(); if (!HFI.needsAligna(*MF)) diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h index 6c77d88033593..7b5e7634ebf62 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -51,7 +51,7 @@ class HexagonDAGToDAGISel : public SelectionDAGISel { return true; } void PreprocessISelDAG() override; - void EmitFunctionEntryCode() override; + void emitFunctionEntryCode() override; void Select(SDNode *N) override; diff --git a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp index 2f871b959a710..964e11d3d7ad7 100644 --- a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -180,7 +180,7 @@ bool MSP430AsmPrinter::runOnMachineFunction(MachineFunction &MF) { } SetupMachineFunction(MF); - EmitFunctionBody(); + emitFunctionBody(); return false; } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 8f75336dce5a4..4a05f4031cec3 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -398,7 +398,7 @@ const char *MipsAsmPrinter::getCurrentABIString() const { } } -void MipsAsmPrinter::EmitFunctionEntryLabel() { +void MipsAsmPrinter::emitFunctionEntryLabel() { MipsTargetStreamer &TS = getTargetStreamer(); // NaCl sandboxing requires that indirect call instructions are masked. @@ -424,7 +424,7 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() { /// EmitFunctionBodyStart - Targets can override this to emit stuff before /// the first basic block in the function. -void MipsAsmPrinter::EmitFunctionBodyStart() { +void MipsAsmPrinter::emitFunctionBodyStart() { MipsTargetStreamer &TS = getTargetStreamer(); MCInstLowering.Initialize(&MF->getContext()); @@ -445,7 +445,7 @@ void MipsAsmPrinter::EmitFunctionBodyStart() { /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. -void MipsAsmPrinter::EmitFunctionBodyEnd() { +void MipsAsmPrinter::emitFunctionBodyEnd() { MipsTargetStreamer &TS = getTargetStreamer(); // There are instruction for this macros, but they must @@ -465,8 +465,8 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() { OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); } -void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) { - AsmPrinter::EmitBasicBlockEnd(MBB); +void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) { + AsmPrinter::emitBasicBlockEnd(MBB); MipsTargetStreamer &TS = getTargetStreamer(); if (MBB.empty()) TS.emitDirectiveInsn(); @@ -770,7 +770,7 @@ printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { } } -void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { +void MipsAsmPrinter::emitStartOfAsmFile(Module &M) { MipsTargetStreamer &TS = getTargetStreamer(); // MipsTargetStreamer has an initialization order problem when emitting an @@ -1122,7 +1122,7 @@ void MipsAsmPrinter::EmitFPCallStub( OutStreamer->PopSection(); } -void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) { +void MipsAsmPrinter::emitEndOfAsmFile(Module &M) { // Emit needed stubs // for (std::map< diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index 173a1312812e3..7df0fe15e96f4 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -138,10 +138,10 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { void printSavedRegsBitmask(); void emitFrameDirective(); const char *getCurrentABIString() const; - void EmitFunctionEntryLabel() override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; - void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override; + void emitFunctionEntryLabel() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; + void emitBasicBlockEnd(const MachineBasicBlock &MBB) override; bool isBlockOnlyReachableByFallthrough( const MachineBasicBlock* MBB) const override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, @@ -154,8 +154,8 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = nullptr); void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O); - void EmitStartOfAsmFile(Module &M) override; - void EmitEndOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; }; diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 4bb3ef81420cb..6d8c40914db71 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -434,13 +434,13 @@ bool NVPTXAsmPrinter::isLoopHeaderOfNoUnroll( return false; } -void NVPTXAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) { - AsmPrinter::EmitBasicBlockStart(MBB); +void NVPTXAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { + AsmPrinter::emitBasicBlockStart(MBB); if (isLoopHeaderOfNoUnroll(MBB)) OutStreamer->EmitRawText(StringRef("\t.pragma \"nounroll\";\n")); } -void NVPTXAsmPrinter::EmitFunctionEntryLabel() { +void NVPTXAsmPrinter::emitFunctionEntryLabel() { SmallString<128> Str; raw_svector_ostream O(Str); @@ -489,14 +489,14 @@ bool NVPTXAsmPrinter::runOnMachineFunction(MachineFunction &F) { return Result; } -void NVPTXAsmPrinter::EmitFunctionBodyStart() { +void NVPTXAsmPrinter::emitFunctionBodyStart() { SmallString<128> Str; raw_svector_ostream O(Str); emitDemotedVars(&MF->getFunction(), O); OutStreamer->EmitRawText(O.str()); } -void NVPTXAsmPrinter::EmitFunctionBodyEnd() { +void NVPTXAsmPrinter::emitFunctionBodyEnd() { VRegMapping.clear(); } diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h index 7a66854d32f4b..9f675a00c2d09 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h @@ -200,10 +200,10 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter { const Function *F; std::string CurrentFnName; - void EmitBasicBlockStart(const MachineBasicBlock &MBB) override; - void EmitFunctionEntryLabel() override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitBasicBlockStart(const MachineBasicBlock &MBB) override; + void emitFunctionEntryLabel() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; void emitImplicitDef(const MachineInstr *MI) const override; void EmitInstruction(const MachineInstr *) override; diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 2348df2801a37..aad74b884f9b4 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -113,7 +113,7 @@ class PPCAsmPrinter : public AsmPrinter { bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void LowerSTACKMAP(StackMaps &SM, const MachineInstr &MI); void LowerPATCHPOINT(StackMaps &SM, const MachineInstr &MI); @@ -138,12 +138,12 @@ class PPCLinuxAsmPrinter : public PPCAsmPrinter { } bool doFinalization(Module &M) override; - void EmitStartOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; - void EmitFunctionEntryLabel() override; + void emitFunctionEntryLabel() override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; void EmitInstruction(const MachineInstr *MI) override; }; @@ -165,9 +165,9 @@ class PPCAIXAsmPrinter : public PPCAsmPrinter { void EmitGlobalVariable(const GlobalVariable *GV) override; - void EmitFunctionDescriptor() override; + void emitFunctionDescriptor() override; - void EmitEndOfAsmFile(Module &) override; + void emitEndOfAsmFile(Module &) override; }; } // end anonymous namespace @@ -317,7 +317,7 @@ MCSymbol *PPCAsmPrinter::lookUpOrCreateTOCEntry(const MCSymbol *Sym) { return TOCEntry; } -void PPCAsmPrinter::EmitEndOfAsmFile(Module &M) { +void PPCAsmPrinter::emitEndOfAsmFile(Module &M) { emitStackMaps(SM); } @@ -1287,7 +1287,7 @@ void PPCLinuxAsmPrinter::EmitInstruction(const MachineInstr *MI) { } } -void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) { +void PPCLinuxAsmPrinter::emitStartOfAsmFile(Module &M) { if (static_cast(TM).isELFv2ABI()) { PPCTargetStreamer *TS = static_cast(OutStreamer->getTargetStreamer()); @@ -1298,10 +1298,10 @@ void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) { if (static_cast(TM).isPPC64() || !isPositionIndependent()) - return AsmPrinter::EmitStartOfAsmFile(M); + return AsmPrinter::emitStartOfAsmFile(M); if (M.getPICLevel() == PICLevel::SmallPIC) - return AsmPrinter::EmitStartOfAsmFile(M); + return AsmPrinter::emitStartOfAsmFile(M); OutStreamer->SwitchSection(OutContext.getELFSection( ".got2", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC)); @@ -1323,12 +1323,12 @@ void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module &M) { OutStreamer->SwitchSection(getObjFileLowering().getTextSection()); } -void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { +void PPCLinuxAsmPrinter::emitFunctionEntryLabel() { // linux/ppc32 - Normal entry label. if (!Subtarget->isPPC64() && (!isPositionIndependent() || MF->getFunction().getParent()->getPICLevel() == PICLevel::SmallPIC)) - return AsmPrinter::EmitFunctionEntryLabel(); + return AsmPrinter::emitFunctionEntryLabel(); if (!Subtarget->isPPC64()) { const PPCFunctionInfo *PPCFI = MF->getInfo(); @@ -1347,7 +1347,7 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { OutStreamer->EmitLabel(CurrentFnSym); return; } else - return AsmPrinter::EmitFunctionEntryLabel(); + return AsmPrinter::emitFunctionEntryLabel(); } // ELFv2 ABI - Normal entry label. @@ -1371,7 +1371,7 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { OutStreamer->EmitLabel(PPCFI->getTOCOffsetSymbol()); OutStreamer->EmitValue(TOCDeltaExpr, 8); } - return AsmPrinter::EmitFunctionEntryLabel(); + return AsmPrinter::emitFunctionEntryLabel(); } // Emit an official procedure descriptor. @@ -1433,7 +1433,7 @@ bool PPCLinuxAsmPrinter::doFinalization(Module &M) { } /// EmitFunctionBodyStart - Emit a global entry point prefix for ELFv2. -void PPCLinuxAsmPrinter::EmitFunctionBodyStart() { +void PPCLinuxAsmPrinter::emitFunctionBodyStart() { // In the ELFv2 ABI, in functions that use the TOC register, we need to // provide two entry points. The ABI guarantees that when calling the // local entry point, r2 is set up by the caller to contain the TOC base @@ -1530,7 +1530,7 @@ void PPCLinuxAsmPrinter::EmitFunctionBodyStart() { /// EmitFunctionBodyEnd - Print the traceback table before the .size /// directive. /// -void PPCLinuxAsmPrinter::EmitFunctionBodyEnd() { +void PPCLinuxAsmPrinter::emitFunctionBodyEnd() { // Only the 64-bit target requires a traceback table. For now, // we only emit the word of zeroes that GDB requires to find // the end of the function, and zeroes for the eight-byte @@ -1637,7 +1637,7 @@ void PPCAIXAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { EmitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); } -void PPCAIXAsmPrinter::EmitFunctionDescriptor() { +void PPCAIXAsmPrinter::emitFunctionDescriptor() { const DataLayout &DL = getDataLayout(); const unsigned PointerSize = DL.getPointerSizeInBits() == 64 ? 8 : 4; @@ -1661,7 +1661,7 @@ void PPCAIXAsmPrinter::EmitFunctionDescriptor() { OutStreamer->SwitchSection(Current.first, Current.second); } -void PPCAIXAsmPrinter::EmitEndOfAsmFile(Module &M) { +void PPCAIXAsmPrinter::emitEndOfAsmFile(Module &M) { // If there are no functions in this module, we will never need to reference // the TOC base. if (M.empty()) diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index f0caf3bc284fa..f85595d338265 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -52,7 +52,7 @@ namespace { void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = nullptr); - void EmitFunctionBodyStart() override; + void emitFunctionBodyStart() override; void EmitInstruction(const MachineInstr *MI) override; static const char *getRegisterName(unsigned RegNo) { @@ -270,7 +270,7 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) } while ((++I != E) && I->isInsideBundle()); // Delay slot check. } -void SparcAsmPrinter::EmitFunctionBodyStart() { +void SparcAsmPrinter::emitFunctionBodyStart() { if (!MF->getSubtarget().is64Bit()) return; diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 67c4aa08f90da..b80dd058cf8ae 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -719,7 +719,7 @@ bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void SystemZAsmPrinter::EmitEndOfAsmFile(Module &M) { +void SystemZAsmPrinter::emitEndOfAsmFile(Module &M) { emitStackMaps(SM); } diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h index d01a17c2ebe25..b9867fb900bd0 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h @@ -34,7 +34,7 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter { StringRef getPassName() const override { return "SystemZ Assembly Printer"; } void EmitInstruction(const MachineInstr *MI) override; void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index adcb24b4be534..0442a48328aea 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -85,7 +85,7 @@ WebAssemblyTargetStreamer *WebAssemblyAsmPrinter::getTargetStreamer() { // WebAssemblyAsmPrinter Implementation. //===----------------------------------------------------------------------===// -void WebAssemblyAsmPrinter::EmitEndOfAsmFile(Module &M) { +void WebAssemblyAsmPrinter::emitEndOfAsmFile(Module &M) { for (auto &It : OutContext.getSymbols()) { // Emit a .globaltype and .eventtype declaration. auto Sym = cast(It.getValue()); @@ -286,7 +286,7 @@ void WebAssemblyAsmPrinter::EmitJumpTableInfo() { // Nothing to do; jump tables are incorporated into the instruction stream. } -void WebAssemblyAsmPrinter::EmitFunctionBodyStart() { +void WebAssemblyAsmPrinter::emitFunctionBodyStart() { const Function &F = MF->getFunction(); SmallVector ResultVTs; SmallVector ParamVTs; @@ -312,7 +312,7 @@ void WebAssemblyAsmPrinter::EmitFunctionBodyStart() { valTypesFromMVTs(MFI->getLocals(), Locals); getTargetStreamer()->emitLocal(Locals); - AsmPrinter::EmitFunctionBodyStart(); + AsmPrinter::emitFunctionBodyStart(); } void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h index 4e55c81dec38a..9ec19ed52bd6e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h @@ -57,12 +57,12 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyAsmPrinter final : public AsmPrinter { // AsmPrinter Implementation. //===------------------------------------------------------------------===// - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void EmitProducerInfo(Module &M); void EmitTargetFeatures(Module &M); void EmitJumpTableInfo() override; void EmitConstantPool() override; - void EmitFunctionBodyStart() override; + void emitFunctionBodyStart() override; void EmitInstruction(const MachineInstr *MI) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp b/llvm/lib/Target/X86/X86AsmPrinter.cpp index 39d16e7999cdb..f2e7ceb9463b4 100644 --- a/llvm/lib/Target/X86/X86AsmPrinter.cpp +++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp @@ -76,7 +76,7 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { } // Emit the rest of the function body. - EmitFunctionBody(); + emitFunctionBody(); // Emit the XRay table for this function. emitXRayTable(); @@ -87,7 +87,7 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { return false; } -void X86AsmPrinter::EmitFunctionBodyStart() { +void X86AsmPrinter::emitFunctionBodyStart() { if (EmitFPOData) { if (auto *XTS = static_cast(OutStreamer->getTargetStreamer())) @@ -97,7 +97,7 @@ void X86AsmPrinter::EmitFunctionBodyStart() { } } -void X86AsmPrinter::EmitFunctionBodyEnd() { +void X86AsmPrinter::emitFunctionBodyEnd() { if (EmitFPOData) { if (auto *XTS = static_cast(OutStreamer->getTargetStreamer())) @@ -575,7 +575,7 @@ bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, return false; } -void X86AsmPrinter::EmitStartOfAsmFile(Module &M) { +void X86AsmPrinter::emitStartOfAsmFile(Module &M) { const Triple &TT = TM.getTargetTriple(); if (TT.isOSBinFormatELF()) { @@ -698,7 +698,7 @@ static void emitNonLazyStubs(MachineModuleInfo *MMI, MCStreamer &OutStreamer) { } } -void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { +void X86AsmPrinter::emitEndOfAsmFile(Module &M) { const Triple &TT = TM.getTargetTriple(); if (TT.isOSBinFormatMachO()) { diff --git a/llvm/lib/Target/X86/X86AsmPrinter.h b/llvm/lib/Target/X86/X86AsmPrinter.h index ee79401dc80d5..29ea0c052bb20 100644 --- a/llvm/lib/Target/X86/X86AsmPrinter.h +++ b/llvm/lib/Target/X86/X86AsmPrinter.h @@ -123,14 +123,14 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter { const X86Subtarget &getSubtarget() const { return *Subtarget; } - void EmitStartOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; - void EmitEndOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void EmitInstruction(const MachineInstr *MI) override; - void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override { - AsmPrinter::EmitBasicBlockEnd(MBB); + void emitBasicBlockEnd(const MachineBasicBlock &MBB) override { + AsmPrinter::emitBasicBlockEnd(MBB); SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); } @@ -147,8 +147,8 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter { } bool runOnMachineFunction(MachineFunction &F) override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; }; } // end namespace llvm diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index e0228284795f5..2ba86738ee3df 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -196,7 +196,7 @@ namespace { return true; } - void EmitFunctionEntryCode() override; + void emitFunctionEntryCode() override; bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override; @@ -1390,7 +1390,7 @@ void X86DAGToDAGISel::emitSpecialCodeForMain() { } } -void X86DAGToDAGISel::EmitFunctionEntryCode() { +void X86DAGToDAGISel::emitFunctionEntryCode() { // If this is main, emit special code for main. const Function &F = MF->getFunction(); if (F.hasExternalLinkage() && F.getName() == "main") diff --git a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index 35dc56e904195..4b5de9ff313ae 100644 --- a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -74,10 +74,10 @@ namespace { void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV); void EmitGlobalVariable(const GlobalVariable *GV) override; - void EmitFunctionEntryLabel() override; + void emitFunctionEntryLabel() override; void EmitInstruction(const MachineInstr *MI) override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; }; } // end of anonymous namespace @@ -165,18 +165,18 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { getTargetStreamer().emitCCBottomData(GVSym->getName()); } -void XCoreAsmPrinter::EmitFunctionBodyStart() { +void XCoreAsmPrinter::emitFunctionBodyStart() { MCInstLowering.Initialize(&MF->getContext()); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. -void XCoreAsmPrinter::EmitFunctionBodyEnd() { +void XCoreAsmPrinter::emitFunctionBodyEnd() { // Emit function end directives getTargetStreamer().emitCCBottomFunction(CurrentFnSym->getName()); } -void XCoreAsmPrinter::EmitFunctionEntryLabel() { +void XCoreAsmPrinter::emitFunctionEntryLabel() { // Mark the start of the function getTargetStreamer().emitCCTopFunction(CurrentFnSym->getName()); OutStreamer->EmitLabel(CurrentFnSym); From c2e8a421ac52c5a17962a99db472be1d0bfdc296 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 13 Feb 2020 11:10:57 -0800 Subject: [PATCH 15/57] [X86] Don't widen 128/256-bit strict compares with vXi1 result to 512-bits on KNL. If we widen the compare we might trigger a spurious exception from the garbage data. We have two choices here. Explicitly force the upper bits to zero. Or use a legacy VEX vcmpps/pd instruction and convert the XMM/YMM result to mask register. I've chosen to go with the second option. I'm not sure which is really best. In some cases we could get rid of the zeroing since the producing instruction probably already zeroed it. But we lose the ability to fold a load. So which is best is dependent on surrounding code. Differential Revision: https://reviews.llvm.org/D74522 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 25 +- llvm/lib/Target/X86/X86InstrAVX512.td | 12 +- llvm/test/CodeGen/X86/vec-strict-cmp-128.ll | 544 ++++++++------------ llvm/test/CodeGen/X86/vec-strict-cmp-256.ll | 544 ++++++++------------ 4 files changed, 474 insertions(+), 651 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1b00d961d2067..5992436e16356 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21645,8 +21645,14 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, bool IsSignaling = Op.getOpcode() == ISD::STRICT_FSETCCS; SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue(); + // If we have a strict compare with a vXi1 result and the input is 128/256 + // bits we can't use a masked compare unless we have VLX. If we use a wider + // compare like we do for non-strict, we might trigger spurious exceptions + // from the upper elements. Instead emit a AVX compare and convert to mask. unsigned Opc; - if (Subtarget.hasAVX512() && VT.getVectorElementType() == MVT::i1) { + if (Subtarget.hasAVX512() && VT.getVectorElementType() == MVT::i1 && + (!IsStrict || Subtarget.hasVLX() || + Op0.getSimpleValueType().is512BitVector())) { assert(VT.getVectorNumElements() <= 16); Opc = IsStrict ? X86ISD::STRICT_CMPM : X86ISD::CMPM; } else { @@ -21742,10 +21748,19 @@ static SDValue LowerVSETCC(SDValue Op, const X86Subtarget &Subtarget, Opc, dl, VT, Op0, Op1, DAG.getTargetConstant(SSECC, dl, MVT::i8)); } - // If this is SSE/AVX CMPP, bitcast the result back to integer to match the - // result type of SETCC. The bitcast is expected to be optimized away - // during combining/isel. - Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp); + if (VT.getSizeInBits() > Op.getSimpleValueType().getSizeInBits()) { + // We emitted a compare with an XMM/YMM result. Finish converting to a + // mask register using a vptestm. + EVT CastVT = EVT(VT).changeVectorElementTypeToInteger(); + Cmp = DAG.getBitcast(CastVT, Cmp); + Cmp = DAG.getSetCC(dl, Op.getSimpleValueType(), Cmp, + DAG.getConstant(0, dl, CastVT), ISD::SETNE); + } else { + // If this is SSE/AVX CMPP, bitcast the result back to integer to match + // the result type of SETCC. The bitcast is expected to be optimized + // away during combining/isel. + Cmp = DAG.getBitcast(Op.getSimpleValueType(), Cmp); + } if (IsStrict) return DAG.getMergeValues({Cmp, Chain}, dl); diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 53a9294c9fef4..1cc7f645ef5f3 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3232,8 +3232,8 @@ def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, multiclass axv512_cmp_packed_cc_no_vlx_lowering { -def : Pat<(Narrow.KVT (X86any_cmpm (Narrow.VT Narrow.RC:$src1), - (Narrow.VT Narrow.RC:$src2), timm:$cc)), +def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1), + (Narrow.VT Narrow.RC:$src2), timm:$cc)), (COPY_TO_REGCLASS (!cast(InstStr#"Zrri") (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), @@ -3250,8 +3250,8 @@ def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, timm:$cc), Narrow.KRC)>; // Broadcast load. -def : Pat<(Narrow.KVT (X86any_cmpm (Narrow.VT Narrow.RC:$src1), - (Narrow.VT (Narrow.BroadcastLdFrag addr:$src2)), timm:$cc)), +def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT Narrow.RC:$src1), + (Narrow.VT (Narrow.BroadcastLdFrag addr:$src2)), timm:$cc)), (COPY_TO_REGCLASS (!cast(InstStr#"Zrmbi") (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), @@ -3266,8 +3266,8 @@ def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, addr:$src2, timm:$cc), Narrow.KRC)>; // Commuted with broadcast load. -def : Pat<(Narrow.KVT (X86any_cmpm (Narrow.VT (Narrow.BroadcastLdFrag addr:$src2)), - (Narrow.VT Narrow.RC:$src1), timm:$cc)), +def : Pat<(Narrow.KVT (X86cmpm (Narrow.VT (Narrow.BroadcastLdFrag addr:$src2)), + (Narrow.VT Narrow.RC:$src1), timm:$cc)), (COPY_TO_REGCLASS (!cast(InstStr#"Zrmbi") (Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)), diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-128.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-128.ll index 7e11f26256030..72d9035e67385 100644 --- a/llvm/test/CodeGen/X86/vec-strict-cmp-128.ll +++ b/llvm/test/CodeGen/X86/vec-strict-cmp-128.ll @@ -73,11 +73,10 @@ define <4 x i32> @test_v4f32_oeq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -87,11 +86,10 @@ define <4 x i32> @test_v4f32_oeq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_oeq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -228,11 +226,11 @@ define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplt_oqps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -242,11 +240,10 @@ define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ogt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplt_oqps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -383,11 +380,11 @@ define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmple_oqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmple_oqps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -397,11 +394,10 @@ define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_oge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmple_oqps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -537,11 +533,10 @@ define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplt_oqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -551,11 +546,10 @@ define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_olt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplt_oqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -691,11 +685,10 @@ define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmple_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmple_oqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -705,11 +698,10 @@ define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ole_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmple_oqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -793,11 +785,10 @@ define <4 x i32> @test_v4f32_one_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_oqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -807,11 +798,10 @@ define <4 x i32> @test_v4f32_one_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_one_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_oqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -888,11 +878,10 @@ define <4 x i32> @test_v4f32_ord_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpordps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpordps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -902,11 +891,10 @@ define <4 x i32> @test_v4f32_ord_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ord_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpordps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpordps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -990,11 +978,10 @@ define <4 x i32> @test_v4f32_ueq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1004,11 +991,10 @@ define <4 x i32> @test_v4f32_ueq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ueq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1144,11 +1130,10 @@ define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnle_uqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1158,11 +1143,10 @@ define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ugt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnle_uqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1298,11 +1282,10 @@ define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1312,11 +1295,10 @@ define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_uge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1453,11 +1435,11 @@ define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnle_uqps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1467,11 +1449,10 @@ define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ult_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnle_uqps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1608,11 +1589,11 @@ define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1622,11 +1603,10 @@ define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ule_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1703,11 +1683,10 @@ define <4 x i32> @test_v4f32_une_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneqps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1717,11 +1696,10 @@ define <4 x i32> @test_v4f32_une_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_une_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneqps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1798,11 +1776,10 @@ define <4 x i32> @test_v4f32_uno_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpunordps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunordps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1812,11 +1789,10 @@ define <4 x i32> @test_v4f32_uno_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_uno_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunordps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunordps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -1893,11 +1869,10 @@ define <2 x i64> @test_v2f64_oeq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1907,11 +1882,10 @@ define <2 x i64> @test_v2f64_oeq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_oeq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2014,11 +1988,11 @@ define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplt_oqpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2028,11 +2002,10 @@ define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ogt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplt_oqpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2135,11 +2108,11 @@ define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmple_oqpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2149,11 +2122,10 @@ define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_oge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmple_oqpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2255,11 +2227,10 @@ define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplt_oqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2269,11 +2240,10 @@ define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_olt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplt_oqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2375,11 +2345,10 @@ define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmple_oqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2389,11 +2358,10 @@ define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ole_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmple_oqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2477,11 +2445,10 @@ define <2 x i64> @test_v2f64_one_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_oqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2491,11 +2458,10 @@ define <2 x i64> @test_v2f64_one_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_one_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_oqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2572,11 +2538,10 @@ define <2 x i64> @test_v2f64_ord_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpordpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpordpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2586,11 +2551,10 @@ define <2 x i64> @test_v2f64_ord_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ord_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpordpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpordpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2674,11 +2638,10 @@ define <2 x i64> @test_v2f64_ueq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2688,11 +2651,10 @@ define <2 x i64> @test_v2f64_ueq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ueq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2794,11 +2756,10 @@ define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnle_uqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2808,11 +2769,10 @@ define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ugt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnle_uqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -2914,11 +2874,10 @@ define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2928,11 +2887,10 @@ define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_uge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3035,11 +2993,11 @@ define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnle_uqpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3049,11 +3007,10 @@ define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ult_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnle_uqpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3156,11 +3113,11 @@ define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3170,11 +3127,10 @@ define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ule_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3251,11 +3207,10 @@ define <2 x i64> @test_v2f64_une_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneqpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3265,11 +3220,10 @@ define <2 x i64> @test_v2f64_une_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_une_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneqpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3346,11 +3300,10 @@ define <2 x i64> @test_v2f64_uno_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpunordpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunordpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3360,11 +3313,10 @@ define <2 x i64> @test_v2f64_uno_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_uno_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunordpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunordpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3446,11 +3398,10 @@ define <4 x i32> @test_v4f32_oeq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_osps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3460,11 +3411,10 @@ define <4 x i32> @test_v4f32_oeq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_oeq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_osps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3543,11 +3493,11 @@ define <4 x i32> @test_v4f32_ogt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpltps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpltps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3557,11 +3507,10 @@ define <4 x i32> @test_v4f32_ogt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ogt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpltps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3640,11 +3589,11 @@ define <4 x i32> @test_v4f32_oge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpleps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpleps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3654,11 +3603,10 @@ define <4 x i32> @test_v4f32_oge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_oge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpleps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpleps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3735,11 +3683,10 @@ define <4 x i32> @test_v4f32_olt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpltps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpltps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3749,11 +3696,10 @@ define <4 x i32> @test_v4f32_olt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_olt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpltps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3830,11 +3776,10 @@ define <4 x i32> @test_v4f32_ole_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpleps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpleps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3844,11 +3789,10 @@ define <4 x i32> @test_v4f32_ole_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ole_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpleps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpleps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -3936,11 +3880,10 @@ define <4 x i32> @test_v4f32_one_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_osps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3950,11 +3893,10 @@ define <4 x i32> @test_v4f32_one_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_one_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_osps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4036,11 +3978,10 @@ define <4 x i32> @test_v4f32_ord_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpord_sps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpord_sps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4050,11 +3991,10 @@ define <4 x i32> @test_v4f32_ord_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ord_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpord_sps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpord_sps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4142,11 +4082,10 @@ define <4 x i32> @test_v4f32_ueq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_usps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4156,11 +4095,10 @@ define <4 x i32> @test_v4f32_ueq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ueq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_usps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4237,11 +4175,10 @@ define <4 x i32> @test_v4f32_ugt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnleps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnleps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4251,11 +4188,10 @@ define <4 x i32> @test_v4f32_ugt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ugt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnleps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnleps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4332,11 +4268,10 @@ define <4 x i32> @test_v4f32_uge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnltps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnltps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4346,11 +4281,10 @@ define <4 x i32> @test_v4f32_uge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_uge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnltps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4429,11 +4363,11 @@ define <4 x i32> @test_v4f32_ult_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnleps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnleps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4443,11 +4377,10 @@ define <4 x i32> @test_v4f32_ult_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ult_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnleps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnleps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4526,11 +4459,11 @@ define <4 x i32> @test_v4f32_ule_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnltps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnltps %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4540,11 +4473,10 @@ define <4 x i32> @test_v4f32_ule_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_ule_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnltps %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4626,11 +4558,10 @@ define <4 x i32> @test_v4f32_une_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_usps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4640,11 +4571,10 @@ define <4 x i32> @test_v4f32_une_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_une_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_usps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4726,11 +4656,10 @@ define <4 x i32> @test_v4f32_uno_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunord_sps 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4740,11 +4669,10 @@ define <4 x i32> @test_v4f32_uno_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, ; ; AVX512F-64-LABEL: test_v4f32_uno_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunord_sps %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4826,11 +4754,10 @@ define <2 x i64> @test_v2f64_oeq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_ospd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4840,11 +4767,10 @@ define <2 x i64> @test_v2f64_oeq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_oeq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_ospd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -4923,11 +4849,11 @@ define <2 x i64> @test_v2f64_ogt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpltpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpltpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -4937,11 +4863,10 @@ define <2 x i64> @test_v2f64_ogt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ogt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpltpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5020,11 +4945,11 @@ define <2 x i64> @test_v2f64_oge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplepd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplepd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5034,11 +4959,10 @@ define <2 x i64> @test_v2f64_oge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_oge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplepd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplepd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5115,11 +5039,10 @@ define <2 x i64> @test_v2f64_olt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpltpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpltpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5129,11 +5052,10 @@ define <2 x i64> @test_v2f64_olt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_olt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpltpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5210,11 +5132,10 @@ define <2 x i64> @test_v2f64_ole_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmplepd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplepd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5224,11 +5145,10 @@ define <2 x i64> @test_v2f64_ole_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ole_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmplepd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplepd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5316,11 +5236,10 @@ define <2 x i64> @test_v2f64_one_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_ospd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5330,11 +5249,10 @@ define <2 x i64> @test_v2f64_one_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_one_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_ospd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5416,11 +5334,10 @@ define <2 x i64> @test_v2f64_ord_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpord_spd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpord_spd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5430,11 +5347,10 @@ define <2 x i64> @test_v2f64_ord_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ord_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpord_spd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpord_spd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5522,11 +5438,10 @@ define <2 x i64> @test_v2f64_ueq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uspd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5536,11 +5451,10 @@ define <2 x i64> @test_v2f64_ueq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ueq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uspd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5617,11 +5531,10 @@ define <2 x i64> @test_v2f64_ugt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlepd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlepd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5631,11 +5544,10 @@ define <2 x i64> @test_v2f64_ugt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ugt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlepd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlepd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5712,11 +5624,10 @@ define <2 x i64> @test_v2f64_uge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnltpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnltpd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5726,11 +5637,10 @@ define <2 x i64> @test_v2f64_uge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_uge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnltpd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5809,11 +5719,11 @@ define <2 x i64> @test_v2f64_ult_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnlepd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlepd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5823,11 +5733,10 @@ define <2 x i64> @test_v2f64_ult_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ult_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlepd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlepd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -5906,11 +5815,11 @@ define <2 x i64> @test_v2f64_ule_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpnltpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnltpd %xmm2, %xmm3, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -5920,11 +5829,10 @@ define <2 x i64> @test_v2f64_ule_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_ule_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnltpd %xmm2, %xmm3, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -6006,11 +5914,10 @@ define <2 x i64> @test_v2f64_une_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_uspd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -6020,11 +5927,10 @@ define <2 x i64> @test_v2f64_une_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_une_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_uspd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper @@ -6106,11 +6012,10 @@ define <2 x i64> @test_v2f64_uno_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-16, %esp ; AVX512F-32-NEXT: subl $16, %esp -; AVX512F-32-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %xmm3 -; AVX512F-32-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunord_spd 8(%ebp), %xmm2, %xmm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -6120,11 +6025,10 @@ define <2 x i64> @test_v2f64_uno_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, ; ; AVX512F-64-LABEL: test_v2f64_uno_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunord_spd %xmm3, %xmm2, %xmm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-64-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/vec-strict-cmp-256.ll b/llvm/test/CodeGen/X86/vec-strict-cmp-256.ll index 225aebfeb65a8..dd0dd95daa330 100644 --- a/llvm/test/CodeGen/X86/vec-strict-cmp-256.ll +++ b/llvm/test/CodeGen/X86/vec-strict-cmp-256.ll @@ -49,11 +49,10 @@ define <8 x i32> @test_v8f32_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -62,11 +61,10 @@ define <8 x i32> @test_v8f32_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_oeq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -121,11 +119,11 @@ define <8 x i32> @test_v8f32_ogt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplt_oqps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -134,11 +132,10 @@ define <8 x i32> @test_v8f32_ogt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ogt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplt_oqps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -193,11 +190,11 @@ define <8 x i32> @test_v8f32_oge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmple_oqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmple_oqps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -206,11 +203,10 @@ define <8 x i32> @test_v8f32_oge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_oge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmple_oqps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -264,11 +260,10 @@ define <8 x i32> @test_v8f32_olt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplt_oqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -277,11 +272,10 @@ define <8 x i32> @test_v8f32_olt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_olt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplt_oqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -335,11 +329,10 @@ define <8 x i32> @test_v8f32_ole_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmple_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmple_oqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -348,11 +341,10 @@ define <8 x i32> @test_v8f32_ole_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ole_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmple_oqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -406,11 +398,10 @@ define <8 x i32> @test_v8f32_one_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_oqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -419,11 +410,10 @@ define <8 x i32> @test_v8f32_one_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_one_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_oqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -477,11 +467,10 @@ define <8 x i32> @test_v8f32_ord_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpordps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpordps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -490,11 +479,10 @@ define <8 x i32> @test_v8f32_ord_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ord_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpordps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpordps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -548,11 +536,10 @@ define <8 x i32> @test_v8f32_ueq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -561,11 +548,10 @@ define <8 x i32> @test_v8f32_ueq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ueq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -619,11 +605,10 @@ define <8 x i32> @test_v8f32_ugt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnle_uqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -632,11 +617,10 @@ define <8 x i32> @test_v8f32_ugt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ugt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnle_uqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -690,11 +674,10 @@ define <8 x i32> @test_v8f32_uge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -703,11 +686,10 @@ define <8 x i32> @test_v8f32_uge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_uge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -762,11 +744,11 @@ define <8 x i32> @test_v8f32_ult_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnle_uqps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -775,11 +757,10 @@ define <8 x i32> @test_v8f32_ult_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ult_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnle_uqps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -834,11 +815,11 @@ define <8 x i32> @test_v8f32_ule_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -847,11 +828,10 @@ define <8 x i32> @test_v8f32_ule_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ule_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -905,11 +885,10 @@ define <8 x i32> @test_v8f32_une_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneqps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneqps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -918,11 +897,10 @@ define <8 x i32> @test_v8f32_une_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_une_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneqps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneqps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -976,11 +954,10 @@ define <8 x i32> @test_v8f32_uno_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpunordps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunordps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -989,11 +966,10 @@ define <8 x i32> @test_v8f32_uno_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_uno_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunordps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunordps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1047,11 +1023,10 @@ define <4 x i64> @test_v4f64_oeq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1060,11 +1035,10 @@ define <4 x i64> @test_v4f64_oeq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_oeq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1119,11 +1093,11 @@ define <4 x i64> @test_v4f64_ogt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplt_oqpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1132,11 +1106,10 @@ define <4 x i64> @test_v4f64_ogt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ogt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplt_oqpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1191,11 +1164,11 @@ define <4 x i64> @test_v4f64_oge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmple_oqpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1204,11 +1177,10 @@ define <4 x i64> @test_v4f64_oge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_oge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmple_oqpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1262,11 +1234,10 @@ define <4 x i64> @test_v4f64_olt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplt_oqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1275,11 +1246,10 @@ define <4 x i64> @test_v4f64_olt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_olt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplt_oqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1333,11 +1303,10 @@ define <4 x i64> @test_v4f64_ole_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmple_oqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1346,11 +1315,10 @@ define <4 x i64> @test_v4f64_ole_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ole_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmple_oqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1404,11 +1372,10 @@ define <4 x i64> @test_v4f64_one_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_oqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1417,11 +1384,10 @@ define <4 x i64> @test_v4f64_one_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_one_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_oqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1475,11 +1441,10 @@ define <4 x i64> @test_v4f64_ord_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpordpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpordpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1488,11 +1453,10 @@ define <4 x i64> @test_v4f64_ord_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ord_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpordpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpordpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1546,11 +1510,10 @@ define <4 x i64> @test_v4f64_ueq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1559,11 +1522,10 @@ define <4 x i64> @test_v4f64_ueq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ueq_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1617,11 +1579,10 @@ define <4 x i64> @test_v4f64_ugt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnle_uqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1630,11 +1591,10 @@ define <4 x i64> @test_v4f64_ugt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ugt_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnle_uqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1688,11 +1648,10 @@ define <4 x i64> @test_v4f64_uge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1701,11 +1660,10 @@ define <4 x i64> @test_v4f64_uge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_uge_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1760,11 +1718,11 @@ define <4 x i64> @test_v4f64_ult_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnle_uqpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1773,11 +1731,10 @@ define <4 x i64> @test_v4f64_ult_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ult_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnle_uqpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1832,11 +1789,11 @@ define <4 x i64> @test_v4f64_ule_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlt_uqpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1845,11 +1802,10 @@ define <4 x i64> @test_v4f64_ule_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ule_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlt_uqpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1903,11 +1859,10 @@ define <4 x i64> @test_v4f64_une_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneqpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneqpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1916,11 +1871,10 @@ define <4 x i64> @test_v4f64_une_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_une_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneqpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneqpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -1974,11 +1928,10 @@ define <4 x i64> @test_v4f64_uno_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpunordpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunordpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -1987,11 +1940,10 @@ define <4 x i64> @test_v4f64_uno_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_uno_q: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunordpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunordpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2045,11 +1997,10 @@ define <8 x i32> @test_v8f32_oeq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_osps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2058,11 +2009,10 @@ define <8 x i32> @test_v8f32_oeq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_oeq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_osps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2117,11 +2067,11 @@ define <8 x i32> @test_v8f32_ogt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpltps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpltps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2130,11 +2080,10 @@ define <8 x i32> @test_v8f32_ogt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ogt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpltps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2189,11 +2138,11 @@ define <8 x i32> @test_v8f32_oge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpleps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpleps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2202,11 +2151,10 @@ define <8 x i32> @test_v8f32_oge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_oge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpleps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpleps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2260,11 +2208,10 @@ define <8 x i32> @test_v8f32_olt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpltps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpltps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2273,11 +2220,10 @@ define <8 x i32> @test_v8f32_olt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_olt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpltps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2331,11 +2277,10 @@ define <8 x i32> @test_v8f32_ole_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpleps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpleps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2344,11 +2289,10 @@ define <8 x i32> @test_v8f32_ole_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ole_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpleps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpleps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2402,11 +2346,10 @@ define <8 x i32> @test_v8f32_one_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_osps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2415,11 +2358,10 @@ define <8 x i32> @test_v8f32_one_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_one_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_osps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2473,11 +2415,10 @@ define <8 x i32> @test_v8f32_ord_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpord_sps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpord_sps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2486,11 +2427,10 @@ define <8 x i32> @test_v8f32_ord_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ord_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpord_sps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpord_sps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2544,11 +2484,10 @@ define <8 x i32> @test_v8f32_ueq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_usps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2557,11 +2496,10 @@ define <8 x i32> @test_v8f32_ueq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ueq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_usps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2615,11 +2553,10 @@ define <8 x i32> @test_v8f32_ugt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnleps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnleps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2628,11 +2565,10 @@ define <8 x i32> @test_v8f32_ugt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ugt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnleps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnleps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2686,11 +2622,10 @@ define <8 x i32> @test_v8f32_uge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnltps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnltps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2699,11 +2634,10 @@ define <8 x i32> @test_v8f32_uge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_uge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnltps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2758,11 +2692,11 @@ define <8 x i32> @test_v8f32_ult_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnleps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnleps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2771,11 +2705,10 @@ define <8 x i32> @test_v8f32_ult_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ult_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnleps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnleps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2830,11 +2763,11 @@ define <8 x i32> @test_v8f32_ule_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnltps %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnltps %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2843,11 +2776,10 @@ define <8 x i32> @test_v8f32_ule_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_ule_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltps %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnltps %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2901,11 +2833,10 @@ define <8 x i32> @test_v8f32_une_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_usps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2914,11 +2845,10 @@ define <8 x i32> @test_v8f32_une_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_une_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_usps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -2972,11 +2902,10 @@ define <8 x i32> @test_v8f32_uno_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovaps 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunord_sps 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -2985,11 +2914,10 @@ define <8 x i32> @test_v8f32_uno_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, ; ; AVX512F-64-LABEL: test_v8f32_uno_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunord_sps %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmd %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3043,11 +2971,10 @@ define <4 x i64> @test_v4f64_oeq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_ospd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3056,11 +2983,10 @@ define <4 x i64> @test_v4f64_oeq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_oeq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_ospd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3115,11 +3041,11 @@ define <4 x i64> @test_v4f64_ogt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpltpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpltpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3128,11 +3054,10 @@ define <4 x i64> @test_v4f64_ogt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ogt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpltpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3187,11 +3112,11 @@ define <4 x i64> @test_v4f64_oge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplepd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmplepd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3200,11 +3125,10 @@ define <4 x i64> @test_v4f64_oge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_oge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplepd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmplepd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3258,11 +3182,10 @@ define <4 x i64> @test_v4f64_olt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpltpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpltpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3271,11 +3194,10 @@ define <4 x i64> @test_v4f64_olt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_olt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpltpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpltpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3329,11 +3251,10 @@ define <4 x i64> @test_v4f64_ole_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmplepd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmplepd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3342,11 +3263,10 @@ define <4 x i64> @test_v4f64_ole_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ole_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmplepd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmplepd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3400,11 +3320,10 @@ define <4 x i64> @test_v4f64_one_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_ospd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3413,11 +3332,10 @@ define <4 x i64> @test_v4f64_one_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_one_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_ospd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3471,11 +3389,10 @@ define <4 x i64> @test_v4f64_ord_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpord_spd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpord_spd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3484,11 +3401,10 @@ define <4 x i64> @test_v4f64_ord_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ord_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpord_spd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpord_spd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3542,11 +3458,10 @@ define <4 x i64> @test_v4f64_ueq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpeq_uspd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3555,11 +3470,10 @@ define <4 x i64> @test_v4f64_ueq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ueq_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpeq_uspd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3613,11 +3527,10 @@ define <4 x i64> @test_v4f64_ugt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlepd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnlepd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3626,11 +3539,10 @@ define <4 x i64> @test_v4f64_ugt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ugt_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlepd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnlepd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3684,11 +3596,10 @@ define <4 x i64> @test_v4f64_uge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnltpd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpnltpd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3697,11 +3608,10 @@ define <4 x i64> @test_v4f64_uge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_uge_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltpd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpnltpd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3756,11 +3666,11 @@ define <4 x i64> @test_v4f64_ult_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnlepd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnlepd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3769,11 +3679,10 @@ define <4 x i64> @test_v4f64_ult_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ult_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnlepd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnlepd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3828,11 +3737,11 @@ define <4 x i64> @test_v4f64_ule_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpnltpd %zmm2, %zmm3, %k1 +; AVX512F-32-NEXT: vcmpnltpd %ymm2, %ymm3, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3841,11 +3750,10 @@ define <4 x i64> @test_v4f64_ule_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_ule_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpnltpd %zmm2, %zmm3, %k1 +; AVX512F-64-NEXT: vcmpnltpd %ymm2, %ymm3, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3899,11 +3807,10 @@ define <4 x i64> @test_v4f64_une_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpneq_uspd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3912,11 +3819,10 @@ define <4 x i64> @test_v4f64_une_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_une_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpneq_uspd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq @@ -3970,11 +3876,10 @@ define <4 x i64> @test_v4f64_uno_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; AVX512F-32-NEXT: movl %esp, %ebp ; AVX512F-32-NEXT: andl $-32, %esp ; AVX512F-32-NEXT: subl $32, %esp -; AVX512F-32-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-32-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-32-NEXT: vmovapd 8(%ebp), %ymm3 -; AVX512F-32-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1 +; AVX512F-32-NEXT: vcmpunord_spd 8(%ebp), %ymm2, %ymm2 +; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-32-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-32-NEXT: movl %ebp, %esp @@ -3983,11 +3888,10 @@ define <4 x i64> @test_v4f64_uno_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, ; ; AVX512F-64-LABEL: test_v4f64_uno_s: ; AVX512F-64: # %bb.0: -; AVX512F-64-NEXT: # kill: def $ymm3 killed $ymm3 def $zmm3 -; AVX512F-64-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2 ; AVX512F-64-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512F-64-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1 +; AVX512F-64-NEXT: vcmpunord_spd %ymm3, %ymm2, %ymm2 +; AVX512F-64-NEXT: vptestmq %zmm2, %zmm2, %k1 ; AVX512F-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1} ; AVX512F-64-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512F-64-NEXT: retq From 0bc77a0f0d1606520c7ad0ea72c434661786a956 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 13:26:21 -0800 Subject: [PATCH 16/57] [AsmPrinter] De-capitalize some AsmPrinter::Emit* functions Similar to rL328848. --- llvm/docs/GarbageCollection.rst | 2 +- llvm/include/llvm/CodeGen/AsmPrinter.h | 29 ++--- llvm/include/llvm/MC/MCELFStreamer.h | 2 +- llvm/include/llvm/MC/MCObjectStreamer.h | 19 ++- llvm/include/llvm/MC/MCStreamer.h | 12 +- llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp | 22 ++-- llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 30 ++--- .../CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 33 +++-- llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h | 24 ++-- llvm/lib/CodeGen/AsmPrinter/DIE.cpp | 46 +++---- .../CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 5 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 57 +++++---- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp | 24 ++-- .../CodeGen/AsmPrinter/ErlangGCPrinter.cpp | 2 +- llvm/lib/MC/MCAsmStreamer.cpp | 27 ++--- llvm/lib/MC/MCDwarf.cpp | 114 +++++++++--------- llvm/lib/MC/MCELFStreamer.cpp | 4 +- llvm/lib/MC/MCObjectStreamer.cpp | 24 ++-- llvm/lib/MC/MCParser/AsmParser.cpp | 12 +- llvm/lib/MC/MCStreamer.cpp | 15 ++- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 4 +- .../ARM/MCTargetDesc/ARMELFStreamer.cpp | 8 +- llvm/lib/Target/BPF/BTFDebug.cpp | 8 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 4 +- llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- .../WebAssemblyTargetStreamer.cpp | 4 +- .../WebAssembly/WebAssemblyAsmPrinter.cpp | 14 +-- llvm/tools/dsymutil/DwarfStreamer.cpp | 28 ++--- .../DebugInfo/DWARF/DwarfGenerator.cpp | 32 ++--- 32 files changed, 308 insertions(+), 305 deletions(-) diff --git a/llvm/docs/GarbageCollection.rst b/llvm/docs/GarbageCollection.rst index 5e671bc10b698..8c6b0466fdb17 100644 --- a/llvm/docs/GarbageCollection.rst +++ b/llvm/docs/GarbageCollection.rst @@ -970,7 +970,7 @@ a realistic example: // Emit the address of the safe point. OS.AddComment("safe point address"); MCSymbol *Label = PI->Label; - AP.EmitLabelPlusOffset(Label/*Hi*/, 0/*Offset*/, 4/*Size*/); + AP.emitLabelPlusOffset(Label/*Hi*/, 0/*Offset*/, 4/*Size*/); } // Stack information never change in safe points! Only print info from the diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 1df889f5722b5..875d32ede9b0d 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -512,38 +512,39 @@ class AsmPrinter : public MachineFunctionPass { /// Emit something like ".long Hi-Lo" where the size in bytes of the directive /// is specified by Size and Hi/Lo specify the labels. This implicitly uses /// .set if it is available. - void EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, + void emitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, unsigned Size) const; /// Emit something like ".uleb128 Hi-Lo". - void EmitLabelDifferenceAsULEB128(const MCSymbol *Hi, + void emitLabelDifferenceAsULEB128(const MCSymbol *Hi, const MCSymbol *Lo) const; /// Emit something like ".long Label+Offset" where the size in bytes of the /// directive is specified by Size and Label specifies the label. This /// implicitly uses .set if it is available. - void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, + void emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, unsigned Size, bool IsSectionRelative = false) const; /// Emit something like ".long Label" where the size in bytes of the directive /// is specified by Size and Label specifies the label. - void EmitLabelReference(const MCSymbol *Label, unsigned Size, + void emitLabelReference(const MCSymbol *Label, unsigned Size, bool IsSectionRelative = false) const { - EmitLabelPlusOffset(Label, 0, Size, IsSectionRelative); + emitLabelPlusOffset(Label, 0, Size, IsSectionRelative); } /// Emit something like ".long Label + Offset". - void EmitDwarfOffset(const MCSymbol *Label, uint64_t Offset) const; + void emitDwarfOffset(const MCSymbol *Label, uint64_t Offset) const; //===------------------------------------------------------------------===// // Dwarf Emission Helper Routines //===------------------------------------------------------------------===// /// Emit the specified signed leb128 value. - void EmitSLEB128(int64_t Value, const char *Desc = nullptr) const; + void emitSLEB128(int64_t Value, const char *Desc = nullptr) const; /// Emit the specified unsigned leb128 value. - void EmitULEB128(uint64_t Value, const char *Desc = nullptr, unsigned PadTo = 0) const; + void emitULEB128(uint64_t Value, const char *Desc = nullptr, + unsigned PadTo = 0) const; /// Emit a .byte 42 directive that corresponds to an encoding. If verbose /// assembly output is enabled, we output comments describing the encoding. @@ -575,10 +576,10 @@ class AsmPrinter : public MachineFunctionPass { } /// Emit reference to a call site with a specified encoding - void EmitCallSiteOffset(const MCSymbol *Hi, const MCSymbol *Lo, + void emitCallSiteOffset(const MCSymbol *Hi, const MCSymbol *Lo, unsigned Encoding) const; /// Emit an integer value corresponding to the call site encoding - void EmitCallSiteValue(uint64_t Value, unsigned Encoding) const; + void emitCallSiteValue(uint64_t Value, unsigned Encoding) const; /// Get the value for DW_AT_APPLE_isa. Zero if no isa encoding specified. virtual unsigned getISAEncoding() { return 0; } @@ -587,7 +588,7 @@ class AsmPrinter : public MachineFunctionPass { /// /// \p Value - The value to emit. /// \p Size - The size of the integer (in bytes) to emit. - virtual void EmitDebugValue(const MCExpr *Value, unsigned Size) const; + virtual void emitDebugValue(const MCExpr *Value, unsigned Size) const; //===------------------------------------------------------------------===// // Dwarf Lowering Routines @@ -603,7 +604,7 @@ class AsmPrinter : public MachineFunctionPass { emitDwarfAbbrev(*Abbrev); // Mark end of abbreviations. - EmitULEB128(0, "EOM(3)"); + emitULEB128(0, "EOM(3)"); } void emitDwarfAbbrev(const DIEAbbrev &Abbrev) const; @@ -659,12 +660,12 @@ class AsmPrinter : public MachineFunctionPass { /// This emits visibility information about symbol, if this is supported by /// the target. - void EmitVisibility(MCSymbol *Sym, unsigned Visibility, + void emitVisibility(MCSymbol *Sym, unsigned Visibility, bool IsDefinition = true) const; /// This emits linkage information about \p GVSym based on \p GV, if this is /// supported by the target. - void EmitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const; + void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const; /// Return the alignment for the specified \p GV. static Align getGVAlignment(const GlobalValue *GV, const DataLayout &DL, diff --git a/llvm/include/llvm/MC/MCELFStreamer.h b/llvm/include/llvm/MC/MCELFStreamer.h index 85534ed6c0850..285af625f21a7 100644 --- a/llvm/include/llvm/MC/MCELFStreamer.h +++ b/llvm/include/llvm/MC/MCELFStreamer.h @@ -41,7 +41,7 @@ class MCELFStreamer : public MCObjectStreamer { void InitSections(bool NoExecStack) override; void ChangeSection(MCSection *Section, const MCExpr *Subsection) override; void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; - void EmitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, MCFragment *F, + void emitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, MCFragment *F, uint64_t Offset) override; void EmitAssemblerFlag(MCAssemblerFlag Flag) override; void EmitThumbFunc(MCSymbol *Func) override; diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h index 9e3f87565e26b..5c7782326d5a7 100644 --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -114,13 +114,13 @@ class MCObjectStreamer : public MCStreamer { /// @{ void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; - virtual void EmitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, MCFragment *F, + virtual void emitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, MCFragment *F, uint64_t Offset); void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) override; void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc = SMLoc()) override; - void EmitULEB128Value(const MCExpr *Value) override; - void EmitSLEB128Value(const MCExpr *Value) override; + void emitULEB128Value(const MCExpr *Value) override; + void emitSLEB128Value(const MCExpr *Value) override; void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) override; void ChangeSection(MCSection *Section, const MCExpr *Subsection) override; void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; @@ -140,14 +140,13 @@ class MCObjectStreamer : public MCStreamer { unsigned MaxBytesToEmit = 0) override; void emitValueToOffset(const MCExpr *Offset, unsigned char Value, SMLoc Loc) override; - void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, - unsigned Column, unsigned Flags, - unsigned Isa, unsigned Discriminator, + void emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, + unsigned Flags, unsigned Isa, + unsigned Discriminator, StringRef FileName) override; - void EmitDwarfAdvanceLineAddr(int64_t LineDelta, const MCSymbol *LastLabel, - const MCSymbol *Label, - unsigned PointerSize); - void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel, + void emitDwarfAdvanceLineAddr(int64_t LineDelta, const MCSymbol *LastLabel, + const MCSymbol *Label, unsigned PointerSize); + void emitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel, const MCSymbol *Label); void EmitCVLocDirective(unsigned FunctionId, unsigned FileNo, unsigned Line, unsigned Column, bool PrologueEnd, bool IsStmt, diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index ff488f17fd8ad..4749671ce163f 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -670,17 +670,17 @@ class MCStreamer { EmitIntValue(Value, Size); } - virtual void EmitULEB128Value(const MCExpr *Value); + virtual void emitULEB128Value(const MCExpr *Value); - virtual void EmitSLEB128Value(const MCExpr *Value); + virtual void emitSLEB128Value(const MCExpr *Value); /// Special case of EmitULEB128Value that avoids the client having to /// pass in a MCExpr for constant integers. - void EmitULEB128IntValue(uint64_t Value, unsigned PadTo = 0); + void emitULEB128IntValue(uint64_t Value, unsigned PadTo = 0); /// Special case of EmitSLEB128Value that avoids the client having to /// pass in a MCExpr for constant integers. - void EmitSLEB128IntValue(int64_t Value); + void emitSLEB128IntValue(int64_t Value); /// Special case of EmitValue that avoids the client having to pass in /// a MCExpr for MCSymbols. @@ -821,7 +821,7 @@ class MCStreamer { /// Associate a filename with a specified logical file number. This /// implements the DWARF2 '.file 4 "foo.c"' assembler directive. - unsigned EmitDwarfFileDirective(unsigned FileNo, StringRef Directory, + unsigned emitDwarfFileDirective(unsigned FileNo, StringRef Directory, StringRef Filename, Optional Checksum = None, Optional Source = None, @@ -851,7 +851,7 @@ class MCStreamer { /// This implements the DWARF2 '.loc fileno lineno ...' assembler /// directive. - virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, + virtual void emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, unsigned Flags, unsigned Isa, unsigned Discriminator, StringRef FileName); diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp index b1b7921ea976a..c274b8cac2dee 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -271,7 +271,7 @@ void AccelTableWriter::emitOffsets(const MCSymbol *Base) const { continue; PrevHash = HashValue; Asm->OutStreamer->AddComment("Offset in Bucket " + Twine(i)); - Asm->EmitLabelDifference(Hash->Sym, Base, sizeof(uint32_t)); + Asm->emitLabelDifference(Hash->Sym, Base, sizeof(uint32_t)); } } } @@ -368,7 +368,7 @@ void Dwarf5AccelTableWriter::Header::emit( AsmPrinter *Asm = Ctx.Asm; Asm->OutStreamer->AddComment("Header: unit length"); - Asm->EmitLabelDifference(Ctx.ContributionEnd, Ctx.ContributionStart, + Asm->emitLabelDifference(Ctx.ContributionEnd, Ctx.ContributionStart, sizeof(uint32_t)); Asm->OutStreamer->EmitLabel(Ctx.ContributionStart); Asm->OutStreamer->AddComment("Header: version"); @@ -386,7 +386,7 @@ void Dwarf5AccelTableWriter::Header::emit( Asm->OutStreamer->AddComment("Header: name count"); Asm->emitInt32(NameCount); Asm->OutStreamer->AddComment("Header: abbreviation table size"); - Asm->EmitLabelDifference(Ctx.AbbrevEnd, Ctx.AbbrevStart, sizeof(uint32_t)); + Asm->emitLabelDifference(Ctx.AbbrevEnd, Ctx.AbbrevStart, sizeof(uint32_t)); Asm->OutStreamer->AddComment("Header: augmentation string size"); assert(AugmentationStringSize % 4 == 0); Asm->emitInt32(AugmentationStringSize); @@ -457,18 +457,18 @@ void Dwarf5AccelTableWriter::emitAbbrevs() const { for (const auto &Abbrev : Abbreviations) { Asm->OutStreamer->AddComment("Abbrev code"); assert(Abbrev.first != 0); - Asm->EmitULEB128(Abbrev.first); + Asm->emitULEB128(Abbrev.first); Asm->OutStreamer->AddComment(dwarf::TagString(Abbrev.first)); - Asm->EmitULEB128(Abbrev.first); + Asm->emitULEB128(Abbrev.first); for (const auto &AttrEnc : Abbrev.second) { - Asm->EmitULEB128(AttrEnc.Index, dwarf::IndexString(AttrEnc.Index).data()); - Asm->EmitULEB128(AttrEnc.Form, + Asm->emitULEB128(AttrEnc.Index, dwarf::IndexString(AttrEnc.Index).data()); + Asm->emitULEB128(AttrEnc.Form, dwarf::FormEncodingString(AttrEnc.Form).data()); } - Asm->EmitULEB128(0, "End of abbrev"); - Asm->EmitULEB128(0, "End of abbrev"); + Asm->emitULEB128(0, "End of abbrev"); + Asm->emitULEB128(0, "End of abbrev"); } - Asm->EmitULEB128(0, "End of abbrev list"); + Asm->emitULEB128(0, "End of abbrev list"); Asm->OutStreamer->EmitLabel(AbbrevEnd); } @@ -478,7 +478,7 @@ void Dwarf5AccelTableWriter::emitEntry(const DataT &Entry) const { assert(AbbrevIt != Abbreviations.end() && "Why wasn't this abbrev generated?"); - Asm->EmitULEB128(AbbrevIt->first, "Abbreviation code"); + Asm->emitULEB128(AbbrevIt->first, "Abbreviation code"); for (const auto &AttrEnc : AbbrevIt->second) { Asm->OutStreamer->AddComment(dwarf::IndexString(AttrEnc.Index)); switch (AttrEnc.Index) { diff --git a/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp b/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp index f11c7de5ed8af..cb6f229402e0c 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp @@ -30,7 +30,7 @@ MCSymbol *AddressPool::emitHeader(AsmPrinter &Asm, MCSection *Section) { MCSymbol *EndLabel = Asm.createTempSymbol(Prefix + "end"); Asm.OutStreamer->AddComment("Length of contribution"); - Asm.EmitLabelDifference(EndLabel, BeginLabel, + Asm.emitLabelDifference(EndLabel, BeginLabel, 4); // TODO: Support DWARF64 format. Asm.OutStreamer->EmitLabel(BeginLabel); Asm.OutStreamer->AddComment("DWARF version number"); diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index f81a291846546..0baf9bf79e0f6 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -397,7 +397,7 @@ static bool canBeHidden(const GlobalValue *GV, const MCAsmInfo &MAI) { return GV->canBeOmittedFromSymbolTable(); } -void AsmPrinter::EmitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const { +void AsmPrinter::emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const { GlobalValue::LinkageTypes Linkage = GV->getLinkage(); switch (Linkage) { case GlobalValue::CommonLinkage: @@ -501,7 +501,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { // getOrCreateEmuTLSControlSym only creates the symbol with name and default // attributes. // GV's or GVSym's attributes will be used for the EmittedSym. - EmitVisibility(EmittedSym, GV->getVisibility(), !GV->isDeclaration()); + emitVisibility(EmittedSym, GV->getVisibility(), !GV->isDeclaration()); if (!GV->hasInitializer()) // External globals require no extra code. return; @@ -551,7 +551,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { TheSection->isVirtualSection()) { if (Size == 0) Size = 1; // zerofill of 0 bytes is undefined. - EmitLinkage(GV, GVSym); + emitLinkage(GV, GVSym); // .zerofill __DATA, __bss, _foo, 400, 5 OutStreamer->EmitZerofill(TheSection, GVSym, Size, Alignment.value()); return; @@ -621,7 +621,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { OutStreamer->SwitchSection(TLVSect); // Emit the linkage here. - EmitLinkage(GV, GVSym); + emitLinkage(GV, GVSym); OutStreamer->EmitLabel(GVSym); // Three pointers in size: @@ -642,7 +642,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { OutStreamer->SwitchSection(TheSection); - EmitLinkage(GV, EmittedInitSym); + emitLinkage(GV, EmittedInitSym); EmitAlignment(Alignment, GV); OutStreamer->EmitLabel(EmittedInitSym); @@ -664,7 +664,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { /// /// \p Value - The value to emit. /// \p Size - The size of the integer (in bytes) to emit. -void AsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { +void AsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const { OutStreamer->EmitValue(Value, Size); } @@ -683,13 +683,13 @@ void AsmPrinter::emitFunctionHeader() { // Print the 'header' of function. OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(&F, TM)); - EmitVisibility(CurrentFnSym, F.getVisibility()); + emitVisibility(CurrentFnSym, F.getVisibility()); if (MAI->needsFunctionDescriptors() && F.getLinkage() != GlobalValue::InternalLinkage) - EmitLinkage(&F, CurrentFnDescSym); + emitLinkage(&F, CurrentFnDescSym); - EmitLinkage(&F, CurrentFnSym); + emitLinkage(&F, CurrentFnSym); if (MAI->hasFunctionAlignment()) EmitAlignment(MF->getAlignment(), &F); @@ -1046,7 +1046,7 @@ void AsmPrinter::emitStackSizeSection(const MachineFunction &MF) { const MCSymbol *FunctionSymbol = getFunctionBegin(); uint64_t StackSize = FrameInfo.getStackSize(); OutStreamer->EmitSymbolValue(FunctionSymbol, TM.getProgramPointerSize()); - OutStreamer->EmitULEB128IntValue(StackSize); + OutStreamer->emitULEB128IntValue(StackSize); OutStreamer->PopSection(); } @@ -1374,7 +1374,7 @@ void AsmPrinter::emitGlobalIndirectSymbol(Module &M, ? MCSA_ELF_TypeIndFunction : MCSA_ELF_TypeFunction); - EmitVisibility(Name, GIS.getVisibility()); + emitVisibility(Name, GIS.getVisibility()); const MCExpr *Expr = lowerConstant(GIS.getIndirectSymbol()); @@ -1459,7 +1459,7 @@ bool AsmPrinter::doFinalization(Module &M) { continue; MCSymbol *Name = getSymbol(&F); - EmitVisibility(Name, V, false); + emitVisibility(Name, V, false); } // Emit the remarks section contents. @@ -2182,7 +2182,7 @@ void AsmPrinter::emitInt64(uint64_t Value) const { /// Emit something like ".long Hi-Lo" where the size in bytes of the directive /// is specified by Size and Hi/Lo specify the labels. This implicitly uses /// .set if it avoids relocations. -void AsmPrinter::EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, +void AsmPrinter::emitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, unsigned Size) const { OutStreamer->emitAbsoluteSymbolDiff(Hi, Lo, Size); } @@ -2190,7 +2190,7 @@ void AsmPrinter::EmitLabelDifference(const MCSymbol *Hi, const MCSymbol *Lo, /// EmitLabelPlusOffset - Emit something like ".long Label+Offset" /// where the size in bytes of the directive is specified by Size and Label /// specifies the label. This implicitly uses .set if it is available. -void AsmPrinter::EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, +void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, unsigned Size, bool IsSectionRelative) const { if (MAI->needsDwarfSectionOffsetDirective() && IsSectionRelative) { @@ -3043,7 +3043,7 @@ void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { void AsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) {} -void AsmPrinter::EmitVisibility(MCSymbol *Sym, unsigned Visibility, +void AsmPrinter::emitVisibility(MCSymbol *Sym, unsigned Visibility, bool IsDefinition) const { MCSymbolAttr Attr = MCSA_Invalid; diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index 992e44d953062..09dc62e439874 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -36,22 +36,23 @@ using namespace llvm; //===----------------------------------------------------------------------===// /// EmitSLEB128 - emit the specified signed leb128 value. -void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const { +void AsmPrinter::emitSLEB128(int64_t Value, const char *Desc) const { if (isVerbose() && Desc) OutStreamer->AddComment(Desc); - OutStreamer->EmitSLEB128IntValue(Value); + OutStreamer->emitSLEB128IntValue(Value); } -void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc, unsigned PadTo) const { +void AsmPrinter::emitULEB128(uint64_t Value, const char *Desc, + unsigned PadTo) const { if (isVerbose() && Desc) OutStreamer->AddComment(Desc); - OutStreamer->EmitULEB128IntValue(Value, PadTo); + OutStreamer->emitULEB128IntValue(Value, PadTo); } /// Emit something like ".uleb128 Hi-Lo". -void AsmPrinter::EmitLabelDifferenceAsULEB128(const MCSymbol *Hi, +void AsmPrinter::emitLabelDifferenceAsULEB128(const MCSymbol *Hi, const MCSymbol *Lo) const { OutStreamer->emitAbsoluteSymbolDiffAsULEB128(Hi, Lo); } @@ -165,7 +166,7 @@ void AsmPrinter::emitDwarfSymbolReference(const MCSymbol *Label, } // Otherwise, emit it as a label difference from the start of the section. - EmitLabelDifference(Label, Label->getSection().getBeginSymbol(), 4); + emitLabelDifference(Label, Label->getSection().getBeginSymbol(), 4); } void AsmPrinter::emitDwarfStringOffset(DwarfStringPoolEntry S) const { @@ -179,25 +180,23 @@ void AsmPrinter::emitDwarfStringOffset(DwarfStringPoolEntry S) const { emitInt32(S.Offset); } -void AsmPrinter::EmitDwarfOffset(const MCSymbol *Label, uint64_t Offset) const { - EmitLabelPlusOffset(Label, Offset, MAI->getCodePointerSize()); +void AsmPrinter::emitDwarfOffset(const MCSymbol *Label, uint64_t Offset) const { + emitLabelPlusOffset(Label, Offset, MAI->getCodePointerSize()); } -void AsmPrinter::EmitCallSiteOffset(const MCSymbol *Hi, - const MCSymbol *Lo, +void AsmPrinter::emitCallSiteOffset(const MCSymbol *Hi, const MCSymbol *Lo, unsigned Encoding) const { // The least significant 3 bits specify the width of the encoding if ((Encoding & 0x7) == dwarf::DW_EH_PE_uleb128) - EmitLabelDifferenceAsULEB128(Hi, Lo); + emitLabelDifferenceAsULEB128(Hi, Lo); else - EmitLabelDifference(Hi, Lo, GetSizeOfEncodedValue(Encoding)); + emitLabelDifference(Hi, Lo, GetSizeOfEncodedValue(Encoding)); } -void AsmPrinter::EmitCallSiteValue(uint64_t Value, - unsigned Encoding) const { +void AsmPrinter::emitCallSiteValue(uint64_t Value, unsigned Encoding) const { // The least significant 3 bits specify the width of the encoding if ((Encoding & 0x7) == dwarf::DW_EH_PE_uleb128) - EmitULEB128(Value); + emitULEB128(Value); else OutStreamer->EmitIntValue(Value, GetSizeOfEncodedValue(Encoding)); } @@ -256,7 +255,7 @@ void AsmPrinter::emitDwarfDIE(const DIE &Die) const { Twine::utohexstr(Die.getOffset()) + ":0x" + Twine::utohexstr(Die.getSize()) + " " + dwarf::TagString(Die.getTag())); - EmitULEB128(Die.getAbbrevNumber()); + emitULEB128(Die.getAbbrevNumber()); // Emit the DIE attribute values. for (const auto &V : Die.values()) { @@ -286,7 +285,7 @@ void AsmPrinter::emitDwarfDIE(const DIE &Die) const { void AsmPrinter::emitDwarfAbbrev(const DIEAbbrev &Abbrev) const { // Emit the abbreviations code (base 1 index.) - EmitULEB128(Abbrev.getNumber(), "Abbreviation Code"); + emitULEB128(Abbrev.getNumber(), "Abbreviation Code"); // Emit the abbreviations data. Abbrev.Emit(this); diff --git a/llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h b/llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h index b60f68ca59b85..90929a217368e 100644 --- a/llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h +++ b/llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h @@ -30,8 +30,9 @@ class ByteStreamer { public: // For now we're just handling the calls we need for dwarf emission/hashing. virtual void EmitInt8(uint8_t Byte, const Twine &Comment = "") = 0; - virtual void EmitSLEB128(uint64_t DWord, const Twine &Comment = "") = 0; - virtual void EmitULEB128(uint64_t DWord, const Twine &Comment = "", unsigned PadTo = 0) = 0; + virtual void emitSLEB128(uint64_t DWord, const Twine &Comment = "") = 0; + virtual void emitULEB128(uint64_t DWord, const Twine &Comment = "", + unsigned PadTo = 0) = 0; }; class APByteStreamer final : public ByteStreamer { @@ -44,13 +45,14 @@ class APByteStreamer final : public ByteStreamer { AP.OutStreamer->AddComment(Comment); AP.emitInt8(Byte); } - void EmitSLEB128(uint64_t DWord, const Twine &Comment) override { + void emitSLEB128(uint64_t DWord, const Twine &Comment) override { AP.OutStreamer->AddComment(Comment); - AP.EmitSLEB128(DWord); + AP.emitSLEB128(DWord); } - void EmitULEB128(uint64_t DWord, const Twine &Comment, unsigned PadTo) override { + void emitULEB128(uint64_t DWord, const Twine &Comment, + unsigned PadTo) override { AP.OutStreamer->AddComment(Comment); - AP.EmitULEB128(DWord, nullptr, PadTo); + AP.emitULEB128(DWord, nullptr, PadTo); } }; @@ -62,10 +64,11 @@ class HashingByteStreamer final : public ByteStreamer { void EmitInt8(uint8_t Byte, const Twine &Comment) override { Hash.update(Byte); } - void EmitSLEB128(uint64_t DWord, const Twine &Comment) override { + void emitSLEB128(uint64_t DWord, const Twine &Comment) override { Hash.addSLEB128(DWord); } - void EmitULEB128(uint64_t DWord, const Twine &Comment, unsigned PadTo) override { + void emitULEB128(uint64_t DWord, const Twine &Comment, + unsigned PadTo) override { Hash.addULEB128(DWord); } }; @@ -90,7 +93,7 @@ class BufferByteStreamer final : public ByteStreamer { if (GenerateComments) Comments.push_back(Comment.str()); } - void EmitSLEB128(uint64_t DWord, const Twine &Comment) override { + void emitSLEB128(uint64_t DWord, const Twine &Comment) override { raw_svector_ostream OSE(Buffer); unsigned Length = encodeSLEB128(DWord, OSE); if (GenerateComments) { @@ -102,7 +105,8 @@ class BufferByteStreamer final : public ByteStreamer { } } - void EmitULEB128(uint64_t DWord, const Twine &Comment, unsigned PadTo) override { + void emitULEB128(uint64_t DWord, const Twine &Comment, + unsigned PadTo) override { raw_svector_ostream OSE(Buffer); unsigned Length = encodeULEB128(DWord, OSE, PadTo); if (GenerateComments) { diff --git a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp index 84b86a71fa5fe..5f137f4702e99 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DIE.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DIE.cpp @@ -67,17 +67,17 @@ void DIEAbbrev::Profile(FoldingSetNodeID &ID) const { /// void DIEAbbrev::Emit(const AsmPrinter *AP) const { // Emit its Dwarf tag type. - AP->EmitULEB128(Tag, dwarf::TagString(Tag).data()); + AP->emitULEB128(Tag, dwarf::TagString(Tag).data()); // Emit whether it has children DIEs. - AP->EmitULEB128((unsigned)Children, dwarf::ChildrenString(Children).data()); + AP->emitULEB128((unsigned)Children, dwarf::ChildrenString(Children).data()); // For each attribute description. for (unsigned i = 0, N = Data.size(); i < N; ++i) { const DIEAbbrevData &AttrData = Data[i]; // Emit attribute type. - AP->EmitULEB128(AttrData.getAttribute(), + AP->emitULEB128(AttrData.getAttribute(), dwarf::AttributeString(AttrData.getAttribute()).data()); // Emit form type. @@ -92,17 +92,17 @@ void DIEAbbrev::Emit(const AsmPrinter *AP) const { llvm_unreachable("Invalid form for specified DWARF version"); } #endif - AP->EmitULEB128(AttrData.getForm(), + AP->emitULEB128(AttrData.getForm(), dwarf::FormEncodingString(AttrData.getForm()).data()); // Emit value for DW_FORM_implicit_const. if (AttrData.getForm() == dwarf::DW_FORM_implicit_const) - AP->EmitSLEB128(AttrData.getValue()); + AP->emitSLEB128(AttrData.getValue()); } // Mark end of abbreviation. - AP->EmitULEB128(0, "EOM(1)"); - AP->EmitULEB128(0, "EOM(2)"); + AP->emitULEB128(0, "EOM(1)"); + AP->emitULEB128(0, "EOM(2)"); } LLVM_DUMP_METHOD @@ -418,10 +418,10 @@ void DIEInteger::EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const { case dwarf::DW_FORM_addrx: case dwarf::DW_FORM_rnglistx: case dwarf::DW_FORM_udata: - Asm->EmitULEB128(Integer); + Asm->emitULEB128(Integer); return; case dwarf::DW_FORM_sdata: - Asm->EmitSLEB128(Integer); + Asm->emitSLEB128(Integer); return; default: llvm_unreachable("DIE Value form not supported yet"); } @@ -466,7 +466,7 @@ void DIEInteger::print(raw_ostream &O) const { /// EmitValue - Emit expression value. /// void DIEExpr::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { - AP->EmitDebugValue(Expr, SizeOf(AP, Form)); + AP->emitDebugValue(Expr, SizeOf(AP, Form)); } /// SizeOf - Determine size of expression value in bytes. @@ -488,11 +488,10 @@ void DIEExpr::print(raw_ostream &O) const { O << "Expr: " << *Expr; } /// EmitValue - Emit label value. /// void DIELabel::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { - AP->EmitLabelReference(Label, SizeOf(AP, Form), - Form == dwarf::DW_FORM_strp || - Form == dwarf::DW_FORM_sec_offset || - Form == dwarf::DW_FORM_ref_addr || - Form == dwarf::DW_FORM_data4); + AP->emitLabelReference( + Label, SizeOf(AP, Form), + Form == dwarf::DW_FORM_strp || Form == dwarf::DW_FORM_sec_offset || + Form == dwarf::DW_FORM_ref_addr || Form == dwarf::DW_FORM_data4); } /// SizeOf - Determine size of label value in bytes. @@ -514,7 +513,7 @@ void DIELabel::print(raw_ostream &O) const { O << "Lbl: " << Label->getName(); } void DIEBaseTypeRef::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { uint64_t Offset = CU->ExprRefedBaseTypes[Index].Die->getOffset(); assert(Offset < (1ULL << (ULEB128PadSize * 7)) && "Offset wont fit"); - AP->EmitULEB128(Offset, nullptr, ULEB128PadSize); + AP->emitULEB128(Offset, nullptr, ULEB128PadSize); } unsigned DIEBaseTypeRef::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { @@ -531,7 +530,7 @@ void DIEBaseTypeRef::print(raw_ostream &O) const { O << "BaseTypeRef: " << Index /// EmitValue - Emit delta value. /// void DIEDelta::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { - AP->EmitLabelDifference(LabelHi, LabelLo, SizeOf(AP, Form)); + AP->emitLabelDifference(LabelHi, LabelLo, SizeOf(AP, Form)); } /// SizeOf - Determine size of delta value in bytes. @@ -641,7 +640,7 @@ void DIEEntry::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { return; case dwarf::DW_FORM_ref_udata: - AP->EmitULEB128(Entry->getOffset()); + AP->emitULEB128(Entry->getOffset()); return; case dwarf::DW_FORM_ref_addr: { @@ -649,7 +648,7 @@ void DIEEntry::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { unsigned Addr = Entry->getDebugSectionOffset(); if (const MCSymbol *SectionSym = Entry->getUnit()->getCrossSectionRelativeBaseAddress()) { - AP->EmitLabelPlusOffset(SectionSym, Addr, SizeOf(AP, Form), true); + AP->emitLabelPlusOffset(SectionSym, Addr, SizeOf(AP, Form), true); return; } @@ -719,7 +718,8 @@ void DIELoc::EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const { case dwarf::DW_FORM_block4: Asm->emitInt32(Size); break; case dwarf::DW_FORM_block: case dwarf::DW_FORM_exprloc: - Asm->EmitULEB128(Size); break; + Asm->emitULEB128(Size); + break; } for (const auto &V : values()) @@ -768,7 +768,9 @@ void DIEBlock::EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const { case dwarf::DW_FORM_block1: Asm->emitInt8(Size); break; case dwarf::DW_FORM_block2: Asm->emitInt16(Size); break; case dwarf::DW_FORM_block4: Asm->emitInt32(Size); break; - case dwarf::DW_FORM_block: Asm->EmitULEB128(Size); break; + case dwarf::DW_FORM_block: + Asm->emitULEB128(Size); + break; case dwarf::DW_FORM_string: break; case dwarf::DW_FORM_data16: break; } @@ -813,7 +815,7 @@ unsigned DIELocList::SizeOf(const AsmPrinter *AP, dwarf::Form Form) const { /// void DIELocList::EmitValue(const AsmPrinter *AP, dwarf::Form Form) const { if (Form == dwarf::DW_FORM_loclistx) { - AP->EmitULEB128(Index); + AP->emitULEB128(Index); return; } DwarfDebug *DD = AP->getDwarfDebug(); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp index 0d501eaa00cdb..ea94067964ecd 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -113,8 +113,9 @@ unsigned DwarfCompileUnit::getOrCreateSourceID(const DIFile *File) { // extend .file to support this. unsigned CUID = Asm->OutStreamer->hasRawTextSupport() ? 0 : getUniqueID(); if (!File) - return Asm->OutStreamer->EmitDwarfFileDirective(0, "", "", None, None, CUID); - return Asm->OutStreamer->EmitDwarfFileDirective( + return Asm->OutStreamer->emitDwarfFileDirective(0, "", "", None, None, + CUID); + return Asm->OutStreamer->emitDwarfFileDirective( 0, File->getDirectory(), File->getFilename(), getMD5AsBytes(File), File->getSource(), CUID); } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index c1e7d9fe0211f..6f011fe497891 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -176,11 +176,11 @@ void DebugLocDwarfExpression::emitOp(uint8_t Op, const char *Comment) { } void DebugLocDwarfExpression::emitSigned(int64_t Value) { - getActiveStreamer().EmitSLEB128(Value, Twine(Value)); + getActiveStreamer().emitSLEB128(Value, Twine(Value)); } void DebugLocDwarfExpression::emitUnsigned(uint64_t Value) { - getActiveStreamer().EmitULEB128(Value, Twine(Value)); + getActiveStreamer().emitULEB128(Value, Twine(Value)); } void DebugLocDwarfExpression::emitData1(uint8_t Value) { @@ -189,7 +189,7 @@ void DebugLocDwarfExpression::emitData1(uint8_t Value) { void DebugLocDwarfExpression::emitBaseTypeRef(uint64_t Idx) { assert(Idx < (1ULL << (ULEB128PadSize * 7)) && "Idx wont fit"); - getActiveStreamer().EmitULEB128(Idx, Twine(Idx), ULEB128PadSize); + getActiveStreamer().emitULEB128(Idx, Twine(Idx), ULEB128PadSize); } bool DebugLocDwarfExpression::isFrameRegister(const TargetRegisterInfo &TRI, @@ -1840,7 +1840,7 @@ static void recordSourceLine(AsmPrinter &Asm, unsigned Line, unsigned Col, FileNo = static_cast(*DCUs[CUID]) .getOrCreateSourceID(Scope->getFile()); } - Asm.OutStreamer->EmitDwarfLocDirective(FileNo, Line, Col, Flags, 0, + Asm.OutStreamer->emitDwarfLocDirective(FileNo, Line, Col, Flags, 0, Discriminator, Fn); } @@ -2148,7 +2148,7 @@ void DwarfDebug::emitDebugPubSections() { void DwarfDebug::emitSectionReference(const DwarfCompileUnit &CU) { if (useSectionsAsReferences()) - Asm->EmitDwarfOffset(CU.getSection()->getBeginSymbol(), + Asm->emitDwarfOffset(CU.getSection()->getBeginSymbol(), CU.getDebugSectionOffset()); else Asm->emitDwarfSymbolReference(CU.getLabelBegin()); @@ -2164,7 +2164,7 @@ void DwarfDebug::emitDebugPubSection(bool GnuStyle, StringRef Name, Asm->OutStreamer->AddComment("Length of Public " + Name + " Info"); MCSymbol *BeginLabel = Asm->createTempSymbol("pub" + Name + "_begin"); MCSymbol *EndLabel = Asm->createTempSymbol("pub" + Name + "_end"); - Asm->EmitLabelDifference(EndLabel, BeginLabel, 4); + Asm->emitLabelDifference(EndLabel, BeginLabel, 4); Asm->OutStreamer->EmitLabel(BeginLabel); @@ -2246,7 +2246,7 @@ void DwarfDebug::emitDebugLocEntry(ByteStreamer &Streamer, uint64_t Offset = CU->ExprRefedBaseTypes[Op.getRawOperand(I)].Die->getOffset(); assert(Offset < (1ULL << (ULEB128PadSize * 7)) && "Offset wont fit"); - Streamer.EmitULEB128(Offset, "", ULEB128PadSize); + Streamer.emitULEB128(Offset, "", ULEB128PadSize); // Make sure comments stay aligned. for (unsigned J = 0; J < ULEB128PadSize; ++J) if (Comment != End) @@ -2337,7 +2337,7 @@ void DwarfDebug::emitDebugLocEntryLocation(const DebugLocStream::Entry &Entry, // Emit the size. Asm->OutStreamer->AddComment("Loc expr size"); if (getDwarfVersion() >= 5) - Asm->EmitULEB128(DebugLocs.getBytes(Entry).size()); + Asm->emitULEB128(DebugLocs.getBytes(Entry).size()); else if (DebugLocs.getBytes(Entry).size() <= std::numeric_limits::max()) Asm->emitInt16(DebugLocs.getBytes(Entry).size()); else { @@ -2357,7 +2357,7 @@ static void emitListsTableHeaderStart(AsmPrinter *Asm, MCSymbol *TableEnd) { // Build the table header, which starts with the length field. Asm->OutStreamer->AddComment("Length"); - Asm->EmitLabelDifference(TableEnd, TableStart, 4); + Asm->emitLabelDifference(TableEnd, TableStart, 4); Asm->OutStreamer->EmitLabel(TableStart); // Version number (DWARF v5 and later). Asm->OutStreamer->AddComment("Version"); @@ -2384,8 +2384,7 @@ static MCSymbol *emitRnglistsTableHeader(AsmPrinter *Asm, Asm->OutStreamer->EmitLabel(Holder.getRnglistsTableBaseSym()); for (const RangeSpanList &List : Holder.getRangeLists()) - Asm->EmitLabelDifference(List.Label, Holder.getRnglistsTableBaseSym(), - 4); + Asm->emitLabelDifference(List.Label, Holder.getRnglistsTableBaseSym(), 4); return TableEnd; } @@ -2406,7 +2405,7 @@ static MCSymbol *emitLoclistsTableHeader(AsmPrinter *Asm, Asm->OutStreamer->EmitLabel(DebugLocs.getSym()); for (const auto &List : DebugLocs.getLists()) - Asm->EmitLabelDifference(List.Label, DebugLocs.getSym(), 4); + Asm->emitLabelDifference(List.Label, DebugLocs.getSym(), 4); return TableEnd; } @@ -2455,7 +2454,7 @@ static void emitRangeList( Asm->OutStreamer->AddComment(StringifyEnum(BaseAddressx)); Asm->emitInt8(BaseAddressx); Asm->OutStreamer->AddComment(" base address index"); - Asm->EmitULEB128(DD.getAddressPool().getIndex(Base)); + Asm->emitULEB128(DD.getAddressPool().getIndex(Base)); } } else if (BaseIsSet && !UseDwarf5) { BaseIsSet = false; @@ -2475,20 +2474,20 @@ static void emitRangeList( Asm->OutStreamer->AddComment(StringifyEnum(OffsetPair)); Asm->emitInt8(OffsetPair); Asm->OutStreamer->AddComment(" starting offset"); - Asm->EmitLabelDifferenceAsULEB128(Begin, Base); + Asm->emitLabelDifferenceAsULEB128(Begin, Base); Asm->OutStreamer->AddComment(" ending offset"); - Asm->EmitLabelDifferenceAsULEB128(End, Base); + Asm->emitLabelDifferenceAsULEB128(End, Base); } else { - Asm->EmitLabelDifference(Begin, Base, Size); - Asm->EmitLabelDifference(End, Base, Size); + Asm->emitLabelDifference(Begin, Base, Size); + Asm->emitLabelDifference(End, Base, Size); } } else if (UseDwarf5) { Asm->OutStreamer->AddComment(StringifyEnum(StartxLength)); Asm->emitInt8(StartxLength); Asm->OutStreamer->AddComment(" start index"); - Asm->EmitULEB128(DD.getAddressPool().getIndex(Begin)); + Asm->emitULEB128(DD.getAddressPool().getIndex(Begin)); Asm->OutStreamer->AddComment(" length"); - Asm->EmitLabelDifferenceAsULEB128(End, Begin); + Asm->emitLabelDifferenceAsULEB128(End, Begin); } else { Asm->OutStreamer->EmitSymbolValue(Begin, Size); Asm->OutStreamer->EmitSymbolValue(End, Size); @@ -2569,10 +2568,10 @@ void DwarfDebug::emitDebugLocDWO() { // addresses in the address pool to minimize object size/relocations. Asm->emitInt8(dwarf::DW_LLE_startx_length); unsigned idx = AddrPool.getIndex(Entry.Begin); - Asm->EmitULEB128(idx); + Asm->emitULEB128(idx); // Also the pre-standard encoding is slightly different, emitting this as // an address-length entry here, but its a ULEB128 in DWARFv5 loclists. - Asm->EmitLabelDifference(Entry.End, Entry.Begin, 4); + Asm->emitLabelDifference(Entry.End, Entry.Begin, 4); emitDebugLocEntryLocation(Entry, List.CU); } Asm->emitInt8(dwarf::DW_LLE_end_of_list); @@ -2717,11 +2716,11 @@ void DwarfDebug::emitDebugARanges() { Asm->OutStreamer->emitFill(Padding, 0xff); for (const ArangeSpan &Span : List) { - Asm->EmitLabelReference(Span.Start, PtrSize); + Asm->emitLabelReference(Span.Start, PtrSize); // Calculate the size as being from the span start to it's end. if (Span.End) { - Asm->EmitLabelDifference(Span.End, Span.Start, PtrSize); + Asm->emitLabelDifference(Span.End, Span.Start, PtrSize); } else { // For symbols without an end marker (e.g. common), we // write a single arange entry containing just that one symbol. @@ -2802,8 +2801,8 @@ void DwarfDebug::handleMacroNodes(DIMacroNodeArray Nodes, DwarfCompileUnit &U) { } void DwarfDebug::emitMacro(DIMacro &M) { - Asm->EmitULEB128(M.getMacinfoType()); - Asm->EmitULEB128(M.getLine()); + Asm->emitULEB128(M.getMacinfoType()); + Asm->emitULEB128(M.getLine()); StringRef Name = M.getName(); StringRef Value = M.getValue(); Asm->OutStreamer->EmitBytes(Name); @@ -2817,11 +2816,11 @@ void DwarfDebug::emitMacro(DIMacro &M) { void DwarfDebug::emitMacroFile(DIMacroFile &F, DwarfCompileUnit &U) { assert(F.getMacinfoType() == dwarf::DW_MACINFO_start_file); - Asm->EmitULEB128(dwarf::DW_MACINFO_start_file); - Asm->EmitULEB128(F.getLine()); - Asm->EmitULEB128(U.getOrCreateSourceID(F.getFile())); + Asm->emitULEB128(dwarf::DW_MACINFO_start_file); + Asm->emitULEB128(F.getLine()); + Asm->emitULEB128(U.getOrCreateSourceID(F.getFile())); handleMacroNodes(F.getElements(), U); - Asm->EmitULEB128(dwarf::DW_MACINFO_end_file); + Asm->emitULEB128(dwarf::DW_MACINFO_end_file); } void DwarfDebug::emitDebugMacinfoImpl(MCSection *Section) { diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp index 76ac2e049fc15..8b15e26d7d9a1 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp @@ -1628,7 +1628,7 @@ void DwarfUnit::emitCommonHeader(bool UseOffsets, dwarf::UnitType UT) { StringRef Prefix = isDwoUnit() ? "debug_info_dwo_" : "debug_info_"; MCSymbol *BeginLabel = Asm->createTempSymbol(Prefix + "start"); EndLabel = Asm->createTempSymbol(Prefix + "end"); - Asm->EmitLabelDifference(EndLabel, BeginLabel, 4); + Asm->emitLabelDifference(EndLabel, BeginLabel, 4); Asm->OutStreamer->EmitLabel(BeginLabel); } else Asm->emitInt32(getHeaderSize() + getUnitDie().getSize()); diff --git a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp index 31dfaaac836eb..583a9ba839dd9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp @@ -447,7 +447,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { // the type table. See PR35809 or GNU as bug 4029. MCSymbol *TTBaseRefLabel = Asm->createTempSymbol("ttbaseref"); TTBaseLabel = Asm->createTempSymbol("ttbase"); - Asm->EmitLabelDifferenceAsULEB128(TTBaseLabel, TTBaseRefLabel); + Asm->emitLabelDifferenceAsULEB128(TTBaseLabel, TTBaseRefLabel); Asm->OutStreamer->EmitLabel(TTBaseRefLabel); } @@ -457,7 +457,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { MCSymbol *CstBeginLabel = Asm->createTempSymbol("cst_begin"); MCSymbol *CstEndLabel = Asm->createTempSymbol("cst_end"); Asm->EmitEncodingByte(CallSiteEncoding, "Call site"); - Asm->EmitLabelDifferenceAsULEB128(CstEndLabel, CstBeginLabel); + Asm->emitLabelDifferenceAsULEB128(CstEndLabel, CstBeginLabel); Asm->OutStreamer->EmitLabel(CstBeginLabel); // SjLj / Wasm Exception handling @@ -472,7 +472,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { Asm->OutStreamer->AddComment(">> Call Site " + Twine(idx) + " <<"); Asm->OutStreamer->AddComment(" On exception at call site "+Twine(idx)); } - Asm->EmitULEB128(idx); + Asm->emitULEB128(idx); // Offset of the first associated action record, relative to the start of // the action table. This value is biased by 1 (1 indicates the start of @@ -484,7 +484,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { Asm->OutStreamer->AddComment(" Action: " + Twine((S.Action - 1) / 2 + 1)); } - Asm->EmitULEB128(S.Action); + Asm->emitULEB128(S.Action); } } else { // Itanium LSDA exception handling @@ -524,23 +524,23 @@ MCSymbol *EHStreamer::emitExceptionTable() { // Offset of the call site relative to the start of the procedure. if (VerboseAsm) Asm->OutStreamer->AddComment(">> Call Site " + Twine(++Entry) + " <<"); - Asm->EmitCallSiteOffset(BeginLabel, EHFuncBeginSym, CallSiteEncoding); + Asm->emitCallSiteOffset(BeginLabel, EHFuncBeginSym, CallSiteEncoding); if (VerboseAsm) Asm->OutStreamer->AddComment(Twine(" Call between ") + BeginLabel->getName() + " and " + EndLabel->getName()); - Asm->EmitCallSiteOffset(EndLabel, BeginLabel, CallSiteEncoding); + Asm->emitCallSiteOffset(EndLabel, BeginLabel, CallSiteEncoding); // Offset of the landing pad relative to the start of the procedure. if (!S.LPad) { if (VerboseAsm) Asm->OutStreamer->AddComment(" has no landing pad"); - Asm->EmitCallSiteValue(0, CallSiteEncoding); + Asm->emitCallSiteValue(0, CallSiteEncoding); } else { if (VerboseAsm) Asm->OutStreamer->AddComment(Twine(" jumps to ") + S.LPad->LandingPadLabel->getName()); - Asm->EmitCallSiteOffset(S.LPad->LandingPadLabel, EHFuncBeginSym, + Asm->emitCallSiteOffset(S.LPad->LandingPadLabel, EHFuncBeginSym, CallSiteEncoding); } @@ -554,7 +554,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { Asm->OutStreamer->AddComment(" On action: " + Twine((S.Action - 1) / 2 + 1)); } - Asm->EmitULEB128(S.Action); + Asm->emitULEB128(S.Action); } } Asm->OutStreamer->EmitLabel(CstEndLabel); @@ -584,7 +584,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { else Asm->OutStreamer->AddComment(" Cleanup"); } - Asm->EmitSLEB128(Action.ValueForTypeID); + Asm->emitSLEB128(Action.ValueForTypeID); // Action Record // @@ -598,7 +598,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { Asm->OutStreamer->AddComment(" Continue to action "+Twine(NextAction)); } } - Asm->EmitSLEB128(Action.NextAction); + Asm->emitSLEB128(Action.NextAction); } if (HaveTTData) { @@ -649,6 +649,6 @@ void EHStreamer::emitTypeInfos(unsigned TTypeEncoding, MCSymbol *TTBaseLabel) { Asm->OutStreamer->AddComment("FilterInfo " + Twine(Entry)); } - Asm->EmitULEB128(TypeID); + Asm->emitULEB128(TypeID); } } diff --git a/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp index 3849644d15844..989da7e0cd413 100644 --- a/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp @@ -84,7 +84,7 @@ void ErlangGCPrinter::finishAssembly(Module &M, GCModuleInfo &Info, // Emit the address of the safe point. OS.AddComment("safe point address"); MCSymbol *Label = PI->Label; - AP.EmitLabelPlusOffset(Label /*Hi*/, 0 /*Offset*/, 4 /*Size*/); + AP.emitLabelPlusOffset(Label /*Hi*/, 0 /*Offset*/, 4 /*Size*/); } // Stack information never change in safe points! Only print info from the diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index 50d030f32c3aa..c2d180813989d 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -198,9 +198,9 @@ class MCAsmStreamer final : public MCStreamer { void EmitIntValueInHex(uint64_t Value, unsigned Size) override; void EmitIntValueInHexWithPadding(uint64_t Value, unsigned Size) override; - void EmitULEB128Value(const MCExpr *Value) override; + void emitULEB128Value(const MCExpr *Value) override; - void EmitSLEB128Value(const MCExpr *Value) override; + void emitSLEB128Value(const MCExpr *Value) override; void EmitDTPRel32Value(const MCExpr *Value) override; void EmitDTPRel64Value(const MCExpr *Value) override; @@ -239,9 +239,9 @@ class MCAsmStreamer final : public MCStreamer { Optional Checksum, Optional Source, unsigned CUID = 0) override; - void EmitDwarfLocDirective(unsigned FileNo, unsigned Line, - unsigned Column, unsigned Flags, - unsigned Isa, unsigned Discriminator, + void emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, + unsigned Flags, unsigned Isa, + unsigned Discriminator, StringRef FileName) override; MCSymbol *getDwarfLineTableSymbol(unsigned CUID) override; @@ -1037,10 +1037,10 @@ void MCAsmStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, } } -void MCAsmStreamer::EmitULEB128Value(const MCExpr *Value) { +void MCAsmStreamer::emitULEB128Value(const MCExpr *Value) { int64_t IntValue; if (Value->evaluateAsAbsolute(IntValue)) { - EmitULEB128IntValue(IntValue); + emitULEB128IntValue(IntValue); return; } OS << "\t.uleb128 "; @@ -1048,10 +1048,10 @@ void MCAsmStreamer::EmitULEB128Value(const MCExpr *Value) { EmitEOL(); } -void MCAsmStreamer::EmitSLEB128Value(const MCExpr *Value) { +void MCAsmStreamer::emitSLEB128Value(const MCExpr *Value) { int64_t IntValue; if (Value->evaluateAsAbsolute(IntValue)) { - EmitSLEB128IntValue(IntValue); + emitSLEB128IntValue(IntValue); return; } OS << "\t.sleb128 "; @@ -1313,10 +1313,9 @@ void MCAsmStreamer::emitDwarfFile0Directive(StringRef Directory, EmitRawText(OS1.str()); } -void MCAsmStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, +void MCAsmStreamer::emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, unsigned Flags, - unsigned Isa, - unsigned Discriminator, + unsigned Isa, unsigned Discriminator, StringRef FileName) { OS << "\t.loc\t" << FileNo << " " << Line << " " << Column; if (MAI->supportsExtendedDwarfLocDirective()) { @@ -1349,8 +1348,8 @@ void MCAsmStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, << Line << ':' << Column; } EmitEOL(); - this->MCStreamer::EmitDwarfLocDirective(FileNo, Line, Column, Flags, - Isa, Discriminator, FileName); + this->MCStreamer::emitDwarfLocDirective(FileNo, Line, Column, Flags, Isa, + Discriminator, FileName); } MCSymbol *MCAsmStreamer::getDwarfLineTableSymbol(unsigned CUID) { diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index 1a328222916b9..e53f00a5b4450 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -146,9 +146,9 @@ makeStartPlusIntExpr(MCContext &Ctx, const MCSymbol &Start, int IntVal) { // This emits the Dwarf line table for the specified section from the entries // in the LineSection. // -static inline void -EmitDwarfLineTable(MCObjectStreamer *MCOS, MCSection *Section, - const MCLineSection::MCDwarfLineEntryCollection &LineEntries) { +static inline void emitDwarfLineTable( + MCObjectStreamer *MCOS, MCSection *Section, + const MCLineSection::MCDwarfLineEntryCollection &LineEntries) { unsigned FileNum = 1; unsigned LastLine = 1; unsigned Column = 0; @@ -164,26 +164,26 @@ EmitDwarfLineTable(MCObjectStreamer *MCOS, MCSection *Section, if (FileNum != LineEntry.getFileNum()) { FileNum = LineEntry.getFileNum(); MCOS->EmitIntValue(dwarf::DW_LNS_set_file, 1); - MCOS->EmitULEB128IntValue(FileNum); + MCOS->emitULEB128IntValue(FileNum); } if (Column != LineEntry.getColumn()) { Column = LineEntry.getColumn(); MCOS->EmitIntValue(dwarf::DW_LNS_set_column, 1); - MCOS->EmitULEB128IntValue(Column); + MCOS->emitULEB128IntValue(Column); } if (Discriminator != LineEntry.getDiscriminator() && MCOS->getContext().getDwarfVersion() >= 4) { Discriminator = LineEntry.getDiscriminator(); unsigned Size = getULEB128Size(Discriminator); MCOS->EmitIntValue(dwarf::DW_LNS_extended_op, 1); - MCOS->EmitULEB128IntValue(Size + 1); + MCOS->emitULEB128IntValue(Size + 1); MCOS->EmitIntValue(dwarf::DW_LNE_set_discriminator, 1); - MCOS->EmitULEB128IntValue(Discriminator); + MCOS->emitULEB128IntValue(Discriminator); } if (Isa != LineEntry.getIsa()) { Isa = LineEntry.getIsa(); MCOS->EmitIntValue(dwarf::DW_LNS_set_isa, 1); - MCOS->EmitULEB128IntValue(Isa); + MCOS->emitULEB128IntValue(Isa); } if ((LineEntry.getFlags() ^ Flags) & DWARF2_FLAG_IS_STMT) { Flags = LineEntry.getFlags(); @@ -202,7 +202,7 @@ EmitDwarfLineTable(MCObjectStreamer *MCOS, MCSection *Section, // line numbers and the increment of the address from the previous Label // and the current Label. const MCAsmInfo *asmInfo = MCOS->getContext().getAsmInfo(); - MCOS->EmitDwarfAdvanceLineAddr(LineDelta, LastLabel, Label, + MCOS->emitDwarfAdvanceLineAddr(LineDelta, LastLabel, Label, asmInfo->getCodePointerSize()); Discriminator = 0; @@ -222,7 +222,7 @@ EmitDwarfLineTable(MCObjectStreamer *MCOS, MCSection *Section, MCOS->SwitchSection(Ctx.getObjectFileInfo()->getDwarfLineSection()); const MCAsmInfo *AsmInfo = Ctx.getAsmInfo(); - MCOS->EmitDwarfAdvanceLineAddr(INT64_MAX, LastLabel, SectionEnd, + MCOS->emitDwarfAdvanceLineAddr(INT64_MAX, LastLabel, SectionEnd, AsmInfo->getCodePointerSize()); } @@ -342,7 +342,7 @@ void MCDwarfLineTableHeader::emitV2FileDirTables(MCStreamer *MCOS) const { assert(!MCDwarfFiles[i].Name.empty()); MCOS->EmitBytes(MCDwarfFiles[i].Name); // FileName and... MCOS->EmitBytes(StringRef("\0", 1)); // its null terminator. - MCOS->EmitULEB128IntValue(MCDwarfFiles[i].DirIndex); // Directory number. + MCOS->emitULEB128IntValue(MCDwarfFiles[i].DirIndex); // Directory number. MCOS->EmitIntValue(0, 1); // Last modification timestamp (always 0). MCOS->EmitIntValue(0, 1); // File size (always 0). } @@ -359,7 +359,7 @@ static void emitOneV5FileEntry(MCStreamer *MCOS, const MCDwarfFile &DwarfFile, MCOS->EmitBytes(DwarfFile.Name); // FileName and... MCOS->EmitBytes(StringRef("\0", 1)); // its null terminator. } - MCOS->EmitULEB128IntValue(DwarfFile.DirIndex); // Directory number. + MCOS->emitULEB128IntValue(DwarfFile.DirIndex); // Directory number. if (EmitMD5) { const MD5::MD5Result &Cksum = *DwarfFile.Checksum; MCOS->EmitBinaryData( @@ -383,10 +383,10 @@ void MCDwarfLineTableHeader::emitV5FileDirTables( // non-split object, these are references to .debug_line_str; in a split // object, they are inline strings. MCOS->EmitIntValue(1, 1); - MCOS->EmitULEB128IntValue(dwarf::DW_LNCT_path); - MCOS->EmitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp + MCOS->emitULEB128IntValue(dwarf::DW_LNCT_path); + MCOS->emitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp : dwarf::DW_FORM_string); - MCOS->EmitULEB128IntValue(MCDwarfDirs.size() + 1); + MCOS->emitULEB128IntValue(MCDwarfDirs.size() + 1); // Try not to emit an empty compilation directory. const StringRef CompDir = CompilationDir.empty() ? MCOS->getContext().getCompilationDir() @@ -415,25 +415,25 @@ void MCDwarfLineTableHeader::emitV5FileDirTables( if (HasSource) Entries += 1; MCOS->EmitIntValue(Entries, 1); - MCOS->EmitULEB128IntValue(dwarf::DW_LNCT_path); - MCOS->EmitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp + MCOS->emitULEB128IntValue(dwarf::DW_LNCT_path); + MCOS->emitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp : dwarf::DW_FORM_string); - MCOS->EmitULEB128IntValue(dwarf::DW_LNCT_directory_index); - MCOS->EmitULEB128IntValue(dwarf::DW_FORM_udata); + MCOS->emitULEB128IntValue(dwarf::DW_LNCT_directory_index); + MCOS->emitULEB128IntValue(dwarf::DW_FORM_udata); if (HasAllMD5) { - MCOS->EmitULEB128IntValue(dwarf::DW_LNCT_MD5); - MCOS->EmitULEB128IntValue(dwarf::DW_FORM_data16); + MCOS->emitULEB128IntValue(dwarf::DW_LNCT_MD5); + MCOS->emitULEB128IntValue(dwarf::DW_FORM_data16); } if (HasSource) { - MCOS->EmitULEB128IntValue(dwarf::DW_LNCT_LLVM_source); - MCOS->EmitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp + MCOS->emitULEB128IntValue(dwarf::DW_LNCT_LLVM_source); + MCOS->emitULEB128IntValue(LineStr ? dwarf::DW_FORM_line_strp : dwarf::DW_FORM_string); } // Then the counted list of files. The root file is file #0, then emit the // files as provide by .file directives. // MCDwarfFiles has an unused element [0] so use size() not size()+1. // But sometimes MCDwarfFiles is empty, in which case we still emit one file. - MCOS->EmitULEB128IntValue(MCDwarfFiles.empty() ? 1 : MCDwarfFiles.size()); + MCOS->emitULEB128IntValue(MCDwarfFiles.empty() ? 1 : MCDwarfFiles.size()); // To accommodate assembler source written for DWARF v4 but trying to emit // v5: If we didn't see a root file explicitly, replicate file #1. assert((!RootFile.Name.empty() || MCDwarfFiles.size() >= 1) && @@ -527,7 +527,7 @@ void MCDwarfLineTable::EmitCU(MCObjectStreamer *MCOS, // Put out the line tables. for (const auto &LineSec : MCLineSections.getMCLineEntries()) - EmitDwarfLineTable(MCOS, LineSec.first, LineSec.second); + emitDwarfLineTable(MCOS, LineSec.first, LineSec.second); // This is the end of the section, so set the value of the symbol at the end // of this section (that was used in a previous expression). @@ -790,8 +790,8 @@ bool MCDwarfLineAddr::FixedEncode(MCContext &Context, // Utility function to write a tuple for .debug_abbrev. static void EmitAbbrev(MCStreamer *MCOS, uint64_t Name, uint64_t Form) { - MCOS->EmitULEB128IntValue(Name); - MCOS->EmitULEB128IntValue(Form); + MCOS->emitULEB128IntValue(Name); + MCOS->emitULEB128IntValue(Form); } // When generating dwarf for assembly source files this emits @@ -801,8 +801,8 @@ static void EmitGenDwarfAbbrev(MCStreamer *MCOS) { MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfAbbrevSection()); // DW_TAG_compile_unit DIE abbrev (1). - MCOS->EmitULEB128IntValue(1); - MCOS->EmitULEB128IntValue(dwarf::DW_TAG_compile_unit); + MCOS->emitULEB128IntValue(1); + MCOS->emitULEB128IntValue(dwarf::DW_TAG_compile_unit); MCOS->EmitIntValue(dwarf::DW_CHILDREN_yes, 1); EmitAbbrev(MCOS, dwarf::DW_AT_stmt_list, context.getDwarfVersion() >= 4 ? dwarf::DW_FORM_sec_offset @@ -827,8 +827,8 @@ static void EmitGenDwarfAbbrev(MCStreamer *MCOS) { EmitAbbrev(MCOS, 0, 0); // DW_TAG_label DIE abbrev (2). - MCOS->EmitULEB128IntValue(2); - MCOS->EmitULEB128IntValue(dwarf::DW_TAG_label); + MCOS->emitULEB128IntValue(2); + MCOS->emitULEB128IntValue(dwarf::DW_TAG_label); MCOS->EmitIntValue(dwarf::DW_CHILDREN_yes, 1); EmitAbbrev(MCOS, dwarf::DW_AT_name, dwarf::DW_FORM_string); EmitAbbrev(MCOS, dwarf::DW_AT_decl_file, dwarf::DW_FORM_data4); @@ -838,8 +838,8 @@ static void EmitGenDwarfAbbrev(MCStreamer *MCOS) { EmitAbbrev(MCOS, 0, 0); // DW_TAG_unspecified_parameters DIE abbrev (3). - MCOS->EmitULEB128IntValue(3); - MCOS->EmitULEB128IntValue(dwarf::DW_TAG_unspecified_parameters); + MCOS->emitULEB128IntValue(3); + MCOS->emitULEB128IntValue(dwarf::DW_TAG_unspecified_parameters); MCOS->EmitIntValue(dwarf::DW_CHILDREN_no, 1); EmitAbbrev(MCOS, 0, 0); @@ -967,7 +967,7 @@ static void EmitGenDwarfInfo(MCStreamer *MCOS, // Second part: the compile_unit DIE. // The DW_TAG_compile_unit DIE abbrev (1). - MCOS->EmitULEB128IntValue(1); + MCOS->emitULEB128IntValue(1); // DW_AT_stmt_list, a 4 byte offset from the start of the .debug_line section, // which is at the start of that section so this is zero. @@ -1059,7 +1059,7 @@ static void EmitGenDwarfInfo(MCStreamer *MCOS, MCOS->getContext().getMCGenDwarfLabelEntries(); for (const auto &Entry : Entries) { // The DW_TAG_label DIE abbrev (2). - MCOS->EmitULEB128IntValue(2); + MCOS->emitULEB128IntValue(2); // AT_name, of the label without any leading underbar. MCOS->EmitBytes(Entry.getName()); @@ -1080,7 +1080,7 @@ static void EmitGenDwarfInfo(MCStreamer *MCOS, MCOS->EmitIntValue(0, 1); // The DW_TAG_unspecified_parameters DIE abbrev (3). - MCOS->EmitULEB128IntValue(3); + MCOS->emitULEB128IntValue(3); // Add the NULL DIE terminating the DW_TAG_unspecified_parameters DIE's. MCOS->EmitIntValue(0, 1); @@ -1339,8 +1339,8 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { Reg2 = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg2); } Streamer.EmitIntValue(dwarf::DW_CFA_register, 1); - Streamer.EmitULEB128IntValue(Reg1); - Streamer.EmitULEB128IntValue(Reg2); + Streamer.emitULEB128IntValue(Reg1); + Streamer.emitULEB128IntValue(Reg2); return; } case MCCFIInstruction::OpWindowSave: @@ -1354,7 +1354,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpUndefined: { unsigned Reg = Instr.getRegister(); Streamer.EmitIntValue(dwarf::DW_CFA_undefined, 1); - Streamer.EmitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Reg); return; } case MCCFIInstruction::OpAdjustCfaOffset: @@ -1369,7 +1369,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { else CFAOffset = -Instr.getOffset(); - Streamer.EmitULEB128IntValue(CFAOffset); + Streamer.emitULEB128IntValue(CFAOffset); return; } @@ -1378,9 +1378,9 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { if (!IsEH) Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa, 1); - Streamer.EmitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Reg); CFAOffset = -Instr.getOffset(); - Streamer.EmitULEB128IntValue(CFAOffset); + Streamer.emitULEB128IntValue(CFAOffset); return; } @@ -1389,7 +1389,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { if (!IsEH) Reg = MRI->getDwarfRegNumFromDwarfEHRegNum(Reg); Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_register, 1); - Streamer.EmitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Reg); return; } @@ -1409,15 +1409,15 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { if (Offset < 0) { Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended_sf, 1); - Streamer.EmitULEB128IntValue(Reg); - Streamer.EmitSLEB128IntValue(Offset); + Streamer.emitULEB128IntValue(Reg); + Streamer.emitSLEB128IntValue(Offset); } else if (Reg < 64) { Streamer.EmitIntValue(dwarf::DW_CFA_offset + Reg, 1); - Streamer.EmitULEB128IntValue(Offset); + Streamer.emitULEB128IntValue(Offset); } else { Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended, 1); - Streamer.EmitULEB128IntValue(Reg); - Streamer.EmitULEB128IntValue(Offset); + Streamer.emitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Offset); } return; } @@ -1430,7 +1430,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { case MCCFIInstruction::OpSameValue: { unsigned Reg = Instr.getRegister(); Streamer.EmitIntValue(dwarf::DW_CFA_same_value, 1); - Streamer.EmitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Reg); return; } case MCCFIInstruction::OpRestore: { @@ -1441,13 +1441,13 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { Streamer.EmitIntValue(dwarf::DW_CFA_restore | Reg, 1); } else { Streamer.EmitIntValue(dwarf::DW_CFA_restore_extended, 1); - Streamer.EmitULEB128IntValue(Reg); + Streamer.emitULEB128IntValue(Reg); } return; } case MCCFIInstruction::OpGnuArgsSize: Streamer.EmitIntValue(dwarf::DW_CFA_GNU_args_size, 1); - Streamer.EmitULEB128IntValue(Instr.getOffset()); + Streamer.emitULEB128IntValue(Instr.getOffset()); return; case MCCFIInstruction::OpEscape: @@ -1469,7 +1469,7 @@ void FrameEmitterImpl::EmitCFIInstructions(ArrayRef Instrs, if (BaseLabel && Label) { MCSymbol *ThisSym = Label; if (ThisSym != BaseLabel) { - Streamer.EmitDwarfAdvanceFrameAddr(BaseLabel, ThisSym); + Streamer.emitDwarfAdvanceFrameAddr(BaseLabel, ThisSym); BaseLabel = ThisSym; } } @@ -1605,10 +1605,10 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { } // Code Alignment Factor - Streamer.EmitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment()); + Streamer.emitULEB128IntValue(context.getAsmInfo()->getMinInstAlignment()); // Data Alignment Factor - Streamer.EmitSLEB128IntValue(getDataAlignmentFactor(Streamer)); + Streamer.emitSLEB128IntValue(getDataAlignmentFactor(Streamer)); // Return Address Register unsigned RAReg = Frame.RAReg; @@ -1620,7 +1620,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { "DWARF 2 encodes return_address_register in one byte"); Streamer.EmitIntValue(RAReg, 1); } else { - Streamer.EmitULEB128IntValue(RAReg); + Streamer.emitULEB128IntValue(RAReg); } // Augmentation Data Length (optional) @@ -1638,7 +1638,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { // Encoding of the FDE pointers augmentationLength += 1; - Streamer.EmitULEB128IntValue(augmentationLength); + Streamer.emitULEB128IntValue(augmentationLength); // Augmentation Data (optional) if (Frame.Personality) { @@ -1723,7 +1723,7 @@ void FrameEmitterImpl::EmitFDE(const MCSymbol &cieStart, if (frame.Lsda) augmentationLength += getSizeForEncoding(Streamer, frame.LsdaEncoding); - Streamer.EmitULEB128IntValue(augmentationLength); + Streamer.emitULEB128IntValue(augmentationLength); // Augmentation Data if (frame.Lsda) diff --git a/llvm/lib/MC/MCELFStreamer.cpp b/llvm/lib/MC/MCELFStreamer.cpp index 0a0c30df9c07f..4d098a824a2bc 100644 --- a/llvm/lib/MC/MCELFStreamer.cpp +++ b/llvm/lib/MC/MCELFStreamer.cpp @@ -106,10 +106,10 @@ void MCELFStreamer::EmitLabel(MCSymbol *S, SMLoc Loc) { Symbol->setType(ELF::STT_TLS); } -void MCELFStreamer::EmitLabelAtPos(MCSymbol *S, SMLoc Loc, MCFragment *F, +void MCELFStreamer::emitLabelAtPos(MCSymbol *S, SMLoc Loc, MCFragment *F, uint64_t Offset) { auto *Symbol = cast(S); - MCObjectStreamer::EmitLabelAtPos(Symbol, Loc, F, Offset); + MCObjectStreamer::emitLabelAtPos(Symbol, Loc, F, Offset); const MCSectionELF &Section = static_cast(*getCurrentSectionOnly()); diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index 3d1358df475f1..29ccfee8fc484 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -154,7 +154,7 @@ void MCObjectStreamer::emitAbsoluteSymbolDiff(const MCSymbol *Hi, void MCObjectStreamer::emitAbsoluteSymbolDiffAsULEB128(const MCSymbol *Hi, const MCSymbol *Lo) { if (Optional Diff = absoluteSymbolDiff(getAssembler(), Hi, Lo)) { - EmitULEB128IntValue(*Diff); + emitULEB128IntValue(*Diff); return; } MCStreamer::emitAbsoluteSymbolDiffAsULEB128(Hi, Lo); @@ -291,7 +291,7 @@ void MCObjectStreamer::EmitLabel(MCSymbol *Symbol, SMLoc Loc) { // Emit a label at a previously emitted fragment/offset position. This must be // within the currently-active section. -void MCObjectStreamer::EmitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, +void MCObjectStreamer::emitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, MCFragment *F, uint64_t Offset) { assert(F->getParent() == getCurrentSectionOnly()); @@ -309,19 +309,19 @@ void MCObjectStreamer::EmitLabelAtPos(MCSymbol *Symbol, SMLoc Loc, } } -void MCObjectStreamer::EmitULEB128Value(const MCExpr *Value) { +void MCObjectStreamer::emitULEB128Value(const MCExpr *Value) { int64_t IntValue; if (Value->evaluateAsAbsolute(IntValue, getAssemblerPtr())) { - EmitULEB128IntValue(IntValue); + emitULEB128IntValue(IntValue); return; } insert(new MCLEBFragment(*Value, false)); } -void MCObjectStreamer::EmitSLEB128Value(const MCExpr *Value) { +void MCObjectStreamer::emitSLEB128Value(const MCExpr *Value) { int64_t IntValue; if (Value->evaluateAsAbsolute(IntValue, getAssemblerPtr())) { - EmitSLEB128IntValue(IntValue); + emitSLEB128IntValue(IntValue); return; } insert(new MCLEBFragment(*Value, true)); @@ -443,7 +443,7 @@ void MCObjectStreamer::EmitBundleUnlock() { llvm_unreachable(BundlingNotImplementedMsg); } -void MCObjectStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, +void MCObjectStreamer::emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, unsigned Flags, unsigned Isa, unsigned Discriminator, @@ -452,8 +452,8 @@ void MCObjectStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, // first one gets a line entry. MCDwarfLineEntry::Make(this, getCurrentSectionOnly()); - this->MCStreamer::EmitDwarfLocDirective(FileNo, Line, Column, Flags, - Isa, Discriminator, FileName); + this->MCStreamer::emitDwarfLocDirective(FileNo, Line, Column, Flags, Isa, + Discriminator, FileName); } static const MCExpr *buildSymbolDiff(MCObjectStreamer &OS, const MCSymbol *A, @@ -473,7 +473,7 @@ static void emitDwarfSetLineAddr(MCObjectStreamer &OS, int PointerSize) { // emit the sequence to set the address OS.EmitIntValue(dwarf::DW_LNS_extended_op, 1); - OS.EmitULEB128IntValue(PointerSize + 1); + OS.emitULEB128IntValue(PointerSize + 1); OS.EmitIntValue(dwarf::DW_LNE_set_address, 1); OS.EmitSymbolValue(Label, PointerSize); @@ -481,7 +481,7 @@ static void emitDwarfSetLineAddr(MCObjectStreamer &OS, MCDwarfLineAddr::Emit(&OS, Params, LineDelta, 0); } -void MCObjectStreamer::EmitDwarfAdvanceLineAddr(int64_t LineDelta, +void MCObjectStreamer::emitDwarfAdvanceLineAddr(int64_t LineDelta, const MCSymbol *LastLabel, const MCSymbol *Label, unsigned PointerSize) { @@ -500,7 +500,7 @@ void MCObjectStreamer::EmitDwarfAdvanceLineAddr(int64_t LineDelta, insert(new MCDwarfLineAddrFragment(LineDelta, *AddrDelta)); } -void MCObjectStreamer::EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel, +void MCObjectStreamer::emitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel, const MCSymbol *Label) { const MCExpr *AddrDelta = buildSymbolDiff(*this, Label, LastLabel); int64_t Res; diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index 30f1147fb6c14..81ddbc8f7fe0c 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -875,7 +875,7 @@ bool AsmParser::enabledGenDwarfForAssembly() { /*Cksum=*/None, /*Source=*/None); const MCDwarfFile &RootFile = getContext().getMCDwarfLineTable(/*CUID=*/0).getRootFile(); - getContext().setGenDwarfFileNumber(getStreamer().EmitDwarfFileDirective( + getContext().setGenDwarfFileNumber(getStreamer().emitDwarfFileDirective( /*CUID=*/0, getContext().getCompilationDir(), RootFile.Name, RootFile.Checksum, RootFile.Source)); } @@ -2249,7 +2249,7 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info, // current Dwarf File is for the CppHashFilename if not then emit the // Dwarf File table for it and adjust the line number for the .loc. if (!CppHashInfo.Filename.empty()) { - unsigned FileNumber = getStreamer().EmitDwarfFileDirective( + unsigned FileNumber = getStreamer().emitDwarfFileDirective( 0, StringRef(), CppHashInfo.Filename); getContext().setGenDwarfFileNumber(FileNumber); @@ -2258,7 +2258,7 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info, Line = CppHashInfo.LineNumber - 1 + (Line - CppHashLocLineNo); } - getStreamer().EmitDwarfLocDirective( + getStreamer().emitDwarfLocDirective( getContext().getGenDwarfFileNumber(), Line, 0, DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0, 0, 0, StringRef()); @@ -3573,7 +3573,7 @@ bool AsmParser::parseDirectiveLoc() { if (parseMany(parseLocOp, false /*hasComma*/)) return true; - getStreamer().EmitDwarfLocDirective(FileNumber, LineNumber, ColumnPos, Flags, + getStreamer().emitDwarfLocDirective(FileNumber, LineNumber, ColumnPos, Flags, Isa, Discriminator, StringRef()); return false; @@ -4831,9 +4831,9 @@ bool AsmParser::parseDirectiveLEB128(bool Signed) { if (parseExpression(Value)) return true; if (Signed) - getStreamer().EmitSLEB128Value(Value); + getStreamer().emitSLEB128Value(Value); else - getStreamer().EmitULEB128Value(Value); + getStreamer().emitULEB128Value(Value); return false; }; diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index 0ab8835367798..e5058ec0329f4 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -143,7 +143,7 @@ void MCStreamer::EmitIntValue(uint64_t Value, unsigned Size) { /// EmitULEB128IntValue - Special case of EmitULEB128Value that avoids the /// client having to pass in a MCExpr for constant integers. -void MCStreamer::EmitULEB128IntValue(uint64_t Value, unsigned PadTo) { +void MCStreamer::emitULEB128IntValue(uint64_t Value, unsigned PadTo) { SmallString<128> Tmp; raw_svector_ostream OSE(Tmp); encodeULEB128(Value, OSE, PadTo); @@ -152,7 +152,7 @@ void MCStreamer::EmitULEB128IntValue(uint64_t Value, unsigned PadTo) { /// EmitSLEB128IntValue - Special case of EmitSLEB128Value that avoids the /// client having to pass in a MCExpr for constant integers. -void MCStreamer::EmitSLEB128IntValue(int64_t Value) { +void MCStreamer::emitSLEB128IntValue(int64_t Value) { SmallString<128> Tmp; raw_svector_ostream OSE(Tmp); encodeSLEB128(Value, OSE); @@ -235,10 +235,9 @@ void MCStreamer::EmitCFIBKeyFrame() { CurFrame->IsBKeyFrame = true; } -void MCStreamer::EmitDwarfLocDirective(unsigned FileNo, unsigned Line, +void MCStreamer::emitDwarfLocDirective(unsigned FileNo, unsigned Line, unsigned Column, unsigned Flags, - unsigned Isa, - unsigned Discriminator, + unsigned Isa, unsigned Discriminator, StringRef FileName) { getContext().setCurrentDwarfLoc(FileNo, Line, Column, Flags, Isa, Discriminator); @@ -1045,7 +1044,7 @@ void MCStreamer::emitAbsoluteSymbolDiffAsULEB128(const MCSymbol *Hi, MCBinaryExpr::createSub(MCSymbolRefExpr::create(Hi, Context), MCSymbolRefExpr::create(Lo, Context), Context); - EmitULEB128Value(Diff); + emitULEB128Value(Diff); } void MCStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) {} @@ -1083,8 +1082,8 @@ void MCStreamer::EmitBinaryData(StringRef Data) { EmitBytes(Data); } void MCStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { visitUsedExpr(*Value); } -void MCStreamer::EmitULEB128Value(const MCExpr *Value) {} -void MCStreamer::EmitSLEB128Value(const MCExpr *Value) {} +void MCStreamer::emitULEB128Value(const MCExpr *Value) {} +void MCStreamer::emitSLEB128Value(const MCExpr *Value) {} void MCStreamer::emitFill(const MCExpr &NumBytes, uint64_t Value, SMLoc Loc) {} void MCStreamer::emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr, SMLoc Loc) {} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 7669bce410996..02942a09d7ef6 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -303,8 +303,8 @@ void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { if (!Align) Align = 4; - EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); - EmitLinkage(GV, GVSym); + emitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration()); + emitLinkage(GV, GVSym); if (auto TS = getTargetStreamer()) TS->emitAMDGPULDS(GVSym, Size, Align); return; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 15f5865cef4e6..cbe347c29c255 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -647,7 +647,7 @@ class ARMELFStreamer : public MCELFStreamer { uint64_t Offset) { auto *Symbol = cast(getContext().getOrCreateSymbol( Name + "." + Twine(MappingSymbolCounter++))); - EmitLabelAtPos(Symbol, Loc, F, Offset); + emitLabelAtPos(Symbol, Loc, F, Offset); Symbol->setType(ELF::STT_NOTYPE); Symbol->setBinding(ELF::STB_LOCAL); Symbol->setExternal(false); @@ -1101,18 +1101,18 @@ void ARMTargetELFStreamer::finishAttributeSection() { // emit each field as its type (ULEB or String) for (size_t i = 0; i < Contents.size(); ++i) { AttributeItem item = Contents[i]; - Streamer.EmitULEB128IntValue(item.Tag); + Streamer.emitULEB128IntValue(item.Tag); switch (item.Type) { default: llvm_unreachable("Invalid attribute type"); case AttributeItem::NumericAttribute: - Streamer.EmitULEB128IntValue(item.IntValue); + Streamer.emitULEB128IntValue(item.IntValue); break; case AttributeItem::TextAttribute: Streamer.EmitBytes(item.StringValue); Streamer.EmitIntValue(0, 1); // '\0' break; case AttributeItem::NumericAndTextAttributes: - Streamer.EmitULEB128IntValue(item.IntValue); + Streamer.emitULEB128IntValue(item.IntValue); Streamer.EmitBytes(item.StringValue); Streamer.EmitIntValue(0, 1); // '\0' break; diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index e868ccad4b1ff..c3647bb5ef700 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -360,7 +360,7 @@ void BTFKindDataSec::emitType(MCStreamer &OS) { for (const auto &V : Vars) { OS.EmitIntValue(std::get<0>(V), 4); - Asm->EmitLabelReference(std::get<1>(V), 4); + Asm->emitLabelReference(std::get<1>(V), 4); OS.EmitIntValue(std::get<2>(V), 4); } } @@ -802,7 +802,7 @@ void BTFDebug::emitBTFExtSection() { OS.EmitIntValue(FuncSec.first, 4); OS.EmitIntValue(FuncSec.second.size(), 4); for (const auto &FuncInfo : FuncSec.second) { - Asm->EmitLabelReference(FuncInfo.Label, 4); + Asm->emitLabelReference(FuncInfo.Label, 4); OS.EmitIntValue(FuncInfo.TypeId, 4); } } @@ -816,7 +816,7 @@ void BTFDebug::emitBTFExtSection() { OS.EmitIntValue(LineSec.first, 4); OS.EmitIntValue(LineSec.second.size(), 4); for (const auto &LineInfo : LineSec.second) { - Asm->EmitLabelReference(LineInfo.Label, 4); + Asm->emitLabelReference(LineInfo.Label, 4); OS.EmitIntValue(LineInfo.FileNameOff, 4); OS.EmitIntValue(LineInfo.LineOff, 4); OS.AddComment("Line " + std::to_string(LineInfo.LineNum) + " Col " + @@ -835,7 +835,7 @@ void BTFDebug::emitBTFExtSection() { OS.EmitIntValue(FieldRelocSec.first, 4); OS.EmitIntValue(FieldRelocSec.second.size(), 4); for (const auto &FieldRelocInfo : FieldRelocSec.second) { - Asm->EmitLabelReference(FieldRelocInfo.Label, 4); + Asm->emitLabelReference(FieldRelocInfo.Label, 4); OS.EmitIntValue(FieldRelocInfo.TypeID, 4); OS.EmitIntValue(FieldRelocInfo.OffsetNameOff, 4); OS.EmitIntValue(FieldRelocInfo.RelocKind, 4); diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 4a05f4031cec3..9cc4ed42d337c 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -1255,7 +1255,7 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, // Emit .dtprelword or .dtpreldword directive // and value for debug thread local expression. -void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { +void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const { if (auto *MipsExpr = dyn_cast(Value)) { if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) { switch (Size) { @@ -1271,7 +1271,7 @@ void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { return; } } - AsmPrinter::EmitDebugValue(Value, Size); + AsmPrinter::emitDebugValue(Value, Size); } // Align all targets of indirect branches on bundle size. Used only if target diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index 7df0fe15e96f4..f9d877cff85aa 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -157,7 +157,7 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { void emitStartOfAsmFile(Module &M) override; void emitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); - void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; + void emitDebugValue(const MCExpr *Value, unsigned Size) const override; }; } // end namespace llvm diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index aad74b884f9b4..1457622d4ce35 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1631,7 +1631,7 @@ void PPCAIXAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { } MCSymbol *EmittedInitSym = GVSym; - EmitLinkage(GV, EmittedInitSym); + emitLinkage(GV, EmittedInitSym); EmitAlignment(getGVAlignment(GV, DL), GV); OutStreamer->EmitLabel(EmittedInitSym); EmitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp index 7c21ed5f974e2..ccba0f073bc1c 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.cpp @@ -113,9 +113,9 @@ void WebAssemblyTargetWasmStreamer::emitLocal(ArrayRef Types) { ++Grouped.back().second; } - Streamer.EmitULEB128IntValue(Grouped.size()); + Streamer.emitULEB128IntValue(Grouped.size()); for (auto Pair : Grouped) { - Streamer.EmitULEB128IntValue(Pair.second); + Streamer.emitULEB128IntValue(Pair.second); emitValueType(Pair.first); } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 0442a48328aea..47cc17f092386 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -208,18 +208,18 @@ void WebAssemblyAsmPrinter::EmitProducerInfo(Module &M) { ".custom_section.producers", SectionKind::getMetadata()); OutStreamer->PushSection(); OutStreamer->SwitchSection(Producers); - OutStreamer->EmitULEB128IntValue(FieldCount); + OutStreamer->emitULEB128IntValue(FieldCount); for (auto &Producers : {std::make_pair("language", &Languages), std::make_pair("processed-by", &Tools)}) { if (Producers.second->empty()) continue; - OutStreamer->EmitULEB128IntValue(strlen(Producers.first)); + OutStreamer->emitULEB128IntValue(strlen(Producers.first)); OutStreamer->EmitBytes(Producers.first); - OutStreamer->EmitULEB128IntValue(Producers.second->size()); + OutStreamer->emitULEB128IntValue(Producers.second->size()); for (auto &Producer : *Producers.second) { - OutStreamer->EmitULEB128IntValue(Producer.first.size()); + OutStreamer->emitULEB128IntValue(Producer.first.size()); OutStreamer->EmitBytes(Producer.first); - OutStreamer->EmitULEB128IntValue(Producer.second.size()); + OutStreamer->emitULEB128IntValue(Producer.second.size()); OutStreamer->EmitBytes(Producer.second); } } @@ -267,10 +267,10 @@ void WebAssemblyAsmPrinter::EmitTargetFeatures(Module &M) { OutStreamer->PushSection(); OutStreamer->SwitchSection(FeaturesSection); - OutStreamer->EmitULEB128IntValue(EmittedFeatures.size()); + OutStreamer->emitULEB128IntValue(EmittedFeatures.size()); for (auto &F : EmittedFeatures) { OutStreamer->EmitIntValue(F.Prefix, 1); - OutStreamer->EmitULEB128IntValue(F.Name.size()); + OutStreamer->emitULEB128IntValue(F.Name.size()); OutStreamer->EmitBytes(F.Name); } diff --git a/llvm/tools/dsymutil/DwarfStreamer.cpp b/llvm/tools/dsymutil/DwarfStreamer.cpp index a219a7542d293..93895bef9032b 100644 --- a/llvm/tools/dsymutil/DwarfStreamer.cpp +++ b/llvm/tools/dsymutil/DwarfStreamer.cpp @@ -382,7 +382,7 @@ void DwarfStreamer::emitUnitRangesEntries(CompileUnit &Unit, unsigned TupleSize = AddressSize * 2; unsigned Padding = offsetToAlignment(HeaderSize, Align(TupleSize)); - Asm->EmitLabelDifference(EndLabel, BeginLabel, 4); // Arange length + Asm->emitLabelDifference(EndLabel, BeginLabel, 4); // Arange length Asm->OutStreamer->EmitLabel(BeginLabel); Asm->emitInt16(dwarf::DW_ARANGES_VERSION); // Version number Asm->emitInt32(Unit.getStartOffset()); // Corresponding unit's offset @@ -505,7 +505,7 @@ void DwarfStreamer::emitLineTableForUnit(MCDwarfLineTableParams Params, // The first 4 bytes is the total length of the information for this // compilation unit (not including these 4 bytes for the length). - Asm->EmitLabelDifference(LineEndSym, LineStartSym, 4); + Asm->emitLabelDifference(LineEndSym, LineStartSym, 4); Asm->OutStreamer->EmitLabel(LineStartSym); // Copy Prologue. MS->EmitBytes(PrologueBytes); @@ -541,7 +541,7 @@ void DwarfStreamer::emitLineTableForUnit(MCDwarfLineTableParams Params, int64_t AddressDelta; if (Address == -1ULL) { MS->EmitIntValue(dwarf::DW_LNS_extended_op, 1); - MS->EmitULEB128IntValue(PointerSize + 1); + MS->emitULEB128IntValue(PointerSize + 1); MS->EmitIntValue(dwarf::DW_LNE_set_address, 1); MS->EmitIntValue(Row.Address.Address, PointerSize); LineSectionSize += 2 + PointerSize + getULEB128Size(PointerSize + 1); @@ -558,13 +558,13 @@ void DwarfStreamer::emitLineTableForUnit(MCDwarfLineTableParams Params, if (FileNum != Row.File) { FileNum = Row.File; MS->EmitIntValue(dwarf::DW_LNS_set_file, 1); - MS->EmitULEB128IntValue(FileNum); + MS->emitULEB128IntValue(FileNum); LineSectionSize += 1 + getULEB128Size(FileNum); } if (Column != Row.Column) { Column = Row.Column; MS->EmitIntValue(dwarf::DW_LNS_set_column, 1); - MS->EmitULEB128IntValue(Column); + MS->emitULEB128IntValue(Column); LineSectionSize += 1 + getULEB128Size(Column); } @@ -574,7 +574,7 @@ void DwarfStreamer::emitLineTableForUnit(MCDwarfLineTableParams Params, if (Isa != Row.Isa) { Isa = Row.Isa; MS->EmitIntValue(dwarf::DW_LNS_set_isa, 1); - MS->EmitULEB128IntValue(Isa); + MS->emitULEB128IntValue(Isa); LineSectionSize += 1 + getULEB128Size(Isa); } if (IsStatement != Row.IsStmt) { @@ -609,12 +609,12 @@ void DwarfStreamer::emitLineTableForUnit(MCDwarfLineTableParams Params, } else { if (LineDelta) { MS->EmitIntValue(dwarf::DW_LNS_advance_line, 1); - MS->EmitSLEB128IntValue(LineDelta); + MS->emitSLEB128IntValue(LineDelta); LineSectionSize += 1 + getSLEB128Size(LineDelta); } if (AddressDelta) { MS->EmitIntValue(dwarf::DW_LNS_advance_pc, 1); - MS->EmitULEB128IntValue(AddressDelta); + MS->emitULEB128IntValue(AddressDelta); LineSectionSize += 1 + getULEB128Size(AddressDelta); } MCDwarfLineAddr::Encode(*MC, Params, std::numeric_limits::max(), @@ -660,14 +660,14 @@ void DwarfStreamer::translateLineTable(DataExtractor Data, uint64_t Offset) { return; } - Asm->EmitLabelDifference(EndLabel, BeginLabel, 4); + Asm->emitLabelDifference(EndLabel, BeginLabel, 4); Asm->OutStreamer->EmitLabel(BeginLabel); Asm->emitInt16(Version); LineSectionSize += 6; MCSymbol *HeaderBeginLabel = MC->createTempSymbol(); MCSymbol *HeaderEndLabel = MC->createTempSymbol(); - Asm->EmitLabelDifference(HeaderEndLabel, HeaderBeginLabel, 4); + Asm->emitLabelDifference(HeaderEndLabel, HeaderBeginLabel, 4); Asm->OutStreamer->EmitLabel(HeaderBeginLabel); Offset += 4; LineSectionSize += 4; @@ -703,9 +703,9 @@ void DwarfStreamer::translateLineTable(DataExtractor Data, uint64_t Offset) { LineSectionSize += Translated.size() + 1; uint64_t OffsetBeforeLEBs = Offset; - Asm->EmitULEB128(Data.getULEB128(&Offset)); - Asm->EmitULEB128(Data.getULEB128(&Offset)); - Asm->EmitULEB128(Data.getULEB128(&Offset)); + Asm->emitULEB128(Data.getULEB128(&Offset)); + Asm->emitULEB128(Data.getULEB128(&Offset)); + Asm->emitULEB128(Data.getULEB128(&Offset)); LineSectionSize += Offset - OffsetBeforeLEBs; } Asm->emitInt8(0); @@ -761,7 +761,7 @@ void DwarfStreamer::emitPubSectionForUnit( if (!HeaderEmitted) { // Emit the header. - Asm->EmitLabelDifference(EndLabel, BeginLabel, 4); // Length + Asm->emitLabelDifference(EndLabel, BeginLabel, 4); // Length Asm->OutStreamer->EmitLabel(BeginLabel); Asm->emitInt16(dwarf::DW_PUBNAMES_VERSION); // Version Asm->emitInt32(Unit.getStartOffset()); // Unit offset diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp index e8662a59bf89a..f53fbdea34f58 100644 --- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp @@ -249,10 +249,10 @@ void dwarfgen::LineTable::writeData(ArrayRef Data, Asm.OutStreamer->EmitIntValue(Entry.Value, Entry.Length); continue; case ULEB: - Asm.EmitULEB128(Entry.Value); + Asm.emitULEB128(Entry.Value); continue; case SLEB: - Asm.EmitSLEB128(Entry.Value); + Asm.emitSLEB128(Entry.Value); continue; } llvm_unreachable("unsupported ValueAndLength Length value"); @@ -264,9 +264,9 @@ MCSymbol *dwarfgen::LineTable::writeDefaultPrologue(AsmPrinter &Asm) const { MCSymbol *UnitEnd = Asm.createTempSymbol("line_unit_end"); if (Format == DwarfFormat::DWARF64) { Asm.emitInt32((int)dwarf::DW_LENGTH_DWARF64); - Asm.EmitLabelDifference(UnitEnd, UnitStart, 8); + Asm.emitLabelDifference(UnitEnd, UnitStart, 8); } else { - Asm.EmitLabelDifference(UnitEnd, UnitStart, 4); + Asm.emitLabelDifference(UnitEnd, UnitStart, 4); } Asm.OutStreamer->EmitLabel(UnitStart); Asm.emitInt16(Version); @@ -277,7 +277,7 @@ MCSymbol *dwarfgen::LineTable::writeDefaultPrologue(AsmPrinter &Asm) const { MCSymbol *PrologueStart = Asm.createTempSymbol("line_prologue_start"); MCSymbol *PrologueEnd = Asm.createTempSymbol("line_prologue_end"); - Asm.EmitLabelDifference(PrologueEnd, PrologueStart, + Asm.emitLabelDifference(PrologueEnd, PrologueStart, Format == DwarfFormat::DWARF64 ? 8 : 4); Asm.OutStreamer->EmitLabel(PrologueStart); @@ -323,9 +323,9 @@ static void writeV2IncludeAndFileTable(const DWARFDebugLine::Prologue &Prologue, for (auto File : Prologue.FileNames) { assert(File.Name.getAsCString() && "expected a string form for file name"); writeCString(*File.Name.getAsCString(), Asm); - Asm.EmitULEB128(File.DirIdx); - Asm.EmitULEB128(File.ModTime); - Asm.EmitULEB128(File.Length); + Asm.emitULEB128(File.DirIdx); + Asm.emitULEB128(File.ModTime); + Asm.emitULEB128(File.Length); } Asm.emitInt8(0); } @@ -335,20 +335,20 @@ static void writeV5IncludeAndFileTable(const DWARFDebugLine::Prologue &Prologue, Asm.emitInt8(1); // directory_entry_format_count. // TODO: Add support for other content descriptions - we currently only // support a single DW_LNCT_path/DW_FORM_string. - Asm.EmitULEB128(DW_LNCT_path); - Asm.EmitULEB128(DW_FORM_string); - Asm.EmitULEB128(Prologue.IncludeDirectories.size()); + Asm.emitULEB128(DW_LNCT_path); + Asm.emitULEB128(DW_FORM_string); + Asm.emitULEB128(Prologue.IncludeDirectories.size()); for (auto Include : Prologue.IncludeDirectories) { assert(Include.getAsCString() && "expected a string form for include dir"); writeCString(*Include.getAsCString(), Asm); } Asm.emitInt8(2); // file_name_entry_format_count. - Asm.EmitULEB128(DW_LNCT_path); - Asm.EmitULEB128(DW_FORM_string); - Asm.EmitULEB128(DW_LNCT_directory_index); - Asm.EmitULEB128(DW_FORM_data1); - Asm.EmitULEB128(Prologue.FileNames.size()); + Asm.emitULEB128(DW_LNCT_path); + Asm.emitULEB128(DW_FORM_string); + Asm.emitULEB128(DW_LNCT_directory_index); + Asm.emitULEB128(DW_FORM_data1); + Asm.emitULEB128(Prologue.FileNames.size()); for (auto File : Prologue.FileNames) { assert(File.Name.getAsCString() && "expected a string form for file name"); writeCString(*File.Name.getAsCString(), Asm); From f7e2227832a6691bf2d07cebf4bd772d5eafbe1a Mon Sep 17 00:00:00 2001 From: Wawha Date: Thu, 13 Feb 2020 22:46:33 +0100 Subject: [PATCH 17/57] [clang] Fix bad line ending (DOS instead of Unix) inside the release notes. --- clang/docs/ReleaseNotes.rst | 582 ++++++++++++++++++------------------ 1 file changed, 291 insertions(+), 291 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index e0a15f8d38a1e..b98abc82d2476 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -1,291 +1,291 @@ -======================================== -Clang 11.0.0 (In-Progress) Release Notes -======================================== - -.. contents:: - :local: - :depth: 2 - -Written by the `LLVM Team `_ - -.. warning:: - - These are in-progress notes for the upcoming Clang 11 release. - Release notes for previous releases can be found on - `the Download Page `_. - -Introduction -============ - -This document contains the release notes for the Clang C/C++/Objective-C -frontend, part of the LLVM Compiler Infrastructure, release 11.0.0. Here we -describe the status of Clang in some detail, including major -improvements from the previous release and new feature work. For the -general LLVM release notes, see `the LLVM -documentation `_. All LLVM -releases may be downloaded from the `LLVM releases web -site `_. - -For more information about Clang or LLVM, including information about the -latest release, please see the `Clang Web Site `_ or the -`LLVM Web Site `_. - -Note that if you are reading this file from a Git checkout or the -main Clang web page, this document applies to the *next* release, not -the current one. To see the release notes for a specific release, please -see the `releases page `_. - -What's New in Clang 11.0.0? -=========================== - -Some of the major new features and improvements to Clang are listed -here. Generic improvements to Clang as a whole or to its underlying -infrastructure are described first, followed by language-specific -sections with improvements to Clang's support for those languages. - -Major New Features ------------------- - -- ... - -Improvements to Clang's diagnostics -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -- ... - -Non-comprehensive list of changes in this release -------------------------------------------------- - - -New Compiler Flags ------------------- - - -- -fstack-clash-protection will provide a protection against the stack clash - attack for x86 architecture through automatic probing of each page of - allocated stack. - -Deprecated Compiler Flags -------------------------- - -The following options are deprecated and ignored. They will be removed in -future versions of Clang. - -- ... - -Modified Compiler Flags ------------------------ - - -New Pragmas in Clang --------------------- - -- ... - -Attribute Changes in Clang --------------------------- - -- ... - -Windows Support ---------------- - -C Language Changes in Clang ---------------------------- - -- ... - -C11 Feature Support -^^^^^^^^^^^^^^^^^^^ - -... - -C++ Language Changes in Clang ------------------------------ - -- Clang now implements a restriction on giving non-C-compatible anonymous - structs a typedef name for linkage purposes, as described in C++ committee - paper `P1766R1 `. This paper was adopted by the - C++ committee as a Defect Report resolution, so it is applied retroactively - to all C++ standard versions. This affects code such as: - - .. code-block:: c++ - - typedef struct { - int f() { return 0; } - } S; - - Previous versions of Clang rejected some constructs of this form - (specifically, where the linkage of the type happened to be computed - before the parser reached the typedef name); those cases are still rejected - in Clang 11. In addition, cases that previous versions of Clang did not - reject now produce an extension warning. This warning can be disabled with - the warning flag ``-Wno-non-c-typedef-for-linkage``. - - Affected code should be updated to provide a tag name for the anonymous - struct: - - .. code-block:: c++ - - struct S { - int f() { return 0; } - }; - - If the code is shared with a C compilation (for example, if the parts that - are not C-compatible are guarded with ``#ifdef __cplusplus``), the typedef - declaration should be retained, but a tag name should still be provided: - - .. code-block:: c++ - - typedef struct S { - int f() { return 0; } - } S; - -C++1z Feature Support -^^^^^^^^^^^^^^^^^^^^^ - -... - -Objective-C Language Changes in Clang -------------------------------------- - - -OpenCL C Language Changes in Clang ----------------------------------- - -... - -ABI Changes in Clang --------------------- - - -OpenMP Support in Clang ------------------------ - -- ... - -CUDA Support in Clang ---------------------- - -- ... - -Internal API Changes --------------------- - -These are major API changes that have happened since the 10.0.0 release of -Clang. If upgrading an external codebase that uses Clang as a library, -this section should help get you past the largest hurdles of upgrading. - - -Build System Changes --------------------- - -These are major changes to the build system that have happened since the 10.0.0 -release of Clang. Users of the build system should adjust accordingly. - -- ... - -AST Matchers ------------- - -- ... - -clang-format ------------- - - -- Option ``IndentCaseBlocks`` has been added to support treating the block - following a switch case label as a scope block which gets indented itself. - It helps avoid having the closing bracket align with the switch statement's - closing bracket (when ``IndentCaseLabels`` is ``false``). - -- Option ``ObjCBreakBeforeNestedBlockParam`` has been added to optionally apply - linebreaks for function arguments declarations before nested blocks. - - .. code-block:: c++ - - switch (fool) { vs. switch (fool) { - case 1: case 1: { - { bar(); - bar(); } break; - } default: { - break; plop(); - default: } - { } - plop(); - } - } - -- Option ``InsertTrailingCommas`` can be set to ``TCS_Wrapped`` to insert - trailing commas in container literals (arrays and objects) that wrap across - multiple lines. It is currently only available for JavaScript and disabled by - default (``TCS_None``). - -- Option ``BraceWrapping.BeforeLambdaBody`` has been added to manage lambda - line break inside function parameter call in Allman style. - - .. code-block:: c++ - - true: - connect( - []() - { - foo(); - bar(); - }); - - false: - connect([]() { - foo(); - bar(); - }); - -libclang --------- - -- ... - -Static Analyzer ---------------- - -- ... - -.. _release-notes-ubsan: - -Undefined Behavior Sanitizer (UBSan) ------------------------------------- - - -Core Analysis Improvements -========================== - -- ... - -New Issues Found -================ - -- ... - -Python Binding Changes ----------------------- - -The following methods have been added: - -- ... - -Significant Known Problems -========================== - -Additional Information -====================== - -A wide variety of additional information is available on the `Clang web -page `_. The web page contains versions of the -API documentation which are up-to-date with the Subversion version of -the source code. You can access versions of these documents specific to -this release by going into the "``clang/docs/``" directory in the Clang -tree. - -If you have any questions or comments about Clang, please feel free to -contact us via the `mailing -list `_. +======================================== +Clang 11.0.0 (In-Progress) Release Notes +======================================== + +.. contents:: + :local: + :depth: 2 + +Written by the `LLVM Team `_ + +.. warning:: + + These are in-progress notes for the upcoming Clang 11 release. + Release notes for previous releases can be found on + `the Download Page `_. + +Introduction +============ + +This document contains the release notes for the Clang C/C++/Objective-C +frontend, part of the LLVM Compiler Infrastructure, release 11.0.0. Here we +describe the status of Clang in some detail, including major +improvements from the previous release and new feature work. For the +general LLVM release notes, see `the LLVM +documentation `_. All LLVM +releases may be downloaded from the `LLVM releases web +site `_. + +For more information about Clang or LLVM, including information about the +latest release, please see the `Clang Web Site `_ or the +`LLVM Web Site `_. + +Note that if you are reading this file from a Git checkout or the +main Clang web page, this document applies to the *next* release, not +the current one. To see the release notes for a specific release, please +see the `releases page `_. + +What's New in Clang 11.0.0? +=========================== + +Some of the major new features and improvements to Clang are listed +here. Generic improvements to Clang as a whole or to its underlying +infrastructure are described first, followed by language-specific +sections with improvements to Clang's support for those languages. + +Major New Features +------------------ + +- ... + +Improvements to Clang's diagnostics +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +- ... + +Non-comprehensive list of changes in this release +------------------------------------------------- + + +New Compiler Flags +------------------ + + +- -fstack-clash-protection will provide a protection against the stack clash + attack for x86 architecture through automatic probing of each page of + allocated stack. + +Deprecated Compiler Flags +------------------------- + +The following options are deprecated and ignored. They will be removed in +future versions of Clang. + +- ... + +Modified Compiler Flags +----------------------- + + +New Pragmas in Clang +-------------------- + +- ... + +Attribute Changes in Clang +-------------------------- + +- ... + +Windows Support +--------------- + +C Language Changes in Clang +--------------------------- + +- ... + +C11 Feature Support +^^^^^^^^^^^^^^^^^^^ + +... + +C++ Language Changes in Clang +----------------------------- + +- Clang now implements a restriction on giving non-C-compatible anonymous + structs a typedef name for linkage purposes, as described in C++ committee + paper `P1766R1 `. This paper was adopted by the + C++ committee as a Defect Report resolution, so it is applied retroactively + to all C++ standard versions. This affects code such as: + + .. code-block:: c++ + + typedef struct { + int f() { return 0; } + } S; + + Previous versions of Clang rejected some constructs of this form + (specifically, where the linkage of the type happened to be computed + before the parser reached the typedef name); those cases are still rejected + in Clang 11. In addition, cases that previous versions of Clang did not + reject now produce an extension warning. This warning can be disabled with + the warning flag ``-Wno-non-c-typedef-for-linkage``. + + Affected code should be updated to provide a tag name for the anonymous + struct: + + .. code-block:: c++ + + struct S { + int f() { return 0; } + }; + + If the code is shared with a C compilation (for example, if the parts that + are not C-compatible are guarded with ``#ifdef __cplusplus``), the typedef + declaration should be retained, but a tag name should still be provided: + + .. code-block:: c++ + + typedef struct S { + int f() { return 0; } + } S; + +C++1z Feature Support +^^^^^^^^^^^^^^^^^^^^^ + +... + +Objective-C Language Changes in Clang +------------------------------------- + + +OpenCL C Language Changes in Clang +---------------------------------- + +... + +ABI Changes in Clang +-------------------- + + +OpenMP Support in Clang +----------------------- + +- ... + +CUDA Support in Clang +--------------------- + +- ... + +Internal API Changes +-------------------- + +These are major API changes that have happened since the 10.0.0 release of +Clang. If upgrading an external codebase that uses Clang as a library, +this section should help get you past the largest hurdles of upgrading. + + +Build System Changes +-------------------- + +These are major changes to the build system that have happened since the 10.0.0 +release of Clang. Users of the build system should adjust accordingly. + +- ... + +AST Matchers +------------ + +- ... + +clang-format +------------ + + +- Option ``IndentCaseBlocks`` has been added to support treating the block + following a switch case label as a scope block which gets indented itself. + It helps avoid having the closing bracket align with the switch statement's + closing bracket (when ``IndentCaseLabels`` is ``false``). + +- Option ``ObjCBreakBeforeNestedBlockParam`` has been added to optionally apply + linebreaks for function arguments declarations before nested blocks. + + .. code-block:: c++ + + switch (fool) { vs. switch (fool) { + case 1: case 1: { + { bar(); + bar(); } break; + } default: { + break; plop(); + default: } + { } + plop(); + } + } + +- Option ``InsertTrailingCommas`` can be set to ``TCS_Wrapped`` to insert + trailing commas in container literals (arrays and objects) that wrap across + multiple lines. It is currently only available for JavaScript and disabled by + default (``TCS_None``). + +- Option ``BraceWrapping.BeforeLambdaBody`` has been added to manage lambda + line break inside function parameter call in Allman style. + + .. code-block:: c++ + + true: + connect( + []() + { + foo(); + bar(); + }); + + false: + connect([]() { + foo(); + bar(); + }); + +libclang +-------- + +- ... + +Static Analyzer +--------------- + +- ... + +.. _release-notes-ubsan: + +Undefined Behavior Sanitizer (UBSan) +------------------------------------ + + +Core Analysis Improvements +========================== + +- ... + +New Issues Found +================ + +- ... + +Python Binding Changes +---------------------- + +The following methods have been added: + +- ... + +Significant Known Problems +========================== + +Additional Information +====================== + +A wide variety of additional information is available on the `Clang web +page `_. The web page contains versions of the +API documentation which are up-to-date with the Subversion version of +the source code. You can access versions of these documents specific to +this release by going into the "``clang/docs/``" directory in the Clang +tree. + +If you have any questions or comments about Clang, please feel free to +contact us via the `mailing +list `_. From fe36127982e0a5889cc0653718e62ba6acccf7c4 Mon Sep 17 00:00:00 2001 From: Francesco Petrogalli Date: Thu, 13 Feb 2020 22:03:41 +0000 Subject: [PATCH 18/57] [build] Fix shared lib builds. --- llvm/lib/DebugInfo/GSYM/LLVMBuild.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/DebugInfo/GSYM/LLVMBuild.txt b/llvm/lib/DebugInfo/GSYM/LLVMBuild.txt index d3cf7653abf41..c27c5f1f38eff 100644 --- a/llvm/lib/DebugInfo/GSYM/LLVMBuild.txt +++ b/llvm/lib/DebugInfo/GSYM/LLVMBuild.txt @@ -18,4 +18,4 @@ type = Library name = DebugInfoGSYM parent = DebugInfo -required_libraries = MC Support +required_libraries = MC Support DebugInfoDWARF From 19b62b79db1bb154b40e8baba9a28ab8aa935b6b Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Thu, 13 Feb 2020 16:08:15 -0500 Subject: [PATCH 19/57] [VectorCombine] try to form vector binop to eliminate an extract element binop (extelt X, C), (extelt Y, C) --> extelt (binop X, Y), C This is a transform that has been considered for canonicalization (instcombine) in the past because it reduces instruction count. But as shown in the x86 tests, it's impossible to know if it's profitable without a cost model. There are many potential target constraints to consider. We have implemented similar transforms in the backend (DAGCombiner and target-specific), but I don't think we have this exact fold there either (and if we did it in SDAG, it wouldn't work across blocks). Note: this patch was intended to handle the more general case where the extract indexes do not match, but it got too big, so I scaled it back to this pattern for now. Differential Revision: https://reviews.llvm.org/D74495 --- .../Transforms/Vectorize/VectorCombine.cpp | 83 ++++++++++++++++++- .../VectorCombine/X86/extract-binop.ll | 56 ++++++++++--- 2 files changed, 126 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index 2c6987893e9e1..a70d962a8f485 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -16,6 +16,7 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/GlobalsModRef.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" #include "llvm/IR/IRBuilder.h" @@ -30,6 +31,7 @@ using namespace llvm::PatternMatch; #define DEBUG_TYPE "vector-combine" STATISTIC(NumVecCmp, "Number of vector compares formed"); +STATISTIC(NumVecBO, "Number of vector binops formed"); static bool foldExtractCmp(Instruction &I, const TargetTransformInfo &TTI) { // Match a cmp with extracted vector operands. @@ -76,6 +78,85 @@ static bool foldExtractCmp(Instruction &I, const TargetTransformInfo &TTI) { return true; } +/// Try to reduce extract element costs by converting scalar binops to vector +/// binops followed by extract. +static bool foldExtractBinop(Instruction &I, const TargetTransformInfo &TTI) { + // It is not safe to transform things like div, urem, etc. because we may + // create undefined behavior when executing those on unknown vector elements. + if (!isSafeToSpeculativelyExecute(&I)) + return false; + + // Match a scalar binop with extracted vector operands: + // bo (extelt X, C0), (extelt Y, C1) + Instruction *Ext0, *Ext1; + if (!match(&I, m_BinOp(m_Instruction(Ext0), m_Instruction(Ext1)))) + return false; + + Value *X, *Y; + uint64_t C0, C1; + if (!match(Ext0, m_ExtractElement(m_Value(X), m_ConstantInt(C0))) || + !match(Ext1, m_ExtractElement(m_Value(Y), m_ConstantInt(C1))) || + X->getType() != Y->getType()) + return false; + + // Check if using a vector binop would be cheaper. + Instruction::BinaryOps BOpcode = cast(I).getOpcode(); + Type *ScalarTy = I.getType(); + Type *VecTy = X->getType(); + int ScalarBOCost = TTI.getArithmeticInstrCost(BOpcode, ScalarTy); + int VecBOCost = TTI.getArithmeticInstrCost(BOpcode, VecTy); + int Extract0Cost = TTI.getVectorInstrCost(Instruction::ExtractElement, + VecTy, C0); + int Extract1Cost = TTI.getVectorInstrCost(Instruction::ExtractElement, + VecTy, C1); + + // Handle a special case - if the extract indexes are the same, the + // replacement sequence does not require a shuffle. Unless the vector binop is + // much more expensive than the scalar binop, this eliminates an extract. + // Extra uses of the extracts mean that we include those costs in the + // vector total because those instructions will not be eliminated. + if (C0 == C1) { + assert(Extract0Cost == Extract1Cost && "Different costs for same extract?"); + int ExtractCost = Extract0Cost; + if (X != Y) { + int ScalarCost = ExtractCost + ExtractCost + ScalarBOCost; + int VecCost = VecBOCost + ExtractCost + + !Ext0->hasOneUse() * ExtractCost + + !Ext1->hasOneUse() * ExtractCost; + if (ScalarCost <= VecCost) + return false; + } else { + // Handle an extra-special case. If the 2 binop operands are identical, + // adjust the formulas to account for that: + // bo (extelt X, C), (extelt X, C) --> extelt (bo X, X), C + // The extra use charge allows for either the CSE'd pattern or an + // unoptimized form with identical values. + bool HasUseTax = Ext0 == Ext1 ? !Ext0->hasNUses(2) + : !Ext0->hasOneUse() || !Ext1->hasOneUse(); + int ScalarCost = ExtractCost + ScalarBOCost; + int VecCost = VecBOCost + ExtractCost + HasUseTax * ExtractCost; + if (ScalarCost <= VecCost) + return false; + } + + // bo (extelt X, C), (extelt Y, C) --> extelt (bo X, Y), C + ++NumVecBO; + IRBuilder<> Builder(&I); + Value *NewBO = Builder.CreateBinOp(BOpcode, X, Y); + if (auto *VecBOInst = dyn_cast(NewBO)) { + // All IR flags are safe to back-propagate because any potential poison + // created in unused vector elements is discarded by the extract. + VecBOInst->copyIRFlags(&I); + } + Value *Extract = Builder.CreateExtractElement(NewBO, Ext0->getOperand(1)); + I.replaceAllUsesWith(Extract); + return true; + } + + // TODO: Handle C0 != C1 by shuffling 1 of the operands. + return false; +} + /// This is the entry point for all transforms. Pass manager differences are /// handled in the callers of this function. static bool runImpl(Function &F, const TargetTransformInfo &TTI, @@ -92,7 +173,7 @@ static bool runImpl(Function &F, const TargetTransformInfo &TTI, // iteratively in this loop rather than waiting until the end. for (Instruction &I : make_range(BB.rbegin(), BB.rend())) { MadeChange |= foldExtractCmp(I, TTI); - // TODO: More transforms go here. + MadeChange |= foldExtractBinop(I, TTI); } } diff --git a/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll b/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll index 1610a323a6211..434d7d37d1e47 100644 --- a/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll +++ b/llvm/test/Transforms/VectorCombine/X86/extract-binop.ll @@ -1,12 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- | FileCheck %s +; Eliminating extract is profitable. + define i8 @ext0_ext0_add(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext0_ext0_add( -; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 -; CHECK-NEXT: [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 0 -; CHECK-NEXT: [[R:%.*]] = add i8 [[E0]], [[E1]] -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: [[TMP1:%.*]] = add <16 x i8> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0 +; CHECK-NEXT: ret i8 [[TMP2]] ; %e0 = extractelement <16 x i8> %x, i32 0 %e1 = extractelement <16 x i8> %y, i32 0 @@ -14,12 +15,13 @@ define i8 @ext0_ext0_add(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Eliminating extract is still profitable. Flags propagate. + define i8 @ext1_ext1_add_flags(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext1_ext1_add_flags( -; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 1 -; CHECK-NEXT: [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 1 -; CHECK-NEXT: [[R:%.*]] = add nuw nsw i8 [[E0]], [[E1]] -; CHECK-NEXT: ret i8 [[R]] +; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw <16 x i8> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x i8> [[TMP1]], i32 1 +; CHECK-NEXT: ret i8 [[TMP2]] ; %e0 = extractelement <16 x i8> %x, i32 1 %e1 = extractelement <16 x i8> %y, i32 1 @@ -27,6 +29,8 @@ define i8 @ext1_ext1_add_flags(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Negative test - eliminating extract is profitable, but vector shift is expensive. + define i8 @ext1_ext1_shl(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext1_ext1_shl( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 1 @@ -40,6 +44,8 @@ define i8 @ext1_ext1_shl(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Negative test - eliminating extract is profitable, but vector multiply is expensive. + define i8 @ext13_ext13_mul(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext13_ext13_mul( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 13 @@ -53,6 +59,8 @@ define i8 @ext13_ext13_mul(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Negative test - cost is irrelevant because sdiv has potential UB. + define i8 @ext0_ext0_sdiv(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext0_ext0_sdiv( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -66,6 +74,8 @@ define i8 @ext0_ext0_sdiv(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Negative test - extracts are free and vector op has same cost as scalar. + define double @ext0_ext0_fadd(<2 x double> %x, <2 x double> %y) { ; CHECK-LABEL: @ext0_ext0_fadd( ; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x double> [[X:%.*]], i32 0 @@ -79,12 +89,13 @@ define double @ext0_ext0_fadd(<2 x double> %x, <2 x double> %y) { ret double %r } +; Eliminating extract is profitable. Flags propagate. + define double @ext1_ext1_fsub(<2 x double> %x, <2 x double> %y) { ; CHECK-LABEL: @ext1_ext1_fsub( -; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x double> [[X:%.*]], i32 1 -; CHECK-NEXT: [[E1:%.*]] = extractelement <2 x double> [[Y:%.*]], i32 1 -; CHECK-NEXT: [[R:%.*]] = fsub fast double [[E0]], [[E1]] -; CHECK-NEXT: ret double [[R]] +; CHECK-NEXT: [[TMP1:%.*]] = fsub fast <2 x double> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 +; CHECK-NEXT: ret double [[TMP2]] ; %e0 = extractelement <2 x double> %x, i32 1 %e1 = extractelement <2 x double> %y, i32 1 @@ -92,6 +103,8 @@ define double @ext1_ext1_fsub(<2 x double> %x, <2 x double> %y) { ret double %r } +; Negative test - type mismatch. + define double @ext1_ext1_fadd_different_types(<2 x double> %x, <4 x double> %y) { ; CHECK-LABEL: @ext1_ext1_fadd_different_types( ; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x double> [[X:%.*]], i32 1 @@ -105,6 +118,8 @@ define double @ext1_ext1_fadd_different_types(<2 x double> %x, <4 x double> %y) ret double %r } +; Negative test - disguised same vector operand; scalar code is cheaper than general case. + define i32 @ext1_ext1_add_same_vec(<4 x i32> %x) { ; CHECK-LABEL: @ext1_ext1_add_same_vec( ; CHECK-NEXT: [[E0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 1 @@ -118,6 +133,8 @@ define i32 @ext1_ext1_add_same_vec(<4 x i32> %x) { ret i32 %r } +; Negative test - same vector operand; scalar code is cheaper than general case. + define i32 @ext1_ext1_add_same_vec_cse(<4 x i32> %x) { ; CHECK-LABEL: @ext1_ext1_add_same_vec_cse( ; CHECK-NEXT: [[E0:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 1 @@ -131,6 +148,9 @@ define i32 @ext1_ext1_add_same_vec_cse(<4 x i32> %x) { declare void @use_i8(i8) +; Negative test - same vector operand; scalar code is cheaper than general case +; and vector code would be more expensive still. + define i8 @ext1_ext1_add_same_vec_extra_use0(<16 x i8> %x) { ; CHECK-LABEL: @ext1_ext1_add_same_vec_extra_use0( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -146,6 +166,9 @@ define i8 @ext1_ext1_add_same_vec_extra_use0(<16 x i8> %x) { ret i8 %r } +; Negative test - same vector operand; scalar code is cheaper than general case +; and vector code would be more expensive still. + define i8 @ext1_ext1_add_same_vec_extra_use1(<16 x i8> %x) { ; CHECK-LABEL: @ext1_ext1_add_same_vec_extra_use1( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -161,6 +184,9 @@ define i8 @ext1_ext1_add_same_vec_extra_use1(<16 x i8> %x) { ret i8 %r } +; Negative test - same vector operand; scalar code is cheaper than general case +; and vector code would be more expensive still. + define i8 @ext1_ext1_add_same_vec_cse_extra_use(<16 x i8> %x) { ; CHECK-LABEL: @ext1_ext1_add_same_vec_cse_extra_use( ; CHECK-NEXT: [[E:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -174,6 +200,8 @@ define i8 @ext1_ext1_add_same_vec_cse_extra_use(<16 x i8> %x) { ret i8 %r } +; Negative test - vector code would not be cheaper. + define i8 @ext1_ext1_add_uses1(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext1_ext1_add_uses1( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -189,6 +217,8 @@ define i8 @ext1_ext1_add_uses1(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; Negative test - vector code would not be cheaper. + define i8 @ext1_ext1_add_uses2(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext1_ext1_add_uses2( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 @@ -204,6 +234,8 @@ define i8 @ext1_ext1_add_uses2(<16 x i8> %x, <16 x i8> %y) { ret i8 %r } +; TODO: Different extract indexes requires a shuffle. + define i8 @ext0_ext1_add(<16 x i8> %x, <16 x i8> %y) { ; CHECK-LABEL: @ext0_ext1_add( ; CHECK-NEXT: [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0 From 8e77b33b3c67aa8f2580671b019eeb3862651ecb Mon Sep 17 00:00:00 2001 From: Vedant Kumar Date: Mon, 10 Feb 2020 15:37:56 -0800 Subject: [PATCH 20/57] [Local] Do not move around dbg.declares during replaceDbgDeclare replaceDbgDeclare is used to update the descriptions of stack variables when they are moved (e.g. by ASan or SafeStack). A side effect of replaceDbgDeclare is that it moves dbg.declares around in the instruction stream (typically by hoisting them into the entry block). This behavior was introduced in llvm/r227544 to fix an assertion failure (llvm.org/PR22386), but no longer appears to be necessary. Hoisting a dbg.declare generally does not create problems. Usually, dbg.declare either describes an argument or an alloca in the entry block, and backends have special handling to emit locations for these. In optimized builds, LowerDbgDeclare places dbg.values in the right spots regardless of where the dbg.declare is. And no one uses replaceDbgDeclare to handle things like VLAs. However, there doesn't seem to be a positive case for moving dbg.declares around anymore, and this reordering can get in the way of understanding other bugs. I propose getting rid of it. Testing: stage2 RelWithDebInfo sanitized build, check-llvm rdar://59397340 Differential Revision: https://reviews.llvm.org/D74517 --- llvm/include/llvm/Transforms/Utils/Local.h | 13 +------------ llvm/lib/CodeGen/SafeStack.cpp | 9 ++++----- .../Instrumentation/AddressSanitizer.cpp | 4 ++-- llvm/lib/Transforms/Utils/InlineFunction.cpp | 4 ---- llvm/lib/Transforms/Utils/Local.cpp | 17 ++++------------- .../AddressSanitizer/debug_info.ll | 6 +----- .../AddressSanitizer/local_stack_base.ll | 6 +++++- .../Inline/alloca-dbgdeclare-merge.ll | 16 +++++++++++----- .../test/Transforms/Inline/alloca-dbgdeclare.ll | 4 ++++ .../Transforms/Inline/inline_dbg_declare.ll | 3 ++- llvm/unittests/Transforms/Utils/LocalTest.cpp | 2 +- 11 files changed, 35 insertions(+), 49 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h index 38e3c14f7ef9c..8ccd9031b568b 100644 --- a/llvm/include/llvm/Transforms/Utils/Local.h +++ b/llvm/include/llvm/Transforms/Utils/Local.h @@ -332,20 +332,9 @@ void findDbgUsers(SmallVectorImpl &DbgInsts, Value *V); /// additional DW_OP_deref is prepended to the expression. If Offset /// is non-zero, a constant displacement is added to the expression /// (between the optional Deref operations). Offset can be negative. -bool replaceDbgDeclare(Value *Address, Value *NewAddress, - Instruction *InsertBefore, DIBuilder &Builder, +bool replaceDbgDeclare(Value *Address, Value *NewAddress, DIBuilder &Builder, uint8_t DIExprFlags, int Offset); -/// Replaces llvm.dbg.declare instruction when the alloca it describes -/// is replaced with a new value. If Deref is true, an additional -/// DW_OP_deref is prepended to the expression. If Offset is non-zero, -/// a constant displacement is added to the expression (between the -/// optional Deref operations). Offset can be negative. The new -/// llvm.dbg.declare is inserted immediately after AI. -bool replaceDbgDeclareForAlloca(AllocaInst *AI, Value *NewAllocaAddress, - DIBuilder &Builder, uint8_t DIExprFlags, - int Offset); - /// Replaces multiple llvm.dbg.value instructions when the alloca it describes /// is replaced with a new value. If Offset is non-zero, a constant displacement /// is added to the expression (after the mandatory Deref). Offset can be diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp index 136a10fb607e9..8808d90175a8f 100644 --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -576,8 +576,8 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( Arg->getName() + ".unsafe-byval"); // Replace alloc with the new location. - replaceDbgDeclare(Arg, BasePointer, BasePointer->getNextNode(), DIB, - DIExpression::ApplyOffset, -Offset); + replaceDbgDeclare(Arg, BasePointer, DIB, DIExpression::ApplyOffset, + -Offset); Arg->replaceAllUsesWith(NewArg); IRB.SetInsertPoint(cast(NewArg)->getNextNode()); IRB.CreateMemCpy(Off, Align, Arg, Arg->getParamAlign(), Size); @@ -588,8 +588,7 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack( IRB.SetInsertPoint(AI); unsigned Offset = SSL.getObjectOffset(AI); - replaceDbgDeclareForAlloca(AI, BasePointer, DIB, DIExpression::ApplyOffset, - -Offset); + replaceDbgDeclare(AI, BasePointer, DIB, DIExpression::ApplyOffset, -Offset); replaceDbgValueForAlloca(AI, BasePointer, DIB, -Offset); // Replace uses of the alloca with the new location. @@ -676,7 +675,7 @@ void SafeStack::moveDynamicAllocasToUnsafeStack( if (AI->hasName() && isa(NewAI)) NewAI->takeName(AI); - replaceDbgDeclareForAlloca(AI, NewAI, DIB, DIExpression::ApplyOffset, 0); + replaceDbgDeclare(AI, NewAI, DIB, DIExpression::ApplyOffset, 0); AI->replaceAllUsesWith(NewAI); AI->eraseFromParent(); } diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp index ae537a83ccb01..98cbd2ca841ff 100644 --- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp @@ -3132,8 +3132,8 @@ void FunctionStackPoisoner::processStaticAllocas() { // Replace Alloca instructions with base+offset. for (const auto &Desc : SVD) { AllocaInst *AI = Desc.AI; - replaceDbgDeclareForAlloca(AI, LocalStackBaseAllocaPtr, DIB, DIExprFlags, - Desc.Offset); + replaceDbgDeclare(AI, LocalStackBaseAllocaPtr, DIB, DIExprFlags, + Desc.Offset); Value *NewAllocaPtr = IRB.CreateIntToPtr( IRB.CreateAdd(LocalStackBase, ConstantInt::get(IntptrTy, Desc.Offset)), AI->getType()); diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index 808937724ea72..fcbe96d340613 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -1848,10 +1848,6 @@ llvm::InlineResult llvm::InlineFunction(CallSite CS, InlineFunctionInfo &IFI, Caller->getEntryBlock().getInstList().splice( InsertPoint, FirstNewBlock->getInstList(), AI->getIterator(), I); } - // Move any dbg.declares describing the allocas into the entry basic block. - DIBuilder DIB(*Caller->getParent()); - for (auto &AI : IFI.StaticAllocas) - replaceDbgDeclareForAlloca(AI, AI, DIB, DIExpression::ApplyOffset, 0); } SmallVector VarArgsToForward; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index aad960230f5ce..0fb5ac8ebcc32 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1568,8 +1568,8 @@ void llvm::findDbgUsers(SmallVectorImpl &DbgUsers, } bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress, - Instruction *InsertBefore, DIBuilder &Builder, - uint8_t DIExprFlags, int Offset) { + DIBuilder &Builder, uint8_t DIExprFlags, + int Offset) { auto DbgAddrs = FindDbgAddrUses(Address); for (DbgVariableIntrinsic *DII : DbgAddrs) { DebugLoc Loc = DII->getDebugLoc(); @@ -1577,23 +1577,14 @@ bool llvm::replaceDbgDeclare(Value *Address, Value *NewAddress, auto *DIExpr = DII->getExpression(); assert(DIVar && "Missing variable"); DIExpr = DIExpression::prepend(DIExpr, DIExprFlags, Offset); - // Insert llvm.dbg.declare immediately before InsertBefore, and remove old + // Insert llvm.dbg.declare immediately before DII, and remove old // llvm.dbg.declare. - Builder.insertDeclare(NewAddress, DIVar, DIExpr, Loc, InsertBefore); - if (DII == InsertBefore) - InsertBefore = InsertBefore->getNextNode(); + Builder.insertDeclare(NewAddress, DIVar, DIExpr, Loc, DII); DII->eraseFromParent(); } return !DbgAddrs.empty(); } -bool llvm::replaceDbgDeclareForAlloca(AllocaInst *AI, Value *NewAllocaAddress, - DIBuilder &Builder, uint8_t DIExprFlags, - int Offset) { - return replaceDbgDeclare(AI, NewAllocaAddress, AI->getNextNode(), Builder, - DIExprFlags, Offset); -} - static void replaceOneDbgValueForAlloca(DbgValueInst *DVI, Value *NewAddress, DIBuilder &Builder, int Offset) { DebugLoc Loc = DVI->getDebugLoc(); diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll index 97faa1aff469f..c0389daddacd4 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll @@ -21,15 +21,11 @@ entry: } ; CHECK: define i32 @_Z3zzzi -; CHECK: entry: -; Verify that llvm.dbg.declare calls are in the entry basic block. -; CHECK-NEXT: [[MyAlloca:%.*]] = alloca i8, i64 64 -; CHECK-NOT: %entry +; CHECK: [[MyAlloca:%.*]] = alloca i8, i64 64 ; Note: these dbg.declares used to contain `ptrtoint` operands. The instruction ; selector would then decline to put the variable in the MachineFunction side ; table. Check that the dbg.declares have `alloca` operands. ; CHECK: call void @llvm.dbg.declare(metadata i8* [[MyAlloca]], metadata ![[ARG_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 32)) -; CHECK-NOT: %entry ; CHECK: call void @llvm.dbg.declare(metadata i8* [[MyAlloca]], metadata ![[VAR_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 48)) declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone diff --git a/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll b/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll index 67e13e56414fd..7bf294cb6b600 100644 --- a/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/local_stack_base.ll @@ -19,12 +19,16 @@ entry: ; CHECK: %[[ALLOCA:.*]] = ptrtoint i8* %MyAlloca to i64 ; CHECK: %[[PHI:.*]] = phi i64 {{.*}} %[[ALLOCA]], ; CHECK: store i64 %[[PHI]], i64* %asan_local_stack_base - ; CHECK: call void @llvm.dbg.declare(metadata i64* %asan_local_stack_base, metadata !12, metadata !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32)), !dbg !13 +; CHECK: call void @llvm.dbg.declare(metadata i64* %asan_local_stack_base, metadata [[VAR_I:![0-9]+]], metadata !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32)), !dbg [[LOC_I:![0-9]+]] %0 = load i32, i32* %i.addr, align 4, !dbg !14 %add = add nsw i32 %0, 2, !dbg !15 ret i32 %add, !dbg !16 } +; CHECK: [[SCOPE:![0-9]+]] = distinct !DISubprogram(name: "foo" +; CHECK: [[VAR_I]] = !DILocalVariable(name: "i", arg: 1, scope: [[SCOPE]] +; CHECK: [[LOC_I]] = !DILocation(line: 1, column: 13, scope: [[SCOPE]] + ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 diff --git a/llvm/test/Transforms/Inline/alloca-dbgdeclare-merge.ll b/llvm/test/Transforms/Inline/alloca-dbgdeclare-merge.ll index e0e51b268fe71..d0a2bf3b1c9f8 100644 --- a/llvm/test/Transforms/Inline/alloca-dbgdeclare-merge.ll +++ b/llvm/test/Transforms/Inline/alloca-dbgdeclare-merge.ll @@ -1,6 +1,5 @@ -; Test that alloca merging in the inliner places dbg.declare calls immediately -; after the merged alloca. Not at the end of the entry BB, and definitely not -; before the alloca. +; Test that alloca merging in the inliner places dbg.declare calls after the +; merged alloca, but does not otherwise reorder them. ; ; clang -g -S -emit-llvm -Xclang -disable-llvm-optzns ; @@ -20,13 +19,20 @@ ;} ; ; RUN: opt -always-inline -S < %s | FileCheck %s + +; FIXME: Why does the dbg.declare for "aaa" occur later in @h than the +; dbg.declare for "bbb"? I'd expect the opposite, given @f is inlined earlier. ; ; CHECK: define void @h() ; CHECK-NEXT: entry: ; CHECK-NEXT: %[[AI:.*]] = alloca [100 x i8] -; CHECK-NEXT: call void @llvm.dbg.declare(metadata [100 x i8]* %[[AI]], -; CHECK-NEXT: call void @llvm.dbg.declare(metadata [100 x i8]* %[[AI]], +; CHECK-NEXT: call void @llvm.dbg.declare(metadata [100 x i8]* %[[AI]], metadata [[BBB:![0-9]+]] +; CHECK-NEXT: bitcast +; CHECK-NEXT: llvm.lifetime.start +; CHECK-NEXT: call void @llvm.dbg.declare(metadata [100 x i8]* %[[AI]], metadata [[AAA:![0-9]+]] +; CHECK: [[AAA]] = !DILocalVariable(name: "aaa" +; CHECK: [[BBB]] = !DILocalVariable(name: "bbb" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll b/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll index 07e931d0d2274..1dbe996343b2d 100644 --- a/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll +++ b/llvm/test/Transforms/Inline/alloca-dbgdeclare.ll @@ -42,6 +42,10 @@ entry: ; CHECK: define void @_Z3fn5v() ; CHECK-NEXT: entry: ; CHECK-NEXT: %agg.tmp.sroa.3.i = alloca [20 x i8], align 4 +; CHECK-NEXT: br label %while.body +; CHECK: while.body: +; CHECK-NEXT: bitcast +; CHECK-NEXT: llvm.lifetime.start ; CHECK-NEXT: call void @llvm.dbg.declare(metadata [20 x i8]* %agg.tmp.sroa.3.i, %agg.tmp.sroa.3 = alloca [20 x i8], align 4 tail call void @llvm.dbg.declare(metadata [20 x i8]* %agg.tmp.sroa.3, metadata !25, metadata !30), !dbg !31 diff --git a/llvm/test/Transforms/Inline/inline_dbg_declare.ll b/llvm/test/Transforms/Inline/inline_dbg_declare.ll index 74ab8537970c7..bfbfb8e76d51d 100644 --- a/llvm/test/Transforms/Inline/inline_dbg_declare.ll +++ b/llvm/test/Transforms/Inline/inline_dbg_declare.ll @@ -42,7 +42,8 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 define void @bar(float* %dst) #0 !dbg !9 { entry: -; CHECK: [[x_addr_i:%[a-zA-Z0-9.]+]] = alloca float, align 4 +; CHECK: [[x_addr_i:%.+]] = alloca float, align 4 +; CHECK: store float {{.*}}, float* [[x_addr_i]] ; CHECK-NEXT: void @llvm.dbg.declare(metadata float* [[x_addr_i]], metadata [[m23:![0-9]+]], metadata !DIExpression()), !dbg [[m24:![0-9]+]] %dst.addr = alloca float*, align 4 diff --git a/llvm/unittests/Transforms/Utils/LocalTest.cpp b/llvm/unittests/Transforms/Utils/LocalTest.cpp index 5551a07beb90d..cd32669ca2f61 100644 --- a/llvm/unittests/Transforms/Utils/LocalTest.cpp +++ b/llvm/unittests/Transforms/Utils/LocalTest.cpp @@ -154,7 +154,7 @@ TEST(Local, ReplaceDbgDeclare) { ASSERT_TRUE(DII); Value *NewBase = Constant::getNullValue(Type::getInt32PtrTy(C)); DIBuilder DIB(*M); - replaceDbgDeclare(AI, NewBase, DII, DIB, DIExpression::ApplyOffset, 0); + replaceDbgDeclare(AI, NewBase, DIB, DIExpression::ApplyOffset, 0); // There should be exactly two dbg.declares. int Declares = 0; From 30910494467256e2c60a86c9c091fb682dbfe376 Mon Sep 17 00:00:00 2001 From: Vedant Kumar Date: Thu, 13 Feb 2020 14:38:42 -0800 Subject: [PATCH 21/57] Add dbgs() output to help track down missing DW_AT_location bugs, NFC --- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 8 +++++++- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 9 ++++++--- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 12 +++++++++--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 7 ++++++- 4 files changed, 28 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 6f011fe497891..72f0f610c8dbc 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -1352,6 +1352,7 @@ void DwarfDebug::ensureAbstractEntityIsCreatedIfScoped(DwarfCompileUnit &CU, void DwarfDebug::collectVariableInfoFromMFTable( DwarfCompileUnit &TheCU, DenseSet &Processed) { SmallDenseMap MFVars; + LLVM_DEBUG(dbgs() << "DwarfDebug: collecting variables from MF side table\n"); for (const auto &VI : Asm->MF->getVariableDbgInfo()) { if (!VI.Var) continue; @@ -1363,13 +1364,18 @@ void DwarfDebug::collectVariableInfoFromMFTable( LexicalScope *Scope = LScopes.findLexicalScope(VI.Loc); // If variable scope is not found then skip this variable. - if (!Scope) + if (!Scope) { + LLVM_DEBUG(dbgs() << "Dropping debug info for " << VI.Var->getName() + << ", no variable scope found\n"); continue; + } ensureAbstractEntityIsCreatedIfScoped(TheCU, Var.first, Scope->getScopeNode()); auto RegVar = std::make_unique( cast(Var.first), Var.second); RegVar->initializeMMI(VI.Expr, VI.Slot); + LLVM_DEBUG(dbgs() << "Created DbgVariable for " << VI.Var->getName() + << "\n"); if (DbgVariable *DbgVar = MFVars.lookup(Var)) DbgVar->addMMIEntry(*RegVar); else if (InfoHolder.addScopeVariable(Scope, RegVar.get())) { diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 9f78a1b4ca9fd..ada09092c4782 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1350,13 +1350,15 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { const DbgDeclareInst *DI = cast(II); assert(DI->getVariable() && "Missing variable"); if (!FuncInfo.MF->getMMI().hasDebugInfo()) { - LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI + << " (!hasDebugInfo)\n"); return true; } const Value *Address = DI->getAddress(); if (!Address || isa(Address)) { - LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI + << " (bad/undef address)\n"); return true; } @@ -1399,7 +1401,8 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) { } else { // We can't yet handle anything else here because it would require // generating code, thus altering codegen because of debug info. - LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << *DI + << " (no materialized reg for address)\n"); } return true; } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index dab8637515668..aa3a848bb1c4b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5945,12 +5945,14 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, DIExpression *Expression = DI.getExpression(); dropDanglingDebugInfo(Variable, Expression); assert(Variable && "Missing variable"); - + LLVM_DEBUG(dbgs() << "SelectionDAG visiting debug intrinsic: " << DI + << "\n"); // Check if address has undef value. const Value *Address = DI.getVariableLocation(); if (!Address || isa(Address) || (Address->use_empty() && !isa(Address))) { - LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI + << " (bad/undef/unused-arg address)\n"); return; } @@ -5979,6 +5981,9 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, SDDbgValue *SDV = DAG.getFrameIndexDbgValue( Variable, Expression, FI, /*IsIndirect*/ true, dl, SDNodeOrder); DAG.AddDbgValue(SDV, getRoot().getNode(), isParameter); + } else { + LLVM_DEBUG(dbgs() << "Skipping " << DI + << " (variable info stashed in MF side table)\n"); } return; } @@ -6013,7 +6018,8 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, // virtual register info from the FuncInfo.ValueMap. if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, true, N)) { - LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n"); + LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI + << " (could not emit func-arg dbg_value)\n"); } } return; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index b83c902642741..51b2439dddc3d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1321,8 +1321,11 @@ static void processDbgDeclares(FunctionLoweringInfo &FuncInfo) { assert(DI->getVariable() && "Missing variable"); assert(DI->getDebugLoc() && "Missing location"); const Value *Address = DI->getAddress(); - if (!Address) + if (!Address) { + LLVM_DEBUG(dbgs() << "processDbgDeclares skipping " << *DI + << " (bad address)\n"); continue; + } // Look through casts and constant offset GEPs. These mostly come from // inalloca. @@ -1347,6 +1350,8 @@ static void processDbgDeclares(FunctionLoweringInfo &FuncInfo) { if (Offset.getBoolValue()) Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset.getZExtValue()); + LLVM_DEBUG(dbgs() << "processDbgDeclares: setVariableDbgInfo FI=" << FI + << ", " << *DI << "\n"); MF->setVariableDbgInfo(DI->getVariable(), Expr, FI, DI->getDebugLoc()); } } From 88ec01ca1bfa4c3a29225db93d36e6d32278190d Mon Sep 17 00:00:00 2001 From: Melanie Blower Date: Thu, 13 Feb 2020 14:40:01 -0800 Subject: [PATCH 22/57] Revert "Revert "Revert "Change clang option -ffp-model=precise to select ffp-contract=on""" This reverts commit abd09053bc7aa6144873c196a7d50aa6ce6ca430. It's causing internal buildbot fails on ppc Conflicts: clang/lib/Driver/ToolChains/Clang.cpp --- clang/docs/UsersManual.rst | 48 ++------------------------- clang/lib/Driver/ToolChains/Clang.cpp | 21 ++++++------ clang/test/CodeGen/ppc-emmintrin.c | 4 +-- clang/test/CodeGen/ppc-xmmintrin.c | 4 +-- clang/test/Driver/fp-model.c | 7 ++-- 5 files changed, 21 insertions(+), 63 deletions(-) diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 6c8c9f8020823..856d5e34bbcc2 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -1190,50 +1190,8 @@ installed. Controlling Floating Point Behavior ----------------------------------- -Clang provides a number of ways to control floating point behavior, including -with command line options and source pragmas. This section -describes the various floating point semantic modes and the corresponding options. - -.. csv-table:: Floating Point Semantic Modes - :header: "Mode", "Values" - :widths: 15, 30, 30 - - "except_behavior", "{ignore, strict, may_trap}", "ffp-exception-behavior" - "fenv_access", "{off, on}", "(none)" - "rounding_mode", "{dynamic, tonearest, downward, upward, towardzero}", "frounding-math" - "contract", "{on, off, fast}", "ffp-contract" - "denormal_fp_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math" - "denormal_fp32_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math-fp32" - "support_math_errno", "{on, off}", "fmath-errno" - "no_honor_nans", "{on, off}", "fhonor-nans" - "no_honor_infinities", "{on, off}", "fhonor-infinities" - "no_signed_zeros", "{on, off}", "fsigned-zeros" - "allow_reciprocal", "{on, off}", "freciprocal-math" - "allow_approximate_fns", "{on, off}", "(none)" - "allow_reassociation", "{on, off}", "fassociative-math" - - -This table describes the option settings that correspond to the three -floating point semantic models: precise (the default), strict, and fast. - - -.. csv-table:: Floating Point Models - :header: "Mode", "Precise", "Strict", "Fast" - :widths: 25, 15, 15, 15 - - "except_behavior", "ignore", "strict", "ignore" - "fenv_access", "off", "on", "off" - "rounding_mode", "tonearest", "dynamic", "tonearest" - "contract", "on", "off", "fast" - "denormal_fp_math", "IEEE", "IEEE", "PreserveSign" - "denormal_fp32_math", "IEEE","IEEE", "PreserveSign" - "support_math_errno", "on", "on", "off" - "no_honor_nans", "off", "off", "on" - "no_honor_infinities", "off", "off", "on" - "no_signed_zeros", "off", "off", "on" - "allow_reciprocal", "off", "off", "on" - "allow_approximate_fns", "off", "off", "on" - "allow_reassociation", "off", "off", "on" +Clang provides a number of ways to control floating point behavior. The options +are listed below. .. option:: -ffast-math @@ -1427,7 +1385,7 @@ Note that floating-point operations performed as part of constant initialization and ``fast``. Details: - * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=on``). This is the default behavior. + * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=fast``). This is the default behavior. * ``strict`` Enables ``-frounding-math`` and ``-ffp-exception-behavior=strict``, and disables contractions (FMA). All of the ``-ffast-math`` enablements are disabled. * ``fast`` Behaves identically to specifying both ``-ffast-math`` and ``ffp-contract=fast`` diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index d1197556aeefd..5a207f3ca9f71 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2525,9 +2525,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath; llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math; - StringRef FPContract = "on"; + StringRef FPContract = ""; bool StrictFPModel = false; + if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) { CmdArgs.push_back("-mlimit-float-precision"); CmdArgs.push_back(A->getValue()); @@ -2550,6 +2551,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, SignedZeros = true; // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; + FPContract = ""; StringRef Val = A->getValue(); if (OFastEnabled && !Val.equals("fast")) { // Only -ffp-model=fast is compatible with OFast, ignore. @@ -2563,10 +2565,12 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // ffp-model= is a Driver option, it is entirely rewritten into more // granular options before being passed into cc1. // Use the gcc option in the switch below. - if (!FPModel.empty() && !FPModel.equals(Val)) + if (!FPModel.empty() && !FPModel.equals(Val)) { D.Diag(clang::diag::warn_drv_overriding_flag_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); + FPContract = ""; + } if (Val.equals("fast")) { optID = options::OPT_ffast_math; FPModel = Val; @@ -2574,14 +2578,13 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, } else if (Val.equals("precise")) { optID = options::OPT_ffp_contract; FPModel = Val; - FPContract = "on"; + FPContract = "fast"; PreciseFPModel = true; } else if (Val.equals("strict")) { StrictFPModel = true; optID = options::OPT_frounding_math; FPExceptionBehavior = "strict"; FPModel = Val; - FPContract = "off"; TrappingMath = true; } else D.Diag(diag::err_drv_unsupported_option_argument) @@ -2660,11 +2663,9 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_contract: { StringRef Val = A->getValue(); if (PreciseFPModel) { - // When -ffp-model=precise is seen on the command line, - // the boolean PreciseFPModel is set to true which indicates - // "the current option is actually PreciseFPModel". The optID - // is changed to OPT_ffp_contract and FPContract is set to "on". - // the argument Val string is "precise": it shouldn't be checked. + // -ffp-model=precise enables ffp-contract=fast as a side effect + // the FPContract value has already been set to a string literal + // and the Val string isn't a pertinent value. ; } else if (Val.equals("fast") || Val.equals("on") || Val.equals("off")) FPContract = Val; @@ -2761,7 +2762,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; DenormalFP32Math = DefaultDenormalFP32Math; - FPContract = "on"; + FPContract = ""; break; } if (StrictFPModel) { diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c index c14b2dd210f89..631b6c9d2614a 100644 --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE // CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> , align 16 // CHECK-BE-DAG: @_mm_shuffle_epi32.permute_selectors = internal constant [4 x i32] [i32 66051, i32 67438087, i32 134810123, i32 202182159], align 4 diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c index d7499cbedc48d..e9466b32257f0 100644 --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE #include diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c index 8ebbc1803c655..a3984acef62b2 100644 --- a/clang/test/Driver/fp-model.c +++ b/clang/test/Driver/fp-model.c @@ -27,9 +27,9 @@ // RUN: | FileCheck --check-prefix=WARN5 %s // WARN5: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ +// RUN: %clang -### -ffp-model=strict -ffp-contract=off -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN6 %s -// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] +// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=off' [-Woverriding-t-option] // RUN: %clang -### -ffp-model=strict -ffp-contract=on -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN7 %s @@ -100,14 +100,13 @@ // RUN: %clang -### -nostdinc -ffp-model=precise -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-PRECISE %s // CHECK-FPM-PRECISE: "-cc1" -// CHECK-FPM-PRECISE: "-ffp-contract=on" +// CHECK-FPM-PRECISE: "-ffp-contract=fast" // CHECK-FPM-PRECISE: "-fno-rounding-math" // RUN: %clang -### -nostdinc -ffp-model=strict -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-STRICT %s // CHECK-FPM-STRICT: "-cc1" // CHECK-FPM-STRICT: "-ftrapping-math" -// CHECK-FPM-STRICT: "-ffp-contract=off" // CHECK-FPM-STRICT: "-frounding-math" // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict" From b21c7999520a83aedcffb7e3f9399bb3603cfcca Mon Sep 17 00:00:00 2001 From: aartbik Date: Thu, 13 Feb 2020 14:50:07 -0800 Subject: [PATCH 23/57] [mlir] [VectorOps] Initial framework for progressively lowering vector.contract Summary: This sets the basic framework for lowering vector.contract progressively into simpler vector.contract operations until a direct vector.reduction operation is reached. More details will be filled out progressively as well. Reviewers: nicolasvasilache Reviewed By: nicolasvasilache Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74520 --- .../mlir/Dialect/VectorOps/VectorOps.h | 6 ++ .../mlir/Dialect/VectorOps/VectorOps.td | 23 ++++++ .../VectorToLLVM/ConvertVectorToLLVM.cpp | 43 +++++++++-- .../Dialect/VectorOps/VectorTransforms.cpp | 72 +++++++++++++++++++ .../VectorOps/vector-contract-transforms.mlir | 26 +++++++ .../lib/Transforms/TestVectorTransforms.cpp | 17 ++++- 6 files changed, 178 insertions(+), 9 deletions(-) create mode 100644 mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorOps.h b/mlir/include/mlir/Dialect/VectorOps/VectorOps.h index 990b477157302..1aee56f90f106 100644 --- a/mlir/include/mlir/Dialect/VectorOps/VectorOps.h +++ b/mlir/include/mlir/Dialect/VectorOps/VectorOps.h @@ -54,6 +54,12 @@ void populateVectorToVectorTransformationPatterns( void populateVectorSlicesLoweringPatterns(OwningRewritePatternList &patterns, MLIRContext *context); +/// Collect a set of vector contraction transformation patterns +/// that express all vector.contract ops in terms of more elementary +/// extraction and reduction ops. +void populateVectorContractLoweringPatterns(OwningRewritePatternList &patterns, + MLIRContext *context); + /// Returns the integer type required for subscripts in the vector dialect. IntegerType getVectorSubscriptType(Builder &builder); diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td b/mlir/include/mlir/Dialect/VectorOps/VectorOps.td index 074a6d0053762..5ead87681ad04 100644 --- a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td +++ b/mlir/include/mlir/Dialect/VectorOps/VectorOps.td @@ -216,6 +216,29 @@ def Vector_ReductionOp : }]; } +// TODO(ajcbik): quick version with "fused" accumulator; next step +// will merge Reduction/ReductionV2 into one with +// an optional accumulator instead +def Vector_ReductionV2Op : + Vector_Op<"reductionv2", [NoSideEffect]>, + Arguments<(ins StrAttr:$kind, VectorOf<[F32, F64]>:$vector, AnyType:$acc)>, + Results<(outs AnyType:$dest)> { + let summary = "reduction operation"; + let description = [{ + As vector.reduction, but with a fused accumulator (add/mul for fp only). + }]; + let verifier = ?; + let assemblyFormat = [{ + $kind `,` $vector `,` $acc attr-dict `:` + type($vector) `,` type($acc) `into` type($dest) + }]; + let extraClassDeclaration = [{ + VectorType getVectorType() { + return vector().getType().cast(); + } + }]; +} + def Vector_BroadcastOp : Vector_Op<"broadcast", [NoSideEffect, PredOpTrait<"source operand and result have same element type", diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index 9fcad2f5063a4..c43fc0e847ad4 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -340,6 +340,33 @@ class VectorReductionOpConversion : public LLVMOpLowering { } }; +// TODO(ajcbik): merge Reduction and ReductionV2 +class VectorReductionV2OpConversion : public LLVMOpLowering { +public: + explicit VectorReductionV2OpConversion(MLIRContext *context, + LLVMTypeConverter &typeConverter) + : LLVMOpLowering(vector::ReductionV2Op::getOperationName(), context, + typeConverter) {} + PatternMatchResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto reductionOp = cast(op); + auto kind = reductionOp.kind(); + Type eltType = reductionOp.dest().getType(); + Type llvmType = lowering.convertType(eltType); + if (kind == "add") { + rewriter.replaceOpWithNewOp( + op, llvmType, operands[1], operands[0]); + return matchSuccess(); + } else if (kind == "mul") { + rewriter.replaceOpWithNewOp( + op, llvmType, operands[1], operands[0]); + return matchSuccess(); + } + return matchFailure(); + } +}; + class VectorShuffleOpConversion : public LLVMOpLowering { public: explicit VectorShuffleOpConversion(MLIRContext *context, @@ -1125,11 +1152,12 @@ void mlir::populateVectorToLLVMConversionPatterns( VectorInsertStridedSliceOpSameRankRewritePattern, VectorStridedSliceOpConversion>(ctx); patterns.insert(ctx, converter); + VectorReductionV2OpConversion, VectorShuffleOpConversion, + VectorExtractElementOpConversion, VectorExtractOpConversion, + VectorFMAOp1DConversion, VectorInsertElementOpConversion, + VectorInsertOpConversion, VectorOuterProductOpConversion, + VectorTypeCastOpConversion, VectorPrintOpConversion>( + ctx, converter); } namespace { @@ -1139,11 +1167,12 @@ struct LowerVectorToLLVMPass : public ModulePass { } // namespace void LowerVectorToLLVMPass::runOnModule() { - // Perform progressive lowering of operations on "slices". - // Folding and DCE get rid of all non-leaking tuple ops. + // Perform progressive lowering of operations on "slices" and + // all contraction operations. Also applies folding and DCE. { OwningRewritePatternList patterns; populateVectorSlicesLoweringPatterns(patterns, &getContext()); + populateVectorContractLoweringPatterns(patterns, &getContext()); applyPatternsGreedily(getModule(), patterns); } diff --git a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp index 8bdeb92afe5e3..fe62666a28388 100644 --- a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp @@ -538,6 +538,7 @@ static bool isIdentitySuffix(AffineMap map) { } namespace { + // Splits vector TransferReadOp into smaller TransferReadOps based on slicing // scheme of its unique ExtractSlicesOp user. struct SplitTransferReadOp : public OpRewritePattern { @@ -862,6 +863,72 @@ class InsertSlicesOpLowering : public OpRewritePattern { } }; +/// Progressive lowering of ConstractionOp. +class ContractionOpLowering : public OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + PatternMatchResult matchAndRewrite(vector::ContractionOp op, + PatternRewriter &rewriter) const override { + // TODO(ajcbik): implement masks + if (llvm::size(op.masks()) != 0) + return matchFailure(); + + auto loc = op.getLoc(); + VectorType lhsType = op.getLhsType(); + VectorType rhsType = op.getRhsType(); + Type resType = op.getResultType(); + + // Find first batch dimension in lhs/rhs, and lower when found. + std::vector> batchDimMap = op.getBatchDimMap(); + if (!batchDimMap.empty()) { + // TODO(ajcbik): implement batch + return matchFailure(); + } + + // Collect contracting dimensions. + std::vector> contractingDimMap = + op.getContractingDimMap(); + DenseSet lhsContractingDimSet; + DenseSet rhsContractingDimSet; + for (auto &dimPair : contractingDimMap) { + lhsContractingDimSet.insert(dimPair.first); + rhsContractingDimSet.insert(dimPair.second); + } + + // Find free dimension in lhs/rhs, and lower first when found. + for (int64_t i = 0, e = lhsType.getRank(); i < e; ++i) { + if (lhsContractingDimSet.count(i) == 0) { + // TODO(ajcbik): implement free + return matchFailure(); + } + } + for (int64_t i = 0, e = rhsType.getRank(); i < e; ++i) { + if (rhsContractingDimSet.count(i) == 0) { + // TODO(ajcbik): implement free + return matchFailure(); + } + } + + // Only contraction dimensions remain. + if (!resType.isa() && lhsType.getRank() == 1 && + rhsType.getRank() == 1) { + // Handle reduction into scalar. + Value zero = rewriter.create(loc, resType, + rewriter.getZeroAttr(resType)); + Value splat = rewriter.create(loc, lhsType, zero); + Value fma = + rewriter.create(loc, op.lhs(), op.rhs(), splat); + StringAttr kind = rewriter.getStringAttr("add"); + rewriter.replaceOpWithNewOp(op, resType, kind, fma, + op.acc()); + return matchSuccess(); + } + // TODO(ajcbik): implement more contraction + return matchFailure(); + } +}; + } // namespace // TODO(andydavis) Add pattern to rewrite ExtractSlices(ConstantMaskOp). @@ -876,3 +943,8 @@ void mlir::vector::populateVectorSlicesLoweringPatterns( OwningRewritePatternList &patterns, MLIRContext *context) { patterns.insert(context); } + +void mlir::vector::populateVectorContractLoweringPatterns( + OwningRewritePatternList &patterns, MLIRContext *context) { + patterns.insert(context); +} diff --git a/mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir b/mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir new file mode 100644 index 0000000000000..6c4cb5f4bfd08 --- /dev/null +++ b/mlir/test/Dialect/VectorOps/vector-contract-transforms.mlir @@ -0,0 +1,26 @@ +// RUN: mlir-opt %s -test-vector-contraction-conversion | FileCheck %s + +#dotp_accesses = [ + affine_map<(i) -> (i)>, + affine_map<(i) -> (i)>, + affine_map<(i) -> ()> +] +#dotp_trait = { + indexing_maps = #dotp_accesses, + iterator_types = ["reduction"] +} + +// CHECK-LABEL: func @extract_contract1 +// CHECK-SAME: %[[A:.*0]]: vector<4xf32>, +// CHECK-SAME: %[[B:.*1]]: vector<4xf32>, +// CHECK-SAME: %[[C:.*2]]: f32 +// CHECK: %[[Z:.*]] = constant dense<0.000000e+00> +// CHECK: %[[F:.*]] = vector.fma %[[A]], %[[B]], %[[Z]] : vector<4xf32> +// CHECK: %[[R:.*]] = vector.reductionv2 "add", %[[F]], %[[C]] +// CHECK: return %[[R]] : f32 + +func @extract_contract1(%arg0: vector<4xf32>, %arg1: vector<4xf32>, %arg2: f32) -> f32 { + %0 = vector.contract #dotp_trait %arg0, %arg1, %arg2 + : vector<4xf32>, vector<4xf32> into f32 + return %0 : f32 +} diff --git a/mlir/test/lib/Transforms/TestVectorTransforms.cpp b/mlir/test/lib/Transforms/TestVectorTransforms.cpp index d0ac7189a4d93..3f35f815d40fe 100644 --- a/mlir/test/lib/Transforms/TestVectorTransforms.cpp +++ b/mlir/test/lib/Transforms/TestVectorTransforms.cpp @@ -42,16 +42,29 @@ struct TestVectorSlicesConversion } }; +struct TestVectorContractionConversion + : public FunctionPass { + void runOnFunction() override { + OwningRewritePatternList patterns; + populateVectorContractLoweringPatterns(patterns, &getContext()); + applyPatternsGreedily(getFunction(), patterns); + } +}; + } // end anonymous namespace namespace mlir { void registerTestVectorConversions() { - PassRegistration pass( + PassRegistration vectorToVectorPass( "test-vector-to-vector-conversion", "Test conversion patterns between ops in the vector dialect"); - PassRegistration slices_pass( + PassRegistration slicesPass( "test-vector-slices-conversion", "Test conversion patterns that lower slices ops in the vector dialect"); + + PassRegistration contractionPass( + "test-vector-contraction-conversion", + "Test conversion patterns that lower contract ops in the vector dialect"); } } // namespace mlir From 4570f2c7cf35388d8b3ab9cc5cdcad4971e31cf2 Mon Sep 17 00:00:00 2001 From: Jim Ingham Date: Thu, 13 Feb 2020 15:48:38 -0800 Subject: [PATCH 24/57] Add a test for debugserver handling threads suspended from within a program. Mach allows you to suspend and resume other threads within a program, so debugserver has to be careful not to interfere with this when it goes to supend and resume threads while stepping over breakpoints and calling functions. Even trickier, if you call a function on a suspended thread, it has to resume the thread to get the expression to run, and then suspend it properly when done. This all works already, but there wasn't a test for it. Adding that here. This same test could be written for a unix that supports pthread_{suspend,resume}_np, but macOS doesn't support these calls, only the mach version. It doesn't look like a lot of Linux'es support this (AIX does apparently...) And IIUC Windows allows you to suspend and resume other threads, but the code for that would look pretty different than this main.c. So for simplicity's sake I wrote this test for Darwin-only. --- lldb/test/API/macosx/thread_suspend/Makefile | 4 + .../TestInternalThreadSuspension.py | 108 ++++++++++++++++++ lldb/test/API/macosx/thread_suspend/main.c | 58 ++++++++++ 3 files changed, 170 insertions(+) create mode 100644 lldb/test/API/macosx/thread_suspend/Makefile create mode 100644 lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py create mode 100644 lldb/test/API/macosx/thread_suspend/main.c diff --git a/lldb/test/API/macosx/thread_suspend/Makefile b/lldb/test/API/macosx/thread_suspend/Makefile new file mode 100644 index 0000000000000..695335e068c0c --- /dev/null +++ b/lldb/test/API/macosx/thread_suspend/Makefile @@ -0,0 +1,4 @@ +C_SOURCES := main.c +CFLAGS_EXTRAS := -std=c99 + +include Makefile.rules diff --git a/lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py b/lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py new file mode 100644 index 0000000000000..301b80058d3d8 --- /dev/null +++ b/lldb/test/API/macosx/thread_suspend/TestInternalThreadSuspension.py @@ -0,0 +1,108 @@ +""" +Make sure that if threads are suspended outside of lldb, debugserver +won't make them run, even if we call an expression on the thread. +""" + +import lldb +from lldbsuite.test.decorators import * +import lldbsuite.test.lldbutil as lldbutil +from lldbsuite.test.lldbtest import * + +class TestSuspendedThreadHandling(TestBase): + + mydir = TestBase.compute_mydir(__file__) + + NO_DEBUG_INFO_TESTCASE = True + + @skipUnlessDarwin + def test_suspended_threads(self): + """Test that debugserver doesn't disturb the suspend count of a thread + that has been suspended from within a program, when navigating breakpoints + on other threads, or calling functions both on the suspended thread and + on other threads.""" + self.build() + self.main_source_file = lldb.SBFileSpec("main.c") + self.suspended_thread_test() + + def setUp(self): + # Call super's setUp(). + TestBase.setUp(self) + # Set up your test case here. If your test doesn't need any set up then + # remove this method from your TestCase class. + + def try_an_expression(self, thread, correct_value, test_bp): + frame = thread.frames[0] + + value = frame.EvaluateExpression('function_to_call()') + self.assertTrue(value.GetError().Success(), "Successfully called the function") + self.assertEqual(value.GetValueAsSigned(), correct_value, "Got expected value for expression") + + # Again, make sure we didn't let the suspend thread breakpoint run: + self.assertEqual(test_bp.GetHitCount(), 0, "First expression allowed the suspend thread to run") + + + def make_bkpt(self, pattern): + bp = self.target.BreakpointCreateBySourceRegex(pattern, self.main_source_file) + self.assertEqual(bp.GetNumLocations(), 1, "Locations for %s"%(pattern)) + return bp + + def suspended_thread_test(self): + (self.target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(self, + "Stop here to get things going", self.main_source_file) + + # Make in the running thread, so the we will have to stop a number of times + # while handling breakpoints. The first couple of times we hit it we will + # run expressions as well. Make sure we don't let the suspended thread run + # during those operations. + rt_bp = self.make_bkpt("Break here to show we can handle breakpoints") + + # Make a breakpoint that we will hit when the running thread exits: + rt_exit_bp = self.make_bkpt("Break here after thread_join") + + # Make a breakpoint in the suspended thread. We should not hit this till we + # resume it after joining the running thread. + st_bp = self.make_bkpt("We allowed the suspend thread to run") + + # Make a breakpoint after pthread_join of the suspend thread to ensure + # that we didn't keep the thread from exiting normally + st_exit_bp = self.make_bkpt(" Break here to make sure the thread exited normally") + + threads = lldbutil.continue_to_breakpoint(process, rt_bp) + self.assertEqual(len(threads), 1, "Hit the running_func breakpoint") + + # Make sure we didn't hit the suspend thread breakpoint: + self.assertEqual(st_bp.GetHitCount(), 0, "Continue allowed the suspend thread to run") + + # Now try an expression on the running thread: + self.try_an_expression(threads[0], 0, st_bp) + + # Continue, and check the same things: + threads = lldbutil.continue_to_breakpoint(process, rt_bp) + self.assertEqual(len(threads), 1, "We didn't hit running breakpoint") + + # Try an expression on the suspended thread: + thread = lldb.SBThread() + for thread in process.threads: + th_name = thread.GetName() + if th_name == None: + continue + if "Look for me" in th_name: + break + self.assertTrue(thread.IsValid(), "We found the suspend thread.") + self.try_an_expression(thread, 1, st_bp) + + # Now set the running thread breakpoint to auto-continue and let it + # run a bit to make sure we still don't let the suspend thread run. + rt_bp.SetAutoContinue(True) + threads = lldbutil.continue_to_breakpoint(process, rt_exit_bp) + self.assertEqual(len(threads), 1) + self.assertEqual(st_bp.GetHitCount(), 0, "Continue again let suspended thread run") + + # Now continue and we SHOULD hit the suspend_func breakpoint: + threads = lldbutil.continue_to_breakpoint(process, st_bp) + self.assertEqual(len(threads), 1, "The thread resumed successfully") + + # Finally, continue again and we should get out of the last pthread_join + # and the process should be about to exit + threads = lldbutil.continue_to_breakpoint(process, st_exit_bp) + self.assertEqual(len(threads), 1, "pthread_join exited successfully") diff --git a/lldb/test/API/macosx/thread_suspend/main.c b/lldb/test/API/macosx/thread_suspend/main.c new file mode 100644 index 0000000000000..03da7a71505c7 --- /dev/null +++ b/lldb/test/API/macosx/thread_suspend/main.c @@ -0,0 +1,58 @@ +#include +#include +#include + +pthread_mutex_t suspend_mutex = PTHREAD_MUTEX_INITIALIZER; +pthread_mutex_t signal_mutex = PTHREAD_MUTEX_INITIALIZER; +pthread_cond_t signal_cond = PTHREAD_COND_INITIALIZER; + +int g_running_count = 0; + +int +function_to_call() { + return g_running_count; +} + +void * +suspend_func (void *unused) { + pthread_setname_np("Look for me"); + pthread_cond_signal(&signal_cond); + pthread_mutex_lock(&suspend_mutex); + + return NULL; // We allowed the suspend thread to run +} + +void * +running_func (void *input) { + while (g_running_count < 10) { + usleep (100); + g_running_count++; // Break here to show we can handle breakpoints + } + return NULL; +} + +int +main() +{ + pthread_t suspend_thread; // Stop here to get things going + + pthread_mutex_lock(&suspend_mutex); + pthread_mutex_lock(&signal_mutex); + pthread_create(&suspend_thread, NULL, suspend_func, NULL); + + pthread_cond_wait(&signal_cond, &signal_mutex); + + mach_port_t th_port = pthread_mach_thread_np(suspend_thread); + thread_suspend(th_port); + + pthread_mutex_unlock(&suspend_mutex); + + pthread_t running_thread; + pthread_create(&running_thread, NULL, running_func, NULL); + + pthread_join(running_thread, NULL); + thread_resume(th_port); // Break here after thread_join + + pthread_join(suspend_thread, NULL); + return 0; // Break here to make sure the thread exited normally +} From b23ec439738a0480eaf57a22ee52f136babaaa66 Mon Sep 17 00:00:00 2001 From: Pavel Iliin Date: Wed, 12 Feb 2020 18:31:18 +0000 Subject: [PATCH 25/57] [AArch64][NFC] Update test checks. This NFC commit updates several llc tests checks by automatically generated ones. --- .../CodeGen/AArch64/arm64-neon-select_cc.ll | 247 +++--- .../CodeGen/AArch64/fp16-vector-shuffle.ll | 155 +++- .../AArch64/neon-bitwise-instructions.ll | 713 +++++++++++++----- 3 files changed, 804 insertions(+), 311 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll index fe765f4ef984e..464726b0d2f30 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-select_cc.ll @@ -1,13 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast \ -; RUN: < %s -verify-machineinstrs -asm-verbose=false | FileCheck %s +; RUN: < %s -verify-machineinstrs | FileCheck %s define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) { ; CHECK-LABEL: test_select_cc_v8i8_i8: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b -; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0] -; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.8b, v3.8b, v2.8b +; CHECK-NEXT: dup v2.8b, v2.b[0] +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i8 %a, %b %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d ret <8x i8> %e @@ -15,9 +19,13 @@ define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) { define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8> %d ) { ; CHECK-LABEL: test_select_cc_v8i8_f32: -; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s -; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0] -; CHECK-NEXT: bsl [[DUPMASK]].8b, v2.8b, v3.8b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0 +; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1 +; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s +; CHECK-NEXT: dup v0.2s, v0.s[0] +; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b +; CHECK-NEXT: ret %cmp31 = fcmp oeq float %a, %b %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d ret <8x i8> %e @@ -25,8 +33,10 @@ define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8> define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8> %d ) { ; CHECK-LABEL: test_select_cc_v8i8_f64: -; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1 -; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fcmeq d0, d0, d1 +; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b +; CHECK-NEXT: ret %cmp31 = fcmp oeq double %a, %b %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d ret <8x i8> %e @@ -34,11 +44,14 @@ define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8 define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d ) { ; CHECK-LABEL: test_select_cc_v16i8_i8: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b -; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0] -; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.16b, v3.16b, v2.16b +; CHECK-NEXT: dup v2.16b, v2.b[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i8 %a, %b %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d ret <16x i8> %e @@ -46,9 +59,13 @@ define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x i8> %d ) { ; CHECK-LABEL: test_select_cc_v16i8_f32: -; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s -; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0] -; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 +; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s +; CHECK-NEXT: dup v0.4s, v0.s[0] +; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b +; CHECK-NEXT: ret %cmp31 = fcmp oeq float %a, %b %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d ret <16x i8> %e @@ -56,9 +73,13 @@ define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16x i8> %d ) { ; CHECK-LABEL: test_select_cc_v16i8_f64: -; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d -; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0] -; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d +; CHECK-NEXT: dup v0.2d, v0.d[0] +; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b +; CHECK-NEXT: ret %cmp31 = fcmp oeq double %a, %b %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d ret <16x i8> %e @@ -66,11 +87,14 @@ define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16 define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d ) { ; CHECK-LABEL: test_select_cc_v4i16: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].4h, v[[LHS]].4h, v[[RHS]].4h -; CHECK: dup [[DUPMASK:v[0-9]+]].4h, [[MASK]].h[0] -; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.4h, v3.4h, v2.4h +; CHECK-NEXT: dup v2.4h, v2.h[0] +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i16 %a, %b %e = select i1 %cmp31, <4x i16> %c, <4x i16> %d ret <4x i16> %e @@ -78,11 +102,14 @@ define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d ) define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d ) { ; CHECK-LABEL: test_select_cc_v8i16: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].8h, v[[LHS]].8h, v[[RHS]].8h -; CHECK: dup [[DUPMASK:v[0-9]+]].8h, [[MASK]].h[0] -; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.8h, v3.8h, v2.8h +; CHECK-NEXT: dup v2.8h, v2.h[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i16 %a, %b %e = select i1 %cmp31, <8x i16> %c, <8x i16> %d ret <8x i16> %e @@ -90,11 +117,14 @@ define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d ) define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) { ; CHECK-LABEL: test_select_cc_v2i32: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].2s, v[[LHS]].2s, v[[RHS]].2s -; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0] -; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.2s, v3.2s, v2.2s +; CHECK-NEXT: dup v2.2s, v2.s[0] +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i32 %a, %b %e = select i1 %cmp31, <2x i32> %c, <2x i32> %d ret <2x i32> %e @@ -102,11 +132,14 @@ define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) { ; CHECK-LABEL: test_select_cc_v4i32: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s -; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0] -; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.4s, v3.4s, v2.4s +; CHECK-NEXT: dup v2.4s, v2.s[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i32 %a, %b %e = select i1 %cmp31, <4x i32> %c, <4x i32> %d ret <4x i32> %e @@ -114,10 +147,13 @@ define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) { ; CHECK-LABEL: test_select_cc_v1i64: -; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0 -; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1 -; CHECK: cmeq d[[MASK:[0-9]+]], d[[LHS]], d[[RHS]] -; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d2, x1 +; CHECK-NEXT: fmov d3, x0 +; CHECK-NEXT: cmeq d2, d3, d2 +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i64 %a, %b %e = select i1 %cmp31, <1x i64> %c, <1x i64> %d ret <1x i64> %e @@ -125,11 +161,14 @@ define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) { ; CHECK-LABEL: test_select_cc_v2i64: -; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0 -; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1 -; CHECK: cmeq [[MASK:v[0-9]+]].2d, v[[LHS]].2d, v[[RHS]].2d -; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0] -; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d2, x1 +; CHECK-NEXT: fmov d3, x0 +; CHECK-NEXT: cmeq v2.2d, v3.2d, v2.2d +; CHECK-NEXT: dup v2.2d, v2.d[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i64 %a, %b %e = select i1 %cmp31, <2x i64> %c, <2x i64> %d ret <2x i64> %e @@ -137,8 +176,12 @@ define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1 x float> %d ) { ; CHECK-LABEL: test_select_cc_v1f32: -; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s -; CHECK-NEXT: bsl [[MASK]].8b, v2.8b, v3.8b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0 +; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1 +; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s +; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b +; CHECK-NEXT: ret %cmp31 = fcmp oeq float %a, %b %e = select i1 %cmp31, <1 x float> %c, <1 x float> %d ret <1 x float> %e @@ -146,9 +189,13 @@ define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1 define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d ) { ; CHECK-LABEL: test_select_cc_v2f32: -; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s -; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0] -; CHECK: bsl [[DUPMASK]].8b, v2.8b, v3.8b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $d0 +; CHECK-NEXT: // kill: def $s1 killed $s1 def $d1 +; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s +; CHECK-NEXT: dup v0.2s, v0.s[0] +; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b +; CHECK-NEXT: ret %cmp31 = fcmp oeq float %a, %b %e = select i1 %cmp31, <2 x float> %c, <2 x float> %d ret <2 x float> %e @@ -156,9 +203,13 @@ define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2 define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x float> %d ) { ; CHECK-LABEL: test_select_cc_v4f32: -; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s -; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0] -; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0 +; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1 +; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s +; CHECK-NEXT: dup v0.4s, v0.s[0] +; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b +; CHECK-NEXT: ret %cmp31 = fcmp oeq float %a, %b %e = select i1 %cmp31, <4x float> %c, <4x float> %d ret <4x float> %e @@ -166,11 +217,14 @@ define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x f define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) { ; CHECK-LABEL: test_select_cc_v4f32_icmp: -; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0 -; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1 -; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s -; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0] -; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s2, w1 +; CHECK-NEXT: fmov s3, w0 +; CHECK-NEXT: cmeq v2.4s, v3.4s, v2.4s +; CHECK-NEXT: dup v2.4s, v2.s[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i32 %a, %b %e = select i1 %cmp31, <4x float> %c, <4x float> %d ret <4x float> %e @@ -178,8 +232,10 @@ define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c, <1 x double> %d ) { ; CHECK-LABEL: test_select_cc_v1f64: -; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1 -; CHECK: bsl v[[MASK]].8b, v2.8b, v3.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fcmeq d0, d0, d1 +; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b +; CHECK-NEXT: ret %cmp31 = fcmp oeq double %a, %b %e = select i1 %cmp31, <1 x double> %c, <1 x double> %d ret <1 x double> %e @@ -187,10 +243,13 @@ define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c, define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) { ; CHECK-LABEL: test_select_cc_v1f64_icmp: -; CHECK-DAG: fmov [[LHS:d[0-9]+]], x0 -; CHECK-DAG: fmov [[RHS:d[0-9]+]], x1 -; CHECK: cmeq d[[MASK:[0-9]+]], [[LHS]], [[RHS]] -; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d2, x1 +; CHECK-NEXT: fmov d3, x0 +; CHECK-NEXT: cmeq d2, d3, d2 +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp31 = icmp eq i64 %a, %b %e = select i1 %cmp31, <1 x double> %c, <1 x double> %d ret <1 x double> %e @@ -198,9 +257,13 @@ define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d ) { ; CHECK-LABEL: test_select_cc_v2f64: -; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d -; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0] -; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d +; CHECK-NEXT: dup v0.2d, v0.d[0] +; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b +; CHECK-NEXT: ret %cmp31 = fcmp oeq double %a, %b %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d ret <2 x double> %e @@ -211,11 +274,13 @@ define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, ; Part of PR21549. define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: test_select_cc_v2i32_icmpi1: -; CHECK: tst w0, #0x1 -; CHECK: csetm [[MASK:w[0-9]+]], ne -; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]] -; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b -; CHECK: mov v0.16b, [[DUPMASK]].16b +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: dup v2.2s, w8 +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cmp = icmp ne i1 %cc, 0 %e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b ret <2 x i32> %e @@ -224,11 +289,14 @@ define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b ; Also make sure we support irregular/non-power-of-2 types such as v3f32. define <3 x float> @test_select_cc_v3f32_fcmp_f32(<3 x float> %a, <3 x float> %b, float %c1, float %c2) #0 { ; CHECK-LABEL: test_select_cc_v3f32_fcmp_f32: -; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].4s, v2.4s, v3.4s -; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0] -; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b -; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s2 killed $s2 def $q2 +; CHECK-NEXT: // kill: def $s3 killed $s3 def $q3 +; CHECK-NEXT: fcmeq v2.4s, v2.4s, v3.4s +; CHECK-NEXT: dup v2.4s, v2.s[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cc = fcmp oeq float %c1, %c2 %r = select i1 %cc, <3 x float> %a, <3 x float> %b ret <3 x float> %r @@ -236,11 +304,14 @@ define <3 x float> @test_select_cc_v3f32_fcmp_f32(<3 x float> %a, <3 x float> %b define <3 x float> @test_select_cc_v3f32_fcmp_f64(<3 x float> %a, <3 x float> %b, double %c1, double %c2) #0 { ; CHECK-LABEL: test_select_cc_v3f32_fcmp_f64: -; CHECK-NEXT: fcmeq [[MASK:v[0-9]+]].2d, v2.2d, v3.2d -; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0] -; CHECK-NEXT: bsl [[DUPMASK:v[0-9]+]].16b, v0.16b, v1.16b -; CHECK-NEXT: mov v0.16b, [[DUPMASK]].16b -; CHECK-NEXT: ret +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d2 killed $d2 def $q2 +; CHECK-NEXT: // kill: def $d3 killed $d3 def $q3 +; CHECK-NEXT: fcmeq v2.2d, v2.2d, v3.2d +; CHECK-NEXT: dup v2.2d, v2.d[0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %cc = fcmp oeq double %c1, %c2 %r = select i1 %cc, <3 x float> %a, <3 x float> %b ret <3 x float> %r diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll index 1f67ff4e938a2..59afe47042ffb 100644 --- a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll +++ b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll @@ -1,9 +1,13 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s ; float16x4_t select_64(float16x4_t a, float16x4_t b, uint16x4_t c) { return vbsl_u16(c, a, b); } define <4 x half> @select_64(<4 x half> %a, <4 x half> %b, <4 x i16> %c) #0 { ; CHECK-LABEL: select_64: -; CHECK: bsl +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret entry: %0 = bitcast <4 x half> %a to <4 x i16> %1 = bitcast <4 x half> %b to <4 x i16> @@ -18,7 +22,10 @@ entry: ; float16x8_t select_128(float16x8_t a, float16x8_t b, uint16x8_t c) { return vbslq_u16(c, a, b); } define <8 x half> @select_128(<8 x half> %a, <8 x half> %b, <8 x i16> %c) #0 { ; CHECK-LABEL: select_128: -; CHECK: bsl +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret entry: %0 = bitcast <8 x half> %a to <8 x i16> %1 = bitcast <8 x half> %b to <8 x i16> @@ -35,7 +42,12 @@ entry: ; } define <4 x half> @lane_64_64(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-LABEL: lane_64_64: -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v0.h[1], v1.h[2] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> ret <4 x half> %0 @@ -46,7 +58,10 @@ entry: ; } define <8 x half> @lane_128_64(<8 x half> %a, <4 x half> %b) #0 { ; CHECK-LABEL: lane_128_64: -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v0.h[1], v1.h[2] +; CHECK-NEXT: ret entry: %0 = bitcast <4 x half> %b to <4 x i16> %vget_lane = extractelement <4 x i16> %0, i32 2 @@ -61,7 +76,11 @@ entry: ; } define <4 x half> @lane_64_128(<4 x half> %a, <8 x half> %b) #0 { ; CHECK-LABEL: lane_64_128: -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.h[3], v1.h[5] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = bitcast <8 x half> %b to <8 x i16> %vgetq_lane = extractelement <8 x i16> %0, i32 5 @@ -76,7 +95,9 @@ entry: ; } define <8 x half> @lane_128_128(<8 x half> %a, <8 x half> %b) #0 { ; CHECK-LABEL: lane_128_128: -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: mov v0.h[3], v1.h[5] +; CHECK-NEXT: ret entry: %0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> ret <8 x half> %0 @@ -87,7 +108,9 @@ entry: ; } define <4 x half> @ext_64(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-LABEL: ext_64: -; CHECK: ext +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6 +; CHECK-NEXT: ret entry: %0 = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> ret <4 x half> %0 @@ -98,7 +121,9 @@ entry: ; } define <8 x half> @ext_128(<8 x half> %a, <8 x half> %b) #0 { ; CHECK-LABEL: ext_128: -; CHECK: ext +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #6 +; CHECK-NEXT: ret entry: %0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> ret <8 x half> %0 @@ -108,9 +133,11 @@ entry: ; return vrev32_s16(a); ; } define <4 x half> @rev32_64(<4 x half> %a) #0 { -entry: ; CHECK-LABEL: rev32_64: -; CHECK: rev32 +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev32 v0.4h, v0.4h +; CHECK-NEXT: ret +entry: %0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> ret <4 x half> %0 } @@ -119,9 +146,11 @@ entry: ; return vrev64_s16(a); ; } define <4 x half> @rev64_64(<4 x half> %a) #0 { -entry: ; CHECK-LABEL: rev64_64: -; CHECK: rev64 +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.4h, v0.4h +; CHECK-NEXT: ret +entry: %0 = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> ret <4 x half> %0 } @@ -130,9 +159,11 @@ entry: ; return vrev32q_s16(a); ; } define <8 x half> @rev32_128(<8 x half> %a) #0 { -entry: ; CHECK-LABEL: rev32_128: -; CHECK: rev32 +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev32 v0.8h, v0.8h +; CHECK-NEXT: ret +entry: %0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> ret <8 x half> %0 } @@ -141,9 +172,11 @@ entry: ; return vrev64q_s16(a); ; } define <8 x half> @rev64_128(<8 x half> %a) #0 { -entry: ; CHECK-LABEL: rev64_128: -; CHECK: rev64 +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: rev64 v0.8h, v0.8h +; CHECK-NEXT: ret +entry: %0 = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> ret <8 x half> %0 } @@ -151,7 +184,9 @@ entry: ; float16x4_t create_64(long long a) { return vcreate_f16(a); } define <4 x half> @create_64(i64 %a) #0 { ; CHECK-LABEL: create_64: -; CHECK: fmov +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: fmov d0, x0 +; CHECK-NEXT: ret entry: %0 = bitcast i64 %a to <4 x half> ret <4 x half> %0 @@ -160,7 +195,10 @@ entry: ; float16x4_t dup_64(__fp16 a) { return vdup_n_f16(a); } define <4 x half> @dup_64(half %a) #0 { ; CHECK-LABEL: dup_64: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0 +; CHECK-NEXT: dup v0.4h, v0.h[0] +; CHECK-NEXT: ret entry: %vecinit = insertelement <4 x half> undef, half %a, i32 0 %vecinit1 = insertelement <4 x half> %vecinit, half %a, i32 1 @@ -171,9 +209,12 @@ entry: ; float16x8_t dup_128(__fp16 a) { return vdupq_n_f16(a); } define <8 x half> @dup_128(half %a) #0 { -entry: ; CHECK-LABEL: dup_128: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0 +; CHECK-NEXT: dup v0.8h, v0.h[0] +; CHECK-NEXT: ret +entry: %vecinit = insertelement <8 x half> undef, half %a, i32 0 %vecinit1 = insertelement <8 x half> %vecinit, half %a, i32 1 %vecinit2 = insertelement <8 x half> %vecinit1, half %a, i32 2 @@ -187,45 +228,59 @@ entry: ; float16x4_t dup_lane_64(float16x4_t a) { return vdup_lane_f16(a, 2); } define <4 x half> @dup_lane_64(<4 x half> %a) #0 { -entry: ; CHECK-LABEL: dup_lane_64: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: dup v0.4h, v0.h[2] +; CHECK-NEXT: ret +entry: %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> ret <4 x half> %shuffle } ; float16x8_t dup_lane_128(float16x4_t a) { return vdupq_lane_f16(a, 2); } define <8 x half> @dup_lane_128(<4 x half> %a) #0 { -entry: ; CHECK-LABEL: dup_lane_128: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: dup v0.8h, v0.h[2] +; CHECK-NEXT: ret +entry: %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <8 x i32> ret <8 x half> %shuffle } ; float16x4_t dup_laneq_64(float16x8_t a) { return vdup_laneq_f16(a, 2); } define <4 x half> @dup_laneq_64(<8 x half> %a) #0 { -entry: ; CHECK-LABEL: dup_laneq_64: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: dup v0.4h, v0.h[2] +; CHECK-NEXT: ret +entry: %shuffle = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> ret <4 x half> %shuffle } ; float16x8_t dup_laneq_128(float16x8_t a) { return vdupq_laneq_f16(a, 2); } define <8 x half> @dup_laneq_128(<8 x half> %a) #0 { -entry: ; CHECK-LABEL: dup_laneq_128: -; CHECK: dup +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: dup v0.8h, v0.h[2] +; CHECK-NEXT: ret +entry: %shuffle = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> ret <8 x half> %shuffle } ; float16x8_t vcombine(float16x4_t a, float16x4_t b) { return vcombine_f16(a, b); } define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 { -entry: ; CHECK-LABEL: vcombine: -; CHECK: mov v0.d[1], v1.d[0] +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret +entry: %shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> ret <8 x half> %shuffle.i } @@ -233,7 +288,10 @@ entry: ; float16x4_t get_high(float16x8_t a) { return vget_high_f16(a); } define <4 x half> @get_high(<8 x half> %a) #0 { ; CHECK-LABEL: get_high: -; CHECK: ext +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> ret <4 x half> %shuffle.i @@ -243,7 +301,9 @@ entry: ; float16x4_t get_low(float16x8_t a) { return vget_low_f16(a); } define <4 x half> @get_low(<8 x half> %a) #0 { ; CHECK-LABEL: get_low: -; CHECK-NOT: ext +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <4 x i32> ret <4 x half> %shuffle.i @@ -252,8 +312,13 @@ entry: ; float16x4_t set_lane_64(float16x4_t a, __fp16 b) { return vset_lane_f16(b, a, 2); } define <4 x half> @set_lane_64(<4 x half> %a, half %b) #0 { ; CHECK-LABEL: set_lane_64: -; CHECK: fmov -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov v0.h[2], w8 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = bitcast half %b to i16 %1 = bitcast <4 x half> %a to <4 x i16> @@ -266,8 +331,11 @@ entry: ; float16x8_t set_lane_128(float16x8_t a, __fp16 b) { return vsetq_lane_f16(b, a, 2); } define <8 x half> @set_lane_128(<8 x half> %a, half %b) #0 { ; CHECK-LABEL: set_lane_128: -; CHECK: fmov -; CHECK: mov v{{[0-9]+}}.h +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $h1 killed $h1 def $s1 +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov v0.h[2], w8 +; CHECK-NEXT: ret entry: %0 = bitcast half %b to i16 %1 = bitcast <8 x half> %a to <8 x i16> @@ -279,8 +347,12 @@ entry: ; __fp16 get_lane_64(float16x4_t a) { return vget_lane_f16(a, 2); } define half @get_lane_64(<4 x half> %a) #0 { ; CHECK-LABEL: get_lane_64: -; CHECK: umov -; CHECK: fmov +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: umov w8, v0.h[2] +; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0 +; CHECK-NEXT: ret entry: %0 = bitcast <4 x half> %a to <4 x i16> %vget_lane = extractelement <4 x i16> %0, i32 2 @@ -291,8 +363,11 @@ entry: ; __fp16 get_lane_128(float16x8_t a) { return vgetq_lane_f16(a, 2); } define half @get_lane_128(<8 x half> %a) #0 { ; CHECK-LABEL: get_lane_128: -; CHECK: umov -; CHECK: fmov +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: umov w8, v0.h[2] +; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0 +; CHECK-NEXT: ret entry: %0 = bitcast <8 x half> %a to <8 x i16> %vgetq_lane = extractelement <8 x i16> %0, i32 2 diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll index 8af8fd2be94bd..4fe52e7cae249 100644 --- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll +++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll @@ -1,15 +1,20 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: and8xi8: -; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, %b; ret <8 x i8> %tmp1 } define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: and16xi8: -; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, %b; ret <16 x i8> %tmp1 } @@ -17,14 +22,18 @@ define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) { define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: orr8xi8: -; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, %b; ret <8 x i8> %tmp1 } define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: orr16xi8: -; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, %b; ret <16 x i8> %tmp1 } @@ -32,22 +41,29 @@ define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) { define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: xor8xi8: -; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <8 x i8> %a, %b; ret <8 x i8> %tmp1 } define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: xor16xi8: -; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <16 x i8> %a, %b; ret <16 x i8> %tmp1 } define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: bsl8xi8_const: -; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: movi d2, #0x00ffff0000ffff +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 > %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 > %tmp3 = or <8 x i8> %tmp1, %tmp2 @@ -56,8 +72,11 @@ define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) { define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: bsl16xi8_const: -; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.2d, #0x000000ffffffff +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 > %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp3 = or <16 x i8> %tmp1, %tmp2 @@ -66,7 +85,9 @@ define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) { define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: orn8xi8: -; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp2 = or <8 x i8> %a, %tmp1 ret <8 x i8> %tmp2 @@ -74,7 +95,9 @@ define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) { define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: orn16xi8: -; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp2 = or <16 x i8> %a, %tmp1 ret <16 x i8> %tmp2 @@ -82,7 +105,9 @@ define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) { define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) { ; CHECK-LABEL: bic8xi8: -; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp2 = and <8 x i8> %a, %tmp1 ret <8 x i8> %tmp2 @@ -90,7 +115,9 @@ define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) { define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) { ; CHECK-LABEL: bic16xi8: -; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > %tmp2 = and <16 x i8> %a, %tmp1 ret <16 x i8> %tmp2 @@ -98,175 +125,225 @@ define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) { define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) { ; CHECK-LABEL: orrimm2s_lsl0: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 255, i32 255> ret <2 x i32> %tmp1 } define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) { ; CHECK-LABEL: orrimm2s_lsl8: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280> ret <2 x i32> %tmp1 } define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) { ; CHECK-LABEL: orrimm2s_lsl16: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680> ret <2 x i32> %tmp1 } define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) { ; CHECK-LABEL: orrimm2s_lsl24: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080> ret <2 x i32> %tmp1 } define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) { ; CHECK-LABEL: orrimm4s_lsl0: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255> ret <4 x i32> %tmp1 } define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) { ; CHECK-LABEL: orrimm4s_lsl8: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280> ret <4 x i32> %tmp1 } define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) { ; CHECK-LABEL: orrimm4s_lsl16: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680> ret <4 x i32> %tmp1 } define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) { ; CHECK-LABEL: orrimm4s_lsl24: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080> ret <4 x i32> %tmp1 } define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) { ; CHECK-LABEL: orrimm4h_lsl0: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 > ret <4 x i16> %tmp1 } define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) { ; CHECK-LABEL: orrimm4h_lsl8: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > ret <4 x i16> %tmp1 } define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) { ; CHECK-LABEL: orrimm8h_lsl0: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 > ret <8 x i16> %tmp1 } define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) { ; CHECK-LABEL: orrimm8h_lsl8: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > ret <8 x i16> %tmp1 } define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) { ; CHECK-LABEL: bicimm2s_lsl0: -; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #16 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 > ret <2 x i32> %tmp1 } define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) { ; CHECK-LABEL: bicimm2s_lsl8: -; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #16, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 > ret <2 x i32> %tmp1 } define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) { ; CHECK-LABEL: bicimm2s_lsl16: -; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #16, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 > ret <2 x i32> %tmp1 } define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) { ; CHECK-LABEL: bicimm2s_lsl124: -; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #16, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839> ret <2 x i32> %tmp1 } define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) { ; CHECK-LABEL: bicimm4s_lsl0: -; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #16 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 > ret <4 x i32> %tmp1 } define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) { ; CHECK-LABEL: bicimm4s_lsl8: -; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #16, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 > ret <4 x i32> %tmp1 } define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) { ; CHECK-LABEL: bicimm4s_lsl16: -; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #16, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 > ret <4 x i32> %tmp1 } define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) { ; CHECK-LABEL: bicimm4s_lsl124: -; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #16, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839> ret <4 x i32> %tmp1 } define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) { ; CHECK-LABEL: bicimm4h_lsl0_a: -; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #16 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > ret <4 x i16> %tmp1 } define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) { ; CHECK-LABEL: bicimm4h_lsl0_b: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > ret <4 x i16> %tmp1 } define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) { ; CHECK-LABEL: bicimm4h_lsl8_a: -; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #16, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> ret <4 x i16> %tmp1 } define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) { ; CHECK-LABEL: bicimm4h_lsl8_b: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255> ret <4 x i16> %tmp1 } define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) { ; CHECK-LABEL: bicimm8h_lsl0_a: -; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #16 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > ret <8 x i16> %tmp1 @@ -274,14 +351,18 @@ define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) { define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) { ; CHECK-LABEL: bicimm8h_lsl0_b: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > ret <8 x i16> %tmp1 } define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) { ; CHECK-LABEL: bicimm8h_lsl8_a: -; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #16, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> ret <8 x i16> %tmp1 @@ -289,133 +370,171 @@ define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) { define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) { ; CHECK-LABEL: bicimm8h_lsl8_b: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> ret <8 x i16> %tmp1 } define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: and2xi32: -; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, %b; ret <2 x i32> %tmp1 } define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: and4xi16: -; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, %b; ret <4 x i16> %tmp1 } define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: and1xi64: -; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, %b; ret <1 x i64> %tmp1 } define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: and4xi32: -; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, %b; ret <4 x i32> %tmp1 } define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: and8xi16: -; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, %b; ret <8 x i16> %tmp1 } define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: and2xi64: -; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, %b; ret <2 x i64> %tmp1 } define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: orr2xi32: -; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, %b; ret <2 x i32> %tmp1 } define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: orr4xi16: -; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, %b; ret <4 x i16> %tmp1 } define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: orr1xi64: -; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, %b; ret <1 x i64> %tmp1 } define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: orr4xi32: -; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, %b; ret <4 x i32> %tmp1 } define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: orr8xi16: -; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, %b; ret <8 x i16> %tmp1 } define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: orr2xi64: -; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, %b; ret <2 x i64> %tmp1 } define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: eor2xi32: -; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <2 x i32> %a, %b; ret <2 x i32> %tmp1 } define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: eor4xi16: -; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <4 x i16> %a, %b; ret <4 x i16> %tmp1 } define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: eor1xi64: -; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <1 x i64> %a, %b; ret <1 x i64> %tmp1 } define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: eor4xi32: -; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <4 x i32> %a, %b; ret <4 x i32> %tmp1 } define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: eor8xi16: -; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <8 x i16> %a, %b; ret <8 x i16> %tmp1 } define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: eor2xi64: -; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <2 x i64> %a, %b; ret <2 x i64> %tmp1 } @@ -423,7 +542,9 @@ define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) { define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: bic2xi32: -; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > %tmp2 = and <2 x i32> %a, %tmp1 ret <2 x i32> %tmp2 @@ -431,7 +552,9 @@ define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) { define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: bic4xi16: -; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > %tmp2 = and <4 x i16> %a, %tmp1 ret <4 x i16> %tmp2 @@ -439,7 +562,9 @@ define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) { define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: bic1xi64: -; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <1 x i64> %b, < i64 -1> %tmp2 = and <1 x i64> %a, %tmp1 ret <1 x i64> %tmp2 @@ -447,7 +572,9 @@ define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) { define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: bic4xi32: -; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> %tmp2 = and <4 x i32> %a, %tmp1 ret <4 x i32> %tmp2 @@ -455,7 +582,9 @@ define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) { define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: bic8xi16: -; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > %tmp2 = and <8 x i16> %a, %tmp1 ret <8 x i16> %tmp2 @@ -463,7 +592,9 @@ define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) { define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: bic2xi64: -; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> %tmp2 = and <2 x i64> %a, %tmp1 ret <2 x i64> %tmp2 @@ -471,7 +602,9 @@ define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) { define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: orn2xi32: -; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > %tmp2 = or <2 x i32> %a, %tmp1 ret <2 x i32> %tmp2 @@ -479,7 +612,9 @@ define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) { define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: orn4xi16: -; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > %tmp2 = or <4 x i16> %a, %tmp1 ret <4 x i16> %tmp2 @@ -487,7 +622,9 @@ define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) { define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: orn1xi64: -; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.8b, v0.8b, v1.8b +; CHECK-NEXT: ret %tmp1 = xor <1 x i64> %b, < i64 -1> %tmp2 = or <1 x i64> %a, %tmp1 ret <1 x i64> %tmp2 @@ -495,7 +632,9 @@ define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) { define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: orn4xi32: -; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> %tmp2 = or <4 x i32> %a, %tmp1 ret <4 x i32> %tmp2 @@ -503,7 +642,9 @@ define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) { define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: orn8xi16: -; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > %tmp2 = or <8 x i16> %a, %tmp1 ret <8 x i16> %tmp2 @@ -511,7 +652,9 @@ define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) { define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: orn2xi64: -; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> %tmp2 = or <2 x i64> %a, %tmp1 ret <2 x i64> %tmp2 @@ -519,8 +662,11 @@ define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) { define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: bsl2xi32_const: -; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffffffff -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: movi d2, #0x000000ffffffff +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 > %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 > %tmp3 = or <2 x i32> %tmp1, %tmp2 @@ -530,8 +676,11 @@ define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) { define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) { ; CHECK-LABEL: bsl4xi16_const: -; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: movi d2, #0x00ffff0000ffff +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 > %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 > %tmp3 = or <4 x i16> %tmp1, %tmp2 @@ -540,8 +689,11 @@ define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) { define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) { ; CHECK-LABEL: bsl1xi64_const: -; CHECK: movi {{d[0-9]+}}, #0xffffffffffffff00 -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: movi d2, #0xffffffffffffff00 +; CHECK-NEXT: bsl v2.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 -256 > %tmp2 = and <1 x i64> %b, < i64 255 > %tmp3 = or <1 x i64> %tmp1, %tmp2 @@ -550,8 +702,11 @@ define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) { define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: bsl4xi32_const: -; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.2d, #0x000000ffffffff +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 > %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 > %tmp3 = or <4 x i32> %tmp1, %tmp2 @@ -560,8 +715,11 @@ define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) { define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) { ; CHECK-LABEL: bsl8xi16_const: -; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: movi v2.2d, #0x000000ffffffff +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 > %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 > %tmp3 = or <8 x i16> %tmp1, %tmp2 @@ -570,7 +728,12 @@ define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) { define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) { ; CHECK-LABEL: bsl2xi64_const: -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI75_0 +; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI75_0] +; CHECK-NEXT: bsl v2.16b, v0.16b, v1.16b +; CHECK-NEXT: mov v0.16b, v2.16b +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 > %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 > %tmp3 = or <2 x i64> %tmp1, %tmp2 @@ -580,7 +743,9 @@ define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) { define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) { ; CHECK-LABEL: bsl8xi8: -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %1 = and <8 x i8> %v1, %v2 %2 = xor <8 x i8> %v1, %3 = and <8 x i8> %2, %v3 @@ -590,7 +755,9 @@ define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) { define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) { ; CHECK-LABEL: bsl4xi16: -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %1 = and <4 x i16> %v1, %v2 %2 = xor <4 x i16> %v1, %3 = and <4 x i16> %2, %v3 @@ -600,7 +767,9 @@ define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) { define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) { ; CHECK-LABEL: bsl2xi32: -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %1 = and <2 x i32> %v1, %v2 %2 = xor <2 x i32> %v1, %3 = and <2 x i32> %2, %v3 @@ -610,7 +779,9 @@ define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) { define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { ; CHECK-LABEL: bsl1xi64: -; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %1 = and <1 x i64> %v1, %v2 %2 = xor <1 x i64> %v1, %3 = and <1 x i64> %2, %v3 @@ -620,7 +791,9 @@ define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) { ; CHECK-LABEL: bsl16xi8: -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b +; CHECK-NEXT: ret %1 = and <16 x i8> %v1, %v2 %2 = xor <16 x i8> %v1, %3 = and <16 x i8> %2, %v3 @@ -630,7 +803,9 @@ define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) { define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) { ; CHECK-LABEL: bsl8xi16: -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b +; CHECK-NEXT: ret %1 = and <8 x i16> %v1, %v2 %2 = xor <8 x i16> %v1, %3 = and <8 x i16> %2, %v3 @@ -640,7 +815,9 @@ define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) { define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { ; CHECK-LABEL: bsl4xi32: -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b +; CHECK-NEXT: ret %1 = and <4 x i32> %v1, %v2 %2 = xor <4 x i32> %v1, %3 = and <4 x i32> %2, %v3 @@ -650,25 +827,33 @@ define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { define <8 x i8> @vselect_v8i8(<8 x i8> %a) { ; CHECK-LABEL: vselect_v8i8: -; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff -; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}} +; CHECK: // %bb.0: +; CHECK-NEXT: movi d1, #0x0000000000ffff +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: orr v0.2s, #0 +; CHECK-NEXT: ret %b = select <8 x i1> , <8 x i8> %a, <8 x i8> ret <8 x i8> %b } define <4 x i16> @vselect_v4i16(<4 x i16> %a) { ; CHECK-LABEL: vselect_v4i16: -; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff -; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}} +; CHECK: // %bb.0: +; CHECK-NEXT: movi d1, #0x0000000000ffff +; CHECK-NEXT: and v0.8b, v0.8b, v1.8b +; CHECK-NEXT: orr v0.2s, #0 +; CHECK-NEXT: ret %b = select <4 x i1> , <4 x i16> %a, <4 x i16> ret <4 x i16> %b } define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK-LABEL: vselect_cmp_ne: -; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %cmp = icmp ne <8 x i8> %a, %b %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c ret <8 x i8> %d @@ -676,8 +861,10 @@ define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK-LABEL: vselect_cmp_eq: -; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %cmp = icmp eq <8 x i8> %a, %b %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c ret <8 x i8> %d @@ -685,9 +872,11 @@ define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK-LABEL: vselect_cmpz_ne: -; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0 -; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 +; CHECK-NEXT: mvn v0.8b, v0.8b +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %cmp = icmp ne <8 x i8> %a, zeroinitializer %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c ret <8 x i8> %d @@ -695,8 +884,10 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK-LABEL: vselect_cmpz_eq: -; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0 -; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: cmeq v0.8b, v0.8b, #0 +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %cmp = icmp eq <8 x i8> %a, zeroinitializer %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c ret <8 x i8> %d @@ -704,8 +895,10 @@ define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { ; CHECK-LABEL: vselect_tst: -; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +; CHECK: // %bb.0: +; CHECK-NEXT: cmtst v0.8b, v0.8b, v1.8b +; CHECK-NEXT: bsl v0.8b, v1.8b, v2.8b +; CHECK-NEXT: ret %tmp3 = and <8 x i8> %a, %b %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c @@ -714,7 +907,9 @@ define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) { ; CHECK-LABEL: bsl2xi64: -; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK: // %bb.0: +; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b +; CHECK-NEXT: ret %1 = and <2 x i64> %v1, %v2 %2 = xor <2 x i64> %v1, %3 = and <2 x i64> %2, %v3 @@ -724,84 +919,108 @@ define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) { define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) { ; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255 +; CHECK-NEXT: ret %val = or <8 x i8> %a, ret <8 x i8> %val } define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) { ; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %val = or <8 x i8> %a, ret <8 x i8> %val } define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) { ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255 +; CHECK-NEXT: ret %val = or <16 x i8> %a, ret <16 x i8> %val } define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) { ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %val = or <16 x i8> %a, ret <16 x i8> %val } define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) { ; CHECK-LABEL: and8imm2s_lsl0: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> ret <8 x i8> %tmp1 } define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) { ; CHECK-LABEL: and8imm2s_lsl8: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> ret <8 x i8> %tmp1 } define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) { ; CHECK-LABEL: and8imm2s_lsl16: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> ret <8 x i8> %tmp1 } define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) { ; CHECK-LABEL: and8imm2s_lsl24: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> ret <8 x i8> %tmp1 } define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) { ; CHECK-LABEL: and16imm2s_lsl0: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535> ret <4 x i16> %tmp1 } define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) { ; CHECK-LABEL: and16imm2s_lsl8: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535> ret <4 x i16> %tmp1 } define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) { ; CHECK-LABEL: and16imm2s_lsl16: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280> ret <4 x i16> %tmp1 } define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) { ; CHECK-LABEL: and16imm2s_lsl24: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511> ret <4 x i16> %tmp1 } @@ -809,448 +1028,576 @@ define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) { define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) { ; CHECK-LABEL: and64imm2s_lsl0: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 -1095216660736> ret <1 x i64> %tmp1 } define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) { ; CHECK-LABEL: and64imm2s_lsl8: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 -280375465148161> ret <1 x i64> %tmp1 } define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) { ; CHECK-LABEL: and64imm2s_lsl16: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 -71776119077928961> ret <1 x i64> %tmp1 } define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) { ; CHECK-LABEL: and64imm2s_lsl24: -; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.2s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 144115183814443007> ret <1 x i64> %tmp1 } define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) { ; CHECK-LABEL: and8imm4s_lsl0: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> ret <16 x i8> %tmp1 } define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) { ; CHECK-LABEL: and8imm4s_lsl8: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> ret <16 x i8> %tmp1 } define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) { ; CHECK-LABEL: and8imm4s_lsl16: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> ret <16 x i8> %tmp1 } define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) { ; CHECK-LABEL: and8imm4s_lsl24: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> ret <16 x i8> %tmp1 } define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) { ; CHECK-LABEL: and16imm4s_lsl0: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535> ret <8 x i16> %tmp1 } define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) { ; CHECK-LABEL: and16imm4s_lsl8: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535> ret <8 x i16> %tmp1 } define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) { ; CHECK-LABEL: and16imm4s_lsl16: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280> ret <8 x i16> %tmp1 } define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) { ; CHECK-LABEL: and16imm4s_lsl24: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511> ret <8 x i16> %tmp1 } define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) { ; CHECK-LABEL: and64imm4s_lsl0: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736> ret <2 x i64> %tmp1 } define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) { ; CHECK-LABEL: and64imm4s_lsl8: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161> ret <2 x i64> %tmp1 } define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) { ; CHECK-LABEL: and64imm4s_lsl16: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961> ret <2 x i64> %tmp1 } define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) { ; CHECK-LABEL: and64imm4s_lsl24: -; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4s, #254, lsl #24 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007> ret <2 x i64> %tmp1 } define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) { ; CHECK-LABEL: and8imm4h_lsl0: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> ret <8 x i8> %tmp1 } define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) { ; CHECK-LABEL: and8imm4h_lsl8: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> ret <8 x i8> %tmp1 } define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) { ; CHECK-LABEL: and16imm4h_lsl0: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360> ret <2 x i32> %tmp1 } define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) { ; CHECK-LABEL: and16imm4h_lsl8: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935> ret <2 x i32> %tmp1 } define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) { ; CHECK-LABEL: and64imm4h_lsl0: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 -71777214294589696> ret <1 x i64> %tmp1 } define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) { ; CHECK-LABEL: and64imm4h_lsl8: -; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <1 x i64> %a, < i64 71777214294589695> ret <1 x i64> %tmp1 } define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) { ; CHECK-LABEL: and8imm8h_lsl0: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 > ret <16 x i8> %tmp1 } define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) { ; CHECK-LABEL: and8imm8h_lsl8: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <16 x i8> %a, ret <16 x i8> %tmp1 } define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) { ; CHECK-LABEL: and16imm8h_lsl0: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> ret <4 x i32> %tmp1 } define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) { ; CHECK-LABEL: and16imm8h_lsl8: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> ret <4 x i32> %tmp1 } define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) { ; CHECK-LABEL: and64imm8h_lsl0: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> ret <2 x i64> %tmp1 } define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) { ; CHECK-LABEL: and64imm8h_lsl8: -; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: bic v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> ret <2 x i64> %tmp1 } define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) { ; CHECK-LABEL: orr8imm2s_lsl0: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> ret <8 x i8> %tmp1 } define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) { ; CHECK-LABEL: orr8imm2s_lsl8: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> ret <8 x i8> %tmp1 } define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) { ; CHECK-LABEL: orr8imm2s_lsl16: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> ret <8 x i8> %tmp1 } define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) { ; CHECK-LABEL: orr8imm2s_lsl24: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> ret <8 x i8> %tmp1 } define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) { ; CHECK-LABEL: orr16imm2s_lsl0: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0> ret <4 x i16> %tmp1 } define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) { ; CHECK-LABEL: orr16imm2s_lsl8: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0> ret <4 x i16> %tmp1 } define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) { ; CHECK-LABEL: orr16imm2s_lsl16: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255> ret <4 x i16> %tmp1 } define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) { ; CHECK-LABEL: orr16imm2s_lsl24: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280> ret <4 x i16> %tmp1 } define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) { ; CHECK-LABEL: orr64imm2s_lsl0: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 1095216660735> ret <1 x i64> %tmp1 } define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) { ; CHECK-LABEL: orr64imm2s_lsl8: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 280375465148160> ret <1 x i64> %tmp1 } define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) { ; CHECK-LABEL: orr64imm2s_lsl16: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 71776119077928960> ret <1 x i64> %tmp1 } define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) { ; CHECK-LABEL: orr64imm2s_lsl24: -; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.2s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 -72057589759737856> ret <1 x i64> %tmp1 } define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) { ; CHECK-LABEL: orr8imm4s_lsl0: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> ret <16 x i8> %tmp1 } define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) { ; CHECK-LABEL: orr8imm4s_lsl8: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> ret <16 x i8> %tmp1 } define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) { ; CHECK-LABEL: orr8imm4s_lsl16: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> ret <16 x i8> %tmp1 } define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) { ; CHECK-LABEL: orr8imm4s_lsl24: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> ret <16 x i8> %tmp1 } define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) { ; CHECK-LABEL: orr16imm4s_lsl0: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0> ret <8 x i16> %tmp1 } define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) { ; CHECK-LABEL: orr16imm4s_lsl8: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0> ret <8 x i16> %tmp1 } define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) { ; CHECK-LABEL: orr16imm4s_lsl16: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255> ret <8 x i16> %tmp1 } define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) { ; CHECK-LABEL: orr16imm4s_lsl24: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280> ret <8 x i16> %tmp1 } define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) { ; CHECK-LABEL: orr64imm4s_lsl0: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735> ret <2 x i64> %tmp1 } define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) { ; CHECK-LABEL: orr64imm4s_lsl8: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160> ret <2 x i64> %tmp1 } define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) { ; CHECK-LABEL: orr64imm4s_lsl16: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #16 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960> ret <2 x i64> %tmp1 } define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) { ; CHECK-LABEL: orr64imm4s_lsl24: -; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4s, #255, lsl #24 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856> ret <2 x i64> %tmp1 } define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) { ; CHECK-LABEL: orr8imm4h_lsl0: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> ret <8 x i8> %tmp1 } define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) { ; CHECK-LABEL: orr8imm4h_lsl8: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> ret <8 x i8> %tmp1 } define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) { ; CHECK-LABEL: orr16imm4h_lsl0: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935> ret <2 x i32> %tmp1 } define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) { ; CHECK-LABEL: orr16imm4h_lsl8: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360> ret <2 x i32> %tmp1 } define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) { ; CHECK-LABEL: orr64imm4h_lsl0: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 71777214294589695> ret <1 x i64> %tmp1 } define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) { ; CHECK-LABEL: orr64imm4h_lsl8: -; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.4h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <1 x i64> %a, < i64 -71777214294589696> ret <1 x i64> %tmp1 } define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) { ; CHECK-LABEL: orr8imm8h_lsl0: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> ret <16 x i8> %tmp1 } define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) { ; CHECK-LABEL: orr8imm8h_lsl8: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> ret <16 x i8> %tmp1 } define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) { ; CHECK-LABEL: orr16imm8h_lsl0: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> ret <4 x i32> %tmp1 } define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) { ; CHECK-LABEL: orr16imm8h_lsl8: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> ret <4 x i32> %tmp1 } define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) { ; CHECK-LABEL: orr64imm8h_lsl0: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> ret <2 x i64> %tmp1 } define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) { ; CHECK-LABEL: orr64imm8h_lsl8: -; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 +; CHECK: // %bb.0: +; CHECK-NEXT: orr v0.8h, #255, lsl #8 +; CHECK-NEXT: ret %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> ret <2 x i64> %tmp1 } From 0a1123eb43f945593b26dd037490e0c909fa3c4f Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 16:17:21 -0800 Subject: [PATCH 26/57] Reland D74436 "Change clang option -ffp-model=precise to select ffp-contract=on" Buildbot are failing with the current revert status. So reland with a fix to fp-model.c --- clang/docs/UsersManual.rst | 48 +++++++++++++++++++-- clang/lib/Driver/ToolChains/Clang.cpp | 21 +++++----- clang/test/CodeGen/ppc-emmintrin.c | 4 +- clang/test/CodeGen/ppc-xmmintrin.c | 4 +- clang/test/Driver/fp-model.c | 60 +++++++++++++-------------- 5 files changed, 88 insertions(+), 49 deletions(-) diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 856d5e34bbcc2..6c8c9f8020823 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -1190,8 +1190,50 @@ installed. Controlling Floating Point Behavior ----------------------------------- -Clang provides a number of ways to control floating point behavior. The options -are listed below. +Clang provides a number of ways to control floating point behavior, including +with command line options and source pragmas. This section +describes the various floating point semantic modes and the corresponding options. + +.. csv-table:: Floating Point Semantic Modes + :header: "Mode", "Values" + :widths: 15, 30, 30 + + "except_behavior", "{ignore, strict, may_trap}", "ffp-exception-behavior" + "fenv_access", "{off, on}", "(none)" + "rounding_mode", "{dynamic, tonearest, downward, upward, towardzero}", "frounding-math" + "contract", "{on, off, fast}", "ffp-contract" + "denormal_fp_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math" + "denormal_fp32_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math-fp32" + "support_math_errno", "{on, off}", "fmath-errno" + "no_honor_nans", "{on, off}", "fhonor-nans" + "no_honor_infinities", "{on, off}", "fhonor-infinities" + "no_signed_zeros", "{on, off}", "fsigned-zeros" + "allow_reciprocal", "{on, off}", "freciprocal-math" + "allow_approximate_fns", "{on, off}", "(none)" + "allow_reassociation", "{on, off}", "fassociative-math" + + +This table describes the option settings that correspond to the three +floating point semantic models: precise (the default), strict, and fast. + + +.. csv-table:: Floating Point Models + :header: "Mode", "Precise", "Strict", "Fast" + :widths: 25, 15, 15, 15 + + "except_behavior", "ignore", "strict", "ignore" + "fenv_access", "off", "on", "off" + "rounding_mode", "tonearest", "dynamic", "tonearest" + "contract", "on", "off", "fast" + "denormal_fp_math", "IEEE", "IEEE", "PreserveSign" + "denormal_fp32_math", "IEEE","IEEE", "PreserveSign" + "support_math_errno", "on", "on", "off" + "no_honor_nans", "off", "off", "on" + "no_honor_infinities", "off", "off", "on" + "no_signed_zeros", "off", "off", "on" + "allow_reciprocal", "off", "off", "on" + "allow_approximate_fns", "off", "off", "on" + "allow_reassociation", "off", "off", "on" .. option:: -ffast-math @@ -1385,7 +1427,7 @@ Note that floating-point operations performed as part of constant initialization and ``fast``. Details: - * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=fast``). This is the default behavior. + * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=on``). This is the default behavior. * ``strict`` Enables ``-frounding-math`` and ``-ffp-exception-behavior=strict``, and disables contractions (FMA). All of the ``-ffast-math`` enablements are disabled. * ``fast`` Behaves identically to specifying both ``-ffast-math`` and ``ffp-contract=fast`` diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 5a207f3ca9f71..d1197556aeefd 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2525,10 +2525,9 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath; llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math; - StringRef FPContract = ""; + StringRef FPContract = "on"; bool StrictFPModel = false; - if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) { CmdArgs.push_back("-mlimit-float-precision"); CmdArgs.push_back(A->getValue()); @@ -2551,7 +2550,6 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, SignedZeros = true; // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; - FPContract = ""; StringRef Val = A->getValue(); if (OFastEnabled && !Val.equals("fast")) { // Only -ffp-model=fast is compatible with OFast, ignore. @@ -2565,12 +2563,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // ffp-model= is a Driver option, it is entirely rewritten into more // granular options before being passed into cc1. // Use the gcc option in the switch below. - if (!FPModel.empty() && !FPModel.equals(Val)) { + if (!FPModel.empty() && !FPModel.equals(Val)) D.Diag(clang::diag::warn_drv_overriding_flag_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); - FPContract = ""; - } if (Val.equals("fast")) { optID = options::OPT_ffast_math; FPModel = Val; @@ -2578,13 +2574,14 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, } else if (Val.equals("precise")) { optID = options::OPT_ffp_contract; FPModel = Val; - FPContract = "fast"; + FPContract = "on"; PreciseFPModel = true; } else if (Val.equals("strict")) { StrictFPModel = true; optID = options::OPT_frounding_math; FPExceptionBehavior = "strict"; FPModel = Val; + FPContract = "off"; TrappingMath = true; } else D.Diag(diag::err_drv_unsupported_option_argument) @@ -2663,9 +2660,11 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_contract: { StringRef Val = A->getValue(); if (PreciseFPModel) { - // -ffp-model=precise enables ffp-contract=fast as a side effect - // the FPContract value has already been set to a string literal - // and the Val string isn't a pertinent value. + // When -ffp-model=precise is seen on the command line, + // the boolean PreciseFPModel is set to true which indicates + // "the current option is actually PreciseFPModel". The optID + // is changed to OPT_ffp_contract and FPContract is set to "on". + // the argument Val string is "precise": it shouldn't be checked. ; } else if (Val.equals("fast") || Val.equals("on") || Val.equals("off")) FPContract = Val; @@ -2762,7 +2761,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; DenormalFP32Math = DefaultDenormalFP32Math; - FPContract = ""; + FPContract = "on"; break; } if (StrictFPModel) { diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c index 631b6c9d2614a..c14b2dd210f89 100644 --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE // CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> , align 16 // CHECK-BE-DAG: @_mm_shuffle_epi32.permute_selectors = internal constant [4 x i32] [i32 66051, i32 67438087, i32 134810123, i32 202182159], align 4 diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c index e9466b32257f0..d7499cbedc48d 100644 --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE #include diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c index a3984acef62b2..de83e4e4c9130 100644 --- a/clang/test/Driver/fp-model.c +++ b/clang/test/Driver/fp-model.c @@ -1,89 +1,87 @@ // Test that incompatible combinations of -ffp-model= options // and other floating point options get a warning diagnostic. -// -// REQUIRES: clang-driver -// RUN: %clang -### -ffp-model=fast -ffp-contract=off -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=fast -ffp-contract=off -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN %s // WARN: warning: overriding '-ffp-model=fast' option with '-ffp-contract=off' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=fast -ffp-contract=on -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=fast -ffp-contract=on -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN1 %s // WARN1: warning: overriding '-ffp-model=fast' option with '-ffp-contract=on' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fassociative-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fassociative-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN2 %s // WARN2: warning: overriding '-ffp-model=strict' option with '-fassociative-math' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffast-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -ffast-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN3 %s // WARN3: warning: overriding '-ffp-model=strict' option with '-ffast-math' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffinite-math-only -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -ffinite-math-only -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN4 %s // WARN4: warning: overriding '-ffp-model=strict' option with '-ffinite-math-only' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN5 %s // WARN5: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=off -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN6 %s -// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=off' [-Woverriding-t-option] +// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=on -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -ffp-contract=on -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN7 %s // WARN7: warning: overriding '-ffp-model=strict' option with '-ffp-contract=on' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fno-honor-infinities -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fno-honor-infinities -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN8 %s // WARN8: warning: overriding '-ffp-model=strict' option with '-fno-honor-infinities' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fno-honor-nans -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fno-honor-nans -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN9 %s // WARN9: warning: overriding '-ffp-model=strict' option with '-fno-honor-nans' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fno-rounding-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fno-rounding-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNa %s // WARNa: warning: overriding '-ffp-model=strict' option with '-fno-rounding-math' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fno-signed-zeros -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fno-signed-zeros -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNb %s // WARNb: warning: overriding '-ffp-model=strict' option with '-fno-signed-zeros' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -fno-trapping-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -fno-trapping-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNc %s // WARNc: warning: overriding '-ffp-model=strict' option with '-fno-trapping-math' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -freciprocal-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -freciprocal-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNd %s // WARNd: warning: overriding '-ffp-model=strict' option with '-freciprocal-math' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -funsafe-math-optimizations -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -funsafe-math-optimizations -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNe %s // WARNe: warning: overriding '-ffp-model=strict' option with '-funsafe-math-optimizations' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -Ofast -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ffp-model=strict -Ofast -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARNf %s // WARNf: warning: overriding '-ffp-model=strict' option with '-Ofast' [-Woverriding-t-option] -// RUN: %clang -### -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-NOROUND %s // CHECK-NOROUND: "-cc1" // CHECK-NOROUND: "-fno-rounding-math" -// RUN: %clang -### -frounding-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -frounding-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-ROUND --implicit-check-not ffp-exception-behavior=strict %s // CHECK-ROUND: "-cc1" // CHECK-ROUND: "-frounding-math" -// RUN: %clang -### -ftrapping-math -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -ftrapping-math -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-TRAP %s // CHECK-TRAP: "-cc1" // CHECK-TRAP: "-ftrapping-math" // CHECK-TRAP: "-ffp-exception-behavior=strict" -// RUN: %clang -### -nostdinc -ffp-model=fast -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-model=fast -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-FAST %s // CHECK-FPM-FAST: "-cc1" // CHECK-FPM-FAST: "-menable-no-infs" @@ -97,41 +95,41 @@ // CHECK-FPM-FAST: "-ffast-math" // CHECK-FPM-FAST: "-ffinite-math-only" -// RUN: %clang -### -nostdinc -ffp-model=precise -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-model=precise -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-PRECISE %s // CHECK-FPM-PRECISE: "-cc1" -// CHECK-FPM-PRECISE: "-ffp-contract=fast" +// CHECK-FPM-PRECISE: "-ffp-contract=on" // CHECK-FPM-PRECISE: "-fno-rounding-math" -// RUN: %clang -### -nostdinc -ffp-model=strict -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-model=strict -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-STRICT %s // CHECK-FPM-STRICT: "-cc1" // CHECK-FPM-STRICT: "-ftrapping-math" +// CHECK-FPM-STRICT: "-ffp-contract=off" // CHECK-FPM-STRICT: "-frounding-math" // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict" -// RUN: %clang -### -nostdinc -ftrapping-math -ffp-exception-behavior=ignore -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ftrapping-math -ffp-exception-behavior=ignore -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-TRAP-IGNORE %s // CHECK-TRAP-IGNORE: "-cc1" // CHECK-TRAP-IGNORE: "-fno-rounding-math" // CHECK-TRAP-IGNORE: "-ffp-exception-behavior=ignore" -// RUN: %clang -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-exception-behavior=strict -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FEB-STRICT %s // CHECK-FEB-STRICT: "-cc1" // CHECK-FEB-STRICT: "-fno-rounding-math" // CHECK-FEB-STRICT: "-ffp-exception-behavior=strict" -// RUN: %clang -### -nostdinc -ffp-exception-behavior=maytrap -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-exception-behavior=maytrap -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FEB-MAYTRAP %s // CHECK-FEB-MAYTRAP: "-cc1" // CHECK-FEB-MAYTRAP: "-fno-rounding-math" // CHECK-FEB-MAYTRAP: "-ffp-exception-behavior=maytrap" -// RUN: %clang -### -nostdinc -ffp-exception-behavior=ignore -c %s 2>&1 \ +// RUN: %clang -target x86_64 -### -nostdinc -ffp-exception-behavior=ignore -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FEB-IGNORE %s // CHECK-FEB-IGNORE: "-cc1" // CHECK-FEB-IGNORE: "-fno-rounding-math" // CHECK-FEB-IGNORE: "-ffp-exception-behavior=ignore" - From 918e90559b08adebff26c342080c65e79cc223ec Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Mon, 3 Feb 2020 21:26:43 -0800 Subject: [PATCH 27/57] [WebAssembly] Make stack pointer args inhibit tail calls Summary: Also make return calls terminator instructions so epilogues are inserted before them rather than after them. Together, these changes make WebAssembly's tail call optimization more stack-safe. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73943 --- .../WebAssembly/WebAssemblyISelLowering.cpp | 69 ++++++++++++------- .../WebAssembly/WebAssemblyInstrCall.td | 2 +- llvm/test/CodeGen/WebAssembly/tailcall.ll | 30 ++++++++ 3 files changed, 75 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index e71290608ce9f..4d45fb95af209 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -648,32 +648,51 @@ WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI, fail(DL, DAG, "WebAssembly doesn't support patch point yet"); if (CLI.IsTailCall) { - bool MustTail = CLI.CS && CLI.CS.isMustTailCall(); - if (Subtarget->hasTailCall() && !CLI.IsVarArg) { - // Do not tail call unless caller and callee return types match - const Function &F = MF.getFunction(); - const TargetMachine &TM = getTargetMachine(); - Type *RetTy = F.getReturnType(); - SmallVector CallerRetTys; - SmallVector CalleeRetTys; - computeLegalValueVTs(F, TM, RetTy, CallerRetTys); - computeLegalValueVTs(F, TM, CLI.RetTy, CalleeRetTys); - bool TypesMatch = CallerRetTys.size() == CalleeRetTys.size() && - std::equal(CallerRetTys.begin(), CallerRetTys.end(), - CalleeRetTys.begin()); - if (!TypesMatch) { - // musttail in this case would be an LLVM IR validation failure - assert(!MustTail); - CLI.IsTailCall = false; - } - } else { + auto NoTail = [&](const char *Msg) { + if (CLI.CS && CLI.CS.isMustTailCall()) + fail(DL, DAG, Msg); CLI.IsTailCall = false; - if (MustTail) { - if (CLI.IsVarArg) { - // The return would pop the argument buffer - fail(DL, DAG, "WebAssembly does not support varargs tail calls"); - } else { - fail(DL, DAG, "WebAssembly 'tail-call' feature not enabled"); + }; + + if (!Subtarget->hasTailCall()) + NoTail("WebAssembly 'tail-call' feature not enabled"); + + // Varargs calls cannot be tail calls because the buffer is on the stack + if (CLI.IsVarArg) + NoTail("WebAssembly does not support varargs tail calls"); + + // Do not tail call unless caller and callee return types match + const Function &F = MF.getFunction(); + const TargetMachine &TM = getTargetMachine(); + Type *RetTy = F.getReturnType(); + SmallVector CallerRetTys; + SmallVector CalleeRetTys; + computeLegalValueVTs(F, TM, RetTy, CallerRetTys); + computeLegalValueVTs(F, TM, CLI.RetTy, CalleeRetTys); + bool TypesMatch = CallerRetTys.size() == CalleeRetTys.size() && + std::equal(CallerRetTys.begin(), CallerRetTys.end(), + CalleeRetTys.begin()); + if (!TypesMatch) + NoTail("WebAssembly tail call requires caller and callee return types to " + "match"); + + // If pointers to local stack values are passed, we cannot tail call + if (CLI.CS) { + for (auto &Arg : CLI.CS.args()) { + Value *Val = Arg.get(); + // Trace the value back through pointer operations + while (true) { + Value *Src = Val->stripPointerCastsAndAliases(); + if (auto *GEP = dyn_cast(Src)) + Src = GEP->getPointerOperand(); + if (Val == Src) + break; + Val = Src; + } + if (isa(Val)) { + NoTail( + "WebAssembly does not support tail calling with stack arguments"); + break; } } } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td index 703c15d58c93a..20b74c6d72d22 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td @@ -74,7 +74,7 @@ defm CALL_VOID : [(WebAssemblycall0 (i32 imm:$callee))], "call \t$callee", "call\t$callee", 0x10>; -let isReturn = 1 in +let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in defm RET_CALL : I<(outs), (ins function32_op:$callee, variable_ops), (outs), (ins function32_op:$callee), diff --git a/llvm/test/CodeGen/WebAssembly/tailcall.ll b/llvm/test/CodeGen/WebAssembly/tailcall.ll index f4d4499bcef7e..96bd9a67569e9 100644 --- a/llvm/test/CodeGen/WebAssembly/tailcall.ll +++ b/llvm/test/CodeGen/WebAssembly/tailcall.ll @@ -209,7 +209,37 @@ define i1 @mismatched_return_trunc() { ret i1 %u } +; Stack-allocated arguments inhibit tail calls +; CHECK-LABEL: stack_arg: +; CHECK: i32.call +define i32 @stack_arg(i32* %x) { + %a = alloca i32 + %v = tail call i32 @stack_arg(i32* %a) + ret i32 %v +} + +; CHECK-LABEL: stack_arg_gep: +; CHECK: i32.call +define i32 @stack_arg_gep(i32* %x) { + %a = alloca { i32, i32 } + %p = getelementptr { i32, i32 }, { i32, i32 }* %a, i32 0, i32 1 + %v = tail call i32 @stack_arg_gep(i32* %p) + ret i32 %v +} + +; CHECK-LABEL: stack_arg_cast: +; CHECK: global.get $push{{[0-9]+}}=, __stack_pointer +; CHECK: global.set __stack_pointer, $pop{{[0-9]+}} +; FAST: i32.call ${{[0-9]+}}=, stack_arg_cast, $pop{{[0-9]+}} +; CHECK: global.set __stack_pointer, $pop{{[0-9]+}} +; SLOW: return_call stack_arg_cast, ${{[0-9]+}} +define i32 @stack_arg_cast(i32 %x) { + %a = alloca [64 x i32] + %i = ptrtoint [64 x i32]* %a to i32 + %v = tail call i32 @stack_arg_cast(i32 %i) + ret i32 %v +} ; Check that the signatures generated for external indirectly ; return-called functions include the proper return types From 1d49eb00d97a8e920ae34ff433419d0cd61641fd Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 16:36:27 -0800 Subject: [PATCH 28/57] [AsmPrinter] De-capitalize all AsmPrinter::Emit* but EmitInstruction Similar to rL328848. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 +- clang/lib/CodeGen/CGCall.cpp | 2 +- clang/lib/CodeGen/CGExprScalar.cpp | 2 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 2 +- clang/lib/CodeGen/CodeGenFunction.cpp | 10 +-- clang/lib/CodeGen/CodeGenFunction.h | 9 +- llvm/docs/GarbageCollection.rst | 2 +- llvm/include/llvm/CodeGen/AsmPrinter.h | 36 ++++---- .../llvm/ExecutionEngine/ExecutionEngine.h | 2 +- llvm/lib/CodeGen/AsmPrinter/ARMException.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 90 +++++++++---------- .../CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 4 +- .../AsmPrinter/AsmPrinterInlineAsm.cpp | 11 ++- llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp | 14 +-- .../CodeGen/AsmPrinter/ErlangGCPrinter.cpp | 2 +- .../lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/WinException.cpp | 2 +- llvm/lib/ExecutionEngine/ExecutionEngine.cpp | 6 +- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 2 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 42 ++++----- llvm/lib/Target/ARM/ARMAsmPrinter.h | 14 +-- llvm/lib/Target/Mips/Mips16HardFloat.cpp | 6 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 6 +- llvm/lib/Target/Mips/MipsAsmPrinter.h | 4 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 8 +- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 4 +- llvm/lib/Target/SystemZ/SystemZAsmPrinter.h | 2 +- .../WebAssembly/WebAssemblyAsmPrinter.cpp | 4 +- .../WebAssembly/WebAssemblyAsmPrinter.h | 4 +- llvm/lib/Target/X86/X86AsmPrinter.cpp | 4 +- llvm/lib/Target/XCore/XCoreAsmPrinter.cpp | 11 ++- 33 files changed, 164 insertions(+), 165 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 509400bfc5740..77f48b92eb014 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -2164,7 +2164,7 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, AlignmentCI = ConstantInt::get(AlignmentCI->getType(), llvm::Value::MaximumAlignment); - EmitAlignmentAssumption(PtrValue, Ptr, + emitAlignmentAssumption(PtrValue, Ptr, /*The expr loc is sufficient.*/ SourceLocation(), AlignmentCI, OffsetValue); return RValue::get(PtrValue); @@ -14555,7 +14555,7 @@ RValue CodeGenFunction::EmitBuiltinAlignTo(const CallExpr *E, bool AlignUp) { Result = Builder.CreatePointerCast(Result, Args.SrcType); // Emit an alignment assumption to ensure that the new alignment is // propagated to loads/stores, etc. - EmitAlignmentAssumption(Result, E, E->getExprLoc(), Args.Alignment); + emitAlignmentAssumption(Result, E, E->getExprLoc(), Args.Alignment); } assert(Result->getType() == Args.SrcType); return RValue::get(Result); diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index 432058bdc17a7..6cc01540febe8 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -3906,7 +3906,7 @@ template class AbstractAssumeAlignedAttrEmitter { void EmitAsAnAssumption(SourceLocation Loc, QualType RetTy, RValue &Ret) { if (!AA) return; - CGF.EmitAlignmentAssumption(Ret.getScalarVal(), RetTy, Loc, + CGF.emitAlignmentAssumption(Ret.getScalarVal(), RetTy, Loc, AA->getLocation(), Alignment, OffsetCI); AA = nullptr; // We're done. Disallow doing anything else. } diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 1f3f4e7b894d6..706aa43a5071b 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -297,7 +297,7 @@ class ScalarExprEmitter Value *AlignmentValue = CGF.EmitScalarExpr(AVAttr->getAlignment()); llvm::ConstantInt *AlignmentCI = cast(AlignmentValue); - CGF.EmitAlignmentAssumption(V, E, AVAttr->getLocation(), AlignmentCI); + CGF.emitAlignmentAssumption(V, E, AVAttr->getLocation(), AlignmentCI); } /// EmitLoadOfLValue - Given an expression with complex type that represents a diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index bba7df70fb196..ea9617cc82ac8 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -1770,7 +1770,7 @@ static void emitAlignedClause(CodeGenFunction &CGF, "alignment is not power of 2"); if (Alignment != 0) { llvm::Value *PtrValue = CGF.EmitScalarExpr(E); - CGF.EmitAlignmentAssumption( + CGF.emitAlignmentAssumption( PtrValue, E, /*No second loc needed*/ SourceLocation(), llvm::ConstantInt::get(CGF.getLLVMContext(), Alignment)); } diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 4798de044a643..bcd936638d614 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -2170,7 +2170,7 @@ void CodeGenFunction::unprotectFromPeepholes(PeepholeProtection protection) { protection.Inst->eraseFromParent(); } -void CodeGenFunction::EmitAlignmentAssumption(llvm::Value *PtrValue, +void CodeGenFunction::emitAlignmentAssumption(llvm::Value *PtrValue, QualType Ty, SourceLocation Loc, SourceLocation AssumptionLoc, llvm::Value *Alignment, @@ -2179,12 +2179,12 @@ void CodeGenFunction::EmitAlignmentAssumption(llvm::Value *PtrValue, llvm::Instruction *Assumption = Builder.CreateAlignmentAssumption( CGM.getDataLayout(), PtrValue, Alignment, OffsetValue, &TheCheck); if (SanOpts.has(SanitizerKind::Alignment)) { - EmitAlignmentAssumptionCheck(PtrValue, Ty, Loc, AssumptionLoc, Alignment, + emitAlignmentAssumptionCheck(PtrValue, Ty, Loc, AssumptionLoc, Alignment, OffsetValue, TheCheck, Assumption); } } -void CodeGenFunction::EmitAlignmentAssumption(llvm::Value *PtrValue, +void CodeGenFunction::emitAlignmentAssumption(llvm::Value *PtrValue, const Expr *E, SourceLocation AssumptionLoc, llvm::Value *Alignment, @@ -2194,7 +2194,7 @@ void CodeGenFunction::EmitAlignmentAssumption(llvm::Value *PtrValue, QualType Ty = E->getType(); SourceLocation Loc = E->getExprLoc(); - EmitAlignmentAssumption(PtrValue, Ty, Loc, AssumptionLoc, Alignment, + emitAlignmentAssumption(PtrValue, Ty, Loc, AssumptionLoc, Alignment, OffsetValue); } @@ -2462,7 +2462,7 @@ void CodeGenFunction::EmitMultiVersionResolver( // Loc), the diagnostic will additionally point a "Note:" to this location. // It should be the location where the __attribute__((assume_aligned)) // was written e.g. -void CodeGenFunction::EmitAlignmentAssumptionCheck( +void CodeGenFunction::emitAlignmentAssumptionCheck( llvm::Value *Ptr, QualType Ty, SourceLocation Loc, SourceLocation SecondaryLoc, llvm::Value *Alignment, llvm::Value *OffsetValue, llvm::Value *TheCheck, diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 7ddd38c7b262b..1e3244d807da0 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -2827,7 +2827,7 @@ class CodeGenFunction : public CodeGenTypeCache { PeepholeProtection protectFromPeepholes(RValue rvalue); void unprotectFromPeepholes(PeepholeProtection protection); - void EmitAlignmentAssumptionCheck(llvm::Value *Ptr, QualType Ty, + void emitAlignmentAssumptionCheck(llvm::Value *Ptr, QualType Ty, SourceLocation Loc, SourceLocation AssumptionLoc, llvm::Value *Alignment, @@ -2835,13 +2835,14 @@ class CodeGenFunction : public CodeGenTypeCache { llvm::Value *TheCheck, llvm::Instruction *Assumption); - void EmitAlignmentAssumption(llvm::Value *PtrValue, QualType Ty, + void emitAlignmentAssumption(llvm::Value *PtrValue, QualType Ty, SourceLocation Loc, SourceLocation AssumptionLoc, llvm::Value *Alignment, llvm::Value *OffsetValue = nullptr); - void EmitAlignmentAssumption(llvm::Value *PtrValue, const Expr *E, - SourceLocation AssumptionLoc, llvm::Value *Alignment, + void emitAlignmentAssumption(llvm::Value *PtrValue, const Expr *E, + SourceLocation AssumptionLoc, + llvm::Value *Alignment, llvm::Value *OffsetValue = nullptr); //===--------------------------------------------------------------------===// diff --git a/llvm/docs/GarbageCollection.rst b/llvm/docs/GarbageCollection.rst index 8c6b0466fdb17..ade944b6d455d 100644 --- a/llvm/docs/GarbageCollection.rst +++ b/llvm/docs/GarbageCollection.rst @@ -958,7 +958,7 @@ a realistic example: // } __gcmap_; // Align to address width. - AP.EmitAlignment(IntPtrSize == 4 ? 2 : 3); + AP.emitAlignment(IntPtrSize == 4 ? 2 : 3); // Emit PointCount. OS.AddComment("safe point count"); diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 875d32ede9b0d..068f3a36e0616 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -354,30 +354,30 @@ class AsmPrinter : public MachineFunctionPass { /// Print to the current output stream assembly representations of the /// constants in the constant pool MCP. This is used to print out constants /// which have been "spilled to memory" by the code generator. - virtual void EmitConstantPool(); + virtual void emitConstantPool(); /// Print assembly representations of the jump tables used by the current /// function to the current output stream. - virtual void EmitJumpTableInfo(); + virtual void emitJumpTableInfo(); /// Emit the specified global variable to the .s file. - virtual void EmitGlobalVariable(const GlobalVariable *GV); + virtual void emitGlobalVariable(const GlobalVariable *GV); /// Check to see if the specified global is a special global used by LLVM. If /// so, emit it and return true, otherwise do nothing and return false. - bool EmitSpecialLLVMGlobal(const GlobalVariable *GV); + bool emitSpecialLLVMGlobal(const GlobalVariable *GV); /// Emit an alignment directive to the specified power of two boundary. If a /// global value is specified, and if that global has an explicit alignment /// requested, it will override the alignment request if required for /// correctness. - void EmitAlignment(Align Alignment, const GlobalObject *GV = nullptr) const; + void emitAlignment(Align Alignment, const GlobalObject *GV = nullptr) const; /// Lower the specified LLVM Constant to an MCExpr. virtual const MCExpr *lowerConstant(const Constant *CV); /// Print a general LLVM constant to the .s file. - void EmitGlobalConstant(const DataLayout &DL, const Constant *CV); + void emitGlobalConstant(const DataLayout &DL, const Constant *CV); /// Unnamed constant global variables solely contaning a pointer to /// another globals variable act like a global variable "proxy", or GOT @@ -443,12 +443,12 @@ class AsmPrinter : public MachineFunctionPass { llvm_unreachable("Function descriptor is target-specific."); } - virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV); + virtual void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV); /// Targets can override this to change how global constants that are part of /// a C++ static/global constructor list are emitted. - virtual void EmitXXStructor(const DataLayout &DL, const Constant *CV) { - EmitGlobalConstant(DL, CV); + virtual void emitXXStructor(const DataLayout &DL, const Constant *CV) { + emitGlobalConstant(DL, CV); } /// Return true if the basic block has exactly one predecessor and the control @@ -549,13 +549,13 @@ class AsmPrinter : public MachineFunctionPass { /// Emit a .byte 42 directive that corresponds to an encoding. If verbose /// assembly output is enabled, we output comments describing the encoding. /// Desc is a string saying what the encoding is specifying (e.g. "LSDA"). - void EmitEncodingByte(unsigned Val, const char *Desc = nullptr) const; + void emitEncodingByte(unsigned Val, const char *Desc = nullptr) const; /// Return the size of the encoding in bytes. unsigned GetSizeOfEncodedValue(unsigned Encoding) const; /// Emit reference to a ttype global with a specified encoding. - void EmitTTypeReference(const GlobalValue *GV, unsigned Encoding) const; + void emitTTypeReference(const GlobalValue *GV, unsigned Encoding) const; /// Emit a reference to a symbol for use in dwarf. Different object formats /// represent this in different ways. Some use a relocation others encode @@ -683,14 +683,14 @@ class AsmPrinter : public MachineFunctionPass { /// Emit a blob of inline asm to the output streamer. void - EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, + emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, const MCTargetOptions &MCOptions, const MDNode *LocMDNode = nullptr, InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT) const; /// This method formats and emits the specified machine instruction that is an /// inline asm. - void EmitInlineAsm(const MachineInstr *MI) const; + void emitInlineAsm(const MachineInstr *MI) const; /// Add inline assembly info to the diagnostics machinery, so we can /// emit file and position info. Returns SrcMgr memory buffer position. @@ -701,14 +701,14 @@ class AsmPrinter : public MachineFunctionPass { // Internal Implementation Details //===------------------------------------------------------------------===// - void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI, + void emitJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid) const; - void EmitLLVMUsedList(const ConstantArray *InitList); + void emitLLVMUsedList(const ConstantArray *InitList); /// Emit llvm.ident metadata in an '.ident' directive. - void EmitModuleIdents(Module &M); + void emitModuleIdents(Module &M); /// Emit bytes for llvm.commandline metadata. - void EmitModuleCommandLines(Module &M); - void EmitXXStructorList(const DataLayout &DL, const Constant *List, + void emitModuleCommandLines(Module &M); + void emitXXStructorList(const DataLayout &DL, const Constant *List, bool isCtor); GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &S); diff --git a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h index 4fb6dad963879..9b41ed4391cf1 100644 --- a/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h +++ b/llvm/include/llvm/ExecutionEngine/ExecutionEngine.h @@ -499,7 +499,7 @@ class ExecutionEngine { void emitGlobals(); - void EmitGlobalVariable(const GlobalVariable *GV); + void emitGlobalVariable(const GlobalVariable *GV); GenericValue getConstantValue(const Constant *C); void LoadValueFromMemory(GenericValue &Result, GenericValue *Ptr, diff --git a/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp b/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp index f6ef85a5b78f1..c17994cfaad9a 100644 --- a/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp @@ -109,7 +109,7 @@ void ARMException::emitTypeInfos(unsigned TTypeEncoding, for (const GlobalValue *GV : reverse(TypeInfos)) { if (VerboseAsm) Asm->OutStreamer->AddComment("TypeInfo " + Twine(Entry--)); - Asm->EmitTTypeReference(GV, TTypeEncoding); + Asm->emitTTypeReference(GV, TTypeEncoding); } Asm->OutStreamer->EmitLabel(TTBaseLabel); @@ -129,7 +129,7 @@ void ARMException::emitTypeInfos(unsigned TTypeEncoding, Asm->OutStreamer->AddComment("FilterInfo " + Twine(Entry)); } - Asm->EmitTTypeReference((TypeID == 0 ? nullptr : TypeInfos[TypeID - 1]), + Asm->emitTTypeReference((TypeID == 0 ? nullptr : TypeInfos[TypeID - 1]), TTypeEncoding); } } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 0baf9bf79e0f6..321c90d4d6471 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -305,7 +305,7 @@ bool AsmPrinter::doInitialization(Module &M) { TM.getTargetFeatureString())); OutStreamer->AddComment("Start of file scope inline assembly"); OutStreamer->AddBlankLine(); - EmitInlineAsm(M.getModuleInlineAsm()+"\n", + emitInlineAsm(M.getModuleInlineAsm() + "\n", OutContext.getSubtargetCopy(*STI), TM.Options.MCOptions); OutStreamer->AddComment("End of file scope inline assembly"); OutStreamer->AddBlankLine(); @@ -466,7 +466,7 @@ MCSymbol *AsmPrinter::getSymbolPreferLocal(const GlobalValue &GV) const { } /// EmitGlobalVariable - Emit the specified global variable to the .s file. -void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { bool IsEmuTLSVar = TM.useEmulatedTLS() && GV->isThreadLocal(); assert(!(IsEmuTLSVar && GV->hasCommonLinkage()) && "No emulated TLS variables in the common section"); @@ -478,7 +478,7 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { if (GV->hasInitializer()) { // Check to see if this is a special global used by LLVM, if so, emit it. - if (EmitSpecialLLVMGlobal(GV)) + if (emitSpecialLLVMGlobal(GV)) return; // Skip the emission of global equivalents. The symbol can be emitted later @@ -607,10 +607,10 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { } else if (GVKind.isThreadData()) { OutStreamer->SwitchSection(TheSection); - EmitAlignment(Alignment, GV); + emitAlignment(Alignment, GV); OutStreamer->EmitLabel(MangSym); - EmitGlobalConstant(GV->getParent()->getDataLayout(), + emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); } @@ -643,14 +643,14 @@ void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { OutStreamer->SwitchSection(TheSection); emitLinkage(GV, EmittedInitSym); - EmitAlignment(Alignment, GV); + emitAlignment(Alignment, GV); OutStreamer->EmitLabel(EmittedInitSym); MCSymbol *LocalAlias = getSymbolPreferLocal(*GV); if (LocalAlias != EmittedInitSym) OutStreamer->EmitLabel(LocalAlias); - EmitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); + emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); if (MAI->hasDotTypeDotSizeDirective()) // .size foo, 42 @@ -679,7 +679,7 @@ void AsmPrinter::emitFunctionHeader() { << GlobalValue::dropLLVMManglingEscape(F.getName()) << '\n'; // Print out constants referenced by the function - EmitConstantPool(); + emitConstantPool(); // Print the 'header' of function. OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(&F, TM)); @@ -691,7 +691,7 @@ void AsmPrinter::emitFunctionHeader() { emitLinkage(&F, CurrentFnSym); if (MAI->hasFunctionAlignment()) - EmitAlignment(MF->getAlignment(), &F); + emitAlignment(MF->getAlignment(), &F); if (MAI->hasDotTypeDotSizeDirective()) OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction); @@ -715,12 +715,12 @@ void AsmPrinter::emitFunctionHeader() { MCSymbol *PrefixSym = OutContext.createLinkerPrivateTempSymbol(); OutStreamer->EmitLabel(PrefixSym); - EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); + emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); // Emit an .alt_entry directive for the actual function symbol. OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_AltEntry); } else { - EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); + emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData()); } } @@ -776,7 +776,7 @@ void AsmPrinter::emitFunctionHeader() { // Emit the prologue data. if (F.hasPrologueData()) - EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrologueData()); + emitGlobalConstant(F.getParent()->getDataLayout(), F.getPrologueData()); } /// EmitFunctionEntryLabel - Emit the label that is the entrypoint for the @@ -1136,7 +1136,7 @@ void AsmPrinter::emitFunctionBody() { break; case TargetOpcode::INLINEASM: case TargetOpcode::INLINEASM_BR: - EmitInlineAsm(&MI); + emitInlineAsm(&MI); break; case TargetOpcode::DBG_VALUE: if (isVerbose()) { @@ -1247,7 +1247,7 @@ void AsmPrinter::emitFunctionBody() { } // Print out jump tables referenced by the function. - EmitJumpTableInfo(); + emitJumpTableInfo(); // Emit post-function debug and/or EH information. for (const HandlerInfo &HI : Handlers) { @@ -1343,7 +1343,7 @@ void AsmPrinter::emitGlobalGOTEquivs() { GlobalGOTEquivs.clear(); for (auto *GV : FailedCandidates) - EmitGlobalVariable(GV); + emitGlobalVariable(GV); } void AsmPrinter::emitGlobalIndirectSymbol(Module &M, @@ -1445,7 +1445,7 @@ bool AsmPrinter::doFinalization(Module &M) { // Emit global variables. for (const auto &G : M.globals()) - EmitGlobalVariable(&G); + emitGlobalVariable(&G); // Emit remaining GOT equivalent globals. emitGlobalGOTEquivs(); @@ -1481,7 +1481,7 @@ bool AsmPrinter::doFinalization(Module &M) { OutStreamer->SwitchSection(TLOF.getDataSection()); const DataLayout &DL = M.getDataLayout(); - EmitAlignment(Align(DL.getPointerSize())); + emitAlignment(Align(DL.getPointerSize())); for (const auto &Stub : Stubs) { OutStreamer->EmitLabel(Stub.first); OutStreamer->EmitSymbolValue(Stub.second.getPointer(), @@ -1508,7 +1508,7 @@ bool AsmPrinter::doFinalization(Module &M) { COFF::IMAGE_SCN_LNK_COMDAT, SectionKind::getReadOnly(), Stub.first->getName(), COFF::IMAGE_COMDAT_SELECT_ANY)); - EmitAlignment(Align(DL.getPointerSize())); + emitAlignment(Align(DL.getPointerSize())); OutStreamer->EmitSymbolAttribute(Stub.first, MCSA_Global); OutStreamer->EmitLabel(Stub.first); OutStreamer->EmitSymbolValue(Stub.second.getPointer(), @@ -1568,10 +1568,10 @@ bool AsmPrinter::doFinalization(Module &M) { MP->finishAssembly(M, *MI, *this); // Emit llvm.ident metadata in an '.ident' directive. - EmitModuleIdents(M); + emitModuleIdents(M); // Emit bytes for llvm.commandline metadata. - EmitModuleCommandLines(M); + emitModuleCommandLines(M); // Emit __morestack address if needed for indirect calls. if (MMI->usesMorestackAddr()) { @@ -1764,7 +1764,7 @@ namespace { /// representations of the constants in the constant pool MCP. This is /// used to print out constants which have been "spilled to memory" by /// the code generator. -void AsmPrinter::EmitConstantPool() { +void AsmPrinter::emitConstantPool() { const MachineConstantPool *MCP = MF->getConstantPool(); const std::vector &CP = MCP->getConstants(); if (CP.empty()) return; @@ -1822,7 +1822,7 @@ void AsmPrinter::EmitConstantPool() { if (CurSection != CPSections[i].S) { OutStreamer->SwitchSection(CPSections[i].S); - EmitAlignment(Align(CPSections[i].Alignment)); + emitAlignment(Align(CPSections[i].Alignment)); CurSection = CPSections[i].S; Offset = 0; } @@ -1839,16 +1839,16 @@ void AsmPrinter::EmitConstantPool() { OutStreamer->EmitLabel(Sym); if (CPE.isMachineConstantPoolEntry()) - EmitMachineConstantPoolValue(CPE.Val.MachineCPVal); + emitMachineConstantPoolValue(CPE.Val.MachineCPVal); else - EmitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); + emitGlobalConstant(getDataLayout(), CPE.Val.ConstVal); } } } -/// EmitJumpTableInfo - Print assembly representations of the jump tables used -/// by the current function to the current output stream. -void AsmPrinter::EmitJumpTableInfo() { +// Print assembly representations of the jump tables used by the current +// function. +void AsmPrinter::emitJumpTableInfo() { const DataLayout &DL = MF->getDataLayout(); const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); if (!MJTI) return; @@ -1869,7 +1869,7 @@ void AsmPrinter::EmitJumpTableInfo() { OutStreamer->SwitchSection(ReadOnlySection); } - EmitAlignment(Align(MJTI->getEntryAlignment(DL))); + emitAlignment(Align(MJTI->getEntryAlignment(DL))); // Jump tables in code sections are marked with a data_region directive // where that's supported. @@ -1921,7 +1921,7 @@ void AsmPrinter::EmitJumpTableInfo() { OutStreamer->EmitLabel(JTISymbol); for (unsigned ii = 0, ee = JTBBs.size(); ii != ee; ++ii) - EmitJumpTableEntry(MJTI, JTBBs[ii], JTI); + emitJumpTableEntry(MJTI, JTBBs[ii], JTI); } if (!JTInDiffSection) OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); @@ -1929,7 +1929,7 @@ void AsmPrinter::EmitJumpTableInfo() { /// EmitJumpTableEntry - Emit a jump table entry for the specified MBB to the /// current stream. -void AsmPrinter::EmitJumpTableEntry(const MachineJumpTableInfo *MJTI, +void AsmPrinter::emitJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned UID) const { assert(MBB && MBB->getNumber() >= 0 && "Invalid basic block"); @@ -1994,10 +1994,10 @@ void AsmPrinter::EmitJumpTableEntry(const MachineJumpTableInfo *MJTI, /// EmitSpecialLLVMGlobal - Check to see if the specified global is a /// special global used by LLVM. If so, emit it and return true, otherwise /// do nothing and return false. -bool AsmPrinter::EmitSpecialLLVMGlobal(const GlobalVariable *GV) { +bool AsmPrinter::emitSpecialLLVMGlobal(const GlobalVariable *GV) { if (GV->getName() == "llvm.used") { if (MAI->hasNoDeadStrip()) // No need to emit this at all. - EmitLLVMUsedList(cast(GV->getInitializer())); + emitLLVMUsedList(cast(GV->getInitializer())); return true; } @@ -2011,14 +2011,14 @@ bool AsmPrinter::EmitSpecialLLVMGlobal(const GlobalVariable *GV) { assert(GV->hasInitializer() && "Not a special LLVM global!"); if (GV->getName() == "llvm.global_ctors") { - EmitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(), + emitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(), /* isCtor */ true); return true; } if (GV->getName() == "llvm.global_dtors") { - EmitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(), + emitXXStructorList(GV->getParent()->getDataLayout(), GV->getInitializer(), /* isCtor */ false); return true; @@ -2029,7 +2029,7 @@ bool AsmPrinter::EmitSpecialLLVMGlobal(const GlobalVariable *GV) { /// EmitLLVMUsedList - For targets that define a MAI::UsedDirective, mark each /// global in the specified llvm.used list. -void AsmPrinter::EmitLLVMUsedList(const ConstantArray *InitList) { +void AsmPrinter::emitLLVMUsedList(const ConstantArray *InitList) { // Should be an array of 'i8*'. for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) { const GlobalValue *GV = @@ -2053,7 +2053,7 @@ struct Structor { /// EmitXXStructorList - Emit the ctor or dtor list taking into account the init /// priority. -void AsmPrinter::EmitXXStructorList(const DataLayout &DL, const Constant *List, +void AsmPrinter::emitXXStructorList(const DataLayout &DL, const Constant *List, bool isCtor) { // Should be an array of '{ i32, void ()*, i8* }' structs. The first value is the // init priority. @@ -2111,12 +2111,12 @@ void AsmPrinter::EmitXXStructorList(const DataLayout &DL, const Constant *List, : Obj.getStaticDtorSection(S.Priority, KeySym)); OutStreamer->SwitchSection(OutputSection); if (OutStreamer->getCurrentSection() != OutStreamer->getPreviousSection()) - EmitAlignment(Align); - EmitXXStructor(DL, S.Func); + emitAlignment(Align); + emitXXStructor(DL, S.Func); } } -void AsmPrinter::EmitModuleIdents(Module &M) { +void AsmPrinter::emitModuleIdents(Module &M) { if (!MAI->hasIdentDirective()) return; @@ -2131,7 +2131,7 @@ void AsmPrinter::EmitModuleIdents(Module &M) { } } -void AsmPrinter::EmitModuleCommandLines(Module &M) { +void AsmPrinter::emitModuleCommandLines(Module &M) { MCSection *CommandLine = getObjFileLowering().getSectionForCommandLines(); if (!CommandLine) return; @@ -2215,7 +2215,7 @@ void AsmPrinter::emitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, // two boundary. If a global value is specified, and if that global has // an explicit alignment requested, it will override the alignment request // if required for correctness. -void AsmPrinter::EmitAlignment(Align Alignment, const GlobalObject *GV) const { +void AsmPrinter::emitAlignment(Align Alignment, const GlobalObject *GV) const { if (GV) Alignment = getGVAlignment(GV, GV->getParent()->getDataLayout(), Alignment); @@ -2816,7 +2816,7 @@ static void emitGlobalConstantImpl(const DataLayout &DL, const Constant *CV, } /// EmitGlobalConstant - Print a general LLVM constant to the .s file. -void AsmPrinter::EmitGlobalConstant(const DataLayout &DL, const Constant *CV) { +void AsmPrinter::emitGlobalConstant(const DataLayout &DL, const Constant *CV) { uint64_t Size = DL.getTypeAllocSize(CV->getType()); if (Size) emitGlobalConstantImpl(DL, CV, *this); @@ -2827,7 +2827,7 @@ void AsmPrinter::EmitGlobalConstant(const DataLayout &DL, const Constant *CV) { } } -void AsmPrinter::EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { +void AsmPrinter::emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { // Target doesn't support this yet! llvm_unreachable("Target does not support EmitMachineConstantPoolValue"); } @@ -2993,7 +2993,7 @@ void AsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { // Emit an alignment directive for this block, if needed. const Align Alignment = MBB.getAlignment(); if (Alignment != Align(1)) - EmitAlignment(Alignment); + emitAlignment(Alignment); // If the block has its address taken, emit any labels that were used to // reference the block. It is possible that there is more than one label @@ -3283,7 +3283,7 @@ void AsmPrinter::emitPatchableFunctionEntries() { OutStreamer->SwitchSection(OutContext.getELFSection( "__patchable_function_entries", ELF::SHT_PROGBITS, Flags)); } - EmitAlignment(Align(PointerSize)); + emitAlignment(Align(PointerSize)); OutStreamer->EmitSymbolValue(CurrentPatchableFunctionEntrySym, PointerSize); } } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index 09dc62e439874..4d66f06b5b8bb 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -106,7 +106,7 @@ static const char *DecodeDWARFEncoding(unsigned Encoding) { /// encoding. If verbose assembly output is enabled, we output comments /// describing the encoding. Desc is an optional string saying what the /// encoding is specifying (e.g. "LSDA"). -void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const { +void AsmPrinter::emitEncodingByte(unsigned Val, const char *Desc) const { if (isVerbose()) { if (Desc) OutStreamer->AddComment(Twine(Desc) + " Encoding = " + @@ -137,7 +137,7 @@ unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const { } } -void AsmPrinter::EmitTTypeReference(const GlobalValue *GV, +void AsmPrinter::emitTTypeReference(const GlobalValue *GV, unsigned Encoding) const { if (GV) { const TargetLoweringObjectFile &TLOF = getObjFileLowering(); diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp index c631cc5360b8b..d96e0abbe6733 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -106,7 +106,7 @@ unsigned AsmPrinter::addInlineAsmDiagBuffer(StringRef AsmStr, /// EmitInlineAsm - Emit a blob of inline asm to the output streamer. -void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, +void AsmPrinter::emitInlineAsm(StringRef Str, const MCSubtargetInfo &STI, const MCTargetOptions &MCOptions, const MDNode *LocMDNode, InlineAsm::AsmDialect Dialect) const { @@ -489,9 +489,9 @@ static void EmitGCCInlineAsmStr(const char *AsmStr, const MachineInstr *MI, OS << '\n' << (char)0; // null terminate string. } -/// EmitInlineAsm - This method formats and emits the specified machine -/// instruction that is an inline asm. -void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const { +/// This method formats and emits the specified machine instruction that is an +/// inline asm. +void AsmPrinter::emitInlineAsm(const MachineInstr *MI) const { assert(MI->isInlineAsm() && "printInlineAsm only works on inline asms"); // Count the number of register definitions to find the asm string. @@ -584,7 +584,7 @@ void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const { SrcMgr.PrintMessage(Loc, SourceMgr::DK_Note, Note); } - EmitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD, + emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD, MI->getInlineAsmDialect()); // Emit the #NOAPP end marker. This has to happen even if verbose-asm isn't @@ -592,7 +592,6 @@ void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const { OutStreamer->emitRawComment(MAI->getInlineAsmEnd()); } - /// PrintSpecial - Print information related to the specified machine instr /// that is independent of the operand, and may be independent of the instr /// itself. This can be useful for portably encoding the comment character diff --git a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp index 583a9ba839dd9..4d19a4932eb96 100644 --- a/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/EHStreamer.cpp @@ -426,7 +426,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { // EHABI). In this case LSDASection will be NULL. if (LSDASection) Asm->OutStreamer->SwitchSection(LSDASection); - Asm->EmitAlignment(Align(4)); + Asm->emitAlignment(Align(4)); // Emit the LSDA. MCSymbol *GCCETSym = @@ -436,8 +436,8 @@ MCSymbol *EHStreamer::emitExceptionTable() { Asm->OutStreamer->EmitLabel(Asm->getCurExceptionSym()); // Emit the LSDA header. - Asm->EmitEncodingByte(dwarf::DW_EH_PE_omit, "@LPStart"); - Asm->EmitEncodingByte(TTypeEncoding, "@TType"); + Asm->emitEncodingByte(dwarf::DW_EH_PE_omit, "@LPStart"); + Asm->emitEncodingByte(TTypeEncoding, "@TType"); MCSymbol *TTBaseLabel = nullptr; if (HaveTTData) { @@ -456,7 +456,7 @@ MCSymbol *EHStreamer::emitExceptionTable() { // Emit the landing pad call site table. MCSymbol *CstBeginLabel = Asm->createTempSymbol("cst_begin"); MCSymbol *CstEndLabel = Asm->createTempSymbol("cst_end"); - Asm->EmitEncodingByte(CallSiteEncoding, "Call site"); + Asm->emitEncodingByte(CallSiteEncoding, "Call site"); Asm->emitLabelDifferenceAsULEB128(CstEndLabel, CstBeginLabel); Asm->OutStreamer->EmitLabel(CstBeginLabel); @@ -602,11 +602,11 @@ MCSymbol *EHStreamer::emitExceptionTable() { } if (HaveTTData) { - Asm->EmitAlignment(Align(4)); + Asm->emitAlignment(Align(4)); emitTypeInfos(TTypeEncoding, TTBaseLabel); } - Asm->EmitAlignment(Align(4)); + Asm->emitAlignment(Align(4)); return GCCETSym; } @@ -629,7 +629,7 @@ void EHStreamer::emitTypeInfos(unsigned TTypeEncoding, MCSymbol *TTBaseLabel) { TypeInfos.rend())) { if (VerboseAsm) Asm->OutStreamer->AddComment("TypeInfo " + Twine(Entry--)); - Asm->EmitTTypeReference(GV, TTypeEncoding); + Asm->emitTTypeReference(GV, TTypeEncoding); } Asm->OutStreamer->EmitLabel(TTBaseLabel); diff --git a/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp index 989da7e0cd413..59a84e6f2d7b9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/ErlangGCPrinter.cpp @@ -72,7 +72,7 @@ void ErlangGCPrinter::finishAssembly(Module &M, GCModuleInfo &Info, **/ // Align to address width. - AP.EmitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); + AP.emitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); // Emit PointCount. OS.AddComment("safe point count"); diff --git a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp index b4eda5fa8c581..b8a5b487db273 100644 --- a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp @@ -129,7 +129,7 @@ void OcamlGCMetadataPrinter::finishAssembly(Module &M, GCModuleInfo &Info, report_fatal_error(" Too much descriptor for ocaml GC"); } AP.emitInt16(NumDescriptors); - AP.EmitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); + AP.emitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); for (GCModuleInfo::FuncInfoVec::iterator I = Info.funcinfo_begin(), IE = Info.funcinfo_end(); @@ -180,7 +180,7 @@ void OcamlGCMetadataPrinter::finishAssembly(Module &M, GCModuleInfo &Info, AP.emitInt16(K->StackOffset); } - AP.EmitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); + AP.emitAlignment(IntPtrSize == 4 ? Align(4) : Align(8)); } } } diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp index 0398675577cd5..e0ddafd6e8c86 100644 --- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -203,7 +203,7 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB, // We want our funclet's entry point to be aligned such that no nops will be // present after the label. - Asm->EmitAlignment(std::max(Asm->MF->getAlignment(), MBB.getAlignment()), + Asm->emitAlignment(std::max(Asm->MF->getAlignment(), MBB.getAlignment()), &F); // Now that we've emitted the alignment directive, point at our funclet. diff --git a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp index 42ce33a8f37ad..64d313e28030c 100644 --- a/llvm/lib/ExecutionEngine/ExecutionEngine.cpp +++ b/llvm/lib/ExecutionEngine/ExecutionEngine.cpp @@ -582,7 +582,7 @@ void *ExecutionEngine::getPointerToGlobal(const GlobalValue *GV) { // Global variable might have been added since interpreter started. if (GlobalVariable *GVar = const_cast(dyn_cast(GV))) - EmitGlobalVariable(GVar); + emitGlobalVariable(GVar); else llvm_unreachable("Global hasn't had an address allocated yet!"); @@ -1276,7 +1276,7 @@ void ExecutionEngine::emitGlobals() { if (GVEntry != &GV) // Not the canonical variable. continue; } - EmitGlobalVariable(&GV); + emitGlobalVariable(&GV); } } } @@ -1285,7 +1285,7 @@ void ExecutionEngine::emitGlobals() { // EmitGlobalVariable - This method emits the specified global variable to the // address specified in GlobalAddresses, or allocates new memory if it's not // already in the map. -void ExecutionEngine::EmitGlobalVariable(const GlobalVariable *GV) { +void ExecutionEngine::emitGlobalVariable(const GlobalVariable *GV) { void *GA = getPointerToGlobalIfAvailable(GV); if (!GA) { diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index 3a2a912180ccb..f2f29099b0cea 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -85,7 +85,7 @@ class AArch64AsmPrinter : public AsmPrinter { } void emitStartOfAsmFile(Module &M) override; - void EmitJumpTableInfo() override; + void emitJumpTableInfo() override; void emitJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned JTI); @@ -225,7 +225,7 @@ void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) { OutStreamer->SwitchSection(Nt); // Emit the note header. - EmitAlignment(Align(8)); + emitAlignment(Align(8)); OutStreamer->EmitIntValue(4, 4); // data size for "GNU\0" OutStreamer->EmitIntValue(4 * 4, 4); // Elf_Prop size OutStreamer->EmitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4); @@ -754,7 +754,7 @@ void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI, printOperand(MI, NOps - 2, OS); } -void AArch64AsmPrinter::EmitJumpTableInfo() { +void AArch64AsmPrinter::emitJumpTableInfo() { const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); if (!MJTI) return; @@ -782,7 +782,7 @@ void AArch64AsmPrinter::EmitJumpTableInfo() { if (JTBBs.empty()) continue; unsigned Size = AFI->getJumpTableEntrySize(JTI); - EmitAlignment(Align(Size)); + emitAlignment(Align(Size)); OutStreamer->EmitLabel(GetJTISymbol(JTI)); for (auto *JTBB : JTBBs) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp index 02942a09d7ef6..3e2c5a58a6e8d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -276,7 +276,7 @@ void AMDGPUAsmPrinter::emitBasicBlockStart(const MachineBasicBlock &MBB) { AsmPrinter::emitBasicBlockStart(MBB); } -void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void AMDGPUAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) { if (GV->hasInitializer() && !isa(GV->getInitializer())) { OutContext.reportError({}, @@ -310,7 +310,7 @@ void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { return; } - AsmPrinter::EmitGlobalVariable(GV); + AsmPrinter::emitGlobalVariable(GV); } bool AMDGPUAsmPrinter::doFinalization(Module &M) { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index 08725399b1a69..a0d5e8aa4b503 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -131,7 +131,7 @@ class AMDGPUAsmPrinter final : public AsmPrinter { void emitBasicBlockStart(const MachineBasicBlock &MBB) override; - void EmitGlobalVariable(const GlobalVariable *GV) override; + void emitGlobalVariable(const GlobalVariable *GV) override; void emitStartOfAsmFile(Module &M) override; diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index dd0db72c7c77c..2ea326949131a 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -76,7 +76,7 @@ void ARMAsmPrinter::emitFunctionEntryLabel() { OutStreamer->EmitLabel(CurrentFnSym); } -void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) { +void ARMAsmPrinter::emitXXStructor(const DataLayout &DL, const Constant *CV) { uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType()); assert(Size && "C++ constructor pointer had zero size!"); @@ -93,11 +93,11 @@ void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) { OutStreamer->EmitValue(E, Size); } -void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { if (PromotedGlobals.count(GV)) // The global was promoted into a constant pool. It should not be emitted. return; - AsmPrinter::EmitGlobalVariable(GV); + AsmPrinter::emitGlobalVariable(GV); } /// runOnMachineFunction - This uses the EmitInstruction() @@ -168,7 +168,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // relatively easy to exceed the thumb branch range within a TU. if (! ThumbIndirectPads.empty()) { OutStreamer->EmitAssemblerFlag(MCAF_Code16); - EmitAlignment(Align(2)); + emitAlignment(Align(2)); for (std::pair &TIP : ThumbIndirectPads) { OutStreamer->EmitLabel(TIP.second); EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) @@ -526,7 +526,7 @@ void ARMAsmPrinter::emitEndOfAsmFile(Module &M) { if (!Stubs.empty()) { // Switch with ".non_lazy_symbol_pointer" directive. OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection()); - EmitAlignment(Align(4)); + emitAlignment(Align(4)); for (auto &Stub : Stubs) emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second); @@ -539,7 +539,7 @@ void ARMAsmPrinter::emitEndOfAsmFile(Module &M) { if (!Stubs.empty()) { // Switch with ".non_lazy_symbol_pointer" directive. OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection()); - EmitAlignment(Align(4)); + emitAlignment(Align(4)); for (auto &Stub : Stubs) emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second); @@ -856,8 +856,8 @@ MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV, llvm_unreachable("unexpected target"); } -void ARMAsmPrinter:: -EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { +void ARMAsmPrinter::emitMachineConstantPoolValue( + MachineConstantPoolValue *MCPV) { const DataLayout &DL = getDataLayout(); int Size = DL.getTypeAllocSize(MCPV->getType()); @@ -881,7 +881,7 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { EmittedPromotedGlobalLabels.insert(GV); } } - return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit()); + return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit()); } MCSymbol *MCSym; @@ -935,13 +935,13 @@ EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { OutStreamer->EmitValue(Expr, Size); } -void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) { +void ARMAsmPrinter::emitJumpTableAddrs(const MachineInstr *MI) { const MachineOperand &MO1 = MI->getOperand(1); unsigned JTI = MO1.getIndex(); // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for // ARM mode tables. - EmitAlignment(Align(4)); + emitAlignment(Align(4)); // Emit a label for the jump table. MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI); @@ -981,13 +981,13 @@ void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) { OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); } -void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) { +void ARMAsmPrinter::emitJumpTableInsts(const MachineInstr *MI) { const MachineOperand &MO1 = MI->getOperand(1); unsigned JTI = MO1.getIndex(); // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for // ARM mode tables. - EmitAlignment(Align(4)); + emitAlignment(Align(4)); // Emit a label for the jump table. MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI); @@ -1009,14 +1009,14 @@ void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) { } } -void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI, +void ARMAsmPrinter::emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth) { assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width"); const MachineOperand &MO1 = MI->getOperand(1); unsigned JTI = MO1.getIndex(); if (Subtarget->isThumb1Only()) - EmitAlignment(Align(4)); + emitAlignment(Align(4)); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI); OutStreamer->EmitLabel(JTISymbol); @@ -1059,7 +1059,7 @@ void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI, OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); // Make sure the next instruction is 2-byte aligned. - EmitAlignment(Align(2)); + emitAlignment(Align(2)); } void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { @@ -1629,20 +1629,20 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; if (MCPE.isMachineConstantPoolEntry()) - EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); else - EmitGlobalConstant(DL, MCPE.Val.ConstVal); + emitGlobalConstant(DL, MCPE.Val.ConstVal); return; } case ARM::JUMPTABLE_ADDRS: - EmitJumpTableAddrs(MI); + emitJumpTableAddrs(MI); return; case ARM::JUMPTABLE_INSTS: - EmitJumpTableInsts(MI); + emitJumpTableInsts(MI); return; case ARM::JUMPTABLE_TBB: case ARM::JUMPTABLE_TBH: - EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); + emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2); return; case ARM::t2BR_JT: { EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h index 22016dedf2f20..cd771df992223 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.h +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h @@ -84,21 +84,21 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override; - void EmitJumpTableAddrs(const MachineInstr *MI); - void EmitJumpTableInsts(const MachineInstr *MI); - void EmitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth); + void emitJumpTableAddrs(const MachineInstr *MI); + void emitJumpTableInsts(const MachineInstr *MI); + void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth); void EmitInstruction(const MachineInstr *MI) override; bool runOnMachineFunction(MachineFunction &F) override; - void EmitConstantPool() override { + void emitConstantPool() override { // we emit constant pools customly! } void emitFunctionBodyEnd() override; void emitFunctionEntryLabel() override; void emitStartOfAsmFile(Module &M) override; void emitEndOfAsmFile(Module &M) override; - void EmitXXStructor(const DataLayout &DL, const Constant *CV) override; - void EmitGlobalVariable(const GlobalVariable *GV) override; + void emitXXStructor(const DataLayout &DL, const Constant *CV) override; + void emitGlobalVariable(const GlobalVariable *GV) override; MCSymbol *GetCPISymbol(unsigned CPID) const override; @@ -150,7 +150,7 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { public: /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. - void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; + void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; }; } // end namespace llvm diff --git a/llvm/lib/Target/Mips/Mips16HardFloat.cpp b/llvm/lib/Target/Mips/Mips16HardFloat.cpp index 10a7451f1bb4a..cc1f72c036323 100644 --- a/llvm/lib/Target/Mips/Mips16HardFloat.cpp +++ b/llvm/lib/Target/Mips/Mips16HardFloat.cpp @@ -43,7 +43,7 @@ namespace { } // end anonymous namespace -static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) { +static void emitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) { std::vector AsmArgTypes; std::vector AsmArgs; @@ -339,7 +339,7 @@ static void assureFPCallStub(Function &F, Module *M, AsmText += "jr $$18\n"; else AsmText += "jr $$25\n"; - EmitInlineAsm(Context, BB, AsmText); + emitInlineAsm(Context, BB, AsmText); new UnreachableInst(Context, BB); } @@ -475,7 +475,7 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV, AsmText += swapFPIntParams(PV, M, LE, false); AsmText += "jr $$25\n"; AsmText += LocalName + " = " + Name + "\n"; - EmitInlineAsm(Context, BB, AsmText); + emitInlineAsm(Context, BB, AsmText); new UnreachableInst(FStub->getContext(), BB); } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 9cc4ed42d337c..22999d3780dab 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -226,9 +226,9 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; if (MCPE.isMachineConstantPoolEntry()) - EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); else - EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); + emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); return; } @@ -404,7 +404,7 @@ void MipsAsmPrinter::emitFunctionEntryLabel() { // NaCl sandboxing requires that indirect call instructions are masked. // This means that function entry points should be bundle-aligned. if (Subtarget->isTargetNaCl()) - EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); + emitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); if (Subtarget->inMicroMipsMode()) { TS.emitDirectiveSetMicroMips(); diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index f9d877cff85aa..5bf68b3f09d14 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -126,11 +126,11 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { bool runOnMachineFunction(MachineFunction &MF) override; - void EmitConstantPool() override { + void emitConstantPool() override { bool UsingConstantPools = (Subtarget->inMips16Mode() && Subtarget->useConstantIslands()); if (!UsingConstantPools) - AsmPrinter::EmitConstantPool(); + AsmPrinter::emitConstantPool(); // we emit constant pools customly! } diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index 1457622d4ce35..f12d85386b7a7 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -163,7 +163,7 @@ class PPCAIXAsmPrinter : public PPCAsmPrinter { const MCExpr *lowerConstant(const Constant *CV) override; - void EmitGlobalVariable(const GlobalVariable *GV) override; + void emitGlobalVariable(const GlobalVariable *GV) override; void emitFunctionDescriptor() override; @@ -1583,7 +1583,7 @@ const MCExpr *PPCAIXAsmPrinter::lowerConstant(const Constant *CV) { return PPCAsmPrinter::lowerConstant(CV); } -void PPCAIXAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void PPCAIXAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { ValidateGV(GV); // Create the symbol, set its storage class. @@ -1632,9 +1632,9 @@ void PPCAIXAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { MCSymbol *EmittedInitSym = GVSym; emitLinkage(GV, EmittedInitSym); - EmitAlignment(getGVAlignment(GV, DL), GV); + emitAlignment(getGVAlignment(GV, DL), GV); OutStreamer->EmitLabel(EmittedInitSym); - EmitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); + emitGlobalConstant(GV->getParent()->getDataLayout(), GV->getInitializer()); } void PPCAIXAsmPrinter::emitFunctionDescriptor() { diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index b80dd058cf8ae..779dd2b12e059 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -685,8 +685,8 @@ getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) { llvm_unreachable("Invalid SystemCPModifier!"); } -void SystemZAsmPrinter:: -EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { +void SystemZAsmPrinter::emitMachineConstantPoolValue( + MachineConstantPoolValue *MCPV) { auto *ZCPV = static_cast(MCPV); const MCExpr *Expr = diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h index b9867fb900bd0..c9374362c89be 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h @@ -33,7 +33,7 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter { // Override AsmPrinter. StringRef getPassName() const override { return "SystemZ Assembly Printer"; } void EmitInstruction(const MachineInstr *MI) override; - void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; + void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; void emitEndOfAsmFile(Module &M) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 47cc17f092386..975234e1fed32 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -277,12 +277,12 @@ void WebAssemblyAsmPrinter::EmitTargetFeatures(Module &M) { OutStreamer->PopSection(); } -void WebAssemblyAsmPrinter::EmitConstantPool() { +void WebAssemblyAsmPrinter::emitConstantPool() { assert(MF->getConstantPool()->getConstants().empty() && "WebAssembly disables constant pools"); } -void WebAssemblyAsmPrinter::EmitJumpTableInfo() { +void WebAssemblyAsmPrinter::emitJumpTableInfo() { // Nothing to do; jump tables are incorporated into the instruction stream. } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h index 9ec19ed52bd6e..fd4b03b63f792 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h @@ -60,8 +60,8 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyAsmPrinter final : public AsmPrinter { void emitEndOfAsmFile(Module &M) override; void EmitProducerInfo(Module &M); void EmitTargetFeatures(Module &M); - void EmitJumpTableInfo() override; - void EmitConstantPool() override; + void emitJumpTableInfo() override; + void emitConstantPool() override; void emitFunctionBodyStart() override; void EmitInstruction(const MachineInstr *MI) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp b/llvm/lib/Target/X86/X86AsmPrinter.cpp index f2e7ceb9463b4..85731e6115dd5 100644 --- a/llvm/lib/Target/X86/X86AsmPrinter.cpp +++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp @@ -597,7 +597,7 @@ void X86AsmPrinter::emitStartOfAsmFile(Module &M) { // Emitting note header. int WordSize = TT.isArch64Bit() ? 8 : 4; - EmitAlignment(WordSize == 4 ? Align(4) : Align(8)); + emitAlignment(WordSize == 4 ? Align(4) : Align(8)); OutStreamer->EmitIntValue(4, 4 /*size*/); // data size for "GNU\0" OutStreamer->EmitIntValue(8 + WordSize, 4 /*size*/); // Elf_Prop size OutStreamer->EmitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4 /*size*/); @@ -607,7 +607,7 @@ void X86AsmPrinter::emitStartOfAsmFile(Module &M) { OutStreamer->EmitIntValue(ELF::GNU_PROPERTY_X86_FEATURE_1_AND, 4); OutStreamer->EmitIntValue(4, 4); // data size OutStreamer->EmitIntValue(FeatureFlagsAnd, 4); // data - EmitAlignment(WordSize == 4 ? Align(4) : Align(8)); // padding + emitAlignment(WordSize == 4 ? Align(4) : Align(8)); // padding OutStreamer->endSection(Nt); OutStreamer->SwitchSection(Cur); diff --git a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index 4b5de9ff313ae..22ddc7919bb80 100644 --- a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -72,7 +72,7 @@ namespace { const char *ExtraCode, raw_ostream &O) override; void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV); - void EmitGlobalVariable(const GlobalVariable *GV) override; + void emitGlobalVariable(const GlobalVariable *GV) override; void emitFunctionEntryLabel() override; void EmitInstruction(const MachineInstr *MI) override; @@ -104,10 +104,9 @@ void XCoreAsmPrinter::emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV) { } } -void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { +void XCoreAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { // Check to see if this is a special global used by LLVM, if so, emit it. - if (!GV->hasInitializer() || - EmitSpecialLLVMGlobal(GV)) + if (!GV->hasInitializer() || emitSpecialLLVMGlobal(GV)) return; const DataLayout &DL = getDataLayout(); @@ -143,7 +142,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { llvm_unreachable("Unknown linkage type!"); } - EmitAlignment(std::max(Alignment, Align(4)), GV); + emitAlignment(std::max(Alignment, Align(4)), GV); if (GV->isThreadLocal()) { report_fatal_error("TLS is not supported by this target!"); @@ -155,7 +154,7 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { } OutStreamer->EmitLabel(GVSym); - EmitGlobalConstant(DL, C); + emitGlobalConstant(DL, C); // The ABI requires that unsigned scalar types smaller than 32 bits // are padded to 32 bits. if (Size < 4) From 5756bc4382a6023c8dcc25f39243a49ac413f9bf Mon Sep 17 00:00:00 2001 From: River Riddle Date: Thu, 13 Feb 2020 17:11:01 -0800 Subject: [PATCH 29/57] [mlir][DeclarativeParser] Add support for formatting enum attributes in the string form. Summary: This revision adds support to the declarative parser for formatting enum attributes in the symbolized form. It uses this new functionality to port several of the SPIRV parsers over to the declarative form. Differential Revision: https://reviews.llvm.org/D74525 --- .../mlir/Dialect/SPIRV/SPIRVNonUniformOps.td | 6 ++ mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td | 6 ++ mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 90 ------------------- mlir/test/Dialect/SPIRV/ops.mlir | 2 +- mlir/tools/mlir-tblgen/OpFormatGen.cpp | 64 ++++++++++++- 5 files changed, 76 insertions(+), 92 deletions(-) diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td index b1478d048b5f4..56c2b59b1e7fb 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVNonUniformOps.td @@ -97,6 +97,10 @@ def SPV_GroupNonUniformBallotOp : SPV_Op<"GroupNonUniformBallot", []> { let results = (outs SPV_IntVec4:$result ); + + let assemblyFormat = [{ + $execution_scope $predicate attr-dict `:` type($result) + }]; } // ----- @@ -145,6 +149,8 @@ def SPV_GroupNonUniformElectOp : SPV_Op<"GroupNonUniformElect", []> { let builders = [ OpBuilder<[{Builder *builder, OperationState &state, spirv::Scope}]> ]; + + let assemblyFormat = "$execution_scope attr-dict `:` type($result)"; } // ----- diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td index 9a578968a59f4..b78ecc3cd8feb 100644 --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVOps.td @@ -162,6 +162,10 @@ def SPV_ControlBarrierOp : SPV_Op<"ControlBarrier", []> { let verifier = [{ return verifyMemorySemantics(*this); }]; let autogenSerialization = 0; + + let assemblyFormat = [{ + $execution_scope `,` $memory_scope `,` $memory_semantics attr-dict + }]; } // ----- @@ -319,6 +323,8 @@ def SPV_MemoryBarrierOp : SPV_Op<"MemoryBarrier", []> { let verifier = [{ return verifyMemorySemantics(*this); }]; let autogenSerialization = 0; + + let assemblyFormat = "$memory_scope `,` $memory_semantics attr-dict"; } // ----- diff --git a/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp b/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp index c8514d4e618e1..6e97c3f58a660 100644 --- a/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp +++ b/mlir/lib/Dialect/SPIRV/SPIRVOps.cpp @@ -1467,32 +1467,6 @@ spirv::ConstantOp spirv::ConstantOp::getOne(Type type, Location loc, llvm_unreachable("unimplemented types for ConstantOp::getOne()"); } -//===----------------------------------------------------------------------===// -// spv.ControlBarrier -//===----------------------------------------------------------------------===// - -static ParseResult parseControlBarrierOp(OpAsmParser &parser, - OperationState &state) { - spirv::Scope executionScope; - spirv::Scope memoryScope; - spirv::MemorySemantics memorySemantics; - - return failure( - parseEnumAttribute(executionScope, parser, state, - kExecutionScopeAttrName) || - parser.parseComma() || - parseEnumAttribute(memoryScope, parser, state, kMemoryScopeAttrName) || - parser.parseComma() || - parseEnumAttribute(memorySemantics, parser, state)); -} - -static void print(spirv::ControlBarrierOp op, OpAsmPrinter &printer) { - printer << spirv::ControlBarrierOp::getOperationName() << " \"" - << stringifyScope(op.execution_scope()) << "\", \"" - << stringifyScope(op.memory_scope()) << "\", \"" - << stringifyMemorySemantics(op.memory_semantics()) << "\""; -} - //===----------------------------------------------------------------------===// // spv.EntryPoint //===----------------------------------------------------------------------===// @@ -1916,28 +1890,6 @@ static LogicalResult verify(spirv::GlobalVariableOp varOp) { // spv.GroupNonUniformBallotOp //===----------------------------------------------------------------------===// -static ParseResult parseGroupNonUniformBallotOp(OpAsmParser &parser, - OperationState &state) { - spirv::Scope executionScope; - OpAsmParser::OperandType operandInfo; - Type resultType; - IntegerType i1Type = parser.getBuilder().getI1Type(); - if (parseEnumAttribute(executionScope, parser, state, - kExecutionScopeAttrName) || - parser.parseOperand(operandInfo) || parser.parseColonType(resultType) || - parser.resolveOperand(operandInfo, i1Type, state.operands)) - return failure(); - - return parser.addTypeToList(resultType, state.types); -} - -static void print(spirv::GroupNonUniformBallotOp ballotOp, - OpAsmPrinter &printer) { - printer << spirv::GroupNonUniformBallotOp::getOperationName() << " \"" - << stringifyScope(ballotOp.execution_scope()) << "\" " - << ballotOp.predicate() << " : " << ballotOp.getType(); -} - static LogicalResult verify(spirv::GroupNonUniformBallotOp ballotOp) { // TODO(antiagainst): check the result integer type's signedness bit is 0. @@ -1959,25 +1911,6 @@ void spirv::GroupNonUniformElectOp::build(Builder *builder, build(builder, state, builder->getI1Type(), scope); } -static ParseResult parseGroupNonUniformElectOp(OpAsmParser &parser, - OperationState &state) { - spirv::Scope executionScope; - Type resultType; - if (parseEnumAttribute(executionScope, parser, state, - kExecutionScopeAttrName) || - parser.parseColonType(resultType)) - return failure(); - - return parser.addTypeToList(resultType, state.types); -} - -static void print(spirv::GroupNonUniformElectOp groupOp, - OpAsmPrinter &printer) { - printer << spirv::GroupNonUniformElectOp::getOperationName() << " \"" - << stringifyScope(groupOp.execution_scope()) - << "\" : " << groupOp.getType(); -} - static LogicalResult verify(spirv::GroupNonUniformElectOp groupOp) { spirv::Scope scope = groupOp.execution_scope(); if (scope != spirv::Scope::Workgroup && scope != spirv::Scope::Subgroup) @@ -1987,8 +1920,6 @@ static LogicalResult verify(spirv::GroupNonUniformElectOp groupOp) { return success(); } - - //===----------------------------------------------------------------------===// // spv.IAdd //===----------------------------------------------------------------------===// @@ -2296,27 +2227,6 @@ static LogicalResult verify(spirv::MergeOp mergeOp) { return success(); } -//===----------------------------------------------------------------------===// -// spv.MemoryBarrier -//===----------------------------------------------------------------------===// - -static ParseResult parseMemoryBarrierOp(OpAsmParser &parser, - OperationState &state) { - spirv::Scope memoryScope; - spirv::MemorySemantics memorySemantics; - - return failure( - parseEnumAttribute(memoryScope, parser, state, kMemoryScopeAttrName) || - parser.parseComma() || - parseEnumAttribute(memorySemantics, parser, state)); -} - -static void print(spirv::MemoryBarrierOp op, OpAsmPrinter &printer) { - printer << spirv::MemoryBarrierOp::getOperationName() << " \"" - << stringifyScope(op.memory_scope()) << "\", \"" - << stringifyMemorySemantics(op.memory_semantics()) << "\""; -} - //===----------------------------------------------------------------------===// // spv.module //===----------------------------------------------------------------------===// diff --git a/mlir/test/Dialect/SPIRV/ops.mlir b/mlir/test/Dialect/SPIRV/ops.mlir index 09a41da2d340a..cf7ab6096689c 100644 --- a/mlir/test/Dialect/SPIRV/ops.mlir +++ b/mlir/test/Dialect/SPIRV/ops.mlir @@ -289,7 +289,7 @@ func @control_barrier_0() -> () { // ----- func @control_barrier_1() -> () { - // expected-error @+1 {{invalid scope attribute specification: "Something"}} + // expected-error @+1 {{invalid execution_scope attribute specification: "Something"}} spv.ControlBarrier "Something", "Device", "Acquire|UniformMemory" return } diff --git a/mlir/tools/mlir-tblgen/OpFormatGen.cpp b/mlir/tools/mlir-tblgen/OpFormatGen.cpp index 91918e099c81d..b8aeb904e1879 100644 --- a/mlir/tools/mlir-tblgen/OpFormatGen.cpp +++ b/mlir/tools/mlir-tblgen/OpFormatGen.cpp @@ -264,6 +264,18 @@ struct OperationFormat { //===----------------------------------------------------------------------===// // Parser Gen +/// Returns if we can format the given attribute as an EnumAttr in the parser +/// format. +static bool canFormatEnumAttr(const NamedAttribute *attr) { + const EnumAttr *enumAttr = dyn_cast(&attr->attr); + if (!enumAttr) + return false; + + // The attribute must have a valid underlying type and a constant builder. + return !enumAttr->getUnderlyingType().empty() && + !enumAttr->getConstBuilderTemplate().empty(); +} + /// The code snippet used to generate a parser call for an attribute. /// /// {0}: The storage type of the attribute. @@ -275,6 +287,30 @@ const char *const attrParserCode = R"( return failure(); )"; +/// The code snippet used to generate a parser call for an enum attribute. +/// +/// {0}: The name of the attribute. +/// {1}: The c++ namespace for the enum symbolize functions. +/// {2}: The function to symbolize a string of the enum. +/// {3}: The constant builder call to create an attribute of the enum type. +const char *const enumAttrParserCode = R"( + { + StringAttr attrVal; + SmallVector attrStorage; + auto loc = parser.getCurrentLocation(); + if (parser.parseAttribute(attrVal, parser.getBuilder().getNoneType(), + "{0}", attrStorage)) + return failure(); + + auto attrOptional = {1}::{2}(attrVal.getValue()); + if (!attrOptional) + return parser.emitError(loc, "invalid ") + << "{0} attribute specification: " << attrVal; + + result.addAttribute("{0}", {3}); + } +)"; + /// The code snippet used to generate a parser call for an operand. /// /// {0}: The name of the operand. @@ -383,6 +419,24 @@ void OperationFormat::genParser(Operator &op, OpClass &opClass) { } else if (auto *attr = dyn_cast(element.get())) { const NamedAttribute *var = attr->getVar(); + // Check to see if we can parse this as an enum attribute. + if (canFormatEnumAttr(var)) { + const EnumAttr &enumAttr = cast(var->attr); + + // Generate the code for building an attribute for this enum. + std::string attrBuilderStr; + { + llvm::raw_string_ostream os(attrBuilderStr); + os << tgfmt(enumAttr.getConstBuilderTemplate(), &attrTypeCtx, + "attrOptional.getValue()"); + } + + body << formatv(enumAttrParserCode, var->name, + enumAttr.getCppNamespace(), + enumAttr.getStringToSymbolFnName(), attrBuilderStr); + continue; + } + // If this attribute has a buildable type, use that when parsing the // attribute. std::string attrTypeStr; @@ -637,7 +691,15 @@ void OperationFormat::genPrinter(Operator &op, OpClass &opClass) { if (auto *attr = dyn_cast(element.get())) { const NamedAttribute *var = attr->getVar(); - // Elide the attribute type if it is buildable.. + // If we are formatting as a enum, symbolize the attribute as a string. + if (canFormatEnumAttr(var)) { + const EnumAttr &enumAttr = cast(var->attr); + body << " p << \"\\\"\" << " << enumAttr.getSymbolToStringFnName() + << "(" << var->name << "()) << \"\\\"\";\n"; + continue; + } + + // Elide the attribute type if it is buildable. Optional attrType = var->attr.getValueType(); if (attrType && attrType->getBuilderCall()) body << " p.printAttributeWithoutType(" << var->name << "Attr());\n"; From e635e48020adbe1139f2de8d2db0d4875d6d75a8 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Thu, 13 Feb 2020 12:53:32 -0800 Subject: [PATCH 30/57] Reinstate llvm-go to test the go bindings. This partially reverts commit 102814b4d36ad004a2e37cd2a1e84bd2c3593d29. --- llvm/tools/llvm-go/CMakeLists.txt | 9 + llvm/tools/llvm-go/llvm-go.go | 311 ++++++++++++++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 llvm/tools/llvm-go/CMakeLists.txt create mode 100644 llvm/tools/llvm-go/llvm-go.go diff --git a/llvm/tools/llvm-go/CMakeLists.txt b/llvm/tools/llvm-go/CMakeLists.txt new file mode 100644 index 0000000000000..20393f728f8f1 --- /dev/null +++ b/llvm/tools/llvm-go/CMakeLists.txt @@ -0,0 +1,9 @@ +if(LLVM_BINDINGS MATCHES "go") + set(binpath ${CMAKE_BINARY_DIR}/bin/llvm-go${CMAKE_EXECUTABLE_SUFFIX}) + add_custom_command(OUTPUT ${binpath} + COMMAND ${GO_EXECUTABLE} build -o ${binpath} llvm-go.go + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/llvm-go.go + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMENT "Building Go executable llvm-go") + add_custom_target(llvm-go ALL DEPENDS ${binpath}) +endif() diff --git a/llvm/tools/llvm-go/llvm-go.go b/llvm/tools/llvm-go/llvm-go.go new file mode 100644 index 0000000000000..a0561dd5fd8d9 --- /dev/null +++ b/llvm/tools/llvm-go/llvm-go.go @@ -0,0 +1,311 @@ +//===-- llvm-go.go - go tool wrapper for LLVM -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This tool lets us build LLVM components within the tree by setting up a +// $GOPATH that resembles a tree fetched in the normal way with "go get". +// +//===----------------------------------------------------------------------===// + +package main + +import ( + "fmt" + "io/ioutil" + "os" + "os/exec" + "path/filepath" + "runtime" + "strings" +) + +const ( + linkmodeComponentLibs = "component-libs" + linkmodeDylib = "dylib" +) + +type pkg struct { + llvmpath, pkgpath string +} + +var packages = []pkg{ + {"bindings/go/llvm", "llvm.org/llvm/bindings/go/llvm"}, +} + +type compilerFlags struct { + cpp, cxx, ld string +} + +var components = []string{ + "all-targets", + "analysis", + "asmparser", + "asmprinter", + "bitreader", + "bitwriter", + "codegen", + "core", + "coroutines", + "debuginfodwarf", + "executionengine", + "instrumentation", + "interpreter", + "ipo", + "irreader", + "linker", + "mc", + "mcjit", + "objcarcopts", + "option", + "profiledata", + "scalaropts", + "support", + "target", +} + +func llvmConfig(args ...string) string { + configpath := os.Getenv("LLVM_CONFIG") + if configpath == "" { + bin, _ := filepath.Split(os.Args[0]) + configpath = filepath.Join(bin, "llvm-config") + } + + cmd := exec.Command(configpath, args...) + cmd.Stderr = os.Stderr + out, err := cmd.Output() + if err != nil { + panic(err.Error()) + } + + outstr := string(out) + outstr = strings.TrimSuffix(outstr, "\n") + outstr = strings.Replace(outstr, "\n", " ", -1) + return outstr +} + +func llvmFlags() compilerFlags { + args := append([]string{"--ldflags", "--libs", "--system-libs"}, components...) + ldflags := llvmConfig(args...) + stdLibOption := "" + if strings.Contains(llvmConfig("--cxxflags"), "-stdlib=libc++") { + // If libc++ is used to build LLVM libraries, -stdlib=libc++ is + // needed to resolve dependent symbols + stdLibOption = "-stdlib=libc++" + } + if runtime.GOOS != "darwin" { + // OS X doesn't like -rpath with cgo. See: + // https://github.com/golang/go/issues/7293 + ldflags = "-Wl,-rpath," + llvmConfig("--libdir") + " " + ldflags + } + return compilerFlags{ + cpp: llvmConfig("--cppflags"), + cxx: "-std=c++14" + " " + stdLibOption, + ld: ldflags, + } +} + +func addTag(args []string, tag string) []string { + args = append([]string{}, args...) + addedTag := false + for i, a := range args { + if strings.HasPrefix(a, "-tags=") { + args[i] = a + " " + tag + addedTag = true + } else if a == "-tags" && i+1 < len(args) { + args[i+1] = args[i+1] + " " + tag + addedTag = true + } + } + if !addedTag { + args = append([]string{args[0], "-tags", tag}, args[1:]...) + } + return args +} + +func printComponents() { + fmt.Println(strings.Join(components, " ")) +} + +func printConfig() { + flags := llvmFlags() + + fmt.Printf(`// +build !byollvm + +// This file is generated by llvm-go, do not edit. + +package llvm + +/* +#cgo CPPFLAGS: %s +#cgo CXXFLAGS: %s +#cgo LDFLAGS: %s +*/ +import "C" + +type (run_build_sh int) +`, flags.cpp, flags.cxx, flags.ld) +} + +func runGoWithLLVMEnv(args []string, cc, cxx, gocmd, llgo, cppflags, cxxflags, ldflags string, packages []pkg) { + args = addTag(args, "byollvm") + + srcdir := llvmConfig("--src-root") + + tmpgopath, err := ioutil.TempDir("", "gopath") + if err != nil { + panic(err.Error()) + } + + for _, p := range packages { + path := filepath.Join(tmpgopath, "src", p.pkgpath) + err := os.MkdirAll(filepath.Dir(path), os.ModePerm) + if err != nil { + panic(err.Error()) + } + + abspath := p.llvmpath + if !filepath.IsAbs(abspath) { + abspath = filepath.Join(srcdir, abspath) + } + + err = os.Symlink(abspath, path) + if err != nil { + panic(err.Error()) + } + } + + newpath := os.Getenv("PATH") + + newgopathlist := []string{tmpgopath} + newgopathlist = append(newgopathlist, filepath.SplitList(os.Getenv("GOPATH"))...) + newgopath := strings.Join(newgopathlist, string(filepath.ListSeparator)) + + flags := llvmFlags() + + newenv := []string{ + "CC=" + cc, + "CXX=" + cxx, + "CGO_CPPFLAGS=" + flags.cpp + " " + cppflags, + "CGO_CXXFLAGS=" + flags.cxx + " " + cxxflags, + "CGO_LDFLAGS=" + flags.ld + " " + ldflags, + "GOPATH=" + newgopath, + "PATH=" + newpath, + } + if llgo != "" { + newenv = append(newenv, "GCCGO="+llgo) + } + + for _, v := range os.Environ() { + if !strings.HasPrefix(v, "CC=") && + !strings.HasPrefix(v, "CXX=") && + !strings.HasPrefix(v, "CGO_CPPFLAGS=") && + !strings.HasPrefix(v, "CGO_CXXFLAGS=") && + !strings.HasPrefix(v, "CGO_LDFLAGS=") && + !strings.HasPrefix(v, "GCCGO=") && + !strings.HasPrefix(v, "GOPATH=") && + !strings.HasPrefix(v, "PATH=") { + newenv = append(newenv, v) + } + } + + gocmdpath, err := exec.LookPath(gocmd) + if err != nil { + panic(err.Error()) + } + + proc, err := os.StartProcess(gocmdpath, append([]string{gocmd}, args...), + &os.ProcAttr{ + Env: newenv, + Files: []*os.File{os.Stdin, os.Stdout, os.Stderr}, + }) + if err != nil { + panic(err.Error()) + } + ps, err := proc.Wait() + if err != nil { + panic(err.Error()) + } + + os.RemoveAll(tmpgopath) + + if !ps.Success() { + os.Exit(1) + } +} + +func usage() { + fmt.Println(`Usage: llvm-go subcommand [flags] + +Available subcommands: build get install run test print-components print-config`) + os.Exit(0) +} + +func main() { + cc := os.Getenv("CC") + cxx := os.Getenv("CXX") + cppflags := os.Getenv("CGO_CPPFLAGS") + cxxflags := os.Getenv("CGO_CXXFLAGS") + ldflags := os.Getenv("CGO_LDFLAGS") + gocmd := "go" + llgo := "" + packagesString := "" + + flags := []struct { + name string + dest *string + }{ + {"cc", &cc}, + {"cxx", &cxx}, + {"go", &gocmd}, + {"llgo", &llgo}, + {"cppflags", &cppflags}, + {"ldflags", &ldflags}, + {"packages", &packagesString}, + } + + args := os.Args[1:] +LOOP: + for { + if len(args) == 0 { + usage() + } + for _, flag := range flags { + if strings.HasPrefix(args[0], flag.name+"=") { + *flag.dest = args[0][len(flag.name)+1:] + args = args[1:] + continue LOOP + } + } + break + } + + packages := packages + if packagesString != "" { + for _, field := range strings.Fields(packagesString) { + pos := strings.IndexRune(field, '=') + if pos == -1 { + fmt.Fprintf(os.Stderr, "invalid packages value %q, expected 'pkgpath=llvmpath [pkgpath=llvmpath ...]'\n", packagesString) + os.Exit(1) + } + packages = append(packages, pkg{ + pkgpath: field[:pos], + llvmpath: field[pos+1:], + }) + } + } + + switch args[0] { + case "build", "get", "install", "run", "test": + runGoWithLLVMEnv(args, cc, cxx, gocmd, llgo, cppflags, cxxflags, ldflags, packages) + case "print-components": + printComponents() + case "print-config": + printConfig() + default: + usage() + } +} From f3b933266a0d1b7e8219f3383ed0c5a664e4d3df Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Thu, 13 Feb 2020 17:18:53 -0800 Subject: [PATCH 31/57] Remove unused lambda argument. --- mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp index 70935f6da70b4..b92bcf7bc2ae9 100644 --- a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp +++ b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp @@ -595,7 +595,7 @@ static LogicalResult processParallelLoop(ParallelOp parallelOp, return val.getParentRegion()->isAncestor(launchOp.getParentRegion()); }; - auto ensureLaunchIndependent = [&launchOp, &rewriter, + auto ensureLaunchIndependent = [&rewriter, launchIndependent](Value val) -> Value { if (launchIndependent(val)) return val; From ec89335c47bf316b6a43055343ea55a0a72a1953 Mon Sep 17 00:00:00 2001 From: "Liu, Chen3" Date: Thu, 13 Feb 2020 21:16:18 +0800 Subject: [PATCH 32/57] [X86] Fix the bug that _mm_mask_cvtsepi64_epi32 generates result without zero the upper 64bit. Differential Revision : https://reviews.llvm.org/D74552 --- llvm/lib/Target/X86/X86IntrinsicsInfo.h | 4 ++-- llvm/test/CodeGen/X86/avx512vl-intrinsics.ll | 20 ++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/X86/X86IntrinsicsInfo.h b/llvm/lib/Target/X86/X86IntrinsicsInfo.h index 40bf28df3b90e..b3080a178dd34 100644 --- a/llvm/lib/Target/X86/X86IntrinsicsInfo.h +++ b/llvm/lib/Target/X86/X86IntrinsicsInfo.h @@ -679,8 +679,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = { X86ISD::VTRUNCS, X86ISD::VMTRUNCS), X86_INTRINSIC_DATA(avx512_mask_pmovs_qb_512, TRUNCATE_TO_REG, X86ISD::VTRUNCS, X86ISD::VMTRUNCS), - X86_INTRINSIC_DATA(avx512_mask_pmovs_qd_128, INTR_TYPE_1OP_MASK, - X86ISD::VTRUNCS, 0), + X86_INTRINSIC_DATA(avx512_mask_pmovs_qd_128, TRUNCATE_TO_REG, + X86ISD::VTRUNCS, X86ISD::VMTRUNCS), X86_INTRINSIC_DATA(avx512_mask_pmovs_qd_256, INTR_TYPE_1OP_MASK, X86ISD::VTRUNCS, 0), X86_INTRINSIC_DATA(avx512_mask_pmovs_qd_512, INTR_TYPE_1OP_MASK, diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll index b5dfa2f11ade8..3c545c8d567ff 100644 --- a/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics.ll @@ -2369,21 +2369,21 @@ define <4 x i32>@test_int_x86_avx512_mask_pmovs_qd_128(<2 x i64> %x0, <4 x i32> ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04] ; X86-NEXT: kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8] -; X86-NEXT: vpmovsqd %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7e,0x08,0x25,0xc0] -; X86-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0x6f,0xc8] -; X86-NEXT: vmovdqa32 %xmm0, %xmm2 {%k1} {z} # encoding: [0x62,0xf1,0x7d,0x89,0x6f,0xd0] -; X86-NEXT: vpaddd %xmm2, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xca] -; X86-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] +; X86-NEXT: vpmovsqd %xmm0, %xmm2 # encoding: [0x62,0xf2,0x7e,0x08,0x25,0xc2] +; X86-NEXT: vpmovsqd %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7e,0x09,0x25,0xc1] +; X86-NEXT: vpmovsqd %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7e,0x89,0x25,0xc0] +; X86-NEXT: vpaddd %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0] +; X86-NEXT: vpaddd %xmm0, %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfe,0xc0] ; X86-NEXT: retl # encoding: [0xc3] ; ; X64-LABEL: test_int_x86_avx512_mask_pmovs_qd_128: ; X64: # %bb.0: ; X64-NEXT: kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf] -; X64-NEXT: vpmovsqd %xmm0, %xmm0 # encoding: [0x62,0xf2,0x7e,0x08,0x25,0xc0] -; X64-NEXT: vmovdqa32 %xmm0, %xmm2 {%k1} {z} # encoding: [0x62,0xf1,0x7d,0x89,0x6f,0xd0] -; X64-NEXT: vmovdqa32 %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf1,0x7d,0x09,0x6f,0xc8] -; X64-NEXT: vpaddd %xmm2, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xca] -; X64-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] +; X64-NEXT: vpmovsqd %xmm0, %xmm2 # encoding: [0x62,0xf2,0x7e,0x08,0x25,0xc2] +; X64-NEXT: vpmovsqd %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7e,0x09,0x25,0xc1] +; X64-NEXT: vpmovsqd %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x7e,0x89,0x25,0xc0] +; X64-NEXT: vpaddd %xmm0, %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0] +; X64-NEXT: vpaddd %xmm0, %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xe9,0xfe,0xc0] ; X64-NEXT: retq # encoding: [0xc3] %res0 = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 -1) %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmovs.qd.128(<2 x i64> %x0, <4 x i32> %x1, i8 %x2) From 5feb80e748924606531ba28c97fe65145c65372e Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 13 Feb 2020 17:39:29 -0800 Subject: [PATCH 33/57] [dsymutil] Fix double relocation of DW_AT_call_return_pc When the DW_AT_call_return_pc matches a relocation, the call return pc would get relocated twice, once because of the relocation in the object file and once because of dsymutil. The same problem exists for the low and high PC and the fix is the same. We remember the low, high and return pc of the original DIE and relocate that, rather than the potentially already relocated value. Reviewed offline by Fred Riss. --- llvm/include/llvm/DWARFLinker/DWARFLinker.h | 3 ++ llvm/lib/DWARFLinker/DWARFLinker.cpp | 5 +++- .../Inputs/private/tmp/call_return_pc/call | Bin 0 -> 4640 bytes .../Inputs/private/tmp/call_return_pc/call.o | Bin 0 -> 2228 bytes .../dsymutil/X86/call-site-entry-reloc.test | 26 ++++++++++++++++++ 5 files changed, 33 insertions(+), 1 deletion(-) create mode 100755 llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call create mode 100644 llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call.o create mode 100644 llvm/test/tools/dsymutil/X86/call-site-entry-reloc.test diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/DWARFLinker.h index 5a8d08148091b..31e8bccbf4081 100644 --- a/llvm/include/llvm/DWARFLinker/DWARFLinker.h +++ b/llvm/include/llvm/DWARFLinker/DWARFLinker.h @@ -582,6 +582,9 @@ class DWARFLinker { /// Value of AT_high_pc in the input DIE uint64_t OrigHighPc = 0; + /// Value of DW_AT_call_return_pc in the input DIE + uint64_t OrigCallReturnPc = 0; + /// Offset to apply to PC addresses inside a function. int64_t PCOffset = 0; diff --git a/llvm/lib/DWARFLinker/DWARFLinker.cpp b/llvm/lib/DWARFLinker/DWARFLinker.cpp index adcbebfc7c77d..03919c805130c 100644 --- a/llvm/lib/DWARFLinker/DWARFLinker.cpp +++ b/llvm/lib/DWARFLinker/DWARFLinker.cpp @@ -1017,7 +1017,8 @@ unsigned DWARFLinker::DIECloner::cloneAddressAttribute( } else if (AttrSpec.Attr == dwarf::DW_AT_call_return_pc) { // Relocate a return PC address within a call site entry. if (Die.getTag() == dwarf::DW_TAG_call_site) - Addr += Info.PCOffset; + Addr = (Info.OrigCallReturnPc ? Info.OrigCallReturnPc : Addr) + + Info.PCOffset; } Die.addValue(DIEAlloc, static_cast(AttrSpec.Attr), @@ -1280,6 +1281,8 @@ DIE *DWARFLinker::DIECloner::cloneDIE( // inlining function. AttrInfo.OrigLowPc = dwarf::toAddress(InputDIE.find(dwarf::DW_AT_low_pc), std::numeric_limits::max()); + AttrInfo.OrigCallReturnPc = + dwarf::toAddress(InputDIE.find(dwarf::DW_AT_call_return_pc), 0); } // Reset the Offset to 0 as we will be working on the local copy of diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call b/llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call new file mode 100755 index 0000000000000000000000000000000000000000..d7587f944e9f761374fe3a50617306a5aa8d7b46 GIT binary patch literal 4640 zcmeHLOKTKC5U$x>O)$YtAc_(Riv)=ec0>Y+xA<60aE(h6L_FB+W0nl=i^*)<=p`Nm zk2&TKc=IRt1H9$zKS&H-^q_b!eqT?InORrx?i5sae^p)8)nCu0X79)6pF<*6T0~ON z)6jW<*OJ3Ze-ovgbyfGu zO()pVpYMaoH*XRUhj$y4^O*nQ((?Vn-KCH_@Dtw^yHw;|60 zY)o?wx(Iv*^X|CF8_Xln5|jd$)(qweX!Jb5e-eIgIp`?V?rwN?!>!o0tws%)G6`iJ z?>_FeAHAR3eS7EA_=Cxr!yB;Wp!&@0DXfCE<}!0Fbp@F9g))QtGmi(pqr!9f7W4(w zS@_(n<62P9>ehzuH1oIfsLQPc(U&kW{{n_#%$E%&Ux_3PBn%`BBn%`BBn%`BBn%`B zBnm^>s5XFpt27c&!$^8*b8{>6xn28x5#f)b^NZ&S;@gb&-@h71aV#Y^t zjYcD^D{BSKAI)bqKCX{_Y!;62zBz-#^VmT6UFCHd>EzQgpIP=@VgaN v!9NT2;_c literal 0 HcmV?d00001 diff --git a/llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call.o b/llvm/test/tools/dsymutil/Inputs/private/tmp/call_return_pc/call.o new file mode 100644 index 0000000000000000000000000000000000000000..df698e8a328451144fe1e97430ff79f32b157194 GIT binary patch literal 2228 zcma)7-D@0G6u*<*Nn<8%wq3z2ifpAqM6w^|gIGlqteS$t(iT#va-E%>O*ZV#E}KcZ zmdch=GzwxxeDO)}$^Ss~MFi2e{tJo^`r<#JV*LH?oV$iGr8#iUx##2l?!D)pJ9F>P zKmIwTl#@{q;4HXGQ38XC;IA3H5B(sqI_H3_4NOJ$=mcpUhr>7-C-#+Bu3q`iwxd}Y zSiHF@r6%ahs#_8=O6z9W*xS;6qcI5giGN{p{nD%B6pM35JX-cQP7qjYTfBDE>d}|R z`&1G?6aA~;&0~L)iO+0P!kC}zZ#NzoR~m1g#Rgg2p_|x8WD3vk_dB7E{BF35q%_{Q zf@e$Y$)+BJ*K6zq%t_-_Wc70bFghWg*lb9IQQryPnmF@lUbgmC+kgM-mvCFR2Dpu6g4U^imUl4}yt?3t z$#=1B$JDl8I_=0Hrt3Epyf(%f6&dj=z&S~eVT*1xcZr{x1AAKzM%cywTIfJ{JC@T(r8x_~) zZWJ@Q^WO8`OGSj=cks!{lrizRD82(5YE*a^M|O|NxmYk5c#`K-CikM}@pzwrlh-13>zRd+Vuqja-nsE5FYTsvYTI-4I-PJaZMeHp@j zj@0DGu-vQ)I)1cO+7Ac2?Os%>)yma!wKTugj@Q83dyO*M^?awZ->pzA^as72Fo??t zmX=p*)v&o-TU}`eezUsRT=K)^MZXc$s*5X&t4k}-F4vxG)oM?x!0&X*fvTuV-0fFr z=|LFp4IL;HoP0*|V;?=H{kL6E0>VEh&{+;BN``!kt7K`3C?1 literal 0 HcmV?d00001 diff --git a/llvm/test/tools/dsymutil/X86/call-site-entry-reloc.test b/llvm/test/tools/dsymutil/X86/call-site-entry-reloc.test new file mode 100644 index 0000000000000..46e947044ffca --- /dev/null +++ b/llvm/test/tools/dsymutil/X86/call-site-entry-reloc.test @@ -0,0 +1,26 @@ +Test binaries created with the following commands: + +$ cat call.c +__attribute__((noinline, noreturn)) void foo() { + asm volatile("" ::: "memory"); + __builtin_unreachable(); +} +__attribute__((noinline)) void bar() { + asm volatile("nop" :::); + foo(); +} + +int main() { bar(); } + +$ clang -g call.c -fomit-frame-pointer -c -Os -o call.o +$ clang -g call.o -o call + +The test requires the return PC to match a relocation (in this case the +DW_AT_high_pc of main). Without this change the value would get relocated +twice. + +RUN: dsymutil -oso-prepend-path %p/../Inputs %p/../Inputs/private/tmp/call_return_pc/call -o %t.dSYM +RUN: llvm-dwarfdump %t.dSYM | FileCheck %s -implicit-check-not=DW_AT_call_return_pc + +CHECK: DW_AT_call_return_pc (0x0000000100000f72) +CHECK: DW_AT_call_return_pc (0x0000000100000f78) From 105a270028abb7a0237dd2af3ddba07471d8c49d Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 20:57:03 -0800 Subject: [PATCH 34/57] [ELF][AArch64] Rename pacPlt to zPacPlt and forceBti to zForceIbt after D71327. NFC We use config->z* for -z options. --- lld/ELF/Config.h | 4 ++-- lld/ELF/Driver.cpp | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h index 221ea21e0880a..dc43534f20ad2 100644 --- a/lld/ELF/Config.h +++ b/lld/ELF/Config.h @@ -152,7 +152,6 @@ struct Configuration { bool exportDynamic; bool fixCortexA53Errata843419; bool fixCortexA8; - bool forceBTI; bool formatBinary = false; bool gcSections; bool gdbIndex; @@ -176,7 +175,6 @@ struct Configuration { bool oFormatBinary; bool omagic; bool optRemarksWithHotness; - bool pacPlt; bool picThunk; bool pie; bool printGcSections; @@ -204,6 +202,7 @@ struct Configuration { bool writeAddends; bool zCombreloc; bool zCopyreloc; + bool zForceBti; bool zForceIbt; bool zGlobal; bool zHazardplt; @@ -216,6 +215,7 @@ struct Configuration { bool zNodlopen; bool zNow; bool zOrigin; + bool zPacPlt; bool zRelro; bool zRodynamic; bool zShstk; diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index 5206c1566a79c..021895aa4e970 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -351,9 +351,9 @@ static void checkOptions() { error("-z force-ibt may not be used with -z retpolineplt"); if (config->emachine != EM_AARCH64) { - if (config->pacPlt) + if (config->zPacPlt) error("-z pac-plt only supported on AArch64"); - if (config->forceBTI) + if (config->zForceBti) error("-z force-bti only supported on AArch64"); } } @@ -907,7 +907,6 @@ static void readConfigs(opt::InputArgList &args) { !args.hasArg(OPT_relocatable); config->fixCortexA8 = args.hasArg(OPT_fix_cortex_a8) && !args.hasArg(OPT_relocatable); - config->forceBTI = hasZOption(args, "force-bti"); config->gcSections = args.hasFlag(OPT_gc_sections, OPT_no_gc_sections, false); config->gnuUnique = args.hasFlag(OPT_gnu_unique, OPT_no_gnu_unique, true); config->gdbIndex = args.hasFlag(OPT_gdb_index, OPT_no_gdb_index, false); @@ -947,7 +946,6 @@ static void readConfigs(opt::InputArgList &args) { config->optimize = args::getInteger(args, OPT_O, 1); config->orphanHandling = getOrphanHandling(args); config->outputFile = args.getLastArgValue(OPT_o); - config->pacPlt = hasZOption(args, "pac-plt"); config->pie = args.hasFlag(OPT_pie, OPT_no_pie, false); config->printIcfSections = args.hasFlag(OPT_print_icf_sections, OPT_no_print_icf_sections, false); @@ -1001,6 +999,7 @@ static void readConfigs(opt::InputArgList &args) { args.hasFlag(OPT_warn_symbol_ordering, OPT_no_warn_symbol_ordering, true); config->zCombreloc = getZFlag(args, "combreloc", "nocombreloc", true); config->zCopyreloc = getZFlag(args, "copyreloc", "nocopyreloc", true); + config->zForceBti = hasZOption(args, "force-bti"); config->zForceIbt = hasZOption(args, "force-ibt"); config->zGlobal = hasZOption(args, "global"); config->zGnustack = getZGnuStack(args); @@ -1015,6 +1014,7 @@ static void readConfigs(opt::InputArgList &args) { config->zNodlopen = hasZOption(args, "nodlopen"); config->zNow = getZFlag(args, "now", "lazy", false); config->zOrigin = hasZOption(args, "origin"); + config->zPacPlt = hasZOption(args, "pac-plt"); config->zRelro = getZFlag(args, "relro", "norelro", true); config->zRetpolineplt = hasZOption(args, "retpolineplt"); config->zRodynamic = hasZOption(args, "rodynamic"); @@ -1735,7 +1735,7 @@ template static uint32_t getAndFeatures() { uint32_t ret = -1; for (InputFile *f : objectFiles) { uint32_t features = cast>(f)->andFeatures; - if (config->forceBTI && !(features & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)) { + if (config->zForceBti && !(features & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)) { warn(toString(f) + ": -z force-bti: file does not have BTI property"); features |= GNU_PROPERTY_AARCH64_FEATURE_1_BTI; } else if (config->zForceIbt && @@ -1749,7 +1749,7 @@ template static uint32_t getAndFeatures() { // Force enable pointer authentication Plt, we don't warn in this case as // this does not require support in the object for correctness. - if (config->pacPlt) + if (config->zPacPlt) ret |= GNU_PROPERTY_AARCH64_FEATURE_1_PAC; // Force enable Shadow Stack. if (config->zShstk) From 5573abceab5eb9c6964b7249eae21f80a88ebf2e Mon Sep 17 00:00:00 2001 From: Evgeniy Brevnov Date: Thu, 16 Jan 2020 15:17:43 +0700 Subject: [PATCH 35/57] [DependenceAnalysis] Dependecies for loads marked with "ivnariant.load" should not be shared with general accesses(PR42151). Summary: This is second attempt to fix the problem with incorrect dependencies reported in presence of invariant load. Initial fix (https://reviews.llvm.org/D64405) was reverted due to a regression reported in https://reviews.llvm.org/D70516. The original fix changed caching behavior for invariant loads. Namely such loads are not put into the second level cache (NonLocalDepInfo). The problem with that fix is the first level cache (CachedNonLocalPointerInfo) still works as if invariant loads were in the second level cache. The solution is in addition to not putting dependence results into the second level cache avoid putting info about invariant loads into the first level cache as well. Reviewers: jdoerfert, reames, hfinkel, efriedma Reviewed By: jdoerfert Subscribers: DaniilSuchkov, hiraditya, bmahjour, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73027 --- .../lib/Analysis/MemoryDependenceAnalysis.cpp | 80 +++++--- .../MemoryDependenceAnalysis/InvariantLoad.ll | 173 ++++++++++++++++++ 2 files changed, 229 insertions(+), 24 deletions(-) create mode 100644 llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll diff --git a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp index 450595cac57b4..ce9944a5ce4be 100644 --- a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp +++ b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp @@ -902,6 +902,11 @@ MemDepResult MemoryDependenceResults::GetNonLocalInfoForBlock( Instruction *QueryInst, const MemoryLocation &Loc, bool isLoad, BasicBlock *BB, NonLocalDepInfo *Cache, unsigned NumSortedEntries) { + bool isInvariantLoad = false; + + if (LoadInst *LI = dyn_cast_or_null(QueryInst)) + isInvariantLoad = LI->getMetadata(LLVMContext::MD_invariant_load); + // Do a binary search to see if we already have an entry for this block in // the cache set. If so, find it. NonLocalDepInfo::iterator Entry = std::upper_bound( @@ -913,6 +918,13 @@ MemDepResult MemoryDependenceResults::GetNonLocalInfoForBlock( if (Entry != Cache->begin() + NumSortedEntries && Entry->getBB() == BB) ExistingResult = &*Entry; + // Use cached result for invariant load only if there is no dependency for non + // invariant load. In this case invariant load can not have any dependency as + // well. + if (ExistingResult && isInvariantLoad && + !ExistingResult->getResult().isNonFuncLocal()) + ExistingResult = nullptr; + // If we have a cached entry, and it is non-dirty, use it as the value for // this dependency. if (ExistingResult && !ExistingResult->getResult().isDirty()) { @@ -941,6 +953,10 @@ MemDepResult MemoryDependenceResults::GetNonLocalInfoForBlock( MemDepResult Dep = getPointerDependencyFrom(Loc, isLoad, ScanPos, BB, QueryInst); + // Don't cache results for invariant load. + if (isInvariantLoad) + return Dep; + // If we had a dirty entry for the block, update it. Otherwise, just add // a new entry. if (ExistingResult) @@ -1029,6 +1045,10 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB( InitialNLPI.Size = Loc.Size; InitialNLPI.AATags = Loc.AATags; + bool isInvariantLoad = false; + if (LoadInst *LI = dyn_cast_or_null(QueryInst)) + isInvariantLoad = LI->getMetadata(LLVMContext::MD_invariant_load); + // Get the NLPI for CacheKey, inserting one into the map if it doesn't // already have one. std::pair Pair = @@ -1037,7 +1057,8 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB( // If we already have a cache entry for this CacheKey, we may need to do some // work to reconcile the cache entry and the current query. - if (!Pair.second) { + // Invariant loads don't participate in caching. Thus no need to reconcile. + if (!isInvariantLoad && !Pair.second) { if (CacheInfo->Size != Loc.Size) { bool ThrowOutEverything; if (CacheInfo->Size.hasValue() && Loc.Size.hasValue()) { @@ -1093,7 +1114,10 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB( // If we have valid cached information for exactly the block we are // investigating, just return it with no recomputation. - if (CacheInfo->Pair == BBSkipFirstBlockPair(StartBB, SkipFirstBlock)) { + // Don't use cached information for invariant loads since it is valid for + // non-invariant loads only. + if (!isInvariantLoad && + CacheInfo->Pair == BBSkipFirstBlockPair(StartBB, SkipFirstBlock)) { // We have a fully cached result for this query then we can just return the // cached results and populate the visited set. However, we have to verify // that we don't already have conflicting results for these blocks. Check @@ -1129,14 +1153,18 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB( return true; } - // Otherwise, either this is a new block, a block with an invalid cache - // pointer or one that we're about to invalidate by putting more info into it - // than its valid cache info. If empty, the result will be valid cache info, - // otherwise it isn't. - if (Cache->empty()) - CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock); - else - CacheInfo->Pair = BBSkipFirstBlockPair(); + // Invariant loads don't affect cache in any way thus no need to update + // CacheInfo as well. + if (!isInvariantLoad) { + // Otherwise, either this is a new block, a block with an invalid cache + // pointer or one that we're about to invalidate by putting more info into + // it than its valid cache info. If empty, the result will be valid cache + // info, otherwise it isn't. + if (Cache->empty()) + CacheInfo->Pair = BBSkipFirstBlockPair(StartBB, SkipFirstBlock); + else + CacheInfo->Pair = BBSkipFirstBlockPair(); + } SmallVector Worklist; Worklist.push_back(StartBB); @@ -1377,22 +1405,26 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB( if (SkipFirstBlock) return false; - bool foundBlock = false; - for (NonLocalDepEntry &I : llvm::reverse(*Cache)) { - if (I.getBB() != BB) - continue; + // Results of invariant loads are not cached thus no need to update cached + // information. + if (!isInvariantLoad) { + bool foundBlock = false; + for (NonLocalDepEntry &I : llvm::reverse(*Cache)) { + if (I.getBB() != BB) + continue; - assert((GotWorklistLimit || I.getResult().isNonLocal() || - !DT.isReachableFromEntry(BB)) && - "Should only be here with transparent block"); - foundBlock = true; - I.setResult(MemDepResult::getUnknown()); - Result.push_back( - NonLocalDepResult(I.getBB(), I.getResult(), Pointer.getAddr())); - break; + assert((GotWorklistLimit || I.getResult().isNonLocal() || + !DT.isReachableFromEntry(BB)) && + "Should only be here with transparent block"); + foundBlock = true; + I.setResult(MemDepResult::getUnknown()); + Result.push_back( + NonLocalDepResult(I.getBB(), I.getResult(), Pointer.getAddr())); + break; + } + (void)foundBlock; (void)GotWorklistLimit; + assert((foundBlock || GotWorklistLimit) && "Current block not in cache?"); } - (void)foundBlock; (void)GotWorklistLimit; - assert((foundBlock || GotWorklistLimit) && "Current block not in cache?"); } // Okay, we're done now. If we added new values to the cache, re-sort it. diff --git a/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll b/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll new file mode 100644 index 0000000000000..152cb175ef608 --- /dev/null +++ b/llvm/test/Analysis/MemoryDependenceAnalysis/InvariantLoad.ll @@ -0,0 +1,173 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -gvn -S | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1" +target triple = "x86_64-unknown-linux-gnu" + +declare void @llvm.memset.p0i8.i8(i8*, i8, i32, i1) +declare void @foo(i8*) + +define i8 @test(i1 %cmp) { +; CHECK-LABEL: @test( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[P:%.*]] = alloca i8 +; CHECK-NEXT: store i8 5, i8* [[P]] +; CHECK-NEXT: br label [[HEADER:%.*]] +; CHECK: header: +; CHECK-NEXT: [[V:%.*]] = phi i8 [ 5, [[ENTRY:%.*]] ], [ -5, [[ALIVE:%.*]] ] +; CHECK-NEXT: [[I:%.*]] = phi i8 [ 0, [[ENTRY]] ], [ [[I_INC:%.*]], [[ALIVE]] ] +; CHECK-NEXT: br i1 [[CMP:%.*]], label [[ALIVE]], label [[DEAD:%.*]] +; CHECK: dead: +; CHECK-NEXT: call void @foo(i8* [[P]]) +; CHECK-NEXT: [[I_1:%.*]] = add i8 [[I]], [[V]] +; CHECK-NEXT: br label [[ALIVE]] +; CHECK: alive: +; CHECK-NEXT: [[I_2:%.*]] = phi i8 [ [[I]], [[HEADER]] ], [ [[I_1]], [[DEAD]] ] +; CHECK-NEXT: store i8 -5, i8* [[P]] +; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* align 1 [[P]], i8 0, i32 1, i1 false) +; CHECK-NEXT: [[I_INC]] = add i8 [[I_2]], 1 +; CHECK-NEXT: [[CMP_LOOP:%.*]] = icmp ugt i8 [[I_INC]], 100 +; CHECK-NEXT: br i1 [[CMP_LOOP]], label [[EXIT:%.*]], label [[HEADER]] +; CHECK: exit: +; CHECK-NEXT: ret i8 0 +; + +entry: + %p = alloca i8 + %addr = getelementptr inbounds i8, i8* %p, i64 0 + store i8 5, i8* %addr + br label %header +header: + %i = phi i8 [0, %entry], [%i.inc, %backedge] + br i1 %cmp, label %alive, label %dead +dead: + call void @foo(i8* %p) + %v = load i8, i8* %addr, !invariant.load !1 + %i.1 = add i8 %i, %v + br label %alive +alive: + %i.2 = phi i8 [%i, %header], [%i.1, %dead] + store i8 -5, i8* %addr + br label %backedge +backedge: + call void @llvm.memset.p0i8.i8(i8 * align 1 %p, i8 0, i32 1, i1 false) + %i.inc = add i8 %i.2, 1 + %cmp.loop = icmp ugt i8 %i.inc, 100 + br i1 %cmp.loop, label %exit, label %header +exit: + %res = load i8, i8* %addr + ret i8 %res +} + +; Check that first two loads are not optimized out while the one marked with +; invariant.load reuses %res1 +define i8 @test2(i1 %cmp, i8 *%p) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[RES1:%.*]] = load i8, i8* [[P:%.*]] +; CHECK-NEXT: call void @foo(i8* [[P]]) +; CHECK-NEXT: br i1 [[CMP:%.*]], label [[B2:%.*]], label [[B1:%.*]] +; CHECK: b1: +; CHECK-NEXT: [[RES2:%.*]] = load i8, i8* [[P]] +; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]] +; CHECK-NEXT: br label [[ALIVE:%.*]] +; CHECK: b2: +; CHECK-NEXT: [[RES_DEAD:%.*]] = add i8 [[RES1]], [[RES1]] +; CHECK-NEXT: br label [[ALIVE]] +; CHECK: alive: +; CHECK-NEXT: [[RES_PHI:%.*]] = phi i8 [ [[RES3]], [[B1]] ], [ [[RES_DEAD]], [[B2]] ] +; CHECK-NEXT: ret i8 [[RES_PHI]] +; + +entry: + %res1 = load i8, i8* %p + call void @foo(i8 *%p) + br i1 %cmp, label %b2, label %b1 +b1: + %res2 = load i8, i8* %p + %res3 = add i8 %res1, %res2 + br label %alive +b2: + %v = load i8, i8* %p, !invariant.load !1 + %res.dead = add i8 %v, %res1 + br label %alive +alive: + %res.phi = phi i8 [%res3, %b1], [%res.dead, %b2] + ret i8 %res.phi +} + +; This is essentially the same test case as the above one but with %b1 and %b2 +; swapped in "br i1 %cmp, label %b1, label %b2" instruction. That helps us to +; ensure that results doesn't depend on visiting order. +define i8 @test3(i1 %cmp, i8 *%p) { +; CHECK-LABEL: @test3( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[RES1:%.*]] = load i8, i8* [[P:%.*]] +; CHECK-NEXT: call void @foo(i8* [[P]]) +; CHECK-NEXT: br i1 [[CMP:%.*]], label [[B1:%.*]], label [[B2:%.*]] +; CHECK: b1: +; CHECK-NEXT: [[RES2:%.*]] = load i8, i8* [[P]] +; CHECK-NEXT: [[RES3:%.*]] = add i8 [[RES1]], [[RES2]] +; CHECK-NEXT: br label [[ALIVE:%.*]] +; CHECK: b2: +; CHECK-NEXT: [[RES_DEAD:%.*]] = add i8 [[RES1]], [[RES1]] +; CHECK-NEXT: br label [[ALIVE]] +; CHECK: alive: +; CHECK-NEXT: [[RES_PHI:%.*]] = phi i8 [ [[RES3]], [[B1]] ], [ [[RES_DEAD]], [[B2]] ] +; CHECK-NEXT: ret i8 [[RES_PHI]] +; +entry: + %res1 = load i8, i8* %p + call void @foo(i8 *%p) + br i1 %cmp, label %b1, label %b2 +b1: + %res2 = load i8, i8* %p + %res3 = add i8 %res1, %res2 + br label %alive +b2: + %v = load i8, i8* %p, !invariant.load !1 + %res.dead = add i8 %v, %res1 + br label %alive +alive: + %res.phi = phi i8 [%res3, %b1], [%res.dead, %b2] + ret i8 %res.phi +} + + +; This is reduced test case catching regression in the first version of the +; fix for invariant loads (https://reviews.llvm.org/D64405). +define void @test4() { +; CHECK-LABEL: @test4( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load float, float* inttoptr (i64 8 to float*), align 4 +; CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], [[TMP0]] +; CHECK-NEXT: br label [[FUSION_LOOP_HEADER_DIM_1_PREHEADER:%.*]] +; CHECK: fusion.loop_header.dim.1.preheader: +; CHECK-NEXT: [[TMP2:%.*]] = phi float [ [[TMP0]], [[ENTRY:%.*]] ], [ [[DOTPRE:%.*]], [[FUSION_LOOP_HEADER_DIM_1_PREHEADER]] ] +; CHECK-NEXT: [[FUSION_INVAR_ADDRESS_DIM_0_03:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[INVAR_INC3:%.*]], [[FUSION_LOOP_HEADER_DIM_1_PREHEADER]] ] +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2 x [1 x [4 x float]]], [2 x [1 x [4 x float]]]* null, i64 0, i64 [[FUSION_INVAR_ADDRESS_DIM_0_03]], i64 0, i64 2 +; CHECK-NEXT: [[TMP4:%.*]] = fmul float [[TMP2]], [[TMP2]] +; CHECK-NEXT: [[INVAR_INC3]] = add nuw nsw i64 [[FUSION_INVAR_ADDRESS_DIM_0_03]], 1 +; CHECK-NEXT: [[DOTPHI_TRANS_INSERT:%.*]] = getelementptr inbounds [2 x [1 x [4 x float]]], [2 x [1 x [4 x float]]]* null, i64 0, i64 [[INVAR_INC3]], i64 0, i64 2 +; CHECK-NEXT: [[DOTPRE]] = load float, float* [[DOTPHI_TRANS_INSERT]], align 4, !invariant.load !0 +; CHECK-NEXT: br label [[FUSION_LOOP_HEADER_DIM_1_PREHEADER]] +; +entry: + %0 = getelementptr inbounds [2 x [1 x [4 x float]]], [2 x [1 x [4 x float]]]* null, i64 0, i64 0, i64 0, i64 2 + %1 = load float, float* %0, align 4 + %2 = fmul float %1, %1 + br label %fusion.loop_header.dim.1.preheader + +fusion.loop_header.dim.1.preheader: ; preds = %fusion.loop_header.dim.1.preheader, %entry + %fusion.invar_address.dim.0.03 = phi i64 [ 0, %entry ], [ %invar.inc3, %fusion.loop_header.dim.1.preheader ] + %3 = getelementptr inbounds [2 x [1 x [4 x float]]], [2 x [1 x [4 x float]]]* null, i64 0, i64 %fusion.invar_address.dim.0.03, i64 0, i64 2 + %4 = load float, float* %3, align 4, !invariant.load !1 + %5 = fmul float %4, %4 + %6 = getelementptr inbounds [2 x [1 x [4 x float]]], [2 x [1 x [4 x float]]]* null, i64 0, i64 %fusion.invar_address.dim.0.03, i64 0, i64 2 + %7 = load float, float* %6, align 4, !invariant.load !1 + %8 = fmul float %7, %7 + %invar.inc3 = add nuw nsw i64 %fusion.invar_address.dim.0.03, 1 + br label %fusion.loop_header.dim.1.preheader +} + +!1 = !{} From f10e2df7bc19a3f05038387d77addd16ab058e06 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 13 Feb 2020 21:49:12 -0800 Subject: [PATCH 36/57] [lldb/Plugins] Have one initializer per ABI plugin After the recent change that grouped some of the ABI plugins together, those plugins ended up with multiple initializers per plugin. This is incompatible with my proposed approach of generating the initializers dynamically, which is why I've grouped them together in a new entry point. Differential revision: https://reviews.llvm.org/D74451 --- lldb/source/API/SystemInitializerFull.cpp | 61 +++++++------------ .../source/Plugins/ABI/AArch64/ABIAArch64.cpp | 24 ++++++++ lldb/source/Plugins/ABI/AArch64/ABIAArch64.h | 17 ++++++ .../Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp | 2 - .../Plugins/ABI/AArch64/ABISysV_arm64.cpp | 2 - .../source/Plugins/ABI/AArch64/CMakeLists.txt | 1 + lldb/source/Plugins/ABI/ARM/ABIARM.cpp | 24 ++++++++ lldb/source/Plugins/ABI/ARM/ABIARM.h | 17 ++++++ lldb/source/Plugins/ABI/ARM/CMakeLists.txt | 1 + lldb/source/Plugins/ABI/Mips/ABIMips.cpp | 24 ++++++++ lldb/source/Plugins/ABI/Mips/ABIMips.h | 17 ++++++ lldb/source/Plugins/ABI/Mips/CMakeLists.txt | 1 + .../source/Plugins/ABI/PowerPC/ABIPowerPC.cpp | 24 ++++++++ lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.h | 17 ++++++ .../source/Plugins/ABI/PowerPC/CMakeLists.txt | 1 + lldb/source/Plugins/ABI/X86/ABIX86.cpp | 30 +++++++++ lldb/source/Plugins/ABI/X86/ABIX86.h | 17 ++++++ lldb/source/Plugins/ABI/X86/CMakeLists.txt | 1 + .../tools/lldb-test/SystemInitializerTest.cpp | 45 ++++---------- 19 files changed, 250 insertions(+), 76 deletions(-) create mode 100644 lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp create mode 100644 lldb/source/Plugins/ABI/AArch64/ABIAArch64.h create mode 100644 lldb/source/Plugins/ABI/ARM/ABIARM.cpp create mode 100644 lldb/source/Plugins/ABI/ARM/ABIARM.h create mode 100644 lldb/source/Plugins/ABI/Mips/ABIMips.cpp create mode 100644 lldb/source/Plugins/ABI/Mips/ABIMips.h create mode 100644 lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.cpp create mode 100644 lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.h create mode 100644 lldb/source/Plugins/ABI/X86/ABIX86.cpp create mode 100644 lldb/source/Plugins/ABI/X86/ABIX86.h diff --git a/lldb/source/API/SystemInitializerFull.cpp b/lldb/source/API/SystemInitializerFull.cpp index 888a7579f84d6..7e2d80fceec80 100644 --- a/lldb/source/API/SystemInitializerFull.cpp +++ b/lldb/source/API/SystemInitializerFull.cpp @@ -24,29 +24,22 @@ #include -LLDB_PLUGIN_DECLARE(ABIMacOSX_arm64) -LLDB_PLUGIN_DECLARE(ABISysV_arm64) -LLDB_PLUGIN_DECLARE(ABIMacOSX_arm) -LLDB_PLUGIN_DECLARE(ABISysV_arm) -LLDB_PLUGIN_DECLARE(ABISysV_arc) -LLDB_PLUGIN_DECLARE(ABISysV_hexagon) -LLDB_PLUGIN_DECLARE(ABISysV_mips) -LLDB_PLUGIN_DECLARE(ABISysV_mips64) -LLDB_PLUGIN_DECLARE(ABISysV_ppc) -LLDB_PLUGIN_DECLARE(ABISysV_ppc64) -LLDB_PLUGIN_DECLARE(ABISysV_s390x) -LLDB_PLUGIN_DECLARE(ABIMacOSX_i386) -LLDB_PLUGIN_DECLARE(ABISysV_i386) -LLDB_PLUGIN_DECLARE(ABISysV_x86_64) -LLDB_PLUGIN_DECLARE(ABIWindows_x86_64) -LLDB_PLUGIN_DECLARE(ObjectFileBreakpad) -LLDB_PLUGIN_DECLARE(ObjectFileELF) -LLDB_PLUGIN_DECLARE(ObjectFileMachO) -LLDB_PLUGIN_DECLARE(ObjectFilePECOFF) -LLDB_PLUGIN_DECLARE(ObjectFileWasm) -LLDB_PLUGIN_DECLARE(ObjectContainerBSDArchive) -LLDB_PLUGIN_DECLARE(ObjectContainerUniversalMachO) -LLDB_PLUGIN_DECLARE(ScriptInterpreterNone) +LLDB_PLUGIN_DECLARE(ABIAArch64); +LLDB_PLUGIN_DECLARE(ABIARM); +LLDB_PLUGIN_DECLARE(ABISysV_arc); +LLDB_PLUGIN_DECLARE(ABISysV_hexagon); +LLDB_PLUGIN_DECLARE(ABIMips); +LLDB_PLUGIN_DECLARE(ABIPowerPC); +LLDB_PLUGIN_DECLARE(ABISysV_s390x); +LLDB_PLUGIN_DECLARE(ABIX86); +LLDB_PLUGIN_DECLARE(ObjectFileBreakpad); +LLDB_PLUGIN_DECLARE(ObjectFileELF); +LLDB_PLUGIN_DECLARE(ObjectFileMachO); +LLDB_PLUGIN_DECLARE(ObjectFilePECOFF); +LLDB_PLUGIN_DECLARE(ObjectFileWasm); +LLDB_PLUGIN_DECLARE(ObjectContainerBSDArchive); +LLDB_PLUGIN_DECLARE(ObjectContainerUniversalMachO); +LLDB_PLUGIN_DECLARE(ScriptInterpreterNone); #if LLDB_ENABLE_PYTHON LLDB_PLUGIN_DECLARE(OperatingSystemPython) LLDB_PLUGIN_DECLARE(ScriptInterpreterPython) @@ -120,26 +113,14 @@ SystemInitializerFull::SystemInitializerFull() {} SystemInitializerFull::~SystemInitializerFull() {} -#define LLDB_PROCESS_AArch64(op) \ - op(ABIMacOSX_arm64); \ - op(ABISysV_arm64); -#define LLDB_PROCESS_ARM(op) \ - op(ABIMacOSX_arm); \ - op(ABISysV_arm); +#define LLDB_PROCESS_AArch64(op) op(ABIAArch64); +#define LLDB_PROCESS_ARM(op) op(ABIARM); #define LLDB_PROCESS_ARC(op) op(ABISysV_arc); #define LLDB_PROCESS_Hexagon(op) op(ABISysV_hexagon); -#define LLDB_PROCESS_Mips(op) \ - op(ABISysV_mips); \ - op(ABISysV_mips64); -#define LLDB_PROCESS_PowerPC(op) \ - op(ABISysV_ppc); \ - op(ABISysV_ppc64); +#define LLDB_PROCESS_Mips(op) op(ABIMips); +#define LLDB_PROCESS_PowerPC(op) op(ABIPowerPC); #define LLDB_PROCESS_SystemZ(op) op(ABISysV_s390x); -#define LLDB_PROCESS_X86(op) \ - op(ABIMacOSX_i386); \ - op(ABISysV_i386); \ - op(ABISysV_x86_64); \ - op(ABIWindows_x86_64); +#define LLDB_PROCESS_X86(op) op(ABIX86); #define LLDB_PROCESS_AMDGPU(op) #define LLDB_PROCESS_AVR(op) diff --git a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp new file mode 100644 index 0000000000000..f37bc1d235897 --- /dev/null +++ b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp @@ -0,0 +1,24 @@ +//===-- AArch64.h ---------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIAArch64.h" +#include "ABIMacOSX_arm64.h" +#include "ABISysV_arm64.h" +#include "lldb/Core/PluginManager.h" + +LLDB_PLUGIN(ABIAArch64) + +void ABIAArch64::Initialize() { + ABISysV_arm64::Initialize(); + ABIMacOSX_arm64::Initialize(); +} + +void ABIAArch64::Terminate() { + ABISysV_arm64::Terminate(); + ABIMacOSX_arm64::Terminate(); +} diff --git a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.h b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.h new file mode 100644 index 0000000000000..90919bec54549 --- /dev/null +++ b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.h @@ -0,0 +1,17 @@ +//===-- AArch64.h -----------------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_ABIAArch64_h_ +#define liblldb_ABIAArch64_h_ + +class ABIAArch64 { +public: + static void Initialize(); + static void Terminate(); +}; +#endif diff --git a/lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp b/lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp index ee38516e30bc4..94f7c2aff641d 100644 --- a/lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp +++ b/lldb/source/Plugins/ABI/AArch64/ABIMacOSX_arm64.cpp @@ -33,8 +33,6 @@ using namespace lldb; using namespace lldb_private; -LLDB_PLUGIN(ABIMacOSX_arm64) - static const char *pluginDesc = "Mac OS X ABI for arm64 targets"; static RegisterInfo g_register_infos[] = { diff --git a/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp b/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp index 606ccbb04287e..96488c1e60257 100644 --- a/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp +++ b/lldb/source/Plugins/ABI/AArch64/ABISysV_arm64.cpp @@ -33,8 +33,6 @@ using namespace lldb; using namespace lldb_private; -LLDB_PLUGIN(ABISysV_arm64) - static RegisterInfo g_register_infos[] = { // NAME ALT SZ OFF ENCODING FORMAT // EH_FRAME DWARF GENERIC diff --git a/lldb/source/Plugins/ABI/AArch64/CMakeLists.txt b/lldb/source/Plugins/ABI/AArch64/CMakeLists.txt index b58a487ee3c23..40db86f092d15 100644 --- a/lldb/source/Plugins/ABI/AArch64/CMakeLists.txt +++ b/lldb/source/Plugins/ABI/AArch64/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_library(lldbPluginABIAArch64 PLUGIN + ABIAArch64.cpp ABIMacOSX_arm64.cpp ABISysV_arm64.cpp diff --git a/lldb/source/Plugins/ABI/ARM/ABIARM.cpp b/lldb/source/Plugins/ABI/ARM/ABIARM.cpp new file mode 100644 index 0000000000000..790cb877b91e2 --- /dev/null +++ b/lldb/source/Plugins/ABI/ARM/ABIARM.cpp @@ -0,0 +1,24 @@ +//===-- ARM.h -------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIARM.h" +#include "ABIMacOSX_arm.h" +#include "ABISysV_arm.h" +#include "lldb/Core/PluginManager.h" + +LLDB_PLUGIN(ABIARM) + +void ABIARM::Initialize() { + ABISysV_arm::Initialize(); + ABIMacOSX_arm::Initialize(); +} + +void ABIARM::Terminate() { + ABISysV_arm::Terminate(); + ABIMacOSX_arm::Terminate(); +} diff --git a/lldb/source/Plugins/ABI/ARM/ABIARM.h b/lldb/source/Plugins/ABI/ARM/ABIARM.h new file mode 100644 index 0000000000000..3ebc7b6f6f535 --- /dev/null +++ b/lldb/source/Plugins/ABI/ARM/ABIARM.h @@ -0,0 +1,17 @@ +//===-- ARM.h -------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_ABIARM_h_ +#define liblldb_ABIARM_h_ + +class ABIARM { +public: + static void Initialize(); + static void Terminate(); +}; +#endif diff --git a/lldb/source/Plugins/ABI/ARM/CMakeLists.txt b/lldb/source/Plugins/ABI/ARM/CMakeLists.txt index 87c74b6b217a7..0082296e5ad12 100644 --- a/lldb/source/Plugins/ABI/ARM/CMakeLists.txt +++ b/lldb/source/Plugins/ABI/ARM/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_library(lldbPluginABIARM PLUGIN + ABIARM.cpp ABIMacOSX_arm.cpp ABISysV_arm.cpp diff --git a/lldb/source/Plugins/ABI/Mips/ABIMips.cpp b/lldb/source/Plugins/ABI/Mips/ABIMips.cpp new file mode 100644 index 0000000000000..08e694a659b41 --- /dev/null +++ b/lldb/source/Plugins/ABI/Mips/ABIMips.cpp @@ -0,0 +1,24 @@ +//===-- Mips.h ------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIMips.h" +#include "ABISysV_mips.h" +#include "ABISysV_mips64.h" +#include "lldb/Core/PluginManager.h" + +LLDB_PLUGIN(ABIMips) + +void ABIMips::Initialize() { + ABISysV_mips::Initialize(); + ABISysV_mips64::Initialize(); +} + +void ABIMips::Terminate() { + ABISysV_mips::Terminate(); + ABISysV_mips64::Terminate(); +} diff --git a/lldb/source/Plugins/ABI/Mips/ABIMips.h b/lldb/source/Plugins/ABI/Mips/ABIMips.h new file mode 100644 index 0000000000000..92cd713ce2d68 --- /dev/null +++ b/lldb/source/Plugins/ABI/Mips/ABIMips.h @@ -0,0 +1,17 @@ +//===-- Mips.h -----------------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_ABIMips_h_ +#define liblldb_ABIMips_h_ + +class ABIMips { +public: + static void Initialize(); + static void Terminate(); +}; +#endif diff --git a/lldb/source/Plugins/ABI/Mips/CMakeLists.txt b/lldb/source/Plugins/ABI/Mips/CMakeLists.txt index 7636cee6e19da..9c3b18a78dad1 100644 --- a/lldb/source/Plugins/ABI/Mips/CMakeLists.txt +++ b/lldb/source/Plugins/ABI/Mips/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_library(lldbPluginABIMips PLUGIN + ABIMips.cpp ABISysV_mips.cpp ABISysV_mips64.cpp diff --git a/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.cpp b/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.cpp new file mode 100644 index 0000000000000..b1591dba6a1bb --- /dev/null +++ b/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.cpp @@ -0,0 +1,24 @@ +//===-- PowerPC.h ---------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIPowerPC.h" +#include "ABISysV_ppc.h" +#include "ABISysV_ppc64.h" +#include "lldb/Core/PluginManager.h" + +LLDB_PLUGIN(ABIPowerPC) + +void ABIPowerPC::Initialize() { + ABISysV_ppc::Initialize(); + ABISysV_ppc64::Initialize(); +} + +void ABIPowerPC::Terminate() { + ABISysV_ppc::Terminate(); + ABISysV_ppc64::Terminate(); +} diff --git a/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.h b/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.h new file mode 100644 index 0000000000000..becbdcd75beed --- /dev/null +++ b/lldb/source/Plugins/ABI/PowerPC/ABIPowerPC.h @@ -0,0 +1,17 @@ +//===-- PowerPC.h -----------------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_ABIPowerPC_h_ +#define liblldb_ABIPowerPC_h_ + +class ABIPowerPC { +public: + static void Initialize(); + static void Terminate(); +}; +#endif diff --git a/lldb/source/Plugins/ABI/PowerPC/CMakeLists.txt b/lldb/source/Plugins/ABI/PowerPC/CMakeLists.txt index 53c663ff48aef..57d8e59a6d5b7 100644 --- a/lldb/source/Plugins/ABI/PowerPC/CMakeLists.txt +++ b/lldb/source/Plugins/ABI/PowerPC/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_library(lldbPluginABIPowerPC PLUGIN + ABIPowerPC.cpp ABISysV_ppc.cpp ABISysV_ppc64.cpp diff --git a/lldb/source/Plugins/ABI/X86/ABIX86.cpp b/lldb/source/Plugins/ABI/X86/ABIX86.cpp new file mode 100644 index 0000000000000..207d0b289d67f --- /dev/null +++ b/lldb/source/Plugins/ABI/X86/ABIX86.cpp @@ -0,0 +1,30 @@ +//===-- X86.h -------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ABIX86.h" +#include "ABIMacOSX_i386.h" +#include "ABISysV_i386.h" +#include "ABISysV_x86_64.h" +#include "ABIWindows_x86_64.h" +#include "lldb/Core/PluginManager.h" + +LLDB_PLUGIN(ABIX86) + +void ABIX86::Initialize() { + ABIMacOSX_i386::Initialize(); + ABISysV_i386::Initialize(); + ABISysV_x86_64::Initialize(); + ABIWindows_x86_64::Initialize(); +} + +void ABIX86::Terminate() { + ABIMacOSX_i386::Terminate(); + ABISysV_i386::Terminate(); + ABISysV_x86_64::Terminate(); + ABIWindows_x86_64::Terminate(); +} diff --git a/lldb/source/Plugins/ABI/X86/ABIX86.h b/lldb/source/Plugins/ABI/X86/ABIX86.h new file mode 100644 index 0000000000000..f99bb0cb0b185 --- /dev/null +++ b/lldb/source/Plugins/ABI/X86/ABIX86.h @@ -0,0 +1,17 @@ +//===-- X86.h ---------------------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef liblldb_ABIX86_h_ +#define liblldb_ABIX86_h_ + +class ABIX86 { +public: + static void Initialize(); + static void Terminate(); +}; +#endif diff --git a/lldb/source/Plugins/ABI/X86/CMakeLists.txt b/lldb/source/Plugins/ABI/X86/CMakeLists.txt index 757abbbd173cf..ec8ed622549ba 100644 --- a/lldb/source/Plugins/ABI/X86/CMakeLists.txt +++ b/lldb/source/Plugins/ABI/X86/CMakeLists.txt @@ -1,4 +1,5 @@ add_lldb_library(lldbPluginABIX86 PLUGIN + ABIX86.cpp ABIMacOSX_i386.cpp ABISysV_i386.cpp ABISysV_x86_64.cpp diff --git a/lldb/tools/lldb-test/SystemInitializerTest.cpp b/lldb/tools/lldb-test/SystemInitializerTest.cpp index 3e82b8cbf1b02..92b4a468d81cf 100644 --- a/lldb/tools/lldb-test/SystemInitializerTest.cpp +++ b/lldb/tools/lldb-test/SystemInitializerTest.cpp @@ -17,21 +17,14 @@ #include -LLDB_PLUGIN_DECLARE(ABIMacOSX_arm64) -LLDB_PLUGIN_DECLARE(ABISysV_arm64) -LLDB_PLUGIN_DECLARE(ABIMacOSX_arm) -LLDB_PLUGIN_DECLARE(ABISysV_arm) -LLDB_PLUGIN_DECLARE(ABISysV_arc) -LLDB_PLUGIN_DECLARE(ABISysV_hexagon) -LLDB_PLUGIN_DECLARE(ABISysV_mips) -LLDB_PLUGIN_DECLARE(ABISysV_mips64) -LLDB_PLUGIN_DECLARE(ABISysV_ppc) -LLDB_PLUGIN_DECLARE(ABISysV_ppc64) -LLDB_PLUGIN_DECLARE(ABISysV_s390x) -LLDB_PLUGIN_DECLARE(ABIMacOSX_i386) -LLDB_PLUGIN_DECLARE(ABISysV_i386) -LLDB_PLUGIN_DECLARE(ABISysV_x86_64) -LLDB_PLUGIN_DECLARE(ABIWindows_x86_64) +LLDB_PLUGIN_DECLARE(ABIAArch64); +LLDB_PLUGIN_DECLARE(ABIARM); +LLDB_PLUGIN_DECLARE(ABISysV_arc); +LLDB_PLUGIN_DECLARE(ABISysV_hexagon); +LLDB_PLUGIN_DECLARE(ABIMips); +LLDB_PLUGIN_DECLARE(ABIPowerPC); +LLDB_PLUGIN_DECLARE(ABISysV_s390x); +LLDB_PLUGIN_DECLARE(ABIX86); LLDB_PLUGIN_DECLARE(ObjectFileBreakpad) LLDB_PLUGIN_DECLARE(ObjectFileELF) LLDB_PLUGIN_DECLARE(ObjectFileMachO) @@ -106,25 +99,13 @@ SystemInitializerTest::SystemInitializerTest() {} SystemInitializerTest::~SystemInitializerTest() {} -#define LLDB_PROCESS_AArch64(op) \ - op(ABIMacOSX_arm64); \ - op(ABISysV_arm64); -#define LLDB_PROCESS_ARM(op) \ - op(ABIMacOSX_arm); \ - op(ABISysV_arm); +#define LLDB_PROCESS_AArch64(op) op(ABIAArch64); +#define LLDB_PROCESS_ARM(op) op(ABIARM); #define LLDB_PROCESS_Hexagon(op) op(ABISysV_hexagon); -#define LLDB_PROCESS_Mips(op) \ - op(ABISysV_mips); \ - op(ABISysV_mips64); -#define LLDB_PROCESS_PowerPC(op) \ - op(ABISysV_ppc); \ - op(ABISysV_ppc64); +#define LLDB_PROCESS_Mips(op) op(ABIMips); +#define LLDB_PROCESS_PowerPC(op) op(ABIPowerPC); #define LLDB_PROCESS_SystemZ(op) op(ABISysV_s390x); -#define LLDB_PROCESS_X86(op) \ - op(ABIMacOSX_i386); \ - op(ABISysV_i386); \ - op(ABISysV_x86_64); \ - op(ABIWindows_x86_64); +#define LLDB_PROCESS_X86(op) op(ABIX86); #define LLDB_PROCESS_AMDGPU(op) #define LLDB_PROCESS_ARC(op) From 16bf89267e5ac01d2b512ce784f23640a82de821 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Thu, 13 Feb 2020 21:55:41 -0800 Subject: [PATCH 37/57] [lldb/Test] Partially revert assertTrue change This reverts b3a0c4d7dcfa252be17ef5f5b63ffaaa83e01a2b for TestBreakpointHitCount.py because it's now timing out on the Windows bot. I'm not sure this is the cause, but the substitution doesn't look correct anyway... --- .../breakpoint/breakpoint_hit_count/TestBreakpointHitCount.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/test/API/functionalities/breakpoint/breakpoint_hit_count/TestBreakpointHitCount.py b/lldb/test/API/functionalities/breakpoint/breakpoint_hit_count/TestBreakpointHitCount.py index 9f8ac82e7f543..0254bf02366da 100644 --- a/lldb/test/API/functionalities/breakpoint/breakpoint_hit_count/TestBreakpointHitCount.py +++ b/lldb/test/API/functionalities/breakpoint/breakpoint_hit_count/TestBreakpointHitCount.py @@ -41,7 +41,7 @@ def test_breakpoint_one_shot(self): "There should be a thread stopped due to breakpoint") frame0 = thread.GetFrameAtIndex(0) - self.assertEquals(frame0.GetFunctionName(), "a(int)" or frame0.GetFunctionName() == "int a(int)"); + self.assertTrue(frame0.GetFunctionName() == "a(int)" or frame0.GetFunctionName() == "int a(int)"); process.Continue() self.assertEqual(process.GetState(), lldb.eStateExited) From bcd24b2d43bded4959338972cdc4c2c960b0a965 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 13 Feb 2020 21:58:16 -0800 Subject: [PATCH 38/57] [AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI* --- llvm/include/llvm/CodeGen/AsmPrinter.h | 2 +- llvm/include/llvm/MC/MCObjectStreamer.h | 12 +- llvm/include/llvm/MC/MCStreamer.h | 56 +++---- llvm/lib/CodeGen/AsmPrinter/ARMException.cpp | 4 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 8 +- .../CodeGen/AsmPrinter/AsmPrinterDwarf.cpp | 24 +-- .../CodeGen/AsmPrinter/DwarfCFIException.cpp | 12 +- llvm/lib/MC/MCAsmStreamer.cpp | 146 +++++++++--------- llvm/lib/MC/MCDwarf.cpp | 14 +- llvm/lib/MC/MCObjectStreamer.cpp | 18 +-- llvm/lib/MC/MCParser/AsmParser.cpp | 42 ++--- llvm/lib/MC/MCStreamer.cpp | 116 +++++++------- llvm/lib/Object/RecordStreamer.cpp | 4 +- llvm/lib/Object/RecordStreamer.h | 2 +- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 50 +++--- .../AArch64/AsmParser/AArch64AsmParser.cpp | 8 +- .../MCTargetDesc/AArch64ELFStreamer.cpp | 4 +- .../MCTargetDesc/AArch64WinCOFFStreamer.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp | 8 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 2 +- llvm/lib/Target/AMDGPU/R600AsmPrinter.h | 2 +- llvm/lib/Target/ARC/ARCAsmPrinter.cpp | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 4 +- llvm/lib/Target/ARM/ARMAsmPrinter.h | 2 +- .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 +- .../ARM/MCTargetDesc/ARMELFStreamer.cpp | 4 +- llvm/lib/Target/AVR/AVRAsmPrinter.cpp | 4 +- .../lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 2 +- .../lib/Target/BPF/AsmParser/BPFAsmParser.cpp | 2 +- llvm/lib/Target/BPF/BPFAsmPrinter.cpp | 4 +- .../Hexagon/AsmParser/HexagonAsmParser.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonAsmPrinter.h | 2 +- .../MCTargetDesc/HexagonMCELFStreamer.cpp | 4 +- .../MCTargetDesc/HexagonMCELFStreamer.h | 2 +- .../Target/Lanai/AsmParser/LanaiAsmParser.cpp | 2 +- llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp | 14 +- .../MSP430/AsmParser/MSP430AsmParser.cpp | 2 +- llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp | 4 +- .../Target/Mips/AsmParser/MipsAsmParser.cpp | 8 +- .../Mips/MCTargetDesc/MipsELFStreamer.cpp | 10 +- .../Mips/MCTargetDesc/MipsELFStreamer.h | 8 +- .../Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 8 +- .../Mips/MCTargetDesc/MipsMCCodeEmitter.h | 2 +- .../Mips/MCTargetDesc/MipsNaClELFStreamer.cpp | 14 +- .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 20 +-- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 12 +- llvm/lib/Target/Mips/MipsAsmPrinter.h | 2 +- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h | 2 +- .../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 2 +- .../PowerPC/MCTargetDesc/PPCELFStreamer.cpp | 6 +- .../PowerPC/MCTargetDesc/PPCELFStreamer.h | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 12 +- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +- .../Target/Sparc/AsmParser/SparcAsmParser.cpp | 2 +- llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 11 +- .../SystemZ/AsmParser/SystemZAsmParser.cpp | 4 +- llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 22 +-- llvm/lib/Target/SystemZ/SystemZAsmPrinter.h | 2 +- llvm/lib/Target/VE/VEAsmPrinter.cpp | 4 +- .../AsmParser/WebAssemblyAsmParser.cpp | 2 +- .../WebAssembly/WebAssemblyAsmPrinter.cpp | 2 +- .../WebAssembly/WebAssemblyAsmPrinter.h | 2 +- .../lib/Target/X86/AsmParser/X86AsmParser.cpp | 16 +- llvm/lib/Target/X86/X86AsmPrinter.h | 2 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 28 ++-- llvm/lib/Target/XCore/XCoreAsmPrinter.cpp | 4 +- llvm/tools/llvm-exegesis/lib/SnippetFile.cpp | 2 +- llvm/tools/llvm-mc/Disassembler.cpp | 2 +- llvm/tools/llvm-mca/CodeRegionGenerator.cpp | 4 +- llvm/tools/llvm-ml/Disassembler.cpp | 2 +- 74 files changed, 419 insertions(+), 420 deletions(-) diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h index 068f3a36e0616..0d3e1cf33f1f4 100644 --- a/llvm/include/llvm/CodeGen/AsmPrinter.h +++ b/llvm/include/llvm/CodeGen/AsmPrinter.h @@ -430,7 +430,7 @@ class AsmPrinter : public MachineFunctionPass { virtual void emitBasicBlockEnd(const MachineBasicBlock &MBB); /// Targets should implement this to emit instructions. - virtual void EmitInstruction(const MachineInstr *) { + virtual void emitInstruction(const MachineInstr *) { llvm_unreachable("EmitInstruction not implemented"); } diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h index 5c7782326d5a7..4a8bb2f4ce815 100644 --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -50,10 +50,10 @@ class MCObjectStreamer : public MCStreamer { SmallVector PendingFixups; virtual void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo&) = 0; - void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; - void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; - MCSymbol *EmitCFILabel() override; - void EmitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI); + void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *emitCFILabel() override; + void emitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI); void resolvePendingFixups(); protected: @@ -70,7 +70,7 @@ class MCObjectStreamer : public MCStreamer { bool isIntegratedAssemblerRequired() const override { return true; } void EmitFrames(MCAsmBackend *MAB); - void EmitCFISections(bool EH, bool Debug) override; + void emitCFISections(bool EH, bool Debug) override; MCFragment *getCurrentFragment() const; @@ -123,7 +123,7 @@ class MCObjectStreamer : public MCStreamer { void emitSLEB128Value(const MCExpr *Value) override; void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) override; void ChangeSection(MCSection *Section, const MCExpr *Subsection) override; - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; /// Emit an instruction to a special fragment, because this instruction /// can change its size during relaxation. diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h index 4749671ce163f..f74a4fdbdf777 100644 --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -233,8 +233,8 @@ class MCStreamer { protected: MCStreamer(MCContext &Ctx); - virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame); - virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame); + virtual void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame); + virtual void emitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame); WinEH::FrameInfo *getCurrentWinFrameInfo() { return CurrentWinFrameInfo; @@ -279,7 +279,7 @@ class MCStreamer { /// When emitting an object file, create and emit a real label. When emitting /// textual assembly, this should do nothing to avoid polluting our output. - virtual MCSymbol *EmitCFILabel(); + virtual MCSymbol *emitCFILabel(); /// Retreive the current frame info if one is available and it is not yet /// closed. Otherwise, issue an error and return null. @@ -847,7 +847,7 @@ class MCStreamer { Optional Source, unsigned CUID = 0); - virtual void EmitCFIBKeyFrame(); + virtual void emitCFIBKeyFrame(); /// This implements the DWARF2 '.loc fileno lineno ...' assembler /// directive. @@ -937,29 +937,29 @@ class MCStreamer { const MCSymbol *Lo); virtual MCSymbol *getDwarfLineTableSymbol(unsigned CUID); - virtual void EmitCFISections(bool EH, bool Debug); - void EmitCFIStartProc(bool IsSimple, SMLoc Loc = SMLoc()); - void EmitCFIEndProc(); - virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset); - virtual void EmitCFIDefCfaOffset(int64_t Offset); - virtual void EmitCFIDefCfaRegister(int64_t Register); - virtual void EmitCFIOffset(int64_t Register, int64_t Offset); - virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding); - virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding); - virtual void EmitCFIRememberState(); - virtual void EmitCFIRestoreState(); - virtual void EmitCFISameValue(int64_t Register); - virtual void EmitCFIRestore(int64_t Register); - virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); - virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); - virtual void EmitCFIEscape(StringRef Values); - virtual void EmitCFIReturnColumn(int64_t Register); - virtual void EmitCFIGnuArgsSize(int64_t Size); - virtual void EmitCFISignalFrame(); - virtual void EmitCFIUndefined(int64_t Register); - virtual void EmitCFIRegister(int64_t Register1, int64_t Register2); - virtual void EmitCFIWindowSave(); - virtual void EmitCFINegateRAState(); + virtual void emitCFISections(bool EH, bool Debug); + void emitCFIStartProc(bool IsSimple, SMLoc Loc = SMLoc()); + void emitCFIEndProc(); + virtual void emitCFIDefCfa(int64_t Register, int64_t Offset); + virtual void emitCFIDefCfaOffset(int64_t Offset); + virtual void emitCFIDefCfaRegister(int64_t Register); + virtual void emitCFIOffset(int64_t Register, int64_t Offset); + virtual void emitCFIPersonality(const MCSymbol *Sym, unsigned Encoding); + virtual void emitCFILsda(const MCSymbol *Sym, unsigned Encoding); + virtual void emitCFIRememberState(); + virtual void emitCFIRestoreState(); + virtual void emitCFISameValue(int64_t Register); + virtual void emitCFIRestore(int64_t Register); + virtual void emitCFIRelOffset(int64_t Register, int64_t Offset); + virtual void emitCFIAdjustCfaOffset(int64_t Adjustment); + virtual void emitCFIEscape(StringRef Values); + virtual void emitCFIReturnColumn(int64_t Register); + virtual void emitCFIGnuArgsSize(int64_t Size); + virtual void emitCFISignalFrame(); + virtual void emitCFIUndefined(int64_t Register); + virtual void emitCFIRegister(int64_t Register1, int64_t Register2); + virtual void emitCFIWindowSave(); + virtual void emitCFINegateRAState(); virtual void EmitWinCFIStartProc(const MCSymbol *Symbol, SMLoc Loc = SMLoc()); virtual void EmitWinCFIEndProc(SMLoc Loc = SMLoc()); @@ -1010,7 +1010,7 @@ class MCStreamer { virtual void EmitAddrsigSym(const MCSymbol *Sym) {} /// Emit the given \p Instruction into the current section. - virtual void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI); + virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI); /// Set the bundle alignment mode from now on in the section. /// The argument is the power of 2 to which the alignment is set. The diff --git a/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp b/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp index c17994cfaad9a..dcf62b20b00c6 100644 --- a/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/ARMException.cpp @@ -46,12 +46,12 @@ void ARMException::beginFunction(const MachineFunction *MF) { if (MoveType == AsmPrinter::CFI_M_Debug) { if (!hasEmittedCFISections) { if (Asm->needsOnlyDebugCFIMoves()) - Asm->OutStreamer->EmitCFISections(false, true); + Asm->OutStreamer->emitCFISections(false, true); hasEmittedCFISections = true; } shouldEmitCFI = true; - Asm->OutStreamer->EmitCFIStartProc(false); + Asm->OutStreamer->emitCFIStartProc(false); } } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 321c90d4d6471..38fbac264430f 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -231,7 +231,7 @@ const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const { } void AsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { - S.EmitInstruction(Inst, getSubtargetInfo()); + S.emitInstruction(Inst, getSubtargetInfo()); } void AsmPrinter::emitInitialRawDwarfLocDirective(const MachineFunction &MF) { @@ -1141,13 +1141,13 @@ void AsmPrinter::emitFunctionBody() { case TargetOpcode::DBG_VALUE: if (isVerbose()) { if (!emitDebugValueComment(&MI, *this)) - EmitInstruction(&MI); + emitInstruction(&MI); } break; case TargetOpcode::DBG_LABEL: if (isVerbose()) { if (!emitDebugLabelComment(&MI, *this)) - EmitInstruction(&MI); + emitInstruction(&MI); } break; case TargetOpcode::IMPLICIT_DEF: @@ -1157,7 +1157,7 @@ void AsmPrinter::emitFunctionBody() { if (isVerbose()) emitKill(&MI, *this); break; default: - EmitInstruction(&MI); + emitInstruction(&MI); break; } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp index 4d66f06b5b8bb..0fbd7da3c1c83 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp @@ -210,40 +210,40 @@ void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const { default: llvm_unreachable("Unexpected instruction"); case MCCFIInstruction::OpDefCfaOffset: - OutStreamer->EmitCFIDefCfaOffset(Inst.getOffset()); + OutStreamer->emitCFIDefCfaOffset(Inst.getOffset()); break; case MCCFIInstruction::OpAdjustCfaOffset: - OutStreamer->EmitCFIAdjustCfaOffset(Inst.getOffset()); + OutStreamer->emitCFIAdjustCfaOffset(Inst.getOffset()); break; case MCCFIInstruction::OpDefCfa: - OutStreamer->EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset()); + OutStreamer->emitCFIDefCfa(Inst.getRegister(), Inst.getOffset()); break; case MCCFIInstruction::OpDefCfaRegister: - OutStreamer->EmitCFIDefCfaRegister(Inst.getRegister()); + OutStreamer->emitCFIDefCfaRegister(Inst.getRegister()); break; case MCCFIInstruction::OpOffset: - OutStreamer->EmitCFIOffset(Inst.getRegister(), Inst.getOffset()); + OutStreamer->emitCFIOffset(Inst.getRegister(), Inst.getOffset()); break; case MCCFIInstruction::OpRegister: - OutStreamer->EmitCFIRegister(Inst.getRegister(), Inst.getRegister2()); + OutStreamer->emitCFIRegister(Inst.getRegister(), Inst.getRegister2()); break; case MCCFIInstruction::OpWindowSave: - OutStreamer->EmitCFIWindowSave(); + OutStreamer->emitCFIWindowSave(); break; case MCCFIInstruction::OpNegateRAState: - OutStreamer->EmitCFINegateRAState(); + OutStreamer->emitCFINegateRAState(); break; case MCCFIInstruction::OpSameValue: - OutStreamer->EmitCFISameValue(Inst.getRegister()); + OutStreamer->emitCFISameValue(Inst.getRegister()); break; case MCCFIInstruction::OpGnuArgsSize: - OutStreamer->EmitCFIGnuArgsSize(Inst.getOffset()); + OutStreamer->emitCFIGnuArgsSize(Inst.getOffset()); break; case MCCFIInstruction::OpEscape: - OutStreamer->EmitCFIEscape(Inst.getValues()); + OutStreamer->emitCFIEscape(Inst.getValues()); break; case MCCFIInstruction::OpRestore: - OutStreamer->EmitCFIRestore(Inst.getRegister()); + OutStreamer->emitCFIRestore(Inst.getRegister()); break; } } diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp index facbf22946e4a..3245ecdbcc880 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp @@ -48,7 +48,7 @@ void DwarfCFIExceptionBase::markFunctionEnd() { void DwarfCFIExceptionBase::endFragment() { if (shouldEmitCFI) - Asm->OutStreamer->EmitCFIEndProc(); + Asm->OutStreamer->emitCFIEndProc(); } DwarfCFIException::DwarfCFIException(AsmPrinter *A) @@ -133,13 +133,13 @@ void DwarfCFIException::beginFragment(const MachineBasicBlock *MBB, if (!hasEmittedCFISections) { if (Asm->needsOnlyDebugCFIMoves()) - Asm->OutStreamer->EmitCFISections(false, true); + Asm->OutStreamer->emitCFISections(false, true); else if (Asm->TM.Options.ForceDwarfFrameSection) - Asm->OutStreamer->EmitCFISections(true, true); + Asm->OutStreamer->emitCFISections(true, true); hasEmittedCFISections = true; } - Asm->OutStreamer->EmitCFIStartProc(/*IsSimple=*/false); + Asm->OutStreamer->emitCFIStartProc(/*IsSimple=*/false); // Indicate personality routine, if any. if (!shouldEmitPersonality) @@ -157,11 +157,11 @@ void DwarfCFIException::beginFragment(const MachineBasicBlock *MBB, const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering(); unsigned PerEncoding = TLOF.getPersonalityEncoding(); const MCSymbol *Sym = TLOF.getCFIPersonalitySymbol(P, Asm->TM, MMI); - Asm->OutStreamer->EmitCFIPersonality(Sym, PerEncoding); + Asm->OutStreamer->emitCFIPersonality(Sym, PerEncoding); // Provide LSDA information. if (shouldEmitLSDA) - Asm->OutStreamer->EmitCFILsda(ESP(Asm), TLOF.getLSDAEncoding()); + Asm->OutStreamer->emitCFILsda(ESP(Asm), TLOF.getLSDAEncoding()); } /// endFunction - Gather and emit post-function exception information. diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index c2d180813989d..b783bcd355a31 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -58,8 +58,8 @@ class MCAsmStreamer final : public MCStreamer { unsigned UseDwarfDirectory : 1; void EmitRegisterName(int64_t Register); - void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; - void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; public: MCAsmStreamer(MCContext &Context, std::unique_ptr os, @@ -288,28 +288,28 @@ class MCAsmStreamer final : public MCStreamer { void EmitCVFPOData(const MCSymbol *ProcSym, SMLoc L) override; void EmitIdent(StringRef IdentString) override; - void EmitCFIBKeyFrame() override; - void EmitCFISections(bool EH, bool Debug) override; - void EmitCFIDefCfa(int64_t Register, int64_t Offset) override; - void EmitCFIDefCfaOffset(int64_t Offset) override; - void EmitCFIDefCfaRegister(int64_t Register) override; - void EmitCFIOffset(int64_t Register, int64_t Offset) override; - void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) override; - void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding) override; - void EmitCFIRememberState() override; - void EmitCFIRestoreState() override; - void EmitCFIRestore(int64_t Register) override; - void EmitCFISameValue(int64_t Register) override; - void EmitCFIRelOffset(int64_t Register, int64_t Offset) override; - void EmitCFIAdjustCfaOffset(int64_t Adjustment) override; - void EmitCFIEscape(StringRef Values) override; - void EmitCFIGnuArgsSize(int64_t Size) override; - void EmitCFISignalFrame() override; - void EmitCFIUndefined(int64_t Register) override; - void EmitCFIRegister(int64_t Register1, int64_t Register2) override; - void EmitCFIWindowSave() override; - void EmitCFINegateRAState() override; - void EmitCFIReturnColumn(int64_t Register) override; + void emitCFIBKeyFrame() override; + void emitCFISections(bool EH, bool Debug) override; + void emitCFIDefCfa(int64_t Register, int64_t Offset) override; + void emitCFIDefCfaOffset(int64_t Offset) override; + void emitCFIDefCfaRegister(int64_t Register) override; + void emitCFIOffset(int64_t Register, int64_t Offset) override; + void emitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) override; + void emitCFILsda(const MCSymbol *Sym, unsigned Encoding) override; + void emitCFIRememberState() override; + void emitCFIRestoreState() override; + void emitCFIRestore(int64_t Register) override; + void emitCFISameValue(int64_t Register) override; + void emitCFIRelOffset(int64_t Register, int64_t Offset) override; + void emitCFIAdjustCfaOffset(int64_t Adjustment) override; + void emitCFIEscape(StringRef Values) override; + void emitCFIGnuArgsSize(int64_t Size) override; + void emitCFISignalFrame() override; + void emitCFIUndefined(int64_t Register) override; + void emitCFIRegister(int64_t Register1, int64_t Register2) override; + void emitCFIWindowSave() override; + void emitCFINegateRAState() override; + void emitCFIReturnColumn(int64_t Register) override; void EmitWinCFIStartProc(const MCSymbol *Symbol, SMLoc Loc) override; void EmitWinCFIEndProc(SMLoc Loc) override; @@ -334,7 +334,7 @@ class MCAsmStreamer final : public MCStreamer { void emitCGProfileEntry(const MCSymbolRefExpr *From, const MCSymbolRefExpr *To, uint64_t Count) override; - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; void EmitBundleAlignMode(unsigned AlignPow2) override; void EmitBundleLock(bool AlignToEnd) override; @@ -1523,8 +1523,8 @@ void MCAsmStreamer::EmitIdent(StringRef IdentString) { EmitEOL(); } -void MCAsmStreamer::EmitCFISections(bool EH, bool Debug) { - MCStreamer::EmitCFISections(EH, Debug); +void MCAsmStreamer::emitCFISections(bool EH, bool Debug) { + MCStreamer::emitCFISections(EH, Debug); OS << "\t.cfi_sections "; if (EH) { OS << ".eh_frame"; @@ -1537,15 +1537,15 @@ void MCAsmStreamer::EmitCFISections(bool EH, bool Debug) { EmitEOL(); } -void MCAsmStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MCAsmStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { OS << "\t.cfi_startproc"; if (Frame.IsSimple) OS << " simple"; EmitEOL(); } -void MCAsmStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { - MCStreamer::EmitCFIEndProcImpl(Frame); +void MCAsmStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { + MCStreamer::emitCFIEndProcImpl(Frame); OS << "\t.cfi_endproc"; EmitEOL(); } @@ -1564,16 +1564,16 @@ void MCAsmStreamer::EmitRegisterName(int64_t Register) { OS << Register; } -void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { - MCStreamer::EmitCFIDefCfa(Register, Offset); +void MCAsmStreamer::emitCFIDefCfa(int64_t Register, int64_t Offset) { + MCStreamer::emitCFIDefCfa(Register, Offset); OS << "\t.cfi_def_cfa "; EmitRegisterName(Register); OS << ", " << Offset; EmitEOL(); } -void MCAsmStreamer::EmitCFIDefCfaOffset(int64_t Offset) { - MCStreamer::EmitCFIDefCfaOffset(Offset); +void MCAsmStreamer::emitCFIDefCfaOffset(int64_t Offset) { + MCStreamer::emitCFIDefCfaOffset(Offset); OS << "\t.cfi_def_cfa_offset " << Offset; EmitEOL(); } @@ -1588,14 +1588,14 @@ static void PrintCFIEscape(llvm::formatted_raw_ostream &OS, StringRef Values) { } } -void MCAsmStreamer::EmitCFIEscape(StringRef Values) { - MCStreamer::EmitCFIEscape(Values); +void MCAsmStreamer::emitCFIEscape(StringRef Values) { + MCStreamer::emitCFIEscape(Values); PrintCFIEscape(OS, Values); EmitEOL(); } -void MCAsmStreamer::EmitCFIGnuArgsSize(int64_t Size) { - MCStreamer::EmitCFIGnuArgsSize(Size); +void MCAsmStreamer::emitCFIGnuArgsSize(int64_t Size) { + MCStreamer::emitCFIGnuArgsSize(Size); uint8_t Buffer[16] = { dwarf::DW_CFA_GNU_args_size }; unsigned Len = encodeULEB128(Size, Buffer + 1) + 1; @@ -1604,114 +1604,114 @@ void MCAsmStreamer::EmitCFIGnuArgsSize(int64_t Size) { EmitEOL(); } -void MCAsmStreamer::EmitCFIDefCfaRegister(int64_t Register) { - MCStreamer::EmitCFIDefCfaRegister(Register); +void MCAsmStreamer::emitCFIDefCfaRegister(int64_t Register) { + MCStreamer::emitCFIDefCfaRegister(Register); OS << "\t.cfi_def_cfa_register "; EmitRegisterName(Register); EmitEOL(); } -void MCAsmStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) { - this->MCStreamer::EmitCFIOffset(Register, Offset); +void MCAsmStreamer::emitCFIOffset(int64_t Register, int64_t Offset) { + this->MCStreamer::emitCFIOffset(Register, Offset); OS << "\t.cfi_offset "; EmitRegisterName(Register); OS << ", " << Offset; EmitEOL(); } -void MCAsmStreamer::EmitCFIPersonality(const MCSymbol *Sym, +void MCAsmStreamer::emitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) { - MCStreamer::EmitCFIPersonality(Sym, Encoding); + MCStreamer::emitCFIPersonality(Sym, Encoding); OS << "\t.cfi_personality " << Encoding << ", "; Sym->print(OS, MAI); EmitEOL(); } -void MCAsmStreamer::EmitCFILsda(const MCSymbol *Sym, unsigned Encoding) { - MCStreamer::EmitCFILsda(Sym, Encoding); +void MCAsmStreamer::emitCFILsda(const MCSymbol *Sym, unsigned Encoding) { + MCStreamer::emitCFILsda(Sym, Encoding); OS << "\t.cfi_lsda " << Encoding << ", "; Sym->print(OS, MAI); EmitEOL(); } -void MCAsmStreamer::EmitCFIRememberState() { - MCStreamer::EmitCFIRememberState(); +void MCAsmStreamer::emitCFIRememberState() { + MCStreamer::emitCFIRememberState(); OS << "\t.cfi_remember_state"; EmitEOL(); } -void MCAsmStreamer::EmitCFIRestoreState() { - MCStreamer::EmitCFIRestoreState(); +void MCAsmStreamer::emitCFIRestoreState() { + MCStreamer::emitCFIRestoreState(); OS << "\t.cfi_restore_state"; EmitEOL(); } -void MCAsmStreamer::EmitCFIRestore(int64_t Register) { - MCStreamer::EmitCFIRestore(Register); +void MCAsmStreamer::emitCFIRestore(int64_t Register) { + MCStreamer::emitCFIRestore(Register); OS << "\t.cfi_restore "; EmitRegisterName(Register); EmitEOL(); } -void MCAsmStreamer::EmitCFISameValue(int64_t Register) { - MCStreamer::EmitCFISameValue(Register); +void MCAsmStreamer::emitCFISameValue(int64_t Register) { + MCStreamer::emitCFISameValue(Register); OS << "\t.cfi_same_value "; EmitRegisterName(Register); EmitEOL(); } -void MCAsmStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) { - MCStreamer::EmitCFIRelOffset(Register, Offset); +void MCAsmStreamer::emitCFIRelOffset(int64_t Register, int64_t Offset) { + MCStreamer::emitCFIRelOffset(Register, Offset); OS << "\t.cfi_rel_offset "; EmitRegisterName(Register); OS << ", " << Offset; EmitEOL(); } -void MCAsmStreamer::EmitCFIAdjustCfaOffset(int64_t Adjustment) { - MCStreamer::EmitCFIAdjustCfaOffset(Adjustment); +void MCAsmStreamer::emitCFIAdjustCfaOffset(int64_t Adjustment) { + MCStreamer::emitCFIAdjustCfaOffset(Adjustment); OS << "\t.cfi_adjust_cfa_offset " << Adjustment; EmitEOL(); } -void MCAsmStreamer::EmitCFISignalFrame() { - MCStreamer::EmitCFISignalFrame(); +void MCAsmStreamer::emitCFISignalFrame() { + MCStreamer::emitCFISignalFrame(); OS << "\t.cfi_signal_frame"; EmitEOL(); } -void MCAsmStreamer::EmitCFIUndefined(int64_t Register) { - MCStreamer::EmitCFIUndefined(Register); +void MCAsmStreamer::emitCFIUndefined(int64_t Register) { + MCStreamer::emitCFIUndefined(Register); OS << "\t.cfi_undefined " << Register; EmitEOL(); } -void MCAsmStreamer::EmitCFIRegister(int64_t Register1, int64_t Register2) { - MCStreamer::EmitCFIRegister(Register1, Register2); +void MCAsmStreamer::emitCFIRegister(int64_t Register1, int64_t Register2) { + MCStreamer::emitCFIRegister(Register1, Register2); OS << "\t.cfi_register " << Register1 << ", " << Register2; EmitEOL(); } -void MCAsmStreamer::EmitCFIWindowSave() { - MCStreamer::EmitCFIWindowSave(); +void MCAsmStreamer::emitCFIWindowSave() { + MCStreamer::emitCFIWindowSave(); OS << "\t.cfi_window_save"; EmitEOL(); } -void MCAsmStreamer::EmitCFINegateRAState() { - MCStreamer::EmitCFINegateRAState(); +void MCAsmStreamer::emitCFINegateRAState() { + MCStreamer::emitCFINegateRAState(); OS << "\t.cfi_negate_ra_state"; EmitEOL(); } -void MCAsmStreamer::EmitCFIReturnColumn(int64_t Register) { - MCStreamer::EmitCFIReturnColumn(Register); +void MCAsmStreamer::emitCFIReturnColumn(int64_t Register) { + MCStreamer::emitCFIReturnColumn(Register); OS << "\t.cfi_return_column " << Register; EmitEOL(); } -void MCAsmStreamer::EmitCFIBKeyFrame() { - MCStreamer::EmitCFIBKeyFrame(); +void MCAsmStreamer::emitCFIBKeyFrame() { + MCStreamer::emitCFIBKeyFrame(); OS << "\t.cfi_b_key_frame"; EmitEOL(); } @@ -1947,7 +1947,7 @@ void MCAsmStreamer::AddEncodingComment(const MCInst &Inst, } } -void MCAsmStreamer::EmitInstruction(const MCInst &Inst, +void MCAsmStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { assert(getCurrentSectionOnly() && "Cannot emit contents before setting section!"); diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp index e53f00a5b4450..9b8b32105c16c 100644 --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1315,9 +1315,9 @@ class FrameEmitterImpl { const MCSymbol &EmitCIE(const MCDwarfFrameInfo &F); void EmitFDE(const MCSymbol &cieStart, const MCDwarfFrameInfo &frame, bool LastInSection, const MCSymbol &SectionStart); - void EmitCFIInstructions(ArrayRef Instrs, + void emitCFIInstructions(ArrayRef Instrs, MCSymbol *BaseLabel); - void EmitCFIInstruction(const MCCFIInstruction &Instr); + void emitCFIInstruction(const MCCFIInstruction &Instr); }; } // end anonymous namespace @@ -1326,7 +1326,7 @@ static void emitEncodingByte(MCObjectStreamer &Streamer, unsigned Encoding) { Streamer.EmitIntValue(Encoding, 1); } -void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { +void FrameEmitterImpl::emitCFIInstruction(const MCCFIInstruction &Instr) { int dataAlignmentFactor = getDataAlignmentFactor(Streamer); auto *MRI = Streamer.getContext().getRegisterInfo(); @@ -1458,7 +1458,7 @@ void FrameEmitterImpl::EmitCFIInstruction(const MCCFIInstruction &Instr) { } /// Emit frame instructions to describe the layout of the frame. -void FrameEmitterImpl::EmitCFIInstructions(ArrayRef Instrs, +void FrameEmitterImpl::emitCFIInstructions(ArrayRef Instrs, MCSymbol *BaseLabel) { for (const MCCFIInstruction &Instr : Instrs) { MCSymbol *Label = Instr.getLabel(); @@ -1474,7 +1474,7 @@ void FrameEmitterImpl::EmitCFIInstructions(ArrayRef Instrs, } } - EmitCFIInstruction(Instr); + emitCFIInstruction(Instr); } } @@ -1661,7 +1661,7 @@ const MCSymbol &FrameEmitterImpl::EmitCIE(const MCDwarfFrameInfo &Frame) { if (!Frame.IsSimple) { const std::vector &Instructions = MAI->getInitialFrameState(); - EmitCFIInstructions(Instructions, nullptr); + emitCFIInstructions(Instructions, nullptr); } InitialCFAOffset = CFAOffset; @@ -1731,7 +1731,7 @@ void FrameEmitterImpl::EmitFDE(const MCSymbol &cieStart, } // Call Frame Instructions - EmitCFIInstructions(frame.Instructions, frame.Begin); + emitCFIInstructions(frame.Instructions, frame.Begin); // Padding // The size of a .eh_frame section has to be a multiple of the alignment diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index 29ccfee8fc484..f9b8733b0dde7 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -219,8 +219,8 @@ void MCObjectStreamer::visitUsedSymbol(const MCSymbol &Sym) { Assembler->registerSymbol(Sym); } -void MCObjectStreamer::EmitCFISections(bool EH, bool Debug) { - MCStreamer::EmitCFISections(EH, Debug); +void MCObjectStreamer::emitCFISections(bool EH, bool Debug) { + MCStreamer::emitCFISections(EH, Debug); EmitEHFrame = EH; EmitDebugFrame = Debug; } @@ -250,19 +250,19 @@ void MCObjectStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, DF->getContents().resize(DF->getContents().size() + Size, 0); } -MCSymbol *MCObjectStreamer::EmitCFILabel() { +MCSymbol *MCObjectStreamer::emitCFILabel() { MCSymbol *Label = getContext().createTempSymbol("cfi", true); EmitLabel(Label); return Label; } -void MCObjectStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MCObjectStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { // We need to create a local symbol to avoid relocations. Frame.Begin = getContext().createTempSymbol(); EmitLabel(Frame.Begin); } -void MCObjectStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { +void MCObjectStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { Frame.End = getContext().createTempSymbol(); EmitLabel(Frame.End); } @@ -365,16 +365,16 @@ bool MCObjectStreamer::mayHaveInstructions(MCSection &Sec) const { return Sec.hasInstructions(); } -void MCObjectStreamer::EmitInstruction(const MCInst &Inst, +void MCObjectStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { getAssembler().getBackend().alignBranchesBegin(*this, Inst); - EmitInstructionImpl(Inst, STI); + emitInstructionImpl(Inst, STI); getAssembler().getBackend().alignBranchesEnd(*this, Inst); } -void MCObjectStreamer::EmitInstructionImpl(const MCInst &Inst, +void MCObjectStreamer::emitInstructionImpl(const MCInst &Inst, const MCSubtargetInfo &STI) { - MCStreamer::EmitInstruction(Inst, STI); + MCStreamer::emitInstruction(Inst, STI); MCSection *Sec = getCurrentSectionOnly(); Sec->setHasInstructions(true); diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index 81ddbc8f7fe0c..048f971bab030 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -4050,7 +4050,7 @@ bool AsmParser::parseDirectiveCFISections() { Debug = true; } - getStreamer().EmitCFISections(EH, Debug); + getStreamer().emitCFISections(EH, Debug); return false; } @@ -4070,14 +4070,14 @@ bool AsmParser::parseDirectiveCFIStartProc() { // expansion which can *ONLY* happen if Clang's cc1as is the API consumer. // Tools like llvm-mc on the other hand are not affected by it, and report // correct context information. - getStreamer().EmitCFIStartProc(!Simple.empty(), Lexer.getLoc()); + getStreamer().emitCFIStartProc(!Simple.empty(), Lexer.getLoc()); return false; } /// parseDirectiveCFIEndProc /// ::= .cfi_endproc bool AsmParser::parseDirectiveCFIEndProc() { - getStreamer().EmitCFIEndProc(); + getStreamer().emitCFIEndProc(); return false; } @@ -4105,7 +4105,7 @@ bool AsmParser::parseDirectiveCFIDefCfa(SMLoc DirectiveLoc) { parseAbsoluteExpression(Offset)) return true; - getStreamer().EmitCFIDefCfa(Register, Offset); + getStreamer().emitCFIDefCfa(Register, Offset); return false; } @@ -4116,7 +4116,7 @@ bool AsmParser::parseDirectiveCFIDefCfaOffset() { if (parseAbsoluteExpression(Offset)) return true; - getStreamer().EmitCFIDefCfaOffset(Offset); + getStreamer().emitCFIDefCfaOffset(Offset); return false; } @@ -4129,14 +4129,14 @@ bool AsmParser::parseDirectiveCFIRegister(SMLoc DirectiveLoc) { parseRegisterOrRegisterNumber(Register2, DirectiveLoc)) return true; - getStreamer().EmitCFIRegister(Register1, Register2); + getStreamer().emitCFIRegister(Register1, Register2); return false; } /// parseDirectiveCFIWindowSave /// ::= .cfi_window_save bool AsmParser::parseDirectiveCFIWindowSave() { - getStreamer().EmitCFIWindowSave(); + getStreamer().emitCFIWindowSave(); return false; } @@ -4147,7 +4147,7 @@ bool AsmParser::parseDirectiveCFIAdjustCfaOffset() { if (parseAbsoluteExpression(Adjustment)) return true; - getStreamer().EmitCFIAdjustCfaOffset(Adjustment); + getStreamer().emitCFIAdjustCfaOffset(Adjustment); return false; } @@ -4158,7 +4158,7 @@ bool AsmParser::parseDirectiveCFIDefCfaRegister(SMLoc DirectiveLoc) { if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) return true; - getStreamer().EmitCFIDefCfaRegister(Register); + getStreamer().emitCFIDefCfaRegister(Register); return false; } @@ -4173,7 +4173,7 @@ bool AsmParser::parseDirectiveCFIOffset(SMLoc DirectiveLoc) { parseAbsoluteExpression(Offset)) return true; - getStreamer().EmitCFIOffset(Register, Offset); + getStreamer().emitCFIOffset(Register, Offset); return false; } @@ -4187,7 +4187,7 @@ bool AsmParser::parseDirectiveCFIRelOffset(SMLoc DirectiveLoc) { parseAbsoluteExpression(Offset)) return true; - getStreamer().EmitCFIRelOffset(Register, Offset); + getStreamer().emitCFIRelOffset(Register, Offset); return false; } @@ -4233,23 +4233,23 @@ bool AsmParser::parseDirectiveCFIPersonalityOrLsda(bool IsPersonality) { MCSymbol *Sym = getContext().getOrCreateSymbol(Name); if (IsPersonality) - getStreamer().EmitCFIPersonality(Sym, Encoding); + getStreamer().emitCFIPersonality(Sym, Encoding); else - getStreamer().EmitCFILsda(Sym, Encoding); + getStreamer().emitCFILsda(Sym, Encoding); return false; } /// parseDirectiveCFIRememberState /// ::= .cfi_remember_state bool AsmParser::parseDirectiveCFIRememberState() { - getStreamer().EmitCFIRememberState(); + getStreamer().emitCFIRememberState(); return false; } /// parseDirectiveCFIRestoreState /// ::= .cfi_remember_state bool AsmParser::parseDirectiveCFIRestoreState() { - getStreamer().EmitCFIRestoreState(); + getStreamer().emitCFIRestoreState(); return false; } @@ -4261,7 +4261,7 @@ bool AsmParser::parseDirectiveCFISameValue(SMLoc DirectiveLoc) { if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) return true; - getStreamer().EmitCFISameValue(Register); + getStreamer().emitCFISameValue(Register); return false; } @@ -4272,7 +4272,7 @@ bool AsmParser::parseDirectiveCFIRestore(SMLoc DirectiveLoc) { if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) return true; - getStreamer().EmitCFIRestore(Register); + getStreamer().emitCFIRestore(Register); return false; } @@ -4295,7 +4295,7 @@ bool AsmParser::parseDirectiveCFIEscape() { Values.push_back((uint8_t)CurrValue); } - getStreamer().EmitCFIEscape(Values); + getStreamer().emitCFIEscape(Values); return false; } @@ -4305,7 +4305,7 @@ bool AsmParser::parseDirectiveCFIReturnColumn(SMLoc DirectiveLoc) { int64_t Register = 0; if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) return true; - getStreamer().EmitCFIReturnColumn(Register); + getStreamer().emitCFIReturnColumn(Register); return false; } @@ -4316,7 +4316,7 @@ bool AsmParser::parseDirectiveCFISignalFrame() { "unexpected token in '.cfi_signal_frame'")) return true; - getStreamer().EmitCFISignalFrame(); + getStreamer().emitCFISignalFrame(); return false; } @@ -4328,7 +4328,7 @@ bool AsmParser::parseDirectiveCFIUndefined(SMLoc DirectiveLoc) { if (parseRegisterOrRegisterNumber(Register, DirectiveLoc)) return true; - getStreamer().EmitCFIUndefined(Register); + getStreamer().emitCFIUndefined(Register); return false; } diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp index e5058ec0329f4..bc7fa1f12aa9a 100644 --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -228,7 +228,7 @@ void MCStreamer::emitDwarfFile0Directive(StringRef Directory, Source); } -void MCStreamer::EmitCFIBKeyFrame() { +void MCStreamer::emitCFIBKeyFrame() { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) return; @@ -414,18 +414,18 @@ void MCStreamer::EmitLabel(MCSymbol *Symbol, SMLoc Loc) { TS->emitLabel(Symbol); } -void MCStreamer::EmitCFISections(bool EH, bool Debug) { +void MCStreamer::emitCFISections(bool EH, bool Debug) { assert(EH || Debug); } -void MCStreamer::EmitCFIStartProc(bool IsSimple, SMLoc Loc) { +void MCStreamer::emitCFIStartProc(bool IsSimple, SMLoc Loc) { if (hasUnfinishedDwarfFrameInfo()) return getContext().reportError( Loc, "starting new .cfi frame before finishing the previous one"); MCDwarfFrameInfo Frame; Frame.IsSimple = IsSimple; - EmitCFIStartProcImpl(Frame); + emitCFIStartProcImpl(Frame); const MCAsmInfo* MAI = Context.getAsmInfo(); if (MAI) { @@ -440,30 +440,30 @@ void MCStreamer::EmitCFIStartProc(bool IsSimple, SMLoc Loc) { DwarfFrameInfos.push_back(Frame); } -void MCStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MCStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { } -void MCStreamer::EmitCFIEndProc() { +void MCStreamer::emitCFIEndProc() { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) return; - EmitCFIEndProcImpl(*CurFrame); + emitCFIEndProcImpl(*CurFrame); } -void MCStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { +void MCStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { // Put a dummy non-null value in Frame.End to mark that this frame has been // closed. Frame.End = (MCSymbol *)1; } -MCSymbol *MCStreamer::EmitCFILabel() { +MCSymbol *MCStreamer::emitCFILabel() { // Return a dummy non-null value so that label fields appear filled in when // generating textual assembly. return (MCSymbol *)1; } -void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIDefCfa(int64_t Register, int64_t Offset) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createDefCfa(Label, Register, Offset); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -473,8 +473,8 @@ void MCStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { CurFrame->CurrentCfaRegister = static_cast(Register); } -void MCStreamer::EmitCFIDefCfaOffset(int64_t Offset) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIDefCfaOffset(int64_t Offset) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createDefCfaOffset(Label, Offset); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -483,8 +483,8 @@ void MCStreamer::EmitCFIDefCfaOffset(int64_t Offset) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIAdjustCfaOffset(int64_t Adjustment) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIAdjustCfaOffset(int64_t Adjustment) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createAdjustCfaOffset(Label, Adjustment); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -493,8 +493,8 @@ void MCStreamer::EmitCFIAdjustCfaOffset(int64_t Adjustment) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIDefCfaRegister(int64_t Register) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIDefCfaRegister(int64_t Register) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createDefCfaRegister(Label, Register); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -504,8 +504,8 @@ void MCStreamer::EmitCFIDefCfaRegister(int64_t Register) { CurFrame->CurrentCfaRegister = static_cast(Register); } -void MCStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIOffset(int64_t Register, int64_t Offset) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createOffset(Label, Register, Offset); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -514,8 +514,8 @@ void MCStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIRelOffset(int64_t Register, int64_t Offset) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createRelOffset(Label, Register, Offset); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -524,7 +524,7 @@ void MCStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIPersonality(const MCSymbol *Sym, +void MCStreamer::emitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) @@ -533,7 +533,7 @@ void MCStreamer::EmitCFIPersonality(const MCSymbol *Sym, CurFrame->PersonalityEncoding = Encoding; } -void MCStreamer::EmitCFILsda(const MCSymbol *Sym, unsigned Encoding) { +void MCStreamer::emitCFILsda(const MCSymbol *Sym, unsigned Encoding) { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) return; @@ -541,8 +541,8 @@ void MCStreamer::EmitCFILsda(const MCSymbol *Sym, unsigned Encoding) { CurFrame->LsdaEncoding = Encoding; } -void MCStreamer::EmitCFIRememberState() { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIRememberState() { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createRememberState(Label); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) @@ -550,9 +550,9 @@ void MCStreamer::EmitCFIRememberState() { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIRestoreState() { +void MCStreamer::emitCFIRestoreState() { // FIXME: Error if there is no matching cfi_remember_state. - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createRestoreState(Label); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) @@ -560,8 +560,8 @@ void MCStreamer::EmitCFIRestoreState() { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFISameValue(int64_t Register) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFISameValue(int64_t Register) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createSameValue(Label, Register); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -570,8 +570,8 @@ void MCStreamer::EmitCFISameValue(int64_t Register) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIRestore(int64_t Register) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIRestore(int64_t Register) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createRestore(Label, Register); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -580,8 +580,8 @@ void MCStreamer::EmitCFIRestore(int64_t Register) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIEscape(StringRef Values) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIEscape(StringRef Values) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createEscape(Label, Values); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) @@ -589,8 +589,8 @@ void MCStreamer::EmitCFIEscape(StringRef Values) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIGnuArgsSize(int64_t Size) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIGnuArgsSize(int64_t Size) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createGnuArgsSize(Label, Size); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -599,15 +599,15 @@ void MCStreamer::EmitCFIGnuArgsSize(int64_t Size) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFISignalFrame() { +void MCStreamer::emitCFISignalFrame() { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) return; CurFrame->IsSignalFrame = true; } -void MCStreamer::EmitCFIUndefined(int64_t Register) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIUndefined(int64_t Register) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createUndefined(Label, Register); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -616,8 +616,8 @@ void MCStreamer::EmitCFIUndefined(int64_t Register) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIRegister(int64_t Register1, int64_t Register2) { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIRegister(int64_t Register1, int64_t Register2) { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createRegister(Label, Register1, Register2); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -626,8 +626,8 @@ void MCStreamer::EmitCFIRegister(int64_t Register1, int64_t Register2) { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIWindowSave() { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFIWindowSave() { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createWindowSave(Label); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); @@ -636,8 +636,8 @@ void MCStreamer::EmitCFIWindowSave() { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFINegateRAState() { - MCSymbol *Label = EmitCFILabel(); +void MCStreamer::emitCFINegateRAState() { + MCSymbol *Label = emitCFILabel(); MCCFIInstruction Instruction = MCCFIInstruction::createNegateRAState(Label); MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) @@ -645,7 +645,7 @@ void MCStreamer::EmitCFINegateRAState() { CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitCFIReturnColumn(int64_t Register) { +void MCStreamer::emitCFIReturnColumn(int64_t Register) { MCDwarfFrameInfo *CurFrame = getCurrentDwarfFrameInfo(); if (!CurFrame) return; @@ -676,7 +676,7 @@ void MCStreamer::EmitWinCFIStartProc(const MCSymbol *Symbol, SMLoc Loc) { getContext().reportError( Loc, "Starting a function before ending the previous one!"); - MCSymbol *StartProc = EmitCFILabel(); + MCSymbol *StartProc = emitCFILabel(); WinFrameInfos.emplace_back( std::make_unique(Symbol, StartProc)); @@ -691,7 +691,7 @@ void MCStreamer::EmitWinCFIEndProc(SMLoc Loc) { if (CurFrame->ChainedParent) getContext().reportError(Loc, "Not all chained regions terminated!"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); CurFrame->End = Label; } @@ -702,7 +702,7 @@ void MCStreamer::EmitWinCFIFuncletOrFuncEnd(SMLoc Loc) { if (CurFrame->ChainedParent) getContext().reportError(Loc, "Not all chained regions terminated!"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); CurFrame->FuncletOrFuncEnd = Label; } @@ -711,7 +711,7 @@ void MCStreamer::EmitWinCFIStartChained(SMLoc Loc) { if (!CurFrame) return; - MCSymbol *StartProc = EmitCFILabel(); + MCSymbol *StartProc = emitCFILabel(); WinFrameInfos.emplace_back(std::make_unique( CurFrame->Function, StartProc, CurFrame)); @@ -727,7 +727,7 @@ void MCStreamer::EmitWinCFIEndChained(SMLoc Loc) { return getContext().reportError( Loc, "End of a chained region outside a chained region!"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); CurFrame->End = Label; CurrentWinFrameInfo = const_cast(CurFrame->ChainedParent); @@ -820,7 +820,7 @@ void MCStreamer::EmitWinCFIPushReg(MCRegister Register, SMLoc Loc) { if (!CurFrame) return; - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::PushNonVol( Label, encodeSEHRegNum(Context, Register)); @@ -841,7 +841,7 @@ void MCStreamer::EmitWinCFISetFrame(MCRegister Register, unsigned Offset, return getContext().reportError( Loc, "frame offset must be less than or equal to 240"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::SetFPReg( Label, encodeSEHRegNum(getContext(), Register), Offset); @@ -860,7 +860,7 @@ void MCStreamer::EmitWinCFIAllocStack(unsigned Size, SMLoc Loc) { return getContext().reportError( Loc, "stack allocation size is not a multiple of 8"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::Alloc(Label, Size); CurFrame->Instructions.push_back(Inst); @@ -876,7 +876,7 @@ void MCStreamer::EmitWinCFISaveReg(MCRegister Register, unsigned Offset, return getContext().reportError( Loc, "register save offset is not 8 byte aligned"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::SaveNonVol( Label, encodeSEHRegNum(Context, Register), Offset); @@ -891,7 +891,7 @@ void MCStreamer::EmitWinCFISaveXMM(MCRegister Register, unsigned Offset, if (Offset & 0x0F) return getContext().reportError(Loc, "offset is not a multiple of 16"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::SaveXMM( Label, encodeSEHRegNum(Context, Register), Offset); @@ -906,7 +906,7 @@ void MCStreamer::EmitWinCFIPushFrame(bool Code, SMLoc Loc) { return getContext().reportError( Loc, "If present, PushMachFrame must be the first UOP"); - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); WinEH::Instruction Inst = Win64EH::Instruction::PushMachFrame(Label, Code); CurFrame->Instructions.push_back(Inst); @@ -917,7 +917,7 @@ void MCStreamer::EmitWinCFIEndProlog(SMLoc Loc) { if (!CurFrame) return; - MCSymbol *Label = EmitCFILabel(); + MCSymbol *Label = emitCFILabel(); CurFrame->PrologEnd = Label; } @@ -1011,7 +1011,7 @@ void MCStreamer::visitUsedExpr(const MCExpr &Expr) { } } -void MCStreamer::EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &) { +void MCStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &) { // Scan for values. for (unsigned i = Inst.getNumOperands(); i--;) if (Inst.getOperand(i).isExpr()) diff --git a/llvm/lib/Object/RecordStreamer.cpp b/llvm/lib/Object/RecordStreamer.cpp index f39a6c28ed50c..553c002e50190 100644 --- a/llvm/lib/Object/RecordStreamer.cpp +++ b/llvm/lib/Object/RecordStreamer.cpp @@ -81,9 +81,9 @@ RecordStreamer::const_iterator RecordStreamer::begin() { RecordStreamer::const_iterator RecordStreamer::end() { return Symbols.end(); } -void RecordStreamer::EmitInstruction(const MCInst &Inst, +void RecordStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - MCStreamer::EmitInstruction(Inst, STI); + MCStreamer::emitInstruction(Inst, STI); } void RecordStreamer::EmitLabel(MCSymbol *Symbol, SMLoc Loc) { diff --git a/llvm/lib/Object/RecordStreamer.h b/llvm/lib/Object/RecordStreamer.h index c8b75bcc6d1df..238148e356e4b 100644 --- a/llvm/lib/Object/RecordStreamer.h +++ b/llvm/lib/Object/RecordStreamer.h @@ -46,7 +46,7 @@ class RecordStreamer : public MCStreamer { public: RecordStreamer(MCContext &Context, const Module &M); - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) override; bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) override; diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp index f2f29099b0cea..da889cccd69e9 100644 --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -112,7 +112,7 @@ class AArch64AsmPrinter : public AsmPrinter { bool emitPseudoExpansionLowering(MCStreamer &OutStreamer, const MachineInstr *MI); - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void getAnalysisUsage(AnalysisUsage &AU) const override { AsmPrinter::getAnalysisUsage(AU); @@ -368,20 +368,20 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { OutStreamer->EmitSymbolAttribute(Sym, MCSA_Hidden); OutStreamer->EmitLabel(Sym); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::UBFMXri) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::UBFMXri) .addReg(AArch64::X16) .addReg(Reg) .addImm(4) .addImm(55), *STI); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBroX) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRBBroX) .addReg(AArch64::W16) .addReg(AArch64::X9) .addReg(AArch64::X16) .addImm(0) .addImm(0), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::SUBSXrs) .addReg(AArch64::XZR) .addReg(AArch64::X16) @@ -389,7 +389,7 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), *STI); MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol(); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::Bcc) .addImm(AArch64CC::NE) .addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym, @@ -397,25 +397,25 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { *STI); MCSymbol *ReturnSym = OutContext.createTempSymbol(); OutStreamer->EmitLabel(ReturnSym); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI); OutStreamer->EmitLabel(HandleMismatchOrPartialSym); if (IsShort) { - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWri) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWri) .addReg(AArch64::WZR) .addReg(AArch64::W16) .addImm(15) .addImm(0), *STI); MCSymbol *HandleMismatchSym = OutContext.createTempSymbol(); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::Bcc) .addImm(AArch64CC::HI) .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::ANDXri) .addReg(AArch64::X17) .addReg(Reg) @@ -423,43 +423,43 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { *STI); unsigned Size = 1 << (AccessInfo & 0xf); if (Size != 1) - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::ADDXri) .addReg(AArch64::X17) .addReg(AArch64::X17) .addImm(Size - 1) .addImm(0), *STI); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWrs) .addReg(AArch64::WZR) .addReg(AArch64::W16) .addReg(AArch64::W17) .addImm(0), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::Bcc) .addImm(AArch64CC::LS) .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::ORRXri) .addReg(AArch64::X16) .addReg(Reg) .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)), *STI); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBui) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRBBui) .addReg(AArch64::W16) .addReg(AArch64::X16) .addImm(0), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::SUBSXrs) .addReg(AArch64::XZR) .addReg(AArch64::X16) .addReg(Reg) .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::Bcc) .addImm(AArch64CC::EQ) .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)), @@ -468,14 +468,14 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { OutStreamer->EmitLabel(HandleMismatchSym); } - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXpre) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXpre) .addReg(AArch64::SP) .addReg(AArch64::X0) .addReg(AArch64::X1) .addReg(AArch64::SP) .addImm(-32), *STI); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXi) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXi) .addReg(AArch64::FP) .addReg(AArch64::LR) .addReg(AArch64::SP) @@ -483,13 +483,13 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { *STI); if (Reg != AArch64::X0) - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ORRXrs) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::ORRXrs) .addReg(AArch64::X0) .addReg(AArch64::XZR) .addReg(Reg) .addImm(0), *STI); - OutStreamer->EmitInstruction(MCInstBuilder(AArch64::MOVZXi) + OutStreamer->emitInstruction(MCInstBuilder(AArch64::MOVZXi) .addReg(AArch64::X1) .addImm(AccessInfo) .addImm(0), @@ -498,14 +498,14 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { // Intentionally load the GOT entry and branch to it, rather than possibly // late binding the function, which may clobber the registers before we have // a chance to save them. - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::ADRP) .addReg(AArch64::X16) .addExpr(AArch64MCExpr::create( HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE, OutContext)), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::LDRXui) .addReg(AArch64::X16) .addReg(AArch64::X16) @@ -513,7 +513,7 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) { HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12, OutContext)), *STI); - OutStreamer->EmitInstruction( + OutStreamer->emitInstruction( MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI); } } @@ -981,7 +981,7 @@ void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) { // instructions) auto-generated. #include "AArch64GenMCPseudoLowering.inc" -void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { +void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) { // Do any auto-generated pseudo lowerings. if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; @@ -1080,7 +1080,7 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) { if (needsCFIMoves() == CFI_M_None) return; - OutStreamer->EmitCFIBKeyFrame(); + OutStreamer->emitCFIBKeyFrame(); return; } } diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index fa3d64b4666d4..f6bc615d8307a 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -4832,7 +4832,7 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return true; Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); return false; } case Match_MissingFeature: { @@ -5322,7 +5322,7 @@ bool AArch64AsmParser::parseDirectiveTLSDescCall(SMLoc L) { Inst.setOpcode(AArch64::TLSDESCCALL); Inst.addOperand(MCOperand::createExpr(Expr)); - getParser().getStreamer().EmitInstruction(Inst, getSTI()); + getParser().getStreamer().emitInstruction(Inst, getSTI()); return false; } @@ -5466,7 +5466,7 @@ bool AArch64AsmParser::parseDirectiveUnreq(SMLoc L) { bool AArch64AsmParser::parseDirectiveCFINegateRAState() { if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) return true; - getStreamer().EmitCFINegateRAState(); + getStreamer().emitCFINegateRAState(); return false; } @@ -5476,7 +5476,7 @@ bool AArch64AsmParser::parseDirectiveCFIBKeyFrame() { if (parseToken(AsmToken::EndOfStatement, "unexpected token in '.cfi_b_key_frame'")) return true; - getStreamer().EmitCFIBKeyFrame(); + getStreamer().emitCFIBKeyFrame(); return false; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp index c33f7e957b54a..f028b5e7fb8ab 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp @@ -102,10 +102,10 @@ class AArch64ELFStreamer : public MCELFStreamer { /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { EmitA64MappingSymbol(); - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); } /// Emit a 32-bit value as an instruction. This is only used for the .inst diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp index 37c6fbb039081..693fba34d9a04 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp @@ -68,7 +68,7 @@ void AArch64TargetWinCOFFStreamer::EmitARM64WinUnwindCode(unsigned UnwindCode, WinEH::FrameInfo *CurFrame = S.EnsureValidWinFrameInfo(SMLoc()); if (!CurFrame) return; - MCSymbol *Label = S.EmitCFILabel(); + MCSymbol *Label = S.emitCFILabel(); auto Inst = WinEH::Instruction(UnwindCode, Label, Reg, Offset); if (InEpilogCFI) CurFrame->EpilogMap[CurrentEpilog].push_back(Inst); @@ -158,7 +158,7 @@ void AArch64TargetWinCOFFStreamer::EmitARM64WinCFIPrologEnd() { if (!CurFrame) return; - MCSymbol *Label = S.EmitCFILabel(); + MCSymbol *Label = S.emitCFILabel(); CurFrame->PrologEnd = Label; WinEH::Instruction Inst = WinEH::Instruction(Win64EH::UOP_End, Label, -1, 0); auto it = CurFrame->Instructions.begin(); @@ -172,7 +172,7 @@ void AArch64TargetWinCOFFStreamer::EmitARM64WinCFIEpilogStart() { return; InEpilogCFI = true; - CurrentEpilog = S.EmitCFILabel(); + CurrentEpilog = S.emitCFILabel(); } void AArch64TargetWinCOFFStreamer::EmitARM64WinCFIEpilogEnd() { @@ -182,7 +182,7 @@ void AArch64TargetWinCOFFStreamer::EmitARM64WinCFIEpilogEnd() { return; InEpilogCFI = false; - MCSymbol *Label = S.EmitCFILabel(); + MCSymbol *Label = S.emitCFILabel(); WinEH::Instruction Inst = WinEH::Instruction(Win64EH::UOP_End, Label, -1, 0); CurFrame->EpilogMap[CurrentEpilog].push_back(Inst); CurrentEpilog = nullptr; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h index a0d5e8aa4b503..54e8338ab4b04 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -121,7 +121,7 @@ class AMDGPUAsmPrinter final : public AsmPrinter { const MachineInstr *MI); /// Implemented in AMDGPUMCInstLower.cpp - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void emitFunctionBodyStart() override; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp index ce7286dabcc8a..99d229c9b74ee 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -254,7 +254,7 @@ const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) { return AsmPrinter::lowerConstant(CV); } -void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) { if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; @@ -272,7 +272,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); while (I != MBB->instr_end() && I->isInsideBundle()) { - EmitInstruction(&*I); + emitInstruction(&*I); ++I; } } else { @@ -381,7 +381,7 @@ void R600MCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { } } -void R600AsmPrinter::EmitInstruction(const MachineInstr *MI) { +void R600AsmPrinter::emitInstruction(const MachineInstr *MI) { const R600Subtarget &STI = MF->getSubtarget(); R600MCInstLower MCInstLowering(OutContext, STI, *this); @@ -396,7 +396,7 @@ void R600AsmPrinter::EmitInstruction(const MachineInstr *MI) { const MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); while (I != MBB->instr_end() && I->isInsideBundle()) { - EmitInstruction(&*I); + emitInstruction(&*I); ++I; } } else { diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 3ef493bcb1565..d3d06fbfaa35d 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -3606,7 +3606,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return true; } Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); return false; case Match_MissingFeature: diff --git a/llvm/lib/Target/AMDGPU/R600AsmPrinter.h b/llvm/lib/Target/AMDGPU/R600AsmPrinter.h index 0da9526d716ea..552d01f81b66c 100644 --- a/llvm/lib/Target/AMDGPU/R600AsmPrinter.h +++ b/llvm/lib/Target/AMDGPU/R600AsmPrinter.h @@ -26,7 +26,7 @@ class R600AsmPrinter final : public AsmPrinter { StringRef getPassName() const override; bool runOnMachineFunction(MachineFunction &MF) override; /// Implemented in AMDGPUMCInstLower.cpp - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; /// Lower the specified LLVM Constant to an MCExpr. /// The AsmPrinter::lowerConstantof does not know how to lower /// addrspacecast, therefore they should be lowered by this function. diff --git a/llvm/lib/Target/ARC/ARCAsmPrinter.cpp b/llvm/lib/Target/ARC/ARCAsmPrinter.cpp index 7915ca0033162..cf511cd5ac0f8 100644 --- a/llvm/lib/Target/ARC/ARCAsmPrinter.cpp +++ b/llvm/lib/Target/ARC/ARCAsmPrinter.cpp @@ -41,12 +41,12 @@ class ARCAsmPrinter : public AsmPrinter { MCInstLowering(&OutContext, *this) {} StringRef getPassName() const override { return "ARC Assembly Printer"; } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; }; } // end anonymous namespace -void ARCAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void ARCAsmPrinter::emitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream O(Str); diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 2ea326949131a..fad872f891fd7 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -100,7 +100,7 @@ void ARMAsmPrinter::emitGlobalVariable(const GlobalVariable *GV) { AsmPrinter::emitGlobalVariable(GV); } -/// runOnMachineFunction - This uses the EmitInstruction() +/// runOnMachineFunction - This uses the emitInstruction() /// method to print assembly for each instruction. /// bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { @@ -1242,7 +1242,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { // instructions) auto-generated. #include "ARMGenMCPseudoLowering.inc" -void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) { const DataLayout &DL = getDataLayout(); MCTargetStreamer &TS = *OutStreamer->getTargetStreamer(); ARMTargetStreamer &ATS = static_cast(TS); diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h index cd771df992223..f8ff047a1d068 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.h +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h @@ -87,7 +87,7 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { void emitJumpTableAddrs(const MachineInstr *MI); void emitJumpTableInsts(const MachineInstr *MI); void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth); - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; bool runOnMachineFunction(MachineFunction &F) override; void emitConstantPool() override { diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index e4f375c6f0431..ba44e3506f9e1 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -245,12 +245,12 @@ class ARMAsmParser : public MCTargetAsmParser { ITInst.setOpcode(ARM::t2IT); ITInst.addOperand(MCOperand::createImm(ITState.Cond)); ITInst.addOperand(MCOperand::createImm(ITState.Mask)); - Out.EmitInstruction(ITInst, getSTI()); + Out.emitInstruction(ITInst, getSTI()); // Emit the conditonal instructions assert(PendingConditionalInsts.size() <= 4); for (const MCInst &Inst : PendingConditionalInsts) { - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); } PendingConditionalInsts.clear(); @@ -10521,7 +10521,7 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, if (isITBlockFull() || isITBlockTerminator(Inst)) flushPendingInstructions(Out); } else { - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); } return false; case Match_NearMisses: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index cbe347c29c255..3e051f00fe704 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -474,14 +474,14 @@ class ARMELFStreamer : public MCELFStreamer { /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to add the appropriate mapping symbol if /// necessary. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { if (IsThumb) EmitThumbMappingSymbol(); else EmitARMMappingSymbol(); - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); } void emitInst(uint32_t Inst, char Suffix) { diff --git a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp index 9b09c7456543f..722eecdc16a14 100644 --- a/llvm/lib/Target/AVR/AVRAsmPrinter.cpp +++ b/llvm/lib/Target/AVR/AVRAsmPrinter.cpp @@ -51,7 +51,7 @@ class AVRAsmPrinter : public AsmPrinter { bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; private: const MCRegisterInfo &MRI; @@ -168,7 +168,7 @@ bool AVRAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void AVRAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void AVRAsmPrinter::emitInstruction(const MachineInstr *MI) { AVRMCInstLower MCInstLowering(OutContext, *this); MCInst I; diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp index 9d0dee8cc293a..566c8e4ee6300 100644 --- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp +++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp @@ -309,7 +309,7 @@ bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc, bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const { Inst.setLoc(Loc); - Out.EmitInstruction(Inst, STI); + Out.emitInstruction(Inst, STI); return false; } diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp index dbcb156a43fd8..57488bc28f982 100644 --- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp +++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp @@ -297,7 +297,7 @@ bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, break; case Match_Success: Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); return false; case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); diff --git a/llvm/lib/Target/BPF/BPFAsmPrinter.cpp b/llvm/lib/Target/BPF/BPFAsmPrinter.cpp index b81386f479d30..37950e105bdc1 100644 --- a/llvm/lib/Target/BPF/BPFAsmPrinter.cpp +++ b/llvm/lib/Target/BPF/BPFAsmPrinter.cpp @@ -48,7 +48,7 @@ class BPFAsmPrinter : public AsmPrinter { bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; private: BTFDebug *BTF; @@ -137,7 +137,7 @@ bool BPFAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void BPFAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void BPFAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst TmpInst; if (!BTF || !BTF->InstLower(MI, TmpInst)) { diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index ae19b138b0c7f..7089ba2f77240 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -492,7 +492,7 @@ bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) { assert(HexagonMCInstrInfo::isBundle(MCB)); - Out.EmitInstruction(MCB, STI); + Out.emitInstruction(MCB, STI); } else return true; // Error diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 30fdde70d01af..eaa772926b01a 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -740,7 +740,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, } /// Print out a single Hexagon MI to the current output stream. -void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void HexagonAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst MCB; MCB.setOpcode(Hexagon::BUNDLE); MCB.addOperand(MCOperand::createImm(0)); @@ -768,7 +768,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { assert(Ok); (void)Ok; if (HexagonMCInstrInfo::bundleSize(MCB) == 0) return; - OutStreamer->EmitInstruction(MCB, getSubtargetInfo()); + OutStreamer->emitInstruction(MCB, getSubtargetInfo()); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonAsmPrinter() { diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h index 6c4b664e83f52..3932def878544 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -46,7 +46,7 @@ class TargetMachine; bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MBB); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp index a799f7f7c0b97..b580b4ae11c33 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -58,7 +58,7 @@ HexagonMCELFStreamer::HexagonMCELFStreamer( : MCELFStreamer(Context, std::move(TAB), std::move(OW), std::move(Emitter)), MCII(createHexagonMCInstrInfo()) {} -void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, +void HexagonMCELFStreamer::emitInstruction(const MCInst &MCB, const MCSubtargetInfo &STI) { assert(MCB.getOpcode() == Hexagon::BUNDLE); assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE); @@ -71,7 +71,7 @@ void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, EmitSymbol(*MCI); } - MCObjectStreamer::EmitInstruction(MCB, STI); + MCObjectStreamer::emitInstruction(MCB, STI); } void HexagonMCELFStreamer::EmitSymbol(const MCInst &Inst) { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h index 6248bd25d433b..edf4ce29f908c 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h @@ -30,7 +30,7 @@ class HexagonMCELFStreamer : public MCELFStreamer { std::unique_ptr Emitter, MCAssembler *Assembler); - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; void EmitSymbol(const MCInst &Inst); void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index 9028f4ad93d98..639ab24b08179 100644 --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -659,7 +659,7 @@ bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { case Match_Success: - Out.EmitInstruction(Inst, SubtargetInfo); + Out.emitInstruction(Inst, SubtargetInfo); Opcode = Inst.getOpcode(); return false; case Match_MissingFeature: diff --git a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp index 749bc623338d2..6bac7c75853de 100644 --- a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp +++ b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp @@ -51,7 +51,7 @@ class LanaiAsmPrinter : public AsmPrinter { void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; bool isBlockOnlyReachableByFallthrough( const MachineBasicBlock *MBB) const override; @@ -155,7 +155,7 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { // Insert save rca instruction immediately before the call. // TODO: We should generate a pc-relative mov instruction here instead // of pc + 16 (should be mov .+16 %rca). - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_I_LO) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_I_LO) .addReg(Lanai::RCA) .addReg(Lanai::PC) .addImm(16), @@ -163,7 +163,7 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { // Push rca onto the stack. // st %rca, [--%sp] - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::SW_RI) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::SW_RI) .addReg(Lanai::RCA) .addReg(Lanai::SP) .addImm(-4) @@ -175,9 +175,9 @@ void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) { MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); TmpInst.setOpcode(Lanai::BT); - OutStreamer->EmitInstruction(TmpInst, STI); + OutStreamer->emitInstruction(TmpInst, STI); } else { - OutStreamer->EmitInstruction(MCInstBuilder(Lanai::ADD_R) + OutStreamer->emitInstruction(MCInstBuilder(Lanai::ADD_R) .addReg(Lanai::PC) .addReg(MI->getOperand(0).getReg()) .addReg(Lanai::R0) @@ -191,10 +191,10 @@ void LanaiAsmPrinter::customEmitInstruction(const MachineInstr *MI) { MCSubtargetInfo STI = getSubtargetInfo(); MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); - OutStreamer->EmitInstruction(TmpInst, STI); + OutStreamer->emitInstruction(TmpInst, STI); } -void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void LanaiAsmPrinter::emitInstruction(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator I = MI->getIterator(); MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp index daa1fb4b52cfc..194a6375e6c5d 100644 --- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp @@ -263,7 +263,7 @@ bool MSP430AsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode, switch (MatchResult) { case Match_Success: Inst.setLoc(Loc); - Out.EmitInstruction(Inst, STI); + Out.emitInstruction(Inst, STI); return false; case Match_MnemonicFail: return Error(Loc, "invalid instruction mnemonic"); diff --git a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp index 964e11d3d7ad7..4576ca3671c37 100644 --- a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp +++ b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -57,7 +57,7 @@ namespace { const char *ExtraCode, raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void EmitInterruptVectorSection(MachineFunction &ISR); }; @@ -148,7 +148,7 @@ bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, } //===----------------------------------------------------------------------===// -void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { +void MSP430AsmPrinter::emitInstruction(const MachineInstr *MI) { MSP430MCInstLower MCInstLowering(OutContext, *this); MCInst TmpInst; diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 21b8d503741eb..4101da95e7b05 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -2313,7 +2313,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, tryExpandInstruction(Inst, IDLoc, Out, STI); switch (ExpandResult) { case MER_NotAMacro: - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); break; case MER_Success: break; @@ -2640,7 +2640,7 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, const MCOperand SecondRegOp = Inst.getOperand(1); JalrInst.addOperand(SecondRegOp); } - Out.EmitInstruction(JalrInst, *STI); + Out.emitInstruction(JalrInst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. @@ -3571,7 +3571,7 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, Inst.addOperand(MCOperand::createImm(Offset.getImm())); } } - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. @@ -3858,7 +3858,7 @@ bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, } Inst.setOpcode(NewOpcode); - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); return false; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp index 1b83e9445fb5c..cfe435314aee6 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp @@ -33,9 +33,9 @@ MipsELFStreamer::MipsELFStreamer(MCContext &Context, std::unique_ptr(RegInfoRecord)); } -void MipsELFStreamer::EmitInstruction(const MCInst &Inst, +void MipsELFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); MCContext &Context = getContext(); const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo(); @@ -53,18 +53,18 @@ void MipsELFStreamer::EmitInstruction(const MCInst &Inst, createPendingLabelRelocs(); } -void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { Frame.Begin = getContext().createTempSymbol(); MCELFStreamer::EmitLabel(Frame.Begin); } -MCSymbol *MipsELFStreamer::EmitCFILabel() { +MCSymbol *MipsELFStreamer::emitCFILabel() { MCSymbol *Label = getContext().createTempSymbol("cfi", true); MCELFStreamer::EmitLabel(Label); return Label; } -void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { Frame.End = getContext().createTempSymbol(); MCELFStreamer::EmitLabel(Frame.End); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h index 2febfbc69b6fe..451b1b08a9245 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h @@ -41,7 +41,7 @@ class MipsELFStreamer : public MCELFStreamer { /// \p Inst is actually emitted. For example, we can inspect the operands and /// gather sufficient information that allows us to reason about the register /// usage for the translation unit. - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; /// Overriding this function allows us to record all labels that should be /// marked as microMIPS. Based on this data marking is done in @@ -61,9 +61,9 @@ class MipsELFStreamer : public MCELFStreamer { // Overriding these functions allows us to avoid recording of these labels // in EmitLabel and later marking them as microMIPS. - void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; - void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; - MCSymbol *EmitCFILabel() override; + void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *emitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 846f508005f58..c483dc46a34f2 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -129,7 +129,7 @@ void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; } -void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, +void MipsMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const { // Output the instruction encoding in little endian byte order. @@ -137,8 +137,8 @@ void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, // mips32r2: 4 | 3 | 2 | 1 // microMIPS: 2 | 1 | 4 | 3 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { - EmitInstruction(Val >> 16, 2, STI, OS); - EmitInstruction(Val, 2, STI, OS); + emitInstruction(Val >> 16, 2, STI, OS); + emitInstruction(Val, 2, STI, OS); } else { for (unsigned i = 0; i < Size; ++i) { unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; @@ -226,7 +226,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, if (!Size) llvm_unreachable("Desc.getSize() returns 0"); - EmitInstruction(Binary, Size, STI, OS); + emitInstruction(Binary, Size, STI, OS); } /// getBranchTargetOpValue - Return binary encoding of the branch diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index ff6e1d62b05f6..16e94c723b347 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -44,7 +44,7 @@ class MipsMCCodeEmitter : public MCCodeEmitter { void EmitByte(unsigned char C, raw_ostream &OS) const; - void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, + void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const; void encodeInstruction(const MCInst &MI, raw_ostream &OS, diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp index 0544758f8a253..f0265d2330ab7 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -105,7 +105,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer { MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(MaskReg)); - MipsELFStreamer::EmitInstruction(MaskInst, STI); + MipsELFStreamer::emitInstruction(MaskInst, STI); } // Sandbox indirect branch or return instruction by inserting mask operation @@ -115,7 +115,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer { EmitBundleLock(false); emitMask(AddrReg, IndirectBranchMaskReg, STI); - MipsELFStreamer::EmitInstruction(MI, STI); + MipsELFStreamer::emitInstruction(MI, STI); EmitBundleUnlock(); } @@ -130,7 +130,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer { unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); emitMask(BaseReg, LoadStoreStackMaskReg, STI); } - MipsELFStreamer::EmitInstruction(MI, STI); + MipsELFStreamer::emitInstruction(MI, STI); if (MaskAfter) { // Sandbox SP change. unsigned SPReg = MI.getOperand(0).getReg(); @@ -143,7 +143,7 @@ class MipsNaClELFStreamer : public MipsELFStreamer { public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to mask dangerous instructions. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { // Sandbox indirect jumps. if (isIndirectJump(Inst)) { @@ -186,20 +186,20 @@ class MipsNaClELFStreamer : public MipsELFStreamer { unsigned TargetReg = Inst.getOperand(1).getReg(); emitMask(TargetReg, IndirectBranchMaskReg, STI); } - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); PendingCall = true; return; } if (PendingCall) { // Finish the sandboxing sequence by emitting branch delay. - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); EmitBundleUnlock(); PendingCall = false; return; } // None of the sandboxing applies, just emit the instruction. - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); } }; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index 054dc79f4aa91..88dcab6d7345b 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -169,7 +169,7 @@ void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, TmpInst.setOpcode(Opcode); TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, @@ -179,7 +179,7 @@ void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.addOperand(Op1); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, @@ -199,7 +199,7 @@ void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -211,7 +211,7 @@ void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg1)); TmpInst.addOperand(Op2); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -230,7 +230,7 @@ void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg2)); TmpInst.addOperand(Op3); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -251,7 +251,7 @@ void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg, @@ -1139,7 +1139,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(HiSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1152,7 +1152,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(LoSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1160,7 +1160,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(RegNo)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); forbidModuleDirective(); } @@ -1269,7 +1269,7 @@ void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation, Inst.addOperand(MCOperand::createReg(Mips::SP)); Inst.addOperand(MCOperand::createImm(SaveLocation)); } - getStreamer().EmitInstruction(Inst, STI); + getStreamer().emitInstruction(Inst, STI); forbidModuleDirective(); } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 22999d3780dab..d6804d95ac7d0 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -185,7 +185,7 @@ static void emitDirectiveRelocJalr(const MachineInstr &MI, } } -void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) { MipsTargetStreamer &TS = getTargetStreamer(); unsigned Opc = MI->getOpcode(); TS.forbidModuleDirective(); @@ -280,7 +280,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { // if (I->isPseudo() && !Subtarget->inMips16Mode() && !isLongBranchPseudo(I->getOpcode())) - llvm_unreachable("Pseudo opcode found in EmitInstruction()"); + llvm_unreachable("Pseudo opcode found in emitInstruction()"); MCInst TmpInst0; MCInstLowering.Lower(&*I, TmpInst0); @@ -860,7 +860,7 @@ void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) { I.setOpcode(Mips::JAL); I.addOperand( MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext))); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, @@ -868,7 +868,7 @@ void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, MCInst I; I.setOpcode(Opcode); I.addOperand(MCOperand::createReg(Reg)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI, @@ -888,7 +888,7 @@ void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI, I.setOpcode(Opcode); I.addOperand(MCOperand::createReg(Reg1)); I.addOperand(MCOperand::createReg(Reg2)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI, @@ -899,7 +899,7 @@ void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI, I.addOperand(MCOperand::createReg(Reg1)); I.addOperand(MCOperand::createReg(Reg2)); I.addOperand(MCOperand::createReg(Reg3)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI, diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index 5bf68b3f09d14..64424b181504a 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -134,7 +134,7 @@ class LLVM_LIBRARY_VISIBILITY MipsAsmPrinter : public AsmPrinter { // we emit constant pools customly! } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void printSavedRegsBitmask(); void emitFrameDirective(); const char *getCurrentABIString() const; diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp index 6d8c40914db71..8d1142792fe60 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp @@ -141,7 +141,7 @@ VisitGlobalVariableForEmission(const GlobalVariable *GV, Visiting.erase(GV); } -void NVPTXAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void NVPTXAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst Inst; lowerToMCInst(MI, Inst); EmitToStreamer(*OutStreamer, Inst); diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h index 9f675a00c2d09..3c1f57af56fd8 100644 --- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h +++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h @@ -206,7 +206,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter { void emitFunctionBodyEnd() override; void emitImplicitDef(const MachineInstr *MI) const override; - void EmitInstruction(const MachineInstr *) override; + void emitInstruction(const MachineInstr *) override; void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI); bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp); MCOperand GetSymbolRef(const MCSymbol *Symbol); diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index 7859b13ecfaa8..6bda0b0405350 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -1155,7 +1155,7 @@ bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // Post-process instructions (typically extended mnemonics) ProcessInstruction(Inst, Operands); Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); return false; case Match_MissingFeature: return Error(IDLoc, "instruction use requires an option to be enabled"); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp index 8290b0655b9bf..18516659de9b8 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp @@ -44,14 +44,14 @@ PPCELFStreamer::PPCELFStreamer(MCContext &Context, std::move(Emitter)), LastLabel(NULL) { } -void PPCELFStreamer::EmitInstruction(const MCInst &Inst, +void PPCELFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { PPCMCCodeEmitter *Emitter = static_cast(getAssembler().getEmitterPtr()); // Special handling is only for prefixed instructions. if (!Emitter->isPrefixedInstruction(Inst)) { - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); return; } @@ -71,7 +71,7 @@ void PPCELFStreamer::EmitInstruction(const MCInst &Inst, // Since the previous emit created a new fragment then adding this instruction // also forces the addition of a new fragment. Inst is now the first // instruction in that new fragment. - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); // The above instruction is forced to start a new fragment because it // comes after a code alignment fragment. Get that new fragment. diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h index 723d1538a6374..2585c0157451b 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h @@ -37,7 +37,7 @@ class PPCELFStreamer : public MCELFStreamer { std::unique_ptr OW, std::unique_ptr Emitter); - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; // EmitLabel updates LastLabel and LastLabelLoc when a new label is emitted. void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index f12d85386b7a7..8cd66e08b0816 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -100,7 +100,7 @@ class PPCAsmPrinter : public AsmPrinter { return AsmPrinter::doInitialization(M); } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; /// This function is for PrintAsmOperand and PrintAsmMemoryOperand, /// invoked by EmitMSInlineAsmStr and EmitGCCInlineAsmStr only. @@ -144,7 +144,7 @@ class PPCLinuxAsmPrinter : public PPCAsmPrinter { void emitFunctionBodyStart() override; void emitFunctionBodyEnd() override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; }; class PPCAIXAsmPrinter : public PPCAsmPrinter { @@ -512,7 +512,7 @@ MCSymbol *PPCAsmPrinter::getMCSymbolForTOCPseudoMO(const MachineOperand &MO) { /// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to /// the current output stream. /// -void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst TmpInst; const bool IsPPC64 = Subtarget->isPPC64(); const bool IsAIX = Subtarget->isAIXABI(); @@ -1149,13 +1149,13 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, TmpInst); } -void PPCLinuxAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) { if (!Subtarget->isPPC64()) - return PPCAsmPrinter::EmitInstruction(MI); + return PPCAsmPrinter::emitInstruction(MI); switch (MI->getOpcode()) { default: - return PPCAsmPrinter::EmitInstruction(MI); + return PPCAsmPrinter::emitInstruction(MI); case TargetOpcode::PATCHABLE_FUNCTION_ENTER: { // .begin: // b .end # lis 0, FuncId[16..32] diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 3e72eb096850e..952277fa5b948 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1682,7 +1682,7 @@ void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { bool Res = compressInst(CInst, Inst, getSTI(), S.getContext()); if (Res) ++RISCVNumInstrsCompressed; - S.EmitInstruction((Res ? CInst : Inst), getSTI()); + S.emitInstruction((Res ? CInst : Inst), getSTI()); } void RISCVAsmParser::emitLoadImm(Register DestReg, int64_t Value, diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index f4aa28bcc0c1b..893dc8ddab861 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -44,7 +44,7 @@ class RISCVAsmPrinter : public AsmPrinter { StringRef getPassName() const override { return "RISCV Assembly Printer"; } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; @@ -77,7 +77,7 @@ void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { // instructions) auto-generated. #include "RISCVGenMCPseudoLowering.inc" -void RISCVAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) { // Do any auto-generated pseudo lowerings. if (emitPseudoExpansionLowering(*OutStreamer, MI)) return; diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index dc75f5ccf973d..16e1596216722 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -602,7 +602,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } for (const MCInst &I : Instructions) { - Out.EmitInstruction(I, getSTI()); + Out.emitInstruction(I, getSTI()); } return false; } diff --git a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index f85595d338265..b4860c818b50d 100644 --- a/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -53,7 +53,7 @@ namespace { const char *Modifier = nullptr); void emitFunctionBodyStart() override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; static const char *getRegisterName(unsigned RegNo) { return SparcInstPrinter::getRegisterName(RegNo); @@ -108,7 +108,7 @@ static void EmitCall(MCStreamer &OutStreamer, MCInst CallInst; CallInst.setOpcode(SP::CALL); CallInst.addOperand(Callee); - OutStreamer.EmitInstruction(CallInst, STI); + OutStreamer.emitInstruction(CallInst, STI); } static void EmitSETHI(MCStreamer &OutStreamer, @@ -119,7 +119,7 @@ static void EmitSETHI(MCStreamer &OutStreamer, SETHIInst.setOpcode(SP::SETHIi); SETHIInst.addOperand(RD); SETHIInst.addOperand(Imm); - OutStreamer.EmitInstruction(SETHIInst, STI); + OutStreamer.emitInstruction(SETHIInst, STI); } static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, @@ -131,7 +131,7 @@ static void EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, Inst.addOperand(RD); Inst.addOperand(RS1); Inst.addOperand(Src2); - OutStreamer.EmitInstruction(Inst, STI); + OutStreamer.emitInstruction(Inst, STI); } static void EmitOR(MCStreamer &OutStreamer, @@ -249,8 +249,7 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } -void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) -{ +void SparcAsmPrinter::emitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { default: break; diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index 00fdb9e846d6a..4709bb6390873 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -1135,7 +1135,7 @@ bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { } // Emit as a regular instruction. - Parser.getStreamer().EmitInstruction(Inst, getSTI()); + Parser.getStreamer().emitInstruction(Inst, getSTI()); return false; } @@ -1288,7 +1288,7 @@ bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, switch (MatchResult) { case Match_Success: Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); return false; case Match_MissingFeature: { diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 779dd2b12e059..954ebfcf4e73b 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -124,7 +124,7 @@ static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { .addImm(0); } -void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) { SystemZMCInstLower Lower(MF->getContext(), *this); MCInst LoweredMI; switch (MI->getOpcode()) { @@ -522,7 +522,6 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { EmitToStreamer(*OutStreamer, LoweredMI); } - // Emit the largest nop instruction smaller than or equal to NumBytes // bytes. Return the size of nop emitted. static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, @@ -532,22 +531,22 @@ static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, return 0; } else if (NumBytes < 4) { - OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCRAsm) - .addImm(0).addReg(SystemZ::R0D), STI); + OutStreamer.emitInstruction( + MCInstBuilder(SystemZ::BCRAsm).addImm(0).addReg(SystemZ::R0D), STI); return 2; } else if (NumBytes < 6) { - OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCAsm) - .addImm(0).addReg(0).addImm(0).addReg(0), - STI); + OutStreamer.emitInstruction( + MCInstBuilder(SystemZ::BCAsm).addImm(0).addReg(0).addImm(0).addReg(0), + STI); return 4; } else { MCSymbol *DotSym = OutContext.createTempSymbol(); const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext); OutStreamer.EmitLabel(DotSym); - OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BRCLAsm) - .addImm(0).addExpr(Dot), STI); + OutStreamer.emitInstruction( + MCInstBuilder(SystemZ::BRCLAsm).addImm(0).addExpr(Dot), STI); return 6; } } @@ -573,8 +572,9 @@ void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__"); const MCSymbolRefExpr *Op = MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_PLT, Ctx); - OutStreamer->EmitInstruction(MCInstBuilder(SystemZ::BRASL) - .addReg(SystemZ::R0D).addExpr(Op), getSubtargetInfo()); + OutStreamer->emitInstruction( + MCInstBuilder(SystemZ::BRASL).addReg(SystemZ::R0D).addExpr(Op), + getSubtargetInfo()); } void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h index c9374362c89be..2d7562c7238da 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h @@ -32,7 +32,7 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter { // Override AsmPrinter. StringRef getPassName() const override { return "SystemZ Assembly Printer"; } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; void emitEndOfAsmFile(Module &M) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp index 918f2a1acdaff..c1e0cc3c422ad 100644 --- a/llvm/lib/Target/VE/VEAsmPrinter.cpp +++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp @@ -46,7 +46,7 @@ class VEAsmPrinter : public AsmPrinter { StringRef getPassName() const override { return "VE Assembly Printer"; } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; static const char *getRegisterName(unsigned RegNo) { return VEInstPrinter::getRegisterName(RegNo); @@ -54,7 +54,7 @@ class VEAsmPrinter : public AsmPrinter { }; } // end of anonymous namespace -void VEAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void VEAsmPrinter::emitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { default: diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp index edd20900d810e..e98887e677bed 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp @@ -839,7 +839,7 @@ class WebAssemblyAsmParser final : public MCTargetAsmParser { if (Op0.getImm() == -1) Op0.setImm(Align); } - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); if (CurrentState == EndFunction) { onEndOfFunction(); } else { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp index 975234e1fed32..be2be2c952392 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp @@ -315,7 +315,7 @@ void WebAssemblyAsmPrinter::emitFunctionBodyStart() { AsmPrinter::emitFunctionBodyStart(); } -void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void WebAssemblyAsmPrinter::emitInstruction(const MachineInstr *MI) { LLVM_DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n'); switch (MI->getOpcode()) { diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h index fd4b03b63f792..883320806d3ea 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h @@ -63,7 +63,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyAsmPrinter final : public AsmPrinter { void emitJumpTableInfo() override; void emitConstantPool() override; void emitFunctionBodyStart() override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index ea4d23d03f292..78562bd1de471 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -930,9 +930,9 @@ class X86AsmParser : public MCTargetAsmParser { bool validateInstruction(MCInst &Inst, const OperandVector &Ops); bool processInstruction(MCInst &Inst, const OperandVector &Ops); - /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds + /// Wrapper around MCStreamer::emitInstruction(). Possibly adds /// instrumentation around Inst. - void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out); + void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out); bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -3149,9 +3149,9 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { static const char *getSubtargetFeatureName(uint64_t Val); -void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands, +void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out) { - Out.EmitInstruction(Inst, getSTI()); + Out.emitInstruction(Inst, getSTI()); } bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, @@ -3186,7 +3186,7 @@ void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, Inst.setOpcode(X86::WAIT); Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - EmitInstruction(Inst, Operands, Out); + emitInstruction(Inst, Operands, Out); Operands[0] = X86Operand::CreateToken(Repl, IDLoc); } } @@ -3293,7 +3293,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - EmitInstruction(Inst, Operands, Out); + emitInstruction(Inst, Operands, Out); Opcode = Inst.getOpcode(); return false; case Match_InvalidImmUnsignedi4: { @@ -3362,7 +3362,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, if (NumSuccessfulMatches == 1) { Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - EmitInstruction(Inst, Operands, Out); + emitInstruction(Inst, Operands, Out); Opcode = Inst.getOpcode(); return false; } @@ -3615,7 +3615,7 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, ; Inst.setLoc(IDLoc); if (!MatchingInlineAsm) - EmitInstruction(Inst, Operands, Out); + emitInstruction(Inst, Operands, Out); Opcode = Inst.getOpcode(); return false; } else if (NumSuccessfulMatches > 1) { diff --git a/llvm/lib/Target/X86/X86AsmPrinter.h b/llvm/lib/Target/X86/X86AsmPrinter.h index 29ea0c052bb20..55da096af44ec 100644 --- a/llvm/lib/Target/X86/X86AsmPrinter.h +++ b/llvm/lib/Target/X86/X86AsmPrinter.h @@ -127,7 +127,7 @@ class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter { void emitEndOfAsmFile(Module &M) override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void emitBasicBlockEnd(const MachineBasicBlock &MBB) override { AsmPrinter::emitBasicBlockEnd(MBB); diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index dd5d56b1ac5a1..439f5e16728fc 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -121,7 +121,7 @@ void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding( } void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) { - OutStreamer->EmitInstruction(Inst, getSubtargetInfo()); + OutStreamer->emitInstruction(Inst, getSubtargetInfo()); SMShadowTracker.count(Inst, getSubtargetInfo(), CodeEmitter.get()); } @@ -1077,7 +1077,7 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) { if (!Is64Bit) { // TODO Do additional checking if the CPU supports multi-byte nops. - OS.EmitInstruction(MCInstBuilder(X86::NOOP), STI); + OS.emitInstruction(MCInstBuilder(X86::NOOP), STI); return 1; } @@ -1156,14 +1156,14 @@ static unsigned EmitNop(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, switch (Opc) { default: llvm_unreachable("Unexpected opcode"); case X86::NOOP: - OS.EmitInstruction(MCInstBuilder(Opc), STI); + OS.emitInstruction(MCInstBuilder(Opc), STI); break; case X86::XCHG16ar: - OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); + OS.emitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); break; case X86::NOOPL: case X86::NOOPW: - OS.EmitInstruction(MCInstBuilder(Opc) + OS.emitInstruction(MCInstBuilder(Opc) .addReg(BaseReg) .addImm(ScaleVal) .addReg(IndexReg) @@ -1238,7 +1238,7 @@ void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI, MCInst CallInst; CallInst.setOpcode(CallOpcode); CallInst.addOperand(CallTargetMCOp); - OutStreamer->EmitInstruction(CallInst, getSubtargetInfo()); + OutStreamer->emitInstruction(CallInst, getSubtargetInfo()); } // Record our statepoint node in the same section used by STACKMAP @@ -1283,7 +1283,7 @@ void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI, MI.addOperand(MaybeOperand.getValue()); OutStreamer->AddComment("on-fault: " + HandlerLabel->getName()); - OutStreamer->EmitInstruction(MI, getSubtargetInfo()); + OutStreamer->emitInstruction(MI, getSubtargetInfo()); } void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, @@ -1335,7 +1335,7 @@ void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI, } } - OutStreamer->EmitInstruction(MCI, getSubtargetInfo()); + OutStreamer->emitInstruction(MCI, getSubtargetInfo()); } // Lower a stackmap of the form: @@ -1681,7 +1681,7 @@ void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI, for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) Ret.addOperand(MaybeOperand.getValue()); - OutStreamer->EmitInstruction(Ret, getSubtargetInfo()); + OutStreamer->emitInstruction(Ret, getSubtargetInfo()); EmitNops(*OutStreamer, 10, Subtarget->is64Bit(), getSubtargetInfo()); recordSled(CurSled, MI, SledKind::FUNCTION_EXIT); } @@ -1720,7 +1720,7 @@ void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, for (auto &MO : make_range(MI.operands_begin() + 1, MI.operands_end())) if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, MO)) TC.addOperand(MaybeOperand.getValue()); - OutStreamer->EmitInstruction(TC, getSubtargetInfo()); + OutStreamer->emitInstruction(TC, getSubtargetInfo()); } // Returns instruction preceding MBBI in MachineFunction. @@ -1964,7 +1964,7 @@ static unsigned getRegisterWidth(const MCOperandInfo &Info) { llvm_unreachable("Unknown register class!"); } -void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { +void X86AsmPrinter::emitInstruction(const MachineInstr *MI) { X86MCInstLower MCInstLowering(*MF, *this); const X86RegisterInfo *RI = MF->getSubtarget().getRegisterInfo(); @@ -2137,7 +2137,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { int stackGrowth = -RI->getSlotSize(); if (HasActiveDwarfFrame && !hasFP) { - OutStreamer->EmitCFIAdjustCfaOffset(-stackGrowth); + OutStreamer->emitCFIAdjustCfaOffset(-stackGrowth); } // Emit the label. @@ -2148,7 +2148,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); if (HasActiveDwarfFrame && !hasFP) { - OutStreamer->EmitCFIAdjustCfaOffset(stackGrowth); + OutStreamer->emitCFIAdjustCfaOffset(stackGrowth); } return; } @@ -2655,7 +2655,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { // after it. SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo()); // Then emit the call - OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo()); + OutStreamer->emitInstruction(TmpInst, getSubtargetInfo()); return; } diff --git a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp index 22ddc7919bb80..6c96f66a391b0 100644 --- a/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp +++ b/llvm/lib/Target/XCore/XCoreAsmPrinter.cpp @@ -75,7 +75,7 @@ namespace { void emitGlobalVariable(const GlobalVariable *GV) override; void emitFunctionEntryLabel() override; - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void emitFunctionBodyStart() override; void emitFunctionBodyEnd() override; }; @@ -255,7 +255,7 @@ bool XCoreAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void XCoreAsmPrinter::emitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream O(Str); diff --git a/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp b/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp index 7941bfa90000b..259ed14a57edf 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetFile.cpp @@ -35,7 +35,7 @@ class BenchmarkCodeStreamer : public MCStreamer, public AsmCommentConsumer { // Implementation of the MCStreamer interface. We only care about // instructions. - void EmitInstruction(const MCInst &Instruction, + void emitInstruction(const MCInst &Instruction, const MCSubtargetInfo &STI) override { Result->Key.Instructions.push_back(Instruction); } diff --git a/llvm/tools/llvm-mc/Disassembler.cpp b/llvm/tools/llvm-mc/Disassembler.cpp index e286c0fff6e15..16ab99548adfc 100644 --- a/llvm/tools/llvm-mc/Disassembler.cpp +++ b/llvm/tools/llvm-mc/Disassembler.cpp @@ -68,7 +68,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm, LLVM_FALLTHROUGH; case MCDisassembler::Success: - Streamer.EmitInstruction(Inst, STI); + Streamer.emitInstruction(Inst, STI); break; } } diff --git a/llvm/tools/llvm-mca/CodeRegionGenerator.cpp b/llvm/tools/llvm-mca/CodeRegionGenerator.cpp index 8ddcd2f4abe21..e9ef085827fa7 100644 --- a/llvm/tools/llvm-mca/CodeRegionGenerator.cpp +++ b/llvm/tools/llvm-mca/CodeRegionGenerator.cpp @@ -47,8 +47,8 @@ class MCStreamerWrapper final : public MCStreamer { : MCStreamer(Context), Regions(R) {} // We only want to intercept the emission of new instructions. - virtual void EmitInstruction(const MCInst &Inst, - const MCSubtargetInfo &/* unused */) override { + virtual void emitInstruction(const MCInst &Inst, + const MCSubtargetInfo & /* unused */) override { Regions.addInstruction(Inst); } diff --git a/llvm/tools/llvm-ml/Disassembler.cpp b/llvm/tools/llvm-ml/Disassembler.cpp index 08cd5e4c43830..8eeddb7179c66 100644 --- a/llvm/tools/llvm-ml/Disassembler.cpp +++ b/llvm/tools/llvm-ml/Disassembler.cpp @@ -64,7 +64,7 @@ static bool PrintInsts(const MCDisassembler &DisAsm, const ByteArrayTy &Bytes, LLVM_FALLTHROUGH; case MCDisassembler::Success: - Streamer.EmitInstruction(Inst, STI); + Streamer.emitInstruction(Inst, STI); break; } } From 65e843c9e0b91d5ac156130f61b378bad2e8e2fd Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 14 Feb 2020 08:33:42 +0100 Subject: [PATCH 39/57] [lldb] Add a test for launch failure and its error message --- .../gdb_remote_client/TestGDBRemoteClient.py | 24 +++++++++++++++++++ .../gdb_remote_client/gdbclientutils.py | 5 ++++ 2 files changed, 29 insertions(+) diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py index 8f0ed9a4933da..238a4559d6fbb 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py @@ -50,6 +50,30 @@ def vAttach(self, pid): target.AttachToProcessWithID(lldb.SBListener(), 47, error) self.assertEquals(error_msg, error.GetCString()) + def test_launch_fail(self): + class MyResponder(MockGDBServerResponder): + # Pretend we don't have any process during the initial queries. + def qC(self): + return "E42" + + def qfThreadInfo(self): + return "OK" # No threads. + + # Then, when we are asked to attach, error out. + def A(self, packet): + return "E47" + + self.server.responder = MyResponder() + + target = self.createTarget("a.yaml") + process = self.connect(target) + lldbutil.expect_state_changes(self, self.dbg.GetListener(), process, [lldb.eStateConnected]) + + error = lldb.SBError() + target.Launch(lldb.SBListener(), None, None, None, None, None, + None, 0, True, error) + self.assertEquals("process launch failed: 'A' packet returned an error: 71", error.GetCString()) + def test_read_registers_using_g_packets(self): """Test reading registers using 'g' packets (default behavior)""" self.dbg.HandleCommand( diff --git a/lldb/test/API/functionalities/gdb_remote_client/gdbclientutils.py b/lldb/test/API/functionalities/gdb_remote_client/gdbclientutils.py index 392aeba5bd688..486485c8e28db 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/gdbclientutils.py +++ b/lldb/test/API/functionalities/gdb_remote_client/gdbclientutils.py @@ -106,6 +106,8 @@ def respond(self, packet): return self.cont() if packet.startswith("vCont;c"): return self.vCont(packet) + if packet[0] == "A": + return self.A(packet) if packet[0] == "g": return self.readRegisters() if packet[0] == "G": @@ -201,6 +203,9 @@ def cont(self): def vCont(self, packet): raise self.UnexpectedPacketException() + def A(self, packet): + return "" + def readRegisters(self): return "00000000" * self.registerCount From b7d6640ba9812ec74a0f86ae7bc9850332f5fd2b Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Fri, 14 Feb 2020 11:22:29 +0300 Subject: [PATCH 40/57] [NFC][clang-tidy] Move recently newly-added tests into checkers/ subdir That's where nowadays those tests reside, those outliers were created before the migration but committed after, so they just awkwardly reside in the old place. --- .../not-null-terminated-result-c.h | 0 .../not-null-terminated-result-cxx.h | 0 .../{ => checkers}/bugprone-bad-signal-to-kill-thread.cpp | 0 ...bugprone-not-null-terminated-result-in-initialization-strlen.c | 0 .../bugprone-not-null-terminated-result-memcpy-before-safe.c | 0 .../bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp | 0 .../bugprone-not-null-terminated-result-memcpy-safe-other.c | 0 .../bugprone-not-null-terminated-result-memcpy-safe.c | 0 .../{ => checkers}/bugprone-not-null-terminated-result-strlen.c | 0 .../{ => checkers}/bugprone-not-null-terminated-result-wcslen.cpp | 0 .../bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp | 0 .../{ => checkers}/bugprone-suspicious-semicolon-constexpr.cpp | 0 .../{ => checkers}/readability-magic-numbers-userliteral.cpp | 0 .../{ => checkers}/readability-make-member-function-const.cpp | 0 ...bility-redundant-access-specifiers-check-first-declaration.cpp | 0 .../{ => checkers}/readability-redundant-access-specifiers.cpp | 0 16 files changed, 0 insertions(+), 0 deletions(-) rename clang-tools-extra/test/clang-tidy/{ => checkers}/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-c.h (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-cxx.h (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-bad-signal-to-kill-thread.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-in-initialization-strlen.c (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-memcpy-before-safe.c (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-memcpy-safe-other.c (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-memcpy-safe.c (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-strlen.c (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-wcslen.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/bugprone-suspicious-semicolon-constexpr.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/readability-magic-numbers-userliteral.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/readability-make-member-function-const.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/readability-redundant-access-specifiers-check-first-declaration.cpp (100%) rename clang-tools-extra/test/clang-tidy/{ => checkers}/readability-redundant-access-specifiers.cpp (100%) diff --git a/clang-tools-extra/test/clang-tidy/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-c.h b/clang-tools-extra/test/clang-tidy/checkers/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-c.h similarity index 100% rename from clang-tools-extra/test/clang-tidy/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-c.h rename to clang-tools-extra/test/clang-tidy/checkers/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-c.h diff --git a/clang-tools-extra/test/clang-tidy/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-cxx.h b/clang-tools-extra/test/clang-tidy/checkers/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-cxx.h similarity index 100% rename from clang-tools-extra/test/clang-tidy/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-cxx.h rename to clang-tools-extra/test/clang-tidy/checkers/Inputs/bugprone-not-null-terminated-result/not-null-terminated-result-cxx.h diff --git a/clang-tools-extra/test/clang-tidy/bugprone-bad-signal-to-kill-thread.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-bad-signal-to-kill-thread.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-bad-signal-to-kill-thread.cpp rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-bad-signal-to-kill-thread.cpp diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-in-initialization-strlen.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-in-initialization-strlen.c similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-in-initialization-strlen.c rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-in-initialization-strlen.c diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-before-safe.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-before-safe.c similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-before-safe.c rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-before-safe.c diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe-cxx.cpp diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe-other.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe-other.c similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe-other.c rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe-other.c diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe.c similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-memcpy-safe.c rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-memcpy-safe.c diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-strlen.c b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-strlen.c similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-strlen.c rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-strlen.c diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-wcslen.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-wcslen.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-wcslen.cpp rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-wcslen.cpp diff --git a/clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-not-null-terminated-result-wmemcpy-safe-cxx.cpp diff --git a/clang-tools-extra/test/clang-tidy/bugprone-suspicious-semicolon-constexpr.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/bugprone-suspicious-semicolon-constexpr.cpp rename to clang-tools-extra/test/clang-tidy/checkers/bugprone-suspicious-semicolon-constexpr.cpp diff --git a/clang-tools-extra/test/clang-tidy/readability-magic-numbers-userliteral.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-magic-numbers-userliteral.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/readability-magic-numbers-userliteral.cpp rename to clang-tools-extra/test/clang-tidy/checkers/readability-magic-numbers-userliteral.cpp diff --git a/clang-tools-extra/test/clang-tidy/readability-make-member-function-const.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-make-member-function-const.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/readability-make-member-function-const.cpp rename to clang-tools-extra/test/clang-tidy/checkers/readability-make-member-function-const.cpp diff --git a/clang-tools-extra/test/clang-tidy/readability-redundant-access-specifiers-check-first-declaration.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-access-specifiers-check-first-declaration.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/readability-redundant-access-specifiers-check-first-declaration.cpp rename to clang-tools-extra/test/clang-tidy/checkers/readability-redundant-access-specifiers-check-first-declaration.cpp diff --git a/clang-tools-extra/test/clang-tidy/readability-redundant-access-specifiers.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-redundant-access-specifiers.cpp similarity index 100% rename from clang-tools-extra/test/clang-tidy/readability-redundant-access-specifiers.cpp rename to clang-tools-extra/test/clang-tidy/checkers/readability-redundant-access-specifiers.cpp From fd01b2f4a6c44acf68756b0f6f631a999d02354d Mon Sep 17 00:00:00 2001 From: Sam Parker Date: Fri, 14 Feb 2020 08:28:26 +0000 Subject: [PATCH 41/57] [NFC][ARM] Convert some pointers to references. --- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 54 ++++++++++----------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index cdd1cb2efc1ce..fde9fa9f82b8e 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -175,9 +175,9 @@ namespace { struct LowOverheadLoop { - MachineLoop *ML = nullptr; - MachineLoopInfo *MLI = nullptr; - ReachingDefAnalysis *RDA = nullptr; + MachineLoop &ML; + MachineLoopInfo &MLI; + ReachingDefAnalysis &RDA; MachineFunction *MF = nullptr; MachineInstr *InsertPt = nullptr; MachineInstr *Start = nullptr; @@ -191,9 +191,9 @@ namespace { bool Revert = false; bool CannotTailPredicate = false; - LowOverheadLoop(MachineLoop *ML, MachineLoopInfo *MLI, - ReachingDefAnalysis *RDA) : ML(ML), MLI(MLI), RDA(RDA) { - MF = ML->getHeader()->getParent(); + LowOverheadLoop(MachineLoop &ML, MachineLoopInfo &MLI, + ReachingDefAnalysis &RDA) : ML(ML), MLI(MLI), RDA(RDA) { + MF = ML.getHeader()->getParent(); } // If this is an MVE instruction, check that we know how to use tail @@ -209,7 +209,7 @@ namespace { // For now, let's keep things really simple and only support a single // block for tail predication. return !Revert && FoundAllComponents() && VCTP && - !CannotTailPredicate && ML->getNumBlocks() == 1; + !CannotTailPredicate && ML.getNumBlocks() == 1; } bool ValidateTailPredicate(MachineInstr *StartInsertPt); @@ -333,19 +333,19 @@ MachineInstr *LowOverheadLoop::isSafeToDefineLR() { // Find an insertion point: // - Is there a (mov lr, Count) before Start? If so, and nothing else writes // to Count before Start, we can insert at that mov. - if (auto *LRDef = RDA->getReachingMIDef(Start, ARM::LR)) - if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) + if (auto *LRDef = RDA.getReachingMIDef(Start, ARM::LR)) + if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) return LRDef; // - Is there a (mov lr, Count) after Start? If so, and nothing else writes // to Count after Start, we can insert at that mov. - if (auto *LRDef = RDA->getLocalLiveOutMIDef(MBB, ARM::LR)) - if (IsMoveLR(LRDef) && RDA->hasSameReachingDef(Start, LRDef, CountReg)) + if (auto *LRDef = RDA.getLocalLiveOutMIDef(MBB, ARM::LR)) + if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) return LRDef; // We've found no suitable LR def and Start doesn't use LR directly. Can we // just define LR anyway? - return RDA->isSafeToDefRegAt(Start, ARM::LR) ? Start : nullptr; + return RDA.isSafeToDefRegAt(Start, ARM::LR) ? Start : nullptr; } bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { @@ -382,7 +382,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { // If the register is defined within loop, then we can't perform TP. // TODO: Check whether this is just a mov of a register that would be // available. - if (RDA->hasLocalDefBefore(VCTP, NumElements)) { + if (RDA.hasLocalDefBefore(VCTP, NumElements)) { LLVM_DEBUG(dbgs() << "ARM Loops: VCTP operand is defined in the loop.\n"); return false; } @@ -393,14 +393,14 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { // TODO: On failing to move an instruction, check if the count is provided by // a mov and whether we can use the mov operand directly. MachineBasicBlock *InsertBB = StartInsertPt->getParent(); - if (!RDA->isReachingDefLiveOut(StartInsertPt, NumElements)) { - if (auto *ElemDef = RDA->getLocalLiveOutMIDef(InsertBB, NumElements)) { - if (RDA->isSafeToMoveForwards(ElemDef, StartInsertPt)) { + if (!RDA.isReachingDefLiveOut(StartInsertPt, NumElements)) { + if (auto *ElemDef = RDA.getLocalLiveOutMIDef(InsertBB, NumElements)) { + if (RDA.isSafeToMoveForwards(ElemDef, StartInsertPt)) { ElemDef->removeFromParent(); InsertBB->insert(MachineBasicBlock::iterator(StartInsertPt), ElemDef); LLVM_DEBUG(dbgs() << "ARM Loops: Moved element count def: " << *ElemDef); - } else if (RDA->isSafeToMoveBackwards(StartInsertPt, ElemDef)) { + } else if (RDA.isSafeToMoveBackwards(StartInsertPt, ElemDef)) { StartInsertPt->removeFromParent(); InsertBB->insertAfter(MachineBasicBlock::iterator(ElemDef), StartInsertPt); @@ -419,7 +419,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { auto CannotProvideElements = [this](MachineBasicBlock *MBB, Register NumElements) { // NumElements is redefined in this block. - if (RDA->hasLocalDefBefore(&MBB->back(), NumElements)) + if (RDA.hasLocalDefBefore(&MBB->back(), NumElements)) return true; // Don't continue searching up through multiple predecessors. @@ -430,7 +430,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { }; // First, find the block that looks like the preheader. - MachineBasicBlock *MBB = MLI->findLoopPreheader(ML, true); + MachineBasicBlock *MBB = MLI.findLoopPreheader(&ML, true); if (!MBB) { LLVM_DEBUG(dbgs() << "ARM Loops: Didn't find preheader.\n"); return false; @@ -467,12 +467,12 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) { }; MBB = VCTP->getParent(); - if (MachineInstr *Def = RDA->getReachingMIDef(&MBB->back(), NumElements)) { + if (MachineInstr *Def = RDA.getReachingMIDef(&MBB->back(), NumElements)) { SmallPtrSet ElementChain; SmallPtrSet Ignore = { VCTP }; unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode()); - if (RDA->isSafeToRemove(Def, ElementChain, Ignore)) { + if (RDA.isSafeToRemove(Def, ElementChain, Ignore)) { bool FoundSub = false; for (auto *MI : ElementChain) { @@ -505,7 +505,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) { // TODO Maybe there's cases where the target doesn't have to be the header, // but for now be safe and revert. - if (End->getOperand(1).getMBB() != ML->getHeader()) { + if (End->getOperand(1).getMBB() != ML.getHeader()) { LLVM_DEBUG(dbgs() << "ARM Loops: LoopEnd is not targetting header.\n"); Revert = true; return; @@ -513,8 +513,8 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) { // The WLS and LE instructions have 12-bits for the label offset. WLS // requires a positive offset, while LE uses negative. - if (BBUtils->getOffsetOf(End) < BBUtils->getOffsetOf(ML->getHeader()) || - !BBUtils->isBBInRange(End, ML->getHeader(), 4094)) { + if (BBUtils->getOffsetOf(End) < BBUtils->getOffsetOf(ML.getHeader()) || + !BBUtils->isBBInRange(End, ML.getHeader(), 4094)) { LLVM_DEBUG(dbgs() << "ARM Loops: LE offset is out-of-range\n"); Revert = true; return; @@ -544,7 +544,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) { return; } - assert(ML->getBlocks().size() == 1 && + assert(ML.getBlocks().size() == 1 && "Shouldn't be processing a loop with more than one block"); CannotTailPredicate = !ValidateTailPredicate(InsertPt); LLVM_DEBUG(if (CannotTailPredicate) @@ -682,7 +682,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) { return nullptr; }; - LowOverheadLoop LoLoop(ML, MLI, RDA); + LowOverheadLoop LoLoop(*ML, *MLI, *RDA); // Search the preheader for the start intrinsic. // FIXME: I don't see why we shouldn't be supporting multiple predecessors // with potentially multiple set.loop.iterations, so we need to enable this. @@ -1073,7 +1073,7 @@ void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) { } } - PostOrderLoopTraversal DFS(*LoLoop.ML, *MLI); + PostOrderLoopTraversal DFS(LoLoop.ML, *MLI); DFS.ProcessLoop(); const SmallVectorImpl &PostOrder = DFS.getOrder(); for (auto *MBB : PostOrder) { From 1674f772b4ea67f62cb93536143107ef2bd25b7f Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Fri, 14 Feb 2020 09:29:56 +0100 Subject: [PATCH 42/57] [VecotrCombine] Fix unused variable for assertion disabled builds --- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index a70d962a8f485..f5a26d012de96 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -107,8 +107,6 @@ static bool foldExtractBinop(Instruction &I, const TargetTransformInfo &TTI) { int VecBOCost = TTI.getArithmeticInstrCost(BOpcode, VecTy); int Extract0Cost = TTI.getVectorInstrCost(Instruction::ExtractElement, VecTy, C0); - int Extract1Cost = TTI.getVectorInstrCost(Instruction::ExtractElement, - VecTy, C1); // Handle a special case - if the extract indexes are the same, the // replacement sequence does not require a shuffle. Unless the vector binop is @@ -116,7 +114,9 @@ static bool foldExtractBinop(Instruction &I, const TargetTransformInfo &TTI) { // Extra uses of the extracts mean that we include those costs in the // vector total because those instructions will not be eliminated. if (C0 == C1) { - assert(Extract0Cost == Extract1Cost && "Different costs for same extract?"); + assert(Extract0Cost == + TTI.getVectorInstrCost(Instruction::ExtractElement, VecTy, C1) && + "Different costs for same extract?"); int ExtractCost = Extract0Cost; if (X != Y) { int ScalarCost = ExtractCost + ExtractCost + ScalarBOCost; From 60431bd728f73544a8c3507a9461ec13b53ced74 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Fri, 14 Feb 2020 09:31:06 +0100 Subject: [PATCH 43/57] [VE] Support for PIC (global data and calls) Summary: Support for PIC with tests for global variables and function calls. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D74536 --- .../lib/Target/VE/MCTargetDesc/VEFixupKinds.h | 22 ++ llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp | 56 +++++ llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h | 8 + llvm/lib/Target/VE/VEAsmPrinter.cpp | 194 ++++++++++++++++++ llvm/lib/Target/VE/VEISelDAGToDAG.cpp | 16 ++ llvm/lib/Target/VE/VEISelLowering.cpp | 81 +++++++- llvm/lib/Target/VE/VEISelLowering.h | 4 +- llvm/lib/Target/VE/VEInstrInfo.cpp | 20 ++ llvm/lib/Target/VE/VEInstrInfo.h | 2 + llvm/lib/Target/VE/VEInstrInfo.td | 40 ++++ llvm/lib/Target/VE/VEMachineFunctionInfo.h | 10 +- llvm/test/CodeGen/VE/pic_access_data.ll | 39 ++++ .../test/CodeGen/VE/pic_access_static_data.ll | 79 +++++++ llvm/test/CodeGen/VE/pic_func_call.ll | 21 ++ .../test/CodeGen/VE/pic_indirect_func_call.ll | 34 +++ 15 files changed, 614 insertions(+), 12 deletions(-) create mode 100644 llvm/test/CodeGen/VE/pic_access_data.ll create mode 100644 llvm/test/CodeGen/VE/pic_access_static_data.ll create mode 100644 llvm/test/CodeGen/VE/pic_func_call.ll create mode 100644 llvm/test/CodeGen/VE/pic_indirect_func_call.ll diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h b/llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h index 65d850c6a1de4..2d796699a3cf7 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h @@ -20,6 +20,28 @@ enum Fixups { /// fixup_ve_lo32 - 32-bit fixup corresponding to foo@lo fixup_ve_lo32, + /// fixup_ve_pc_hi32 - 32-bit fixup corresponding to foo@pc_hi + fixup_ve_pc_hi32, + + /// fixup_ve_pc_lo32 - 32-bit fixup corresponding to foo@pc_lo + fixup_ve_pc_lo32, + + /// fixup_ve_got_hi32 - 32-bit fixup corresponding to foo@got_hi + fixup_ve_got_hi32, + + /// fixup_ve_got_lo32 - 32-bit fixup corresponding to foo@got_lo + fixup_ve_got_lo32, + + /// fixup_ve_gotoff_hi32 - 32-bit fixup corresponding to foo@gotoff_hi + fixup_ve_gotoff_hi32, + + /// fixup_ve_gotoff_lo32 - 32-bit fixup corresponding to foo@gotoff_lo + fixup_ve_gotoff_lo32, + + /// fixup_ve_plt_hi32/lo32 + fixup_ve_plt_hi32, + fixup_ve_plt_lo32, + // Marker LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp index 6782323832932..abb490eb12746 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.cpp @@ -46,6 +46,14 @@ bool VEMCExpr::printVariantKind(raw_ostream &OS, VariantKind Kind) { case VK_VE_HI32: case VK_VE_LO32: + case VK_VE_PC_HI32: + case VK_VE_PC_LO32: + case VK_VE_GOT_HI32: + case VK_VE_GOT_LO32: + case VK_VE_GOTOFF_HI32: + case VK_VE_GOTOFF_LO32: + case VK_VE_PLT_HI32: + case VK_VE_PLT_LO32: return false; // OS << "@("; break; } return true; @@ -61,6 +69,30 @@ void VEMCExpr::printVariantKindSuffix(raw_ostream &OS, VariantKind Kind) { case VK_VE_LO32: OS << "@lo"; break; + case VK_VE_PC_HI32: + OS << "@pc_hi"; + break; + case VK_VE_PC_LO32: + OS << "@pc_lo"; + break; + case VK_VE_GOT_HI32: + OS << "@got_hi"; + break; + case VK_VE_GOT_LO32: + OS << "@got_lo"; + break; + case VK_VE_GOTOFF_HI32: + OS << "@gotoff_hi"; + break; + case VK_VE_GOTOFF_LO32: + OS << "@gotoff_lo"; + break; + case VK_VE_PLT_HI32: + OS << "@plt_hi"; + break; + case VK_VE_PLT_LO32: + OS << "@plt_lo"; + break; } } @@ -68,6 +100,14 @@ VEMCExpr::VariantKind VEMCExpr::parseVariantKind(StringRef name) { return StringSwitch(name) .Case("hi", VK_VE_HI32) .Case("lo", VK_VE_LO32) + .Case("pc_hi", VK_VE_PC_HI32) + .Case("pc_lo", VK_VE_PC_LO32) + .Case("got_hi", VK_VE_GOT_HI32) + .Case("got_lo", VK_VE_GOT_LO32) + .Case("gotoff_hi", VK_VE_GOTOFF_HI32) + .Case("gotoff_lo", VK_VE_GOTOFF_LO32) + .Case("plt_hi", VK_VE_PLT_HI32) + .Case("plt_lo", VK_VE_PLT_LO32) .Default(VK_VE_None); } @@ -79,6 +119,22 @@ VE::Fixups VEMCExpr::getFixupKind(VEMCExpr::VariantKind Kind) { return VE::fixup_ve_hi32; case VK_VE_LO32: return VE::fixup_ve_lo32; + case VK_VE_PC_HI32: + return VE::fixup_ve_pc_hi32; + case VK_VE_PC_LO32: + return VE::fixup_ve_pc_lo32; + case VK_VE_GOT_HI32: + return VE::fixup_ve_got_hi32; + case VK_VE_GOT_LO32: + return VE::fixup_ve_got_lo32; + case VK_VE_GOTOFF_HI32: + return VE::fixup_ve_gotoff_hi32; + case VK_VE_GOTOFF_LO32: + return VE::fixup_ve_gotoff_lo32; + case VK_VE_PLT_HI32: + return VE::fixup_ve_plt_hi32; + case VK_VE_PLT_LO32: + return VE::fixup_ve_plt_lo32; } } diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h b/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h index d8515608d7b7c..8e884443e41ff 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h @@ -26,6 +26,14 @@ class VEMCExpr : public MCTargetExpr { VK_VE_None, VK_VE_HI32, VK_VE_LO32, + VK_VE_PC_HI32, + VK_VE_PC_LO32, + VK_VE_GOT_HI32, + VK_VE_GOT_LO32, + VK_VE_GOTOFF_HI32, + VK_VE_GOTOFF_LO32, + VK_VE_PLT_HI32, + VK_VE_PLT_LO32, }; private: diff --git a/llvm/lib/Target/VE/VEAsmPrinter.cpp b/llvm/lib/Target/VE/VEAsmPrinter.cpp index c1e0cc3c422ad..6e6acffcb4027 100644 --- a/llvm/lib/Target/VE/VEAsmPrinter.cpp +++ b/llvm/lib/Target/VE/VEAsmPrinter.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "InstPrinter/VEInstPrinter.h" +#include "MCTargetDesc/VEMCExpr.h" #include "MCTargetDesc/VETargetStreamer.h" #include "VE.h" #include "VEInstrInfo.h" @@ -46,6 +47,11 @@ class VEAsmPrinter : public AsmPrinter { StringRef getPassName() const override { return "VE Assembly Printer"; } + void lowerGETGOTAndEmitMCInsts(const MachineInstr *MI, + const MCSubtargetInfo &STI); + void lowerGETFunPLTAndEmitMCInsts(const MachineInstr *MI, + const MCSubtargetInfo &STI); + void emitInstruction(const MachineInstr *MI) override; static const char *getRegisterName(unsigned RegNo) { @@ -54,6 +60,187 @@ class VEAsmPrinter : public AsmPrinter { }; } // end of anonymous namespace +static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym, + MCContext &OutContext) { + const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::create(Sym, OutContext); + const VEMCExpr *expr = VEMCExpr::create(Kind, MCSym, OutContext); + return MCOperand::createExpr(expr); +} + +static MCOperand createGOTRelExprOp(VEMCExpr::VariantKind Kind, + MCSymbol *GOTLabel, MCContext &OutContext) { + const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext); + const VEMCExpr *expr = VEMCExpr::create(Kind, GOT, OutContext); + return MCOperand::createExpr(expr); +} + +static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst SICInst; + SICInst.setOpcode(VE::SIC); + SICInst.addOperand(RD); + OutStreamer.emitInstruction(SICInst, STI); +} + +static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst LEAInst; + LEAInst.setOpcode(VE::LEAzzi); + LEAInst.addOperand(RD); + LEAInst.addOperand(Imm); + OutStreamer.emitInstruction(LEAInst, STI); +} + +static void emitLEASLzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst LEASLInst; + LEASLInst.setOpcode(VE::LEASLzzi); + LEASLInst.addOperand(RD); + LEASLInst.addOperand(Imm); + OutStreamer.emitInstruction(LEASLInst, STI); +} + +static void emitLEAzii(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, + MCOperand &RD, const MCSubtargetInfo &STI) { + MCInst LEAInst; + LEAInst.setOpcode(VE::LEAzii); + LEAInst.addOperand(RD); + LEAInst.addOperand(RS1); + LEAInst.addOperand(Imm); + OutStreamer.emitInstruction(LEAInst, STI); +} + +static void emitLEASLrri(MCStreamer &OutStreamer, MCOperand &RS1, + MCOperand &RS2, MCOperand &Imm, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst LEASLInst; + LEASLInst.setOpcode(VE::LEASLrri); + LEASLInst.addOperand(RS1); + LEASLInst.addOperand(RS2); + LEASLInst.addOperand(RD); + LEASLInst.addOperand(Imm); + OutStreamer.emitInstruction(LEASLInst, STI); +} + +static void emitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, + MCOperand &Src2, MCOperand &RD, + const MCSubtargetInfo &STI) { + MCInst Inst; + Inst.setOpcode(Opcode); + Inst.addOperand(RD); + Inst.addOperand(RS1); + Inst.addOperand(Src2); + OutStreamer.emitInstruction(Inst, STI); +} + +static void emitANDrm0(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, + MCOperand &RD, const MCSubtargetInfo &STI) { + emitBinary(OutStreamer, VE::ANDrm0, RS1, Imm, RD, STI); +} + +static void emitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, + VEMCExpr::VariantKind HiKind, VEMCExpr::VariantKind LoKind, + MCOperand &RD, MCContext &OutContext, + const MCSubtargetInfo &STI) { + + MCOperand hi = createVEMCOperand(HiKind, GOTSym, OutContext); + MCOperand lo = createVEMCOperand(LoKind, GOTSym, OutContext); + MCOperand ci32 = MCOperand::createImm(32); + emitLEAzzi(OutStreamer, lo, RD, STI); + emitANDrm0(OutStreamer, RD, ci32, RD, STI); + emitLEASLzzi(OutStreamer, hi, RD, STI); +} + +void VEAsmPrinter::lowerGETGOTAndEmitMCInsts(const MachineInstr *MI, + const MCSubtargetInfo &STI) { + MCSymbol *GOTLabel = + OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); + + const MachineOperand &MO = MI->getOperand(0); + MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); + + if (!isPositionIndependent()) { + // Just load the address of GOT to MCRegOP. + switch (TM.getCodeModel()) { + default: + llvm_unreachable("Unsupported absolute code model"); + case CodeModel::Small: + case CodeModel::Medium: + case CodeModel::Large: + emitHiLo(*OutStreamer, GOTLabel, VEMCExpr::VK_VE_HI32, + VEMCExpr::VK_VE_LO32, MCRegOP, OutContext, STI); + break; + } + return; + } + + MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT + MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT + + // lea %got, _GLOBAL_OFFSET_TABLE_@PC_LO(-24) + // and %got, %got, (32)0 + // sic %plt + // lea.sl %got, _GLOBAL_OFFSET_TABLE_@PC_HI(%got, %plt) + MCOperand cim24 = MCOperand::createImm(-24); + MCOperand loImm = + createGOTRelExprOp(VEMCExpr::VK_VE_PC_LO32, GOTLabel, OutContext); + emitLEAzii(*OutStreamer, cim24, loImm, MCRegOP, STI); + MCOperand ci32 = MCOperand::createImm(32); + emitANDrm0(*OutStreamer, MCRegOP, ci32, MCRegOP, STI); + emitSIC(*OutStreamer, RegPLT, STI); + MCOperand hiImm = + createGOTRelExprOp(VEMCExpr::VK_VE_PC_HI32, GOTLabel, OutContext); + emitLEASLrri(*OutStreamer, RegGOT, RegPLT, hiImm, MCRegOP, STI); +} + +void VEAsmPrinter::lowerGETFunPLTAndEmitMCInsts(const MachineInstr *MI, + const MCSubtargetInfo &STI) { + const MachineOperand &MO = MI->getOperand(0); + MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); + const MachineOperand &Addr = MI->getOperand(1); + MCSymbol *AddrSym = nullptr; + + switch (Addr.getType()) { + default: + llvm_unreachable(""); + return; + case MachineOperand::MO_MachineBasicBlock: + report_fatal_error("MBB is not supported yet"); + return; + case MachineOperand::MO_ConstantPoolIndex: + report_fatal_error("ConstantPool is not supported yet"); + return; + case MachineOperand::MO_ExternalSymbol: + AddrSym = GetExternalSymbolSymbol(Addr.getSymbolName()); + break; + case MachineOperand::MO_GlobalAddress: + AddrSym = getSymbol(Addr.getGlobal()); + break; + } + + if (!isPositionIndependent()) { + llvm_unreachable("Unsupported uses of %plt in not PIC code"); + return; + } + + MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT + + // lea %dst, %plt_lo(func)(-24) + // and %dst, %dst, (32)0 + // sic %plt ; FIXME: is it safe to use %plt here? + // lea.sl %dst, %plt_hi(func)(%dst, %plt) + MCOperand cim24 = MCOperand::createImm(-24); + MCOperand loImm = + createGOTRelExprOp(VEMCExpr::VK_VE_PLT_LO32, AddrSym, OutContext); + emitLEAzii(*OutStreamer, cim24, loImm, MCRegOP, STI); + MCOperand ci32 = MCOperand::createImm(32); + emitANDrm0(*OutStreamer, MCRegOP, ci32, MCRegOP, STI); + emitSIC(*OutStreamer, RegPLT, STI); + MCOperand hiImm = + createGOTRelExprOp(VEMCExpr::VK_VE_PLT_HI32, AddrSym, OutContext); + emitLEASLrri(*OutStreamer, MCRegOP, RegPLT, hiImm, MCRegOP, STI); +} + void VEAsmPrinter::emitInstruction(const MachineInstr *MI) { switch (MI->getOpcode()) { @@ -62,7 +249,14 @@ void VEAsmPrinter::emitInstruction(const MachineInstr *MI) { case TargetOpcode::DBG_VALUE: // FIXME: Debug Value. return; + case VE::GETGOT: + lowerGETGOTAndEmitMCInsts(MI, getSubtargetInfo()); + return; + case VE::GETFUNPLT: + lowerGETFunPLTAndEmitMCInsts(MI, getSubtargetInfo()); + return; } + MachineBasicBlock::const_instr_iterator I = MI->getIterator(); MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end(); do { diff --git a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp index bb7ab594ebc3e..c5c449b89e979 100644 --- a/llvm/lib/Target/VE/VEISelDAGToDAG.cpp +++ b/llvm/lib/Target/VE/VEISelDAGToDAG.cpp @@ -53,6 +53,9 @@ class VEDAGToDAGISel : public SelectionDAGISel { // Include the pieces autogenerated from the target description. #include "VEGenDAGISel.inc" + +private: + SDNode *getGlobalBaseReg(); }; } // end anonymous namespace @@ -119,9 +122,22 @@ void VEDAGToDAGISel::Select(SDNode *N) { return; // Already selected. } + switch (N->getOpcode()) { + case VEISD::GLOBAL_BASE_REG: + ReplaceNode(N, getGlobalBaseReg()); + return; + } + SelectCode(N); } +SDNode *VEDAGToDAGISel::getGlobalBaseReg() { + Register GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); + return CurDAG + ->getRegister(GlobalBaseReg, TLI->getPointerTy(CurDAG->getDataLayout())) + .getNode(); +} + /// createVEISelDag - This pass converts a legalized DAG into a /// VE-specific DAG, ready for instruction scheduling. /// diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index e0411dae1727d..70dc35989ff2d 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -312,16 +312,42 @@ SDValue VETargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Likewise ExternalSymbol -> TargetExternalSymbol. SDValue Callee = CLI.Callee; - assert(!isPositionIndependent() && "TODO PIC"); + bool IsPICCall = isPositionIndependent(); + + // PC-relative references to external symbols should go through $stub. + // If so, we need to prepare GlobalBaseReg first. + const TargetMachine &TM = DAG.getTarget(); + const Module *Mod = DAG.getMachineFunction().getFunction().getParent(); + const GlobalValue *GV = nullptr; + auto *CalleeG = dyn_cast(Callee); + if (CalleeG) + GV = CalleeG->getGlobal(); + bool Local = TM.shouldAssumeDSOLocal(*Mod, GV); + bool UsePlt = !Local; + MachineFunction &MF = DAG.getMachineFunction(); // Turn GlobalAddress/ExternalSymbol node into a value node // containing the address of them here. - if (isa(Callee)) { - Callee = - makeHiLoPair(Callee, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG); - } else if (isa(Callee)) { - Callee = - makeHiLoPair(Callee, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG); + if (CalleeG) { + if (IsPICCall) { + if (UsePlt) + Subtarget->getInstrInfo()->getGlobalBaseReg(&MF); + Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0); + Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee); + } else { + Callee = + makeHiLoPair(Callee, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG); + } + } else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) { + if (IsPICCall) { + if (UsePlt) + Subtarget->getInstrInfo()->getGlobalBaseReg(&MF); + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); + Callee = DAG.getNode(VEISD::GETFUNPLT, DL, PtrVT, Callee); + } else { + Callee = + makeHiLoPair(Callee, VEMCExpr::VK_VE_HI32, VEMCExpr::VK_VE_LO32, DAG); + } } RegsToPass.push_back(std::make_pair(VE::SX12, Callee)); @@ -613,8 +639,10 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const { break; TARGET_NODE_CASE(Lo) TARGET_NODE_CASE(Hi) + TARGET_NODE_CASE(GETFUNPLT) TARGET_NODE_CASE(CALL) TARGET_NODE_CASE(RET_FLAG) + TARGET_NODE_CASE(GLOBAL_BASE_REG) } #undef TARGET_NODE_CASE return nullptr; @@ -658,8 +686,43 @@ SDValue VETargetLowering::makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, // or ExternalSymbol SDNode. SDValue VETargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - - assert(!isPositionIndependent() && "TODO implement PIC"); + EVT PtrVT = Op.getValueType(); + + // Handle PIC mode first. VE needs a got load for every variable! + if (isPositionIndependent()) { + // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this + // function has calls. + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setHasCalls(true); + auto GlobalN = dyn_cast(Op); + + if (isa(Op) || + (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) { + // Create following instructions for local linkage PIC code. + // lea %s35, %gotoff_lo(.LCPI0_0) + // and %s35, %s35, (32)0 + // lea.sl %s35, %gotoff_hi(.LCPI0_0)(%s35) + // adds.l %s35, %s15, %s35 ; %s15 is GOT + // FIXME: use lea.sl %s35, %gotoff_hi(.LCPI0_0)(%s35, %s15) + SDValue HiLo = makeHiLoPair(Op, VEMCExpr::VK_VE_GOTOFF_HI32, + VEMCExpr::VK_VE_GOTOFF_LO32, DAG); + SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT); + return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo); + } + // Create following instructions for not local linkage PIC code. + // lea %s35, %got_lo(.LCPI0_0) + // and %s35, %s35, (32)0 + // lea.sl %s35, %got_hi(.LCPI0_0)(%s35) + // adds.l %s35, %s15, %s35 ; %s15 is GOT + // ld %s35, (,%s35) + // FIXME: use lea.sl %s35, %gotoff_hi(.LCPI0_0)(%s35, %s15) + SDValue HiLo = makeHiLoPair(Op, VEMCExpr::VK_VE_GOT_HI32, + VEMCExpr::VK_VE_GOT_LO32, DAG); + SDValue GlobalBase = DAG.getNode(VEISD::GLOBAL_BASE_REG, DL, PtrVT); + SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, GlobalBase, HiLo); + return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), AbsAddr, + MachinePointerInfo::getGOT(DAG.getMachineFunction())); + } // This is one of the absolute code models. switch (getTargetMachine().getCodeModel()) { diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h index 1fe0122457b3d..0d3796ebb60e9 100644 --- a/llvm/lib/Target/VE/VEISelLowering.h +++ b/llvm/lib/Target/VE/VEISelLowering.h @@ -27,8 +27,10 @@ enum NodeType : unsigned { Hi, Lo, // Hi/Lo operations, typically on a global address. + GETFUNPLT, // load function address through %plt insturction CALL, // A call instruction. - RET_FLAG, // Return with a flag operand. + RET_FLAG, // Return with a flag operand. + GLOBAL_BASE_REG, // Global base reg for PIC. }; } diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index e51e48fc4dbb3..8d2fff7b76dff 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -12,6 +12,7 @@ #include "VEInstrInfo.h" #include "VE.h" +#include "VEMachineFunctionInfo.h" #include "VESubtarget.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" @@ -404,6 +405,25 @@ void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, report_fatal_error("Can't load this register from stack slot"); } +Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { + VEMachineFunctionInfo *VEFI = MF->getInfo(); + Register GlobalBaseReg = VEFI->getGlobalBaseReg(); + if (GlobalBaseReg != 0) + return GlobalBaseReg; + + // We use %s15 (%got) as a global base register + GlobalBaseReg = VE::SX15; + + // Insert a pseudo instruction to set the GlobalBaseReg into the first + // MBB of the function + MachineBasicBlock &FirstMBB = MF->front(); + MachineBasicBlock::iterator MBBI = FirstMBB.begin(); + DebugLoc dl; + BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); + VEFI->setGlobalBaseReg(GlobalBaseReg); + return GlobalBaseReg; +} + bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { switch (MI.getOpcode()) { case VE::EXTEND_STACK: { diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h index 0fc9e48c1b0e1..47021efa9016f 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.h +++ b/llvm/lib/Target/VE/VEInstrInfo.h @@ -76,6 +76,8 @@ class VEInstrInfo : public VEGenInstrInfo { const TargetRegisterInfo *TRI) const override; /// } Stack Spill & Reload + Register getGlobalBaseReg(MachineFunction *MF) const; + // Lower pseudo instructions after register allocation. bool expandPostRAPseudo(MachineInstr &MI) const override; diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index f788b3232f7e6..8fb89c83c5ffe 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -210,6 +210,13 @@ def call : SDNode<"VEISD::CALL", SDT_SPCall, def retflag : SDNode<"VEISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def getGOT : Operand; + +// GETFUNPLT for PIC +def GetFunPLT : SDNode<"VEISD::GETFUNPLT", SDTIntUnaryOp>; + + //===----------------------------------------------------------------------===// // VE Flag Conditions //===----------------------------------------------------------------------===// @@ -264,6 +271,17 @@ multiclass RMmopc, let cz = 1; let hasSideEffects = 0; } + def zii : RM< + opc, (outs RC:$sx), (ins immOp:$sy, immOp2:$imm32), + !strconcat(opcStr, " $sx, ${imm32}(${sy})"), + [/* Not define DAG pattern here to avoid llvm uses LEAzii for all add + instructions. + (set Ty:$sx, (OpNode (Ty simm7:$sy), (Ty simm32:$imm32))) */]> { + let cy = 0; + let cz = 0; + let sz = 0; + let hasSideEffects = 0; + } def zzi : RM< opc, (outs RC:$sx), (ins immOp2:$imm32), !strconcat(opcStr, " $sx, $imm32")> { @@ -1031,6 +1049,11 @@ def MONC : RR< 0x3F, (outs), (ins), "monc">; +// Save Instruction Counter + +let cx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 /* , Uses = [IC] */ in +def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">; + //===----------------------------------------------------------------------===// // Instructions for CodeGenOnly //===----------------------------------------------------------------------===// @@ -1208,6 +1231,23 @@ def : Pat<(brcc cond:$cond, f64:$l, f64:$r, bb:$addr), // Pseudo Instructions //===----------------------------------------------------------------------===// +// GETGOT for PIC +let Defs = [SX15 /* %got */, SX16 /* %plt */], hasSideEffects = 0 in { + def GETGOT : Pseudo<(outs getGOT:$getpcseq), (ins), "$getpcseq">; +} + +// GETFUNPLT for PIC +let hasSideEffects = 0 in +def GETFUNPLT : Pseudo<(outs I64:$dst), (ins i64imm:$addr), + "$dst, $addr", + [(set iPTR:$dst, (GetFunPLT tglobaladdr:$addr))] >; + +def : Pat<(GetFunPLT tglobaladdr:$dst), + (GETFUNPLT tglobaladdr:$dst)>; +def : Pat<(GetFunPLT texternalsym:$dst), + (GETFUNPLT texternalsym:$dst)>; + + let Defs = [SX11], Uses = [SX11], hasSideEffects = 0 in { def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt, i64imm:$amt2), "# ADJCALLSTACKDOWN $amt, $amt2", diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.h b/llvm/lib/Target/VE/VEMachineFunctionInfo.h index be919a99b5179..16b25fed3f11d 100644 --- a/llvm/lib/Target/VE/VEMachineFunctionInfo.h +++ b/llvm/lib/Target/VE/VEMachineFunctionInfo.h @@ -20,6 +20,8 @@ class VEMachineFunctionInfo : public MachineFunctionInfo { virtual void anchor(); private: + Register GlobalBaseReg; + /// VarArgsFrameOffset - Frame offset to start of varargs area. int VarArgsFrameOffset; @@ -27,9 +29,13 @@ class VEMachineFunctionInfo : public MachineFunctionInfo { bool IsLeafProc; public: - VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {} + VEMachineFunctionInfo() + : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {} explicit VEMachineFunctionInfo(MachineFunction &MF) - : VarArgsFrameOffset(0), IsLeafProc(false) {} + : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {} + + Register getGlobalBaseReg() const { return GlobalBaseReg; } + void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; } diff --git a/llvm/test/CodeGen/VE/pic_access_data.ll b/llvm/test/CodeGen/VE/pic_access_data.ll new file mode 100644 index 0000000000000..0cfabe8048802 --- /dev/null +++ b/llvm/test/CodeGen/VE/pic_access_data.ll @@ -0,0 +1,39 @@ +; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s + +@dst = external global i32, align 4 +@ptr = external global i32*, align 8 +@src = external global i32, align 4 + +define i32 @func() { +; CHECK-LABEL: func: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; CHECK-NEXT: and %s15, %s15, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; CHECK-NEXT: lea %s0, dst@got_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, dst@got_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: ld %s1, (,%s0) +; CHECK-NEXT: lea %s0, ptr@got_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, ptr@got_hi(%s0) +; CHECK-NEXT: lea %s2, src@got_lo +; CHECK-NEXT: and %s2, %s2, (32)0 +; CHECK-NEXT: lea.sl %s2, src@got_hi(%s2) +; CHECK-NEXT: adds.l %s2, %s15, %s2 +; CHECK-NEXT: ld %s2, (,%s2) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: ld %s0, (,%s0) +; CHECK-NEXT: ldl.sx %s2, (,%s2) +; CHECK-NEXT: st %s1, (,%s0) +; CHECK-NEXT: or %s0, 1, (0)1 +; CHECK-NEXT: stl %s2, (,%s1) +; CHECK-NEXT: or %s11, 0, %s9 + + store i32* @dst, i32** @ptr, align 8 + %1 = load i32, i32* @src, align 4 + store i32 %1, i32* @dst, align 4 + ret i32 1 +} diff --git a/llvm/test/CodeGen/VE/pic_access_static_data.ll b/llvm/test/CodeGen/VE/pic_access_static_data.ll new file mode 100644 index 0000000000000..b95ae66a6f781 --- /dev/null +++ b/llvm/test/CodeGen/VE/pic_access_static_data.ll @@ -0,0 +1,79 @@ +; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s + +@dst = internal unnamed_addr global i32 0, align 4 +@src = internal unnamed_addr global i1 false, align 4 +@.str = private unnamed_addr constant [3 x i8] c"%d\00", align 1 + +define void @func() { +; CHECK-LABEL: func: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; CHECK-NEXT: and %s15, %s15, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; CHECK-NEXT: lea %s0, src@gotoff_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, src@gotoff_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: ld1b.zx %s0, (,%s0) +; CHECK-NEXT: or %s1, 0, (0)1 +; CHECK-NEXT: lea %s2, 100 +; CHECK-NEXT: cmov.w.ne %s1, %s2, %s0 +; CHECK-NEXT: lea %s0, dst@gotoff_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: stl %s1, (,%s0) +; CHECK-NEXT: or %s11, 0, %s9 + + %1 = load i1, i1* @src, align 4 + %2 = select i1 %1, i32 100, i32 0 + store i32 %2, i32* @dst, align 4 + ret void +} + +; Function Attrs: nounwind +define i32 @main() { +; CHECK-LABEL: main: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; CHECK-NEXT: and %s15, %s15, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; CHECK-NEXT: lea %s0, src@gotoff_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, src@gotoff_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: or %s1, 1, (0)1 +; CHECK-NEXT: st1b %s1, (,%s0) +; CHECK-NEXT: lea %s12, func@plt_lo(-24) +; CHECK-NEXT: and %s12, %s12, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s12, func@plt_hi(%s16, %s12) +; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: lea %s0, dst@gotoff_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, dst@gotoff_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: ldl.sx %s1, (,%s0) +; CHECK-NEXT: stl %s1, 184(,%s11) +; CHECK-NEXT: lea %s0, .L.str@gotoff_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, .L.str@gotoff_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: lea %s12, printf@plt_lo(-24) +; CHECK-NEXT: and %s12, %s12, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s12, printf@plt_hi(%s16, %s12) +; CHECK-NEXT: st %s0, 176(,%s11) +; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + store i1 true, i1* @src, align 4 + tail call void @func() + %1 = load i32, i32* @dst, align 4 + %2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i32 %1) + ret i32 0 +} + +declare i32 @printf(i8* nocapture readonly, ...) diff --git a/llvm/test/CodeGen/VE/pic_func_call.ll b/llvm/test/CodeGen/VE/pic_func_call.ll new file mode 100644 index 0000000000000..a5f8a6acc075d --- /dev/null +++ b/llvm/test/CodeGen/VE/pic_func_call.ll @@ -0,0 +1,21 @@ +; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define void @func() { +; CHECK-LABEL: func: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; CHECK-NEXT: and %s15, %s15, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; CHECK-NEXT: lea %s12, function@plt_lo(-24) +; CHECK-NEXT: and %s12, %s12, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s12, function@plt_hi(%s16, %s12) +; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: or %s11, 0, %s9 + + call void bitcast (void (...)* @function to void ()*)() + ret void +} + +declare void @function(...) diff --git a/llvm/test/CodeGen/VE/pic_indirect_func_call.ll b/llvm/test/CodeGen/VE/pic_indirect_func_call.ll new file mode 100644 index 0000000000000..17069667029e3 --- /dev/null +++ b/llvm/test/CodeGen/VE/pic_indirect_func_call.ll @@ -0,0 +1,34 @@ +; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s + +@ptr = external global void (...)*, align 8 + +define void @func() { +; CHECK-LABEL: func: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24) +; CHECK-NEXT: and %s15, %s15, (32)0 +; CHECK-NEXT: sic %s16 +; CHECK-NEXT: lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15) +; CHECK-NEXT: lea %s0, function@got_lo +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, function@got_hi(%s0) +; CHECK-NEXT: adds.l %s0, %s15, %s0 +; CHECK-NEXT: ld %s0, (,%s0) +; CHECK-NEXT: lea %s1, ptr@got_lo +; CHECK-NEXT: and %s1, %s1, (32)0 +; CHECK-NEXT: lea.sl %s1, ptr@got_hi(%s1) +; CHECK-NEXT: adds.l %s1, %s15, %s1 +; CHECK-NEXT: ld %s1, (,%s1) +; CHECK-NEXT: st %s0, (,%s1) +; CHECK-NEXT: or %s12, 0, %s0 +; CHECK-NEXT: bsic %lr, (,%s12) +; CHECK-NEXT: or %s11, 0, %s9 + + store void (...)* @function, void (...)** @ptr, align 8 + %1 = load void (...)*, void (...)** @ptr, align 8 + %2 = bitcast void (...)* %1 to void ()* + call void %2() + ret void +} + +declare void @function(...) From 189c701332eb2d80c0bf6bf132abeb4e1ec9e6ce Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 14 Feb 2020 09:35:13 +0100 Subject: [PATCH 44/57] [lldb] Remove accidentally checked-in debugging code --- .../breakpoint-events/TestVSCode_breakpointEvents.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/lldb/test/API/tools/lldb-vscode/breakpoint-events/TestVSCode_breakpointEvents.py b/lldb/test/API/tools/lldb-vscode/breakpoint-events/TestVSCode_breakpointEvents.py index e99297c35e321..e9d826073f217 100644 --- a/lldb/test/API/tools/lldb-vscode/breakpoint-events/TestVSCode_breakpointEvents.py +++ b/lldb/test/API/tools/lldb-vscode/breakpoint-events/TestVSCode_breakpointEvents.py @@ -116,7 +116,3 @@ def test_breakpoint_events(self): "breakpoint event is has a line number") self.assertTrue("foo.cpp" in breakpoint['source']['path'], "breakpoint event path contains foo.cpp") - - output = self.get_console() # REMOVE PRIOR TO CHECKIN - with open("/tmp/b", "w") as f: - f.write(output) From 39cb2a8fc79976171b20369ff756f7fa43232b50 Mon Sep 17 00:00:00 2001 From: Alex Zinenko Date: Fri, 14 Feb 2020 10:18:19 +0100 Subject: [PATCH 45/57] [mlir] Fix argument attribute attribute reassignment in ConvertStandardToLLVM The commit switching the calling convention for memrefs (5a1778057) inadvertently introduced a bug in the function argument attribute conversion: due to incorrect indexing of function arguments it was not assigning the attributes to the arguments beyond those generated from the first original argument. This was not caught in the commit since the test suite does have a test for converting multi-argument functions with argument attributes. Fix the bug and add relevant tests. --- .../Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp | 4 ++-- mlir/test/Conversion/StandardToLLVM/convert-argattrs.mlir | 8 ++++++++ .../StandardToLLVM/convert-static-memref-ops.mlir | 4 ++-- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp index 57ebe42ac6886..f613a39a96128 100644 --- a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp +++ b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp @@ -921,8 +921,8 @@ struct FuncOpConversionBase : public LLVMLegalizationPattern { assert(mapping.hasValue() && "unexpected deletion of function argument"); SmallString<8> name; - for (size_t j = mapping->inputNo; j < mapping->size; ++j) { - impl::getArgAttrName(j, name); + for (size_t j = 0; j < mapping->size; ++j) { + impl::getArgAttrName(mapping->inputNo + j, name); attributes.push_back(rewriter.getNamedAttr(name, attr)); } } diff --git a/mlir/test/Conversion/StandardToLLVM/convert-argattrs.mlir b/mlir/test/Conversion/StandardToLLVM/convert-argattrs.mlir index f2cd0f8e694d8..2831aefc10f92 100644 --- a/mlir/test/Conversion/StandardToLLVM/convert-argattrs.mlir +++ b/mlir/test/Conversion/StandardToLLVM/convert-argattrs.mlir @@ -9,3 +9,11 @@ func @check_attributes(%static: memref<10x20xf32> {dialect.a = true, dialect.b = return } +// CHECK-LABEL: func @check_multiple +// Make sure arguments attributes are attached to the right argument. We match +// commas in the argument list for this purpose. +// CHECK: %{{.*}}: !llvm{{.*}} {first.arg = true}, %{{.*}}: !llvm{{.*}} {first.arg = true}, %{{.*}}: !llvm{{.*}} {first.arg = true}, +// CHECK-SAME: %{{.*}}: !llvm{{.*}} {second.arg = 42 : i32}, %{{.*}}: !llvm{{.*}} {second.arg = 42 : i32}, %{{.*}}: !llvm{{.*}} {second.arg = 42 : i32}) +func @check_multiple(%first: memref {first.arg = true}, %second: memref {second.arg = 42 : i32}) { + return +} diff --git a/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir b/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir index b47d355f77f60..105a80dec7a71 100644 --- a/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir +++ b/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir @@ -3,8 +3,8 @@ // RUN: mlir-opt -convert-std-to-llvm='use-bare-ptr-memref-call-conv=1' -split-input-file %s | FileCheck %s --check-prefix=BAREPTR // BAREPTR-LABEL: func @check_noalias -// BAREPTR-SAME: %{{.*}}: !llvm<"float*"> {llvm.noalias = true} -func @check_noalias(%static : memref<2xf32> {llvm.noalias = true}) { +// BAREPTR-SAME: %{{.*}}: !llvm<"float*"> {llvm.noalias = true}, %{{.*}}: !llvm<"float*"> {llvm.noalias = true} +func @check_noalias(%static : memref<2xf32> {llvm.noalias = true}, %other : memref<2xf32> {llvm.noalias = true}) { return } From 07211d951d584b19951ad8dedbaf7c728297f4b5 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Thu, 13 Feb 2020 14:40:09 +0100 Subject: [PATCH 46/57] [lldb/dotest] Remove the "exclusive test subdir" concept Summary: This was added in 2018 (r339929), when we were still using the hand-rolled test runner. It does not seem to be relevant anymore. In fact as far as I can tell, it's a big no-op now as the exclusive_test_subdir variable is never set. Reviewers: vsk, JDevlieghere Subscribers: lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D74551 --- .../Python/lldbsuite/test/configuration.py | 36 ------------------- lldb/packages/Python/lldbsuite/test/dotest.py | 10 +----- 2 files changed, 1 insertion(+), 45 deletions(-) diff --git a/lldb/packages/Python/lldbsuite/test/configuration.py b/lldb/packages/Python/lldbsuite/test/configuration.py index faf31e7dbcf8e..ce6f46ae476f3 100644 --- a/lldb/packages/Python/lldbsuite/test/configuration.py +++ b/lldb/packages/Python/lldbsuite/test/configuration.py @@ -117,11 +117,6 @@ # The clang module cache directory used by clang. clang_module_cache_dir = None -# The only directory to scan for tests. If multiple test directories are -# specified, and an exclusive test subdirectory is specified, the latter option -# takes precedence. -exclusive_test_subdir = None - # Test results handling globals results_filename = None results_formatter_name = None @@ -153,37 +148,6 @@ def shouldSkipBecauseOfCategories(test_categories): return False -def get_absolute_path_to_exclusive_test_subdir(): - """ - If an exclusive test subdirectory is specified, return its absolute path. - Otherwise return None. - """ - test_directory = os.path.dirname(os.path.realpath(__file__)) - - if not exclusive_test_subdir: - return - - if len(exclusive_test_subdir) > 0: - test_subdir = os.path.join(test_directory, exclusive_test_subdir) - if os.path.isdir(test_subdir): - return test_subdir - - print('specified test subdirectory {} is not a valid directory\n' - .format(test_subdir)) - - -def get_absolute_path_to_root_test_dir(): - """ - If an exclusive test subdirectory is specified, return its absolute path. - Otherwise, return the absolute path of the root test directory. - """ - test_subdir = get_absolute_path_to_exclusive_test_subdir() - if test_subdir: - return test_subdir - - return os.path.dirname(os.path.realpath(__file__)) - - def get_filecheck_path(): """ Get the path to the FileCheck testing tool. diff --git a/lldb/packages/Python/lldbsuite/test/dotest.py b/lldb/packages/Python/lldbsuite/test/dotest.py index 4863004c0b72c..5dddc996eda52 100644 --- a/lldb/packages/Python/lldbsuite/test/dotest.py +++ b/lldb/packages/Python/lldbsuite/test/dotest.py @@ -1051,15 +1051,7 @@ def run_suite(): "netbsd" in target_platform or "windows" in target_platform) - # Collect tests from the specified testing directories. If a test - # subdirectory filter is explicitly specified, limit the search to that - # subdirectory. - exclusive_test_subdir = configuration.get_absolute_path_to_exclusive_test_subdir() - if exclusive_test_subdir: - dirs_to_search = [exclusive_test_subdir] - else: - dirs_to_search = configuration.testdirs - for testdir in dirs_to_search: + for testdir in configuration.testdirs: for (dirpath, dirnames, filenames) in os.walk(testdir): visit('Test', dirpath, filenames) From 850cb135a3b8f7e226a40186954599187fe0f6b2 Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Fri, 14 Feb 2020 09:12:41 +0000 Subject: [PATCH 47/57] Do not build the CUBIN conversion pass when NVPTX Backend isn't configured This pass would currently build, but fail to run when this backend isn't linked in. On the other hand, we'd like it to initialize only the NVPTX backend, which isn't possible if we continue to build it without the backend available. Instead of building a broken configuration, let's skip building the pass entirely. Differential Revision: https://reviews.llvm.org/D74592 --- mlir/CMakeLists.txt | 2 ++ mlir/include/mlir/InitAllPasses.h | 2 ++ mlir/lib/Conversion/GPUToCUDA/CMakeLists.txt | 11 ++++++++++- .../Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp | 7 ++++--- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/mlir/CMakeLists.txt b/mlir/CMakeLists.txt index 4b46939aa88db..b9980c3795b3a 100644 --- a/mlir/CMakeLists.txt +++ b/mlir/CMakeLists.txt @@ -44,6 +44,8 @@ if ("NVPTX" IN_LIST LLVM_TARGETS_TO_BUILD) else() set(MLIR_CUDA_CONVERSIONS_ENABLED 0) endif() +# TODO: we should use a config.h file like LLVM does +add_definitions(-DMLIR_CUDA_CONVERSIONS_ENABLED=${MLIR_CUDA_CONVERSIONS_ENABLED}) set(MLIR_CUDA_RUNNER_ENABLED 0 CACHE BOOL "Enable building the mlir CUDA runner") diff --git a/mlir/include/mlir/InitAllPasses.h b/mlir/include/mlir/InitAllPasses.h index b867e0624916e..6b28041bf9807 100644 --- a/mlir/include/mlir/InitAllPasses.h +++ b/mlir/include/mlir/InitAllPasses.h @@ -90,8 +90,10 @@ inline void registerAllPasses() { // CUDA createConvertGpuLaunchFuncToCudaCallsPass(); +#if MLIR_CUDA_CONVERSIONS_ENABLED createConvertGPUKernelToCubinPass( [](const std::string &, Location, StringRef) { return nullptr; }); +#endif createLowerGpuOpsToNVVMOpsPass(); // Linalg diff --git a/mlir/lib/Conversion/GPUToCUDA/CMakeLists.txt b/mlir/lib/Conversion/GPUToCUDA/CMakeLists.txt index a758f7b935efd..484bc9dbd89c3 100644 --- a/mlir/lib/Conversion/GPUToCUDA/CMakeLists.txt +++ b/mlir/lib/Conversion/GPUToCUDA/CMakeLists.txt @@ -1,7 +1,16 @@ -add_llvm_library(MLIRGPUtoCUDATransforms +set(LLVM_OPTIONAL_SOURCES ConvertKernelFuncToCubin.cpp +) + +set(SOURCES ConvertLaunchFuncToCudaCalls.cpp ) + +if (MLIR_CUDA_CONVERSIONS_ENABLED) + list(APPEND SOURCES "ConvertKernelFuncToCubin.cpp") +endif() + +add_llvm_library(MLIRGPUtoCUDATransforms ${SOURCES}) target_link_libraries(MLIRGPUtoCUDATransforms MLIRGPU MLIRLLVMIR diff --git a/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp b/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp index fe571cf31548b..140026eaf6434 100644 --- a/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp +++ b/mlir/lib/Conversion/GPUToCUDA/ConvertKernelFuncToCubin.cpp @@ -57,9 +57,10 @@ class GpuKernelToCubinPass gpu::GPUModuleOp module = getOperation(); // Make sure the NVPTX target is initialized. - llvm::InitializeAllTargets(); - llvm::InitializeAllTargetMCs(); - llvm::InitializeAllAsmPrinters(); + LLVMInitializeNVPTXTarget(); + LLVMInitializeNVPTXTargetInfo(); + LLVMInitializeNVPTXTargetMC(); + LLVMInitializeNVPTXAsmPrinter(); auto llvmModule = translateModuleToNVVMIR(module); if (!llvmModule) From 4e1c49cf4d8ba69e914593ad7117afec72fdb6c7 Mon Sep 17 00:00:00 2001 From: James Henderson Date: Thu, 13 Feb 2020 10:21:55 +0000 Subject: [PATCH 48/57] [doc] Clarify responsibility for fixing experimental target problems Experimental targets are meant to be maintained by the community behind the target. They are not monitored by the primary build bots. This change clarifies that it is this communities responsibility for things like test fixes related to the target caused by changes unrelated to that target. See http://lists.llvm.org/pipermail/llvm-dev/2020-February/139115.html for a full discussion. Reviewed by: rupprecht, lattner, MaskRay Differential Revision: https://reviews.llvm.org/D74538 --- llvm/docs/DeveloperPolicy.rst | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/llvm/docs/DeveloperPolicy.rst b/llvm/docs/DeveloperPolicy.rst index 883556fc95363..e38ce93217b31 100644 --- a/llvm/docs/DeveloperPolicy.rst +++ b/llvm/docs/DeveloperPolicy.rst @@ -570,9 +570,15 @@ and then trying to fix emergent problems in-tree is problematic for a variety of reasons. For these reasons, new targets are *always* added as *experimental* until -they can be proven stable, and later moved to non-experimental. The difference -between both classes is that experimental targets are not built by default -(need to be added to -DLLVM_TARGETS_TO_BUILD at CMake time). +they can be proven stable, and later moved to non-experimental. The differences +between both classes are: + +* Experimental targets are not built by default (they need to be explicitly + enabled at CMake time). + +* Test failures, bugs, and build breakages that only appear when the + experimental target is enabled, caused by changes unrelated to the target, are + the responsibility of the community behind the target to fix. The basic rules for a back-end to be upstreamed in **experimental** mode are: From a82f35e17621a036cb726244ee5cb9708545fb93 Mon Sep 17 00:00:00 2001 From: Roger Ferrer Ibanez Date: Thu, 12 Dec 2019 09:19:10 +0000 Subject: [PATCH 49/57] [OpenMP] Lower taskwait using OpenMP IR Builder The code generation is exactly the same as it was. But not that the special handling of untied tasks is still handled by emitUntiedSwitch in clang. Differential Revision: https://reviews.llvm.org/D69828 --- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 17 ++++++++++++----- clang/test/OpenMP/task_codegen.cpp | 4 ++++ clang/test/OpenMP/taskwait_codegen.cpp | 4 ++++ .../llvm/Frontend/OpenMP/OMPIRBuilder.h | 10 ++++++++++ llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 1 + llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 18 ++++++++++++++++++ 6 files changed, 49 insertions(+), 5 deletions(-) diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index fe672f3461288..554d95a256eca 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -6340,11 +6340,18 @@ void CGOpenMPRuntime::emitTaskwaitCall(CodeGenFunction &CGF, SourceLocation Loc) { if (!CGF.HaveInsertPoint()) return; - // Build call kmp_int32 __kmpc_omp_taskwait(ident_t *loc, kmp_int32 - // global_tid); - llvm::Value *Args[] = {emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc)}; - // Ignore return result until untied tasks are supported. - CGF.EmitRuntimeCall(createRuntimeFunction(OMPRTL__kmpc_omp_taskwait), Args); + + llvm::OpenMPIRBuilder *OMPBuilder = CGF.CGM.getOpenMPIRBuilder(); + if (OMPBuilder) { + OMPBuilder->CreateTaskwait(CGF.Builder); + } else { + // Build call kmp_int32 __kmpc_omp_taskwait(ident_t *loc, kmp_int32 + // global_tid); + llvm::Value *Args[] = {emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc)}; + // Ignore return result until untied tasks are supported. + CGF.EmitRuntimeCall(createRuntimeFunction(OMPRTL__kmpc_omp_taskwait), Args); + } + if (auto *Region = dyn_cast_or_null(CGF.CapturedStmtInfo)) Region->emitUntiedSwitch(CGF); } diff --git a/clang/test/OpenMP/task_codegen.cpp b/clang/test/OpenMP/task_codegen.cpp index cf9f030825630..47c31fb217ad9 100644 --- a/clang/test/OpenMP/task_codegen.cpp +++ b/clang/test/OpenMP/task_codegen.cpp @@ -1,6 +1,10 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s diff --git a/clang/test/OpenMP/taskwait_codegen.cpp b/clang/test/OpenMP/taskwait_codegen.cpp index 22f381b351996..20c332b3732b1 100644 --- a/clang/test/OpenMP/taskwait_codegen.cpp +++ b/clang/test/OpenMP/taskwait_codegen.cpp @@ -1,6 +1,10 @@ // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c++ -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// +// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fopenmp-enable-irbuilder -x c++ -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-apple-darwin10 -emit-pch -o %t %s diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index a1470bc04958a..c1ec28abd34c2 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -176,6 +176,11 @@ class OpenMPIRBuilder { /// \param Loc The location where the flush directive was encountered void CreateFlush(const LocationDescription &Loc); + /// Generator for '#omp taskwait' + /// + /// \param Loc The location where the taskwait directive was encountered. + void CreateTaskwait(const LocationDescription& Loc); + ///} @@ -241,6 +246,11 @@ class OpenMPIRBuilder { FinalizationStack.back().DK == DK; } + /// Generate a taskwait runtime call. + /// + /// \param Loc The location at which the request originated and is fulfilled. + void emitTaskwaitImpl(const LocationDescription &Loc); + /// Return the current thread ID. /// /// \param Ident The ident (ident_t*) describing the query origin. diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 3525c427b8bc8..7d6f29ba26339 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -169,6 +169,7 @@ __OMP_RTL(__kmpc_cancel_barrier, false, Int32, IdentPtr, Int32) __OMP_RTL(__kmpc_flush, false, Void, IdentPtr) __OMP_RTL(__kmpc_global_thread_num, false, Int32, IdentPtr) __OMP_RTL(__kmpc_fork_call, true, Void, IdentPtr, Int32, ParallelTaskPtr) +__OMP_RTL(__kmpc_omp_taskwait, false, Int32, IdentPtr, Int32) __OMP_RTL(__kmpc_push_num_threads, false, Void, IdentPtr, Int32, /* Int */ Int32) __OMP_RTL(__kmpc_push_proc_bind, false, Void, IdentPtr, Int32, /* Int */ Int32) diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index d3f63d4ee8e7d..9d17dbe2d8940 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -691,3 +691,21 @@ void OpenMPIRBuilder::CreateFlush(const LocationDescription &Loc) return; emitFlush(Loc); } + +void OpenMPIRBuilder::emitTaskwaitImpl(const LocationDescription &Loc) { + // Build call kmp_int32 __kmpc_omp_taskwait(ident_t *loc, kmp_int32 + // global_tid); + Constant *SrcLocStr = getOrCreateSrcLocStr(Loc); + Value *Ident = getOrCreateIdent(SrcLocStr); + Value *Args[] = {Ident, getOrCreateThreadID(Ident)}; + + // Ignore return result until untied tasks are supported. + Builder.CreateCall(getOrCreateRuntimeFunction(OMPRTL___kmpc_omp_taskwait), + Args); +} + +void OpenMPIRBuilder::CreateTaskwait(const LocationDescription &Loc) { + if (!updateToLocation(Loc)) + return; + emitTaskwaitImpl(Loc); +} From 9dc84e9b02d1e402503906099d42fbae4da7d8d9 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Thu, 6 Feb 2020 06:24:39 -0800 Subject: [PATCH 50/57] [lldb/DWARF] Don't hold a unique SymbolFileDWARFDwo in a DWARFUnit This is the second dwp preparatory patch. When a SymbolFileDWARFDwo will hold more than one split unit, it will not be able to be uniquely owned by a single DWARFUnit. I achieve this by changing the unique_ptr member of DWARFUnit to shared_ptr. The shared_ptr points to a DWARFUnit, but it is in fact holding the entire SymbolFileDWARFDwo alive. This is the same method used by llvm DWARFUnit (except that is uses the DWARFContext class). Differential Revision: https://reviews.llvm.org/D73782 --- .../Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 57 ++++++++----------- .../Plugins/SymbolFile/DWARF/DWARFUnit.h | 2 +- .../SymbolFile/DWARF/SymbolFileDWARF.cpp | 4 +- .../SymbolFile/DWARF/SymbolFileDWARF.h | 2 +- .../SymbolFile/DWARF/SymbolFileDWARFDwo.cpp | 19 +++---- .../SymbolFile/DWARF/SymbolFileDWARFDwo.h | 10 ++-- 6 files changed, 42 insertions(+), 52 deletions(-) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp index e4a89160969ec..1e8c465979b5e 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp @@ -188,7 +188,7 @@ void DWARFUnit::ExtractDIEsRWLocked() { // simultaneously. We also don't need to do that as the dwo file will // contain a superset of information. So, we don't even attempt to parse // any remaining DIEs. - if (m_dwo_symbol_file) { + if (m_dwo) { m_die_array.front().SetHasChildren(false); break; } @@ -249,10 +249,8 @@ void DWARFUnit::ExtractDIEsRWLocked() { m_die_array.shrink_to_fit(); - if (m_dwo_symbol_file) { - DWARFUnit *dwo_cu = m_dwo_symbol_file->GetCompileUnit(); - dwo_cu->ExtractDIEsIfNeeded(); - } + if (m_dwo) + m_dwo->ExtractDIEsIfNeeded(); } // This is used when a split dwarf is enabled. @@ -339,12 +337,14 @@ void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry &cu_die) { if (m_is_dwo) return; - std::unique_ptr dwo_symbol_file = + std::shared_ptr dwo_symbol_file = m_dwarf.GetDwoSymbolFileForCompileUnit(*this, cu_die); if (!dwo_symbol_file) return; - DWARFUnit *dwo_cu = dwo_symbol_file->GetCompileUnit(); + uint64_t main_dwo_id = + cu_die.GetAttributeValueAsUnsigned(this, DW_AT_GNU_dwo_id, 0); + DWARFUnit *dwo_cu = dwo_symbol_file->GetDWOCompileUnitForHash(main_dwo_id); if (!dwo_cu) return; // Can't fetch the compile unit from the dwo file. dwo_cu->SetUserData(this); @@ -353,16 +353,6 @@ void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry &cu_die) { if (!dwo_cu_die.IsValid()) return; // Can't fetch the compile unit DIE from the dwo file. - uint64_t main_dwo_id = - cu_die.GetAttributeValueAsUnsigned(this, DW_AT_GNU_dwo_id, 0); - uint64_t sub_dwo_id = - dwo_cu_die.GetAttributeValueAsUnsigned(DW_AT_GNU_dwo_id, 0); - if (main_dwo_id != sub_dwo_id) - return; // The 2 dwo ID isn't match. Don't use the dwo file as it belongs to - // a differectn compilation. - - m_dwo_symbol_file = std::move(dwo_symbol_file); - // Here for DWO CU we want to use the address base set in the skeleton unit // (DW_AT_addr_base) if it is available and use the DW_AT_GNU_addr_base // otherwise. We do that because pre-DWARF v5 could use the DW_AT_GNU_* @@ -376,21 +366,22 @@ void DWARFUnit::AddUnitDIE(const DWARFDebugInfoEntry &cu_die) { if (GetVersion() <= 4 && gnu_ranges_base) dwo_cu->SetRangesBase(*gnu_ranges_base); - else if (m_dwo_symbol_file->GetDWARFContext() + else if (dwo_symbol_file->GetDWARFContext() .getOrLoadRngListsData() .GetByteSize() > 0) dwo_cu->SetRangesBase(llvm::DWARFListTableHeader::getHeaderSize(DWARF32)); - if (GetVersion() >= 5 && m_dwo_symbol_file->GetDWARFContext() - .getOrLoadLocListsData() - .GetByteSize() > 0) + if (GetVersion() >= 5 && + dwo_symbol_file->GetDWARFContext().getOrLoadLocListsData().GetByteSize() > + 0) dwo_cu->SetLoclistsBase(llvm::DWARFListTableHeader::getHeaderSize(DWARF32)); dwo_cu->SetBaseAddress(GetBaseAddress()); - for (size_t i = 0; i < m_dwo_symbol_file->DebugInfo()->GetNumUnits(); ++i) { - DWARFUnit *unit = m_dwo_symbol_file->DebugInfo()->GetUnitAtIndex(i); + for (size_t i = 0; i < dwo_symbol_file->DebugInfo()->GetNumUnits(); ++i) { + DWARFUnit *unit = dwo_symbol_file->DebugInfo()->GetUnitAtIndex(i); SetDwoStrOffsetsBase(unit); } + m_dwo = std::shared_ptr(std::move(dwo_symbol_file), dwo_cu); } DWARFDIE DWARFUnit::LookupAddress(const dw_addr_t address) { @@ -507,8 +498,8 @@ void DWARFUnit::ClearDIEsRWLocked() { m_die_array.clear(); m_die_array.shrink_to_fit(); - if (m_dwo_symbol_file) - m_dwo_symbol_file->GetCompileUnit()->ClearDIEsRWLocked(); + if (m_dwo) + m_dwo->ClearDIEsRWLocked(); } lldb::ByteOrder DWARFUnit::GetByteOrder() const { @@ -549,8 +540,9 @@ DWARFUnit::GetDIE(dw_offset_t die_offset) { } DWARFUnit &DWARFUnit::GetNonSkeletonUnit() { - if (SymbolFileDWARFDwo *dwo = GetDwoSymbolFile()) - return *dwo->GetCompileUnit(); + ExtractUnitDIEIfNeeded(); + if (m_dwo) + return *m_dwo; return *this; } @@ -755,7 +747,9 @@ void DWARFUnit::ComputeAbsolutePath() { SymbolFileDWARFDwo *DWARFUnit::GetDwoSymbolFile() { ExtractUnitDIEIfNeeded(); - return m_dwo_symbol_file.get(); + if (m_dwo) + return &llvm::cast(m_dwo->GetSymbolFileDWARF()); + return nullptr; } const DWARFDebugAranges &DWARFUnit::GetFunctionAranges() { @@ -765,11 +759,10 @@ const DWARFDebugAranges &DWARFUnit::GetFunctionAranges() { if (die) die->BuildFunctionAddressRangeTable(this, m_func_aranges_up.get()); - if (m_dwo_symbol_file) { - DWARFUnit *dwo_cu = m_dwo_symbol_file->GetCompileUnit(); - const DWARFDebugInfoEntry *dwo_die = dwo_cu->DIEPtr(); + if (m_dwo) { + const DWARFDebugInfoEntry *dwo_die = m_dwo->DIEPtr(); if (dwo_die) - dwo_die->BuildFunctionAddressRangeTable(dwo_cu, + dwo_die->BuildFunctionAddressRangeTable(m_dwo.get(), m_func_aranges_up.get()); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h index 73edf62e73d4a..7852e5ad8efdd 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h @@ -277,7 +277,7 @@ class DWARFUnit : public lldb_private::UserID { } SymbolFileDWARF &m_dwarf; - std::unique_ptr m_dwo_symbol_file; + std::shared_ptr m_dwo; DWARFUnitHeader m_header; const DWARFAbbreviationDeclarationSet *m_abbrevs = nullptr; void *m_user_data = nullptr; diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index 39484f0a198b5..b45d84870ffbf 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -1556,7 +1556,7 @@ llvm::Optional SymbolFileDWARF::GetDWOId() { return {}; } -std::unique_ptr +std::shared_ptr SymbolFileDWARF::GetDwoSymbolFileForCompileUnit( DWARFUnit &unit, const DWARFDebugInfoEntry &cu_die) { // If this is a Darwin-style debug map (non-.dSYM) symbol file, @@ -1611,7 +1611,7 @@ SymbolFileDWARF::GetDwoSymbolFileForCompileUnit( if (dwo_obj_file == nullptr) return nullptr; - return std::make_unique(*this, dwo_obj_file, + return std::make_shared(*this, dwo_obj_file, dwarf_cu->GetID()); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h index 23df3a2762a52..c9fd678a7f560 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h @@ -270,7 +270,7 @@ class SymbolFileDWARF : public lldb_private::SymbolFile, lldb::user_id_t GetUID(DIERef ref); - std::unique_ptr + std::shared_ptr GetDwoSymbolFileForCompileUnit(DWARFUnit &dwarf_cu, const DWARFDebugInfoEntry &cu_die); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp index d7d1b03e5124b..cf33d05119418 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp @@ -49,13 +49,17 @@ void SymbolFileDWARFDwo::LoadSectionData(lldb::SectionType sect_type, SymbolFileDWARF::LoadSectionData(sect_type, data); } -DWARFCompileUnit *SymbolFileDWARFDwo::GetCompileUnit() { - if (!m_cu) - m_cu = ComputeCompileUnit(); - return m_cu; +DWARFCompileUnit *SymbolFileDWARFDwo::GetDWOCompileUnitForHash(uint64_t hash) { + DWARFCompileUnit *cu = FindSingleCompileUnit(); + if (!cu) + return nullptr; + if (hash != + cu->GetUnitDIEOnly().GetAttributeValueAsUnsigned(DW_AT_GNU_dwo_id, 0)) + return nullptr; + return cu; } -DWARFCompileUnit *SymbolFileDWARFDwo::ComputeCompileUnit() { +DWARFCompileUnit *SymbolFileDWARFDwo::FindSingleCompileUnit() { DWARFDebugInfo *debug_info = DebugInfo(); if (!debug_info) return nullptr; @@ -79,11 +83,6 @@ DWARFCompileUnit *SymbolFileDWARFDwo::ComputeCompileUnit() { return cu; } -DWARFUnit * -SymbolFileDWARFDwo::GetDWARFCompileUnit(lldb_private::CompileUnit *comp_unit) { - return GetCompileUnit(); -} - SymbolFileDWARF::DIEToTypePtr &SymbolFileDWARFDwo::GetDIEToType() { return GetBaseSymbolFile().GetDIEToType(); } diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h index 1002d0bb54c68..37cc2cb419d14 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h @@ -29,10 +29,7 @@ class SymbolFileDWARFDwo : public SymbolFileDWARF { ~SymbolFileDWARFDwo() override = default; - DWARFCompileUnit *GetCompileUnit(); - - DWARFUnit * - GetDWARFCompileUnit(lldb_private::CompileUnit *comp_unit) override; + DWARFCompileUnit *GetDWOCompileUnitForHash(uint64_t hash); size_t GetObjCMethodDIEOffsets(lldb_private::ConstString class_name, DIEArray &method_die_offsets) override; @@ -68,10 +65,11 @@ class SymbolFileDWARFDwo : public SymbolFileDWARF { SymbolFileDWARF &GetBaseSymbolFile() { return m_base_symbol_file; } - DWARFCompileUnit *ComputeCompileUnit(); + /// If this file contains exactly one compile unit, this function will return + /// it. Otherwise it returns nullptr. + DWARFCompileUnit *FindSingleCompileUnit(); SymbolFileDWARF &m_base_symbol_file; - DWARFCompileUnit *m_cu = nullptr; }; #endif // SymbolFileDWARFDwo_SymbolFileDWARFDwo_h_ From fe6983a75ae08dc63e2068f521670562ad77c599 Mon Sep 17 00:00:00 2001 From: James Henderson Date: Mon, 3 Feb 2020 16:43:03 +0000 Subject: [PATCH 51/57] [DebugInfo] Error if unsupported address size detected in line table Prior to this patch, if a DW_LNE_set_address opcode was parsed with an address size (i.e. with a length after the opcode) of anything other 1, 2, 4, or 8, an llvm_unreachable would be hit, as the data extractor does not support other values. This patch introduces a new error check that verifies the address size is one of the supported sizes, in common with other places within the DWARF parsing. This patch also fixes calculation of a generated line table's size in unit tests. One of the tests in this patch highlighted a bug introduced in 1271cde4745, when non-byte operands were used as arguments for extended or standard opcodes. Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D73962 --- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 32 +++++-- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 94 +++++++++++++++++++ .../DebugInfo/DWARF/DwarfGenerator.cpp | 21 ++++- .../DebugInfo/DWARF/DwarfGenerator.h | 7 +- 4 files changed, 142 insertions(+), 12 deletions(-) diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp index 7bdc72ae7aa89..436318ba8b162 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp @@ -665,7 +665,9 @@ Error DWARFDebugLine::LineTable::parse( // from the size of the operand. { uint8_t ExtractorAddressSize = DebugLineData.getAddressSize(); - if (ExtractorAddressSize != Len - 1 && ExtractorAddressSize != 0) + uint64_t OpcodeAddressSize = Len - 1; + if (ExtractorAddressSize != OpcodeAddressSize && + ExtractorAddressSize != 0) RecoverableErrorHandler(createStringError( errc::invalid_argument, "mismatching address size at offset 0x%8.8" PRIx64 @@ -673,14 +675,26 @@ Error DWARFDebugLine::LineTable::parse( ExtOffset, ExtractorAddressSize, Len - 1)); // Assume that the line table is correct and temporarily override the - // address size. - DebugLineData.setAddressSize(Len - 1); - State.Row.Address.Address = DebugLineData.getRelocatedAddress( - OffsetPtr, &State.Row.Address.SectionIndex); - - // Restore the address size if the extractor already had it. - if (ExtractorAddressSize != 0) - DebugLineData.setAddressSize(ExtractorAddressSize); + // address size. If the size is unsupported, give up trying to read + // the address and continue to the next opcode. + if (OpcodeAddressSize != 1 && OpcodeAddressSize != 2 && + OpcodeAddressSize != 4 && OpcodeAddressSize != 8) { + RecoverableErrorHandler(createStringError( + errc::invalid_argument, + "address size 0x%2.2" PRIx64 + " of DW_LNE_set_address opcode at offset 0x%8.8" PRIx64 + " is unsupported", + OpcodeAddressSize, ExtOffset)); + *OffsetPtr += OpcodeAddressSize; + } else { + DebugLineData.setAddressSize(OpcodeAddressSize); + State.Row.Address.Address = DebugLineData.getRelocatedAddress( + OffsetPtr, &State.Row.Address.SectionIndex); + + // Restore the address size if the extractor already had it. + if (ExtractorAddressSize != 0) + DebugLineData.setAddressSize(ExtractorAddressSize); + } if (OS) *OS << format(" (0x%16.16" PRIx64 ")", State.Row.Address.Address); diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp index d6d96916c4e9a..0552b5ad6f7ba 100644 --- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp @@ -640,6 +640,100 @@ TEST_F(DebugLineBasicFixture, EXPECT_EQ((*ExpectedLineTable)->Rows[1].Address.Address, Addr2); } +TEST_F(DebugLineBasicFixture, + ErrorForUnsupportedAddressSizeInSetAddressLength) { + // Use DWARF v4, and 0 for data extractor address size so that the address + // size is derived from the opcode length. + if (!setupGenerator(4, 0)) + return; + + LineTable < = Gen->addLineTable(); + // 4 == length of the extended opcode, i.e. 1 for the opcode itself and 3 for + // the Half (2) + Byte (1) operand, representing the unsupported address size. + LT.addExtendedOpcode(4, DW_LNE_set_address, + {{0x1234, LineTable::Half}, {0x56, LineTable::Byte}}); + LT.addStandardOpcode(DW_LNS_copy, {}); + // Special opcode to ensure the address has changed between the first and last + // row in the sequence. Without this, the sequence will not be recorded. + LT.addByte(0xaa); + LT.addExtendedOpcode(1, DW_LNE_end_sequence, {}); + + generate(); + + auto ExpectedLineTable = Line.getOrParseLineTable(LineData, 0, *Context, + nullptr, RecordRecoverable); + checkError( + "address size 0x03 of DW_LNE_set_address opcode at offset 0x00000030 is " + "unsupported", + std::move(Recoverable)); + ASSERT_THAT_EXPECTED(ExpectedLineTable, Succeeded()); + ASSERT_EQ((*ExpectedLineTable)->Rows.size(), 3u); + EXPECT_EQ((*ExpectedLineTable)->Sequences.size(), 1u); + // Show that the set address opcode is ignored in this case. + EXPECT_EQ((*ExpectedLineTable)->Rows[0].Address.Address, 0); +} + +TEST_F(DebugLineBasicFixture, ErrorForAddressSizeGreaterThanByteSize) { + // Use DWARF v4, and 0 for data extractor address size so that the address + // size is derived from the opcode length. + if (!setupGenerator(4, 0)) + return; + + LineTable < = Gen->addLineTable(); + // Specifically use an operand size that has a trailing byte of a supported + // size (8), so that any potential truncation would result in a valid size. + std::vector Operands(0x108); + LT.addExtendedOpcode(Operands.size() + 1, DW_LNE_set_address, Operands); + LT.addExtendedOpcode(1, DW_LNE_end_sequence, {}); + + generate(); + + auto ExpectedLineTable = Line.getOrParseLineTable(LineData, 0, *Context, + nullptr, RecordRecoverable); + checkError( + "address size 0x108 of DW_LNE_set_address opcode at offset 0x00000031 is " + "unsupported", + std::move(Recoverable)); + ASSERT_THAT_EXPECTED(ExpectedLineTable, Succeeded()); +} + +TEST_F(DebugLineBasicFixture, ErrorForUnsupportedAddressSizeDefinedInHeader) { + // Use 0 for data extractor address size so that it does not clash with the + // header address size. + if (!setupGenerator(5, 0)) + return; + + LineTable < = Gen->addLineTable(); + // AddressSize + 1 == length of the extended opcode, i.e. 1 for the opcode + // itself and 9 for the Quad (8) + Byte (1) operand representing the + // unsupported address size. + uint8_t AddressSize = 9; + LT.addExtendedOpcode(AddressSize + 1, DW_LNE_set_address, + {{0x12345678, LineTable::Quad}, {0, LineTable::Byte}}); + LT.addStandardOpcode(DW_LNS_copy, {}); + // Special opcode to ensure the address has changed between the first and last + // row in the sequence. Without this, the sequence will not be recorded. + LT.addByte(0xaa); + LT.addExtendedOpcode(1, DW_LNE_end_sequence, {}); + DWARFDebugLine::Prologue Prologue = LT.createBasicPrologue(); + Prologue.FormParams.AddrSize = AddressSize; + LT.setPrologue(Prologue); + + generate(); + + auto ExpectedLineTable = Line.getOrParseLineTable(LineData, 0, *Context, + nullptr, RecordRecoverable); + checkError( + "address size 0x09 of DW_LNE_set_address opcode at offset 0x00000038 is " + "unsupported", + std::move(Recoverable)); + ASSERT_THAT_EXPECTED(ExpectedLineTable, Succeeded()); + ASSERT_EQ((*ExpectedLineTable)->Rows.size(), 3u); + EXPECT_EQ((*ExpectedLineTable)->Sequences.size(), 1u); + // Show that the set address opcode is ignored in this case. + EXPECT_EQ((*ExpectedLineTable)->Rows[0].Address.Address, 0); +} + TEST_F(DebugLineBasicFixture, CallbackUsedForUnterminatedSequence) { if (!setupGenerator()) return; diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp index f53fbdea34f58..f4e407ea84b1e 100644 --- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp @@ -27,6 +27,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetOptionsCommandFlags.inc" #include "llvm/PassAnalysisSupport.h" +#include "llvm/Support/LEB128.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetLoweringObjectFile.h" @@ -175,7 +176,7 @@ DWARFDebugLine::Prologue dwarfgen::LineTable::createBasicPrologue() const { P.TotalLength += 4; P.FormParams.Format = DWARF64; } - P.TotalLength += Contents.size(); + P.TotalLength += getContentsSize(); P.FormParams.Version = Version; P.MinInstLength = 1; P.MaxOpsPerInst = 1; @@ -259,6 +260,24 @@ void dwarfgen::LineTable::writeData(ArrayRef Data, } } +size_t dwarfgen::LineTable::getContentsSize() const { + size_t Size = 0; + for (auto Entry : Contents) { + switch (Entry.Length) { + case ULEB: + Size += getULEB128Size(Entry.Value); + break; + case SLEB: + Size += getSLEB128Size(Entry.Value); + break; + default: + Size += Entry.Length; + break; + } + } + return Size; +} + MCSymbol *dwarfgen::LineTable::writeDefaultPrologue(AsmPrinter &Asm) const { MCSymbol *UnitStart = Asm.createTempSymbol("line_unit_start"); MCSymbol *UnitEnd = Asm.createTempSymbol("line_unit_end"); diff --git a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h index 2f95e29b84581..9ba8eab1a15be 100644 --- a/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h +++ b/llvm/unittests/DebugInfo/DWARF/DwarfGenerator.h @@ -171,8 +171,8 @@ class LineTable { enum ValueLength { Byte = 1, Half = 2, Long = 4, Quad = 8, ULEB, SLEB }; struct ValueAndLength { - uint64_t Value; - ValueLength Length; + uint64_t Value = 0; + ValueLength Length = Byte; }; LineTable(uint16_t Version, dwarf::DwarfFormat Format, uint8_t AddrSize, @@ -214,6 +214,9 @@ class LineTable { void writeProloguePayload(const DWARFDebugLine::Prologue &Prologue, AsmPrinter &Asm) const; + // Calculate the number of bytes the Contents will take up. + size_t getContentsSize() const; + llvm::Optional Prologue; std::vector CustomPrologue; std::vector Contents; From 430fc538e6dc2f3b1b6093755080efdcf206cd3f Mon Sep 17 00:00:00 2001 From: Andrew Ng Date: Tue, 11 Feb 2020 12:28:17 +0000 Subject: [PATCH 52/57] [llvm-ar] Simplify Windows comparePaths NFCI Replace use of widenPath in comparePaths with UTF8ToUTF16. widenPath does a lot more than just conversion from UTF-8 to UTF-16. This is not necessary for CompareStringOrdinal and could possibly even cause problems. Differential Revision: https://reviews.llvm.org/D74477 --- llvm/tools/llvm-ar/llvm-ar.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/tools/llvm-ar/llvm-ar.cpp b/llvm/tools/llvm-ar/llvm-ar.cpp index 61ab8051edede..d95226c5d8e37 100644 --- a/llvm/tools/llvm-ar/llvm-ar.cpp +++ b/llvm/tools/llvm-ar/llvm-ar.cpp @@ -21,6 +21,7 @@ #include "llvm/Object/ObjectFile.h" #include "llvm/Support/Chrono.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ConvertUTF.h" #include "llvm/Support/Errc.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Format.h" @@ -518,8 +519,8 @@ static bool comparePaths(StringRef Path1, StringRef Path2) { // binary equivalence and allows for case insensitivity. #ifdef _WIN32 SmallVector WPath1, WPath2; - failIfError(sys::path::widenPath(normalizePath(Path1), WPath1)); - failIfError(sys::path::widenPath(normalizePath(Path2), WPath2)); + failIfError(sys::windows::UTF8ToUTF16(normalizePath(Path1), WPath1)); + failIfError(sys::windows::UTF8ToUTF16(normalizePath(Path2), WPath2)); return CompareStringOrdinal(WPath1.data(), WPath1.size(), WPath2.data(), WPath2.size(), true) == CSTR_EQUAL; From 2bef1c0e5645639bda1807f7df970da97792b0c8 Mon Sep 17 00:00:00 2001 From: Roger Ferrer Ibanez Date: Thu, 12 Dec 2019 08:55:46 +0000 Subject: [PATCH 53/57] [OpenMP] Lower taskyield using OpenMP IR Builder This is similar to D69828. Special codegen for enclosing untied tasks is still done in clang. Differential Revision: https://reviews.llvm.org/D70799 --- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 17 ++++++++++++----- clang/test/OpenMP/taskyield_codegen.cpp | 4 ++++ .../include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 11 +++++++++++ llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 1 + llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 17 +++++++++++++++++ 5 files changed, 45 insertions(+), 5 deletions(-) diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 554d95a256eca..7440434df5081 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -3295,11 +3295,18 @@ void CGOpenMPRuntime::emitTaskyieldCall(CodeGenFunction &CGF, SourceLocation Loc) { if (!CGF.HaveInsertPoint()) return; - // Build call __kmpc_omp_taskyield(loc, thread_id, 0); - llvm::Value *Args[] = { - emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc), - llvm::ConstantInt::get(CGM.IntTy, /*V=*/0, /*isSigned=*/true)}; - CGF.EmitRuntimeCall(createRuntimeFunction(OMPRTL__kmpc_omp_taskyield), Args); + llvm::OpenMPIRBuilder *OMPBuilder = CGF.CGM.getOpenMPIRBuilder(); + if (OMPBuilder) { + OMPBuilder->CreateTaskyield(CGF.Builder); + } else { + // Build call __kmpc_omp_taskyield(loc, thread_id, 0); + llvm::Value *Args[] = { + emitUpdateLocation(CGF, Loc), getThreadID(CGF, Loc), + llvm::ConstantInt::get(CGM.IntTy, /*V=*/0, /*isSigned=*/true)}; + CGF.EmitRuntimeCall(createRuntimeFunction(OMPRTL__kmpc_omp_taskyield), + Args); + } + if (auto *Region = dyn_cast_or_null(CGF.CapturedStmtInfo)) Region->emitUntiedSwitch(CGF); } diff --git a/clang/test/OpenMP/taskyield_codegen.cpp b/clang/test/OpenMP/taskyield_codegen.cpp index d57071f48aa8f..ce8a729771d73 100644 --- a/clang/test/OpenMP/taskyield_codegen.cpp +++ b/clang/test/OpenMP/taskyield_codegen.cpp @@ -1,6 +1,10 @@ // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s +// +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s +// RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -emit-pch -o %t %s diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index c1ec28abd34c2..d0e9e40370bb1 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -171,6 +171,7 @@ class OpenMPIRBuilder { Value *IfCondition, Value *NumThreads, omp::ProcBindKind ProcBind, bool IsCancellable); + /// Generator for '#omp flush' /// /// \param Loc The location where the flush directive was encountered @@ -181,6 +182,11 @@ class OpenMPIRBuilder { /// \param Loc The location where the taskwait directive was encountered. void CreateTaskwait(const LocationDescription& Loc); + /// Generator for '#omp taskyield' + /// + /// \param Loc The location where the taskyield directive was encountered. + void CreateTaskyield(const LocationDescription& Loc); + ///} @@ -251,6 +257,11 @@ class OpenMPIRBuilder { /// \param Loc The location at which the request originated and is fulfilled. void emitTaskwaitImpl(const LocationDescription &Loc); + /// Generate a taskyield runtime call. + /// + /// \param Loc The location at which the request originated and is fulfilled. + void emitTaskyieldImpl(const LocationDescription &Loc); + /// Return the current thread ID. /// /// \param Ident The ident (ident_t*) describing the query origin. diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index 7d6f29ba26339..e0318ab3c551f 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -170,6 +170,7 @@ __OMP_RTL(__kmpc_flush, false, Void, IdentPtr) __OMP_RTL(__kmpc_global_thread_num, false, Int32, IdentPtr) __OMP_RTL(__kmpc_fork_call, true, Void, IdentPtr, Int32, ParallelTaskPtr) __OMP_RTL(__kmpc_omp_taskwait, false, Int32, IdentPtr, Int32) +__OMP_RTL(__kmpc_omp_taskyield, false, Int32, IdentPtr, Int32, Int32) __OMP_RTL(__kmpc_push_num_threads, false, Void, IdentPtr, Int32, /* Int */ Int32) __OMP_RTL(__kmpc_push_proc_bind, false, Void, IdentPtr, Int32, /* Int */ Int32) diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 9d17dbe2d8940..b011a3ee9b934 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -709,3 +709,20 @@ void OpenMPIRBuilder::CreateTaskwait(const LocationDescription &Loc) { return; emitTaskwaitImpl(Loc); } + +void OpenMPIRBuilder::emitTaskyieldImpl(const LocationDescription &Loc) { + // Build call __kmpc_omp_taskyield(loc, thread_id, 0); + Constant *SrcLocStr = getOrCreateSrcLocStr(Loc); + Value *Ident = getOrCreateIdent(SrcLocStr); + Constant *I32Null = ConstantInt::getNullValue(Int32); + Value *Args[] = {Ident, getOrCreateThreadID(Ident), I32Null}; + + Builder.CreateCall(getOrCreateRuntimeFunction(OMPRTL___kmpc_omp_taskyield), + Args); +} + +void OpenMPIRBuilder::CreateTaskyield(const LocationDescription &Loc) { + if (!updateToLocation(Loc)) + return; + emitTaskyieldImpl(Loc); +} From de1c2877a9ff12899ef50e179ade748fba8ab0c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Marques?= Date: Fri, 14 Feb 2020 11:49:18 +0000 Subject: [PATCH 54/57] llvm/cmake/config.guess: add support for riscv32 and riscv64 Summary: LLVM configuration fails with 'unable to guess system type' on riscv64. Add support for detecting riscv32 and riscv64 systems. Patch by Gokturk Yuksek (gokturk) Reviewers: erichkeane, rengolin, mgorny, aaron.ballman, beanz, luismarques Reviewed By: luismarques Tags: #llvm Differential Revision: https://reviews.llvm.org/D68899 --- llvm/cmake/config.guess | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/llvm/cmake/config.guess b/llvm/cmake/config.guess index ccb30f4e75e8f..26d120601e494 100644 --- a/llvm/cmake/config.guess +++ b/llvm/cmake/config.guess @@ -973,6 +973,30 @@ EOF ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit ;; + riscv32:Linux:*:* | riscv64:Linux:*:*) + LIBC=gnu + eval $set_cc_for_build + # Do not check for __GLIBC__ because uclibc defines it too + sed 's/^ //' << EOF >$dummy.c + #include + #if defined(__UCLIBC__) + LIBC=uclibc + #elif defined(__dietlibc__) + LIBC=dietlibc + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` + + # There is no features test macro for musl + # Follow the GNU's config.guess approach of + # checking the output of ldd + if command -v ldd >/dev/null && \ + ldd --version 2>&1 | grep -q ^musl; then + LIBC=musl + fi + + echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit ;; From 2492075add88af24bfc0c9af8a9af61b880c0ebb Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 14 Feb 2020 11:54:55 +0000 Subject: [PATCH 55/57] [X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SSSE3 targets Without PSHUFB we are better using ROTL (expanding to OR(SHL,SRL)) than using the generic v16i8 shuffle lowering - but if we can widen to v8i16 or more then the existing shuffles are still the better option. REAPPLIED: Original commit rG11c16e71598d was reverted at rGde1d90299b16 as it wasn't accounting for later lowering. This version emits ROTLI or the OR(VSHLI/VSRLI) directly to avoid the issue. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 33 ++- llvm/test/CodeGen/X86/bitreverse.ll | 13 +- llvm/test/CodeGen/X86/bswap-vector.ll | 51 ++-- llvm/test/CodeGen/X86/vector-bitreverse.ll | 235 ++++++++---------- .../CodeGen/X86/vector-shuffle-128-v16.ll | 26 +- 5 files changed, 157 insertions(+), 201 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5992436e16356..3bc3c4a97825b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -11704,7 +11704,7 @@ static int matchShuffleAsBitRotate(ArrayRef Mask, int NumSubElts) { return RotateAmt; } -/// Lower shuffle using ISD::ROTL rotations. +/// Lower shuffle using X86ISD::VROTLI rotations. static SDValue lowerShuffleAsBitRotate(const SDLoc &DL, MVT VT, SDValue V1, ArrayRef Mask, const X86Subtarget &Subtarget, @@ -11716,25 +11716,46 @@ static SDValue lowerShuffleAsBitRotate(const SDLoc &DL, MVT VT, SDValue V1, assert(EltSizeInBits < 64 && "Can't rotate 64-bit integers"); // Only XOP + AVX512 targets have bit rotation instructions. + // If we at least have SSSE3 (PSHUFB) then we shouldn't attempt to use this. bool IsLegal = (VT.is128BitVector() && Subtarget.hasXOP()) || Subtarget.hasAVX512(); - if (!IsLegal) + if (!IsLegal && Subtarget.hasSSE3()) return SDValue(); // AVX512 only has vXi32/vXi64 rotates, so limit the rotation sub group size. - int MinSubElts = Subtarget.hasXOP() ? 2 : std::max(32 / EltSizeInBits, 2); + int MinSubElts = Subtarget.hasAVX512() ? std::max(32 / EltSizeInBits, 2) : 2; int MaxSubElts = 64 / EltSizeInBits; for (int NumSubElts = MinSubElts; NumSubElts <= MaxSubElts; NumSubElts *= 2) { int RotateAmt = matchShuffleAsBitRotate(Mask, NumSubElts); if (RotateAmt < 0) continue; - int RotateAmtInBits = RotateAmt * EltSizeInBits; + int NumElts = VT.getVectorNumElements(); MVT RotateSVT = MVT::getIntegerVT(EltSizeInBits * NumSubElts); MVT RotateVT = MVT::getVectorVT(RotateSVT, NumElts / NumSubElts); + + // For pre-SSSE3 targets, if we are shuffling vXi8 elts then ISD::ROTL, + // expanded to OR(SRL,SHL), will be more efficient, but if they can + // widen to vXi16 or more then existing lowering should will be better. + int RotateAmtInBits = RotateAmt * EltSizeInBits; + if (!IsLegal) { + if ((RotateAmtInBits % 16) == 0) + return SDValue(); + // TODO: Use getTargetVShiftByConstNode. + unsigned ShlAmt = RotateAmtInBits; + unsigned SrlAmt = RotateSVT.getScalarSizeInBits() - RotateAmtInBits; + V1 = DAG.getBitcast(RotateVT, V1); + SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1, + DAG.getTargetConstant(ShlAmt, DL, MVT::i8)); + SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1, + DAG.getTargetConstant(SrlAmt, DL, MVT::i8)); + SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL); + return DAG.getBitcast(VT, Rot); + } + SDValue Rot = - DAG.getNode(ISD::ROTL, DL, RotateVT, DAG.getBitcast(RotateVT, V1), - DAG.getConstant(RotateAmtInBits, DL, RotateVT)); + DAG.getNode(X86ISD::VROTLI, DL, RotateVT, DAG.getBitcast(RotateVT, V1), + DAG.getTargetConstant(RotateAmtInBits, DL, MVT::i8)); return DAG.getBitcast(VT, Rot); } diff --git a/llvm/test/CodeGen/X86/bitreverse.ll b/llvm/test/CodeGen/X86/bitreverse.ll index e2b58f9a26360..343d9fb2da2de 100644 --- a/llvm/test/CodeGen/X86/bitreverse.ll +++ b/llvm/test/CodeGen/X86/bitreverse.ll @@ -52,15 +52,10 @@ define <2 x i16> @test_bitreverse_v2i16(<2 x i16> %a) nounwind { ; ; X64-LABEL: test_bitreverse_v2i16: ; X64: # %bb.0: -; X64-NEXT: pxor %xmm1, %xmm1 -; X64-NEXT: movdqa %xmm0, %xmm2 -; X64-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; X64-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; X64-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; X64-NEXT: packuswb %xmm2, %xmm0 +; X64-NEXT: movdqa %xmm0, %xmm1 +; X64-NEXT: psrlw $8, %xmm1 +; X64-NEXT: psllw $8, %xmm0 +; X64-NEXT: por %xmm1, %xmm0 ; X64-NEXT: movdqa %xmm0, %xmm1 ; X64-NEXT: psllw $4, %xmm1 ; X64-NEXT: pand {{.*}}(%rip), %xmm1 diff --git a/llvm/test/CodeGen/X86/bswap-vector.ll b/llvm/test/CodeGen/X86/bswap-vector.ll index 222e0d7d84bfc..d959f224137cc 100644 --- a/llvm/test/CodeGen/X86/bswap-vector.ll +++ b/llvm/test/CodeGen/X86/bswap-vector.ll @@ -11,15 +11,10 @@ declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) define <8 x i16> @test1(<8 x i16> %v) { ; CHECK-NOSSSE3-LABEL: test1: ; CHECK-NOSSSE3: # %bb.0: # %entry -; CHECK-NOSSSE3-NEXT: pxor %xmm1, %xmm1 -; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm2 -; CHECK-NOSSSE3-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: packuswb %xmm2, %xmm0 +; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm1 +; CHECK-NOSSSE3-NEXT: psrlw $8, %xmm1 +; CHECK-NOSSSE3-NEXT: psllw $8, %xmm0 +; CHECK-NOSSSE3-NEXT: por %xmm1, %xmm0 ; CHECK-NOSSSE3-NEXT: ret{{[l|q]}} ; ; CHECK-SSSE3-LABEL: test1: @@ -132,23 +127,14 @@ declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) define <16 x i16> @test4(<16 x i16> %v) { ; CHECK-NOSSSE3-LABEL: test4: ; CHECK-NOSSSE3: # %bb.0: # %entry -; CHECK-NOSSSE3-NEXT: pxor %xmm2, %xmm2 -; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm3 -; CHECK-NOSSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: packuswb %xmm3, %xmm0 -; CHECK-NOSSSE3-NEXT: movdqa %xmm1, %xmm3 -; CHECK-NOSSSE3-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: packuswb %xmm3, %xmm1 +; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm2 +; CHECK-NOSSSE3-NEXT: psrlw $8, %xmm2 +; CHECK-NOSSSE3-NEXT: psllw $8, %xmm0 +; CHECK-NOSSSE3-NEXT: por %xmm2, %xmm0 +; CHECK-NOSSSE3-NEXT: movdqa %xmm1, %xmm2 +; CHECK-NOSSSE3-NEXT: psrlw $8, %xmm2 +; CHECK-NOSSSE3-NEXT: psllw $8, %xmm1 +; CHECK-NOSSSE3-NEXT: por %xmm2, %xmm1 ; CHECK-NOSSSE3-NEXT: ret{{[l|q]}} ; ; CHECK-SSSE3-LABEL: test4: @@ -252,15 +238,10 @@ declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>) define <4 x i16> @test7(<4 x i16> %v) { ; CHECK-NOSSSE3-LABEL: test7: ; CHECK-NOSSSE3: # %bb.0: # %entry -; CHECK-NOSSSE3-NEXT: pxor %xmm1, %xmm1 -; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm2 -; CHECK-NOSSSE3-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; CHECK-NOSSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; CHECK-NOSSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; CHECK-NOSSSE3-NEXT: packuswb %xmm2, %xmm0 +; CHECK-NOSSSE3-NEXT: movdqa %xmm0, %xmm1 +; CHECK-NOSSSE3-NEXT: psrlw $8, %xmm1 +; CHECK-NOSSSE3-NEXT: psllw $8, %xmm0 +; CHECK-NOSSSE3-NEXT: por %xmm1, %xmm0 ; CHECK-NOSSSE3-NEXT: ret{{[l|q]}} ; ; CHECK-SSSE3-LABEL: test7: diff --git a/llvm/test/CodeGen/X86/vector-bitreverse.ll b/llvm/test/CodeGen/X86/vector-bitreverse.ll index 954d7a2c52a28..f421ac303d876 100644 --- a/llvm/test/CodeGen/X86/vector-bitreverse.ll +++ b/llvm/test/CodeGen/X86/vector-bitreverse.ll @@ -295,15 +295,10 @@ define <16 x i8> @test_bitreverse_v16i8(<16 x i8> %a) nounwind { define <8 x i16> @test_bitreverse_v8i16(<8 x i16> %a) nounwind { ; SSE2-LABEL: test_bitreverse_v8i16: ; SSE2: # %bb.0: -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm2, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm1 ; SSE2-NEXT: psllw $4, %xmm1 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1 @@ -647,63 +642,54 @@ define <16 x i16> @test_bitreverse_v16i16(<16 x i16> %a) nounwind { ; SSE2-LABEL: test_bitreverse_v16i16: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm4[8],xmm1[9],xmm4[9],xmm1[10],xmm4[10],xmm1[11],xmm4[11],xmm1[12],xmm4[12],xmm1[13],xmm4[13],xmm1[14],xmm4[14],xmm1[15],xmm4[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3],xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: psllw $4, %xmm3 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; SSE2-NEXT: movdqa %xmm1, %xmm5 -; SSE2-NEXT: pandn %xmm3, %xmm5 +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: pandn %xmm3, %xmm4 ; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pand %xmm1, %xmm0 -; SSE2-NEXT: por %xmm5, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] -; SSE2-NEXT: movdqa %xmm0, %xmm5 -; SSE2-NEXT: pand %xmm3, %xmm5 -; SSE2-NEXT: psllw $2, %xmm5 -; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] -; SSE2-NEXT: pand %xmm8, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm4 +; SSE2-NEXT: pand %xmm3, %xmm4 +; SSE2-NEXT: psllw $2, %xmm4 +; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] +; SSE2-NEXT: pand %xmm5, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0 -; SSE2-NEXT: por %xmm5, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] -; SSE2-NEXT: movdqa %xmm0, %xmm6 -; SSE2-NEXT: pand %xmm5, %xmm6 -; SSE2-NEXT: paddb %xmm6, %xmm6 -; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] -; SSE2-NEXT: pand %xmm7, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] +; SSE2-NEXT: movdqa %xmm0, %xmm7 +; SSE2-NEXT: pand %xmm4, %xmm7 +; SSE2-NEXT: paddb %xmm7, %xmm7 +; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] +; SSE2-NEXT: pand %xmm6, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm0 -; SSE2-NEXT: por %xmm6, %xmm0 -; SSE2-NEXT: movdqa %xmm2, %xmm6 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm4[8],xmm6[9],xmm4[9],xmm6[10],xmm4[10],xmm6[11],xmm4[11],xmm6[12],xmm4[12],xmm6[13],xmm4[13],xmm6[14],xmm4[14],xmm6[15],xmm4[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1],xmm2[2],xmm4[2],xmm2[3],xmm4[3],xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm6, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: psllw $4, %xmm4 +; SSE2-NEXT: por %xmm7, %xmm0 +; SSE2-NEXT: movdqa %xmm2, %xmm7 +; SSE2-NEXT: psrlw $8, %xmm7 +; SSE2-NEXT: psllw $8, %xmm2 +; SSE2-NEXT: por %xmm7, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm7 +; SSE2-NEXT: psllw $4, %xmm7 ; SSE2-NEXT: psrlw $4, %xmm2 ; SSE2-NEXT: pand %xmm1, %xmm2 -; SSE2-NEXT: pandn %xmm4, %xmm1 +; SSE2-NEXT: pandn %xmm7, %xmm1 ; SSE2-NEXT: por %xmm2, %xmm1 ; SSE2-NEXT: pand %xmm1, %xmm3 ; SSE2-NEXT: psllw $2, %xmm3 -; SSE2-NEXT: pand %xmm8, %xmm1 +; SSE2-NEXT: pand %xmm5, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm1 ; SSE2-NEXT: por %xmm3, %xmm1 -; SSE2-NEXT: pand %xmm1, %xmm5 -; SSE2-NEXT: paddb %xmm5, %xmm5 -; SSE2-NEXT: pand %xmm7, %xmm1 +; SSE2-NEXT: pand %xmm1, %xmm4 +; SSE2-NEXT: paddb %xmm4, %xmm4 +; SSE2-NEXT: pand %xmm6, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1 -; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_bitreverse_v16i16: @@ -1387,118 +1373,101 @@ define <64 x i8> @test_bitreverse_v64i8(<64 x i8> %a) nounwind { define <32 x i16> @test_bitreverse_v32i16(<32 x i16> %a) nounwind { ; SSE2-LABEL: test_bitreverse_v32i16: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm3, %xmm11 -; SSE2-NEXT: pxor %xmm10, %xmm10 +; SSE2-NEXT: movdqa %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm10[8],xmm3[9],xmm10[9],xmm3[10],xmm10[10],xmm3[11],xmm10[11],xmm3[12],xmm10[12],xmm3[13],xmm10[13],xmm3[14],xmm10[14],xmm3[15],xmm10[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm10[0],xmm0[1],xmm10[1],xmm0[2],xmm10[2],xmm0[3],xmm10[3],xmm0[4],xmm10[4],xmm0[5],xmm10[5],xmm0[6],xmm10[6],xmm0[7],xmm10[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm3, %xmm0 +; SSE2-NEXT: psrlw $8, %xmm3 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: por %xmm3, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: psllw $4, %xmm5 ; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; SSE2-NEXT: movdqa %xmm3, %xmm7 -; SSE2-NEXT: pandn %xmm5, %xmm7 +; SSE2-NEXT: movdqa %xmm3, %xmm6 +; SSE2-NEXT: pandn %xmm5, %xmm6 ; SSE2-NEXT: psrlw $4, %xmm0 ; SSE2-NEXT: pand %xmm3, %xmm0 -; SSE2-NEXT: por %xmm7, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] -; SSE2-NEXT: movdqa %xmm0, %xmm7 -; SSE2-NEXT: pand %xmm5, %xmm7 -; SSE2-NEXT: psllw $2, %xmm7 +; SSE2-NEXT: por %xmm6, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm10 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] +; SSE2-NEXT: movdqa %xmm0, %xmm6 +; SSE2-NEXT: pand %xmm10, %xmm6 +; SSE2-NEXT: psllw $2, %xmm6 ; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [204,204,204,204,204,204,204,204,204,204,204,204,204,204,204,204] ; SSE2-NEXT: pand %xmm8, %xmm0 ; SSE2-NEXT: psrlw $2, %xmm0 -; SSE2-NEXT: por %xmm7, %xmm0 -; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] -; SSE2-NEXT: movdqa %xmm0, %xmm6 -; SSE2-NEXT: pand %xmm7, %xmm6 -; SSE2-NEXT: paddb %xmm6, %xmm6 +; SSE2-NEXT: por %xmm6, %xmm0 +; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] +; SSE2-NEXT: movdqa %xmm0, %xmm7 +; SSE2-NEXT: pand %xmm6, %xmm7 +; SSE2-NEXT: paddb %xmm7, %xmm7 ; SSE2-NEXT: movdqa {{.*#+}} xmm9 = [170,170,170,170,170,170,170,170,170,170,170,170,170,170,170,170] ; SSE2-NEXT: pand %xmm9, %xmm0 ; SSE2-NEXT: psrlw $1, %xmm0 -; SSE2-NEXT: por %xmm6, %xmm0 -; SSE2-NEXT: movdqa %xmm1, %xmm6 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm6 = xmm6[8],xmm10[8],xmm6[9],xmm10[9],xmm6[10],xmm10[10],xmm6[11],xmm10[11],xmm6[12],xmm10[12],xmm6[13],xmm10[13],xmm6[14],xmm10[14],xmm6[15],xmm10[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm10[0],xmm1[1],xmm10[1],xmm1[2],xmm10[2],xmm1[3],xmm10[3],xmm1[4],xmm10[4],xmm1[5],xmm10[5],xmm1[6],xmm10[6],xmm1[7],xmm10[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm6, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm6 -; SSE2-NEXT: psllw $4, %xmm6 -; SSE2-NEXT: movdqa %xmm3, %xmm4 -; SSE2-NEXT: pandn %xmm6, %xmm4 +; SSE2-NEXT: por %xmm7, %xmm0 +; SSE2-NEXT: movdqa %xmm1, %xmm7 +; SSE2-NEXT: psrlw $8, %xmm7 +; SSE2-NEXT: psllw $8, %xmm1 +; SSE2-NEXT: por %xmm7, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm7 +; SSE2-NEXT: psllw $4, %xmm7 +; SSE2-NEXT: movdqa %xmm3, %xmm5 +; SSE2-NEXT: pandn %xmm7, %xmm5 ; SSE2-NEXT: psrlw $4, %xmm1 ; SSE2-NEXT: pand %xmm3, %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm4 -; SSE2-NEXT: pand %xmm5, %xmm4 -; SSE2-NEXT: psllw $2, %xmm4 +; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: pand %xmm10, %xmm5 +; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: pand %xmm8, %xmm1 ; SSE2-NEXT: psrlw $2, %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm4 -; SSE2-NEXT: pand %xmm7, %xmm4 -; SSE2-NEXT: paddb %xmm4, %xmm4 +; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: pand %xmm6, %xmm5 +; SSE2-NEXT: paddb %xmm5, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm1 ; SSE2-NEXT: psrlw $1, %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm10[8],xmm4[9],xmm10[9],xmm4[10],xmm10[10],xmm4[11],xmm10[11],xmm4[12],xmm10[12],xmm4[13],xmm10[13],xmm4[14],xmm10[14],xmm4[15],xmm10[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm10[0],xmm2[1],xmm10[1],xmm2[2],xmm10[2],xmm2[3],xmm10[3],xmm2[4],xmm10[4],xmm2[5],xmm10[5],xmm2[6],xmm10[6],xmm2[7],xmm10[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm4, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: psllw $4, %xmm4 -; SSE2-NEXT: movdqa %xmm3, %xmm6 -; SSE2-NEXT: pandn %xmm4, %xmm6 +; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: psrlw $8, %xmm5 +; SSE2-NEXT: psllw $8, %xmm2 +; SSE2-NEXT: por %xmm5, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: psllw $4, %xmm5 +; SSE2-NEXT: movdqa %xmm3, %xmm7 +; SSE2-NEXT: pandn %xmm5, %xmm7 ; SSE2-NEXT: psrlw $4, %xmm2 ; SSE2-NEXT: pand %xmm3, %xmm2 -; SSE2-NEXT: por %xmm6, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: pand %xmm5, %xmm4 -; SSE2-NEXT: psllw $2, %xmm4 +; SSE2-NEXT: por %xmm7, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: pand %xmm10, %xmm5 +; SSE2-NEXT: psllw $2, %xmm5 ; SSE2-NEXT: pand %xmm8, %xmm2 ; SSE2-NEXT: psrlw $2, %xmm2 -; SSE2-NEXT: por %xmm4, %xmm2 -; SSE2-NEXT: movdqa %xmm2, %xmm4 -; SSE2-NEXT: pand %xmm7, %xmm4 -; SSE2-NEXT: paddb %xmm4, %xmm4 +; SSE2-NEXT: por %xmm5, %xmm2 +; SSE2-NEXT: movdqa %xmm2, %xmm5 +; SSE2-NEXT: pand %xmm6, %xmm5 +; SSE2-NEXT: paddb %xmm5, %xmm5 ; SSE2-NEXT: pand %xmm9, %xmm2 ; SSE2-NEXT: psrlw $1, %xmm2 -; SSE2-NEXT: por %xmm4, %xmm2 -; SSE2-NEXT: movdqa %xmm11, %xmm4 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm4 = xmm4[8],xmm10[8],xmm4[9],xmm10[9],xmm4[10],xmm10[10],xmm4[11],xmm10[11],xmm4[12],xmm10[12],xmm4[13],xmm10[13],xmm4[14],xmm10[14],xmm4[15],xmm10[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm11 = xmm11[0],xmm10[0],xmm11[1],xmm10[1],xmm11[2],xmm10[2],xmm11[3],xmm10[3],xmm11[4],xmm10[4],xmm11[5],xmm10[5],xmm11[6],xmm10[6],xmm11[7],xmm10[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm6 = xmm11[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm6 = xmm6[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm4, %xmm6 -; SSE2-NEXT: movdqa %xmm6, %xmm4 -; SSE2-NEXT: psllw $4, %xmm4 -; SSE2-NEXT: psrlw $4, %xmm6 -; SSE2-NEXT: pand %xmm3, %xmm6 -; SSE2-NEXT: pandn %xmm4, %xmm3 -; SSE2-NEXT: por %xmm6, %xmm3 -; SSE2-NEXT: pand %xmm3, %xmm5 -; SSE2-NEXT: psllw $2, %xmm5 +; SSE2-NEXT: por %xmm5, %xmm2 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: psrlw $8, %xmm5 +; SSE2-NEXT: psllw $8, %xmm4 +; SSE2-NEXT: por %xmm5, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm5 +; SSE2-NEXT: psllw $4, %xmm5 +; SSE2-NEXT: psrlw $4, %xmm4 +; SSE2-NEXT: pand %xmm3, %xmm4 +; SSE2-NEXT: pandn %xmm5, %xmm3 +; SSE2-NEXT: por %xmm4, %xmm3 +; SSE2-NEXT: pand %xmm3, %xmm10 +; SSE2-NEXT: psllw $2, %xmm10 ; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: psrlw $2, %xmm3 -; SSE2-NEXT: por %xmm5, %xmm3 -; SSE2-NEXT: pand %xmm3, %xmm7 -; SSE2-NEXT: paddb %xmm7, %xmm7 +; SSE2-NEXT: por %xmm10, %xmm3 +; SSE2-NEXT: pand %xmm3, %xmm6 +; SSE2-NEXT: paddb %xmm6, %xmm6 ; SSE2-NEXT: pand %xmm9, %xmm3 ; SSE2-NEXT: psrlw $1, %xmm3 -; SSE2-NEXT: por %xmm7, %xmm3 +; SSE2-NEXT: por %xmm6, %xmm3 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test_bitreverse_v32i16: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll index c6c34bacaa335..c9329251de311 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll @@ -458,15 +458,10 @@ define <16 x i8> @shuffle_v16i8_03_02_01_00_07_06_05_04_11_10_09_08_15_14_13_12( define <16 x i8> @shuffle_v16i8_01_00_03_02_05_04_07_06_09_08_11_10_13_12_15_14(<16 x i8> %a, <16 x i8> %b) { ; SSE2-LABEL: shuffle_v16i8_01_00_03_02_05_04_07_06_09_08_11_10_13_12_15_14: ; SSE2: # %bb.0: -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,4,7,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,0,3,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,7,6] -; SSE2-NEXT: packuswb %xmm2, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: shuffle_v16i8_01_00_03_02_05_04_07_06_09_08_11_10_13_12_15_14: @@ -1891,15 +1886,10 @@ define <16 x i8> @shuffle_v16i8_zz_zz_zz_zz_zz_zz_zz_zz_zz_zz_01_02_03_04_05_06( define <16 x i8> @shuffle_v16i8_03_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14(<16 x i8> %a) { ; SSE2-LABEL: shuffle_v16i8_03_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14: ; SSE2: # %bb.0: -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: movdqa %xmm0, %xmm2 -; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] -; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,0,1,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,4,5,6] -; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,0,1,2,4,5,6,7] -; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,4,5,6] -; SSE2-NEXT: packuswb %xmm2, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm1 +; SSE2-NEXT: psrld $24, %xmm1 +; SSE2-NEXT: pslld $8, %xmm0 +; SSE2-NEXT: por %xmm1, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: shuffle_v16i8_03_00_01_02_07_04_05_06_11_08_09_10_15_12_13_14: From a57ad008b449a95249a42582370a5f0fefccbf03 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Fri, 14 Feb 2020 12:57:10 +0100 Subject: [PATCH 56/57] [lldb] Print result when expect_expr unexpectedly succeeds --- lldb/packages/Python/lldbsuite/test/lldbtest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py index fa93cce73be55..784d6ecd2ddfb 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbtest.py +++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py @@ -2397,7 +2397,7 @@ def expect_expr( eval_result = frame.EvaluateExpression(expr) if error_msg: - self.assertFalse(eval_result.IsValid()) + self.assertFalse(eval_result.IsValid(), "Unexpected success with result: '" + str(eval_result) + "'") self.assertEqual(error_msg, eval_result.GetError().GetCString()) return From c45fb35b5e0b45357a9bfae500ec5403545dbc77 Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Thu, 30 Jan 2020 14:00:51 +0100 Subject: [PATCH 57/57] [clang][DeclPrinter] Implement visitors for {TemplateType,NonTypeTemplate}Parms Reviewers: sammccall, hokein Subscribers: kristof.beyls, jkorous, arphaman, usaxena95, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D73693 --- .../clangd/unittests/FindTargetTests.cpp | 9 +-- clang/lib/AST/DeclPrinter.cpp | 68 +++++++++++-------- clang/unittests/AST/DeclPrinterTest.cpp | 10 +++ 3 files changed, 51 insertions(+), 36 deletions(-) diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp index be4b37c8f453b..fa091b2a25036 100644 --- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp +++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp @@ -215,8 +215,7 @@ TEST_F(TargetDeclTest, NestedNameSpecifier) { template int x = [[T::]]y; )cpp"; - // FIXME: We don't do a good job printing TemplateTypeParmDecls, apparently! - EXPECT_DECLS("NestedNameSpecifierLoc", ""); + EXPECT_DECLS("NestedNameSpecifierLoc", "typename T"); Code = R"cpp( namespace a { int x; } @@ -256,8 +255,7 @@ TEST_F(TargetDeclTest, Types) { template void foo() { [[T]] x; } )cpp"; - // FIXME: We don't do a good job printing TemplateTypeParmDecls, apparently! - EXPECT_DECLS("TemplateTypeParmTypeLoc", ""); + EXPECT_DECLS("TemplateTypeParmTypeLoc", "class T"); Flags.clear(); // FIXME: Auto-completion in a template requires disabling delayed template @@ -290,8 +288,7 @@ TEST_F(TargetDeclTest, Types) { static const int size = sizeof...([[E]]); }; )cpp"; - // FIXME: We don't do a good job printing TemplateTypeParmDecls, apparently! - EXPECT_DECLS("SizeOfPackExpr", ""); + EXPECT_DECLS("SizeOfPackExpr", "typename ...E"); Code = R"cpp( template diff --git a/clang/lib/AST/DeclPrinter.cpp b/clang/lib/AST/DeclPrinter.cpp index 4cedcbed06447..23dc9e562d4f5 100644 --- a/clang/lib/AST/DeclPrinter.cpp +++ b/clang/lib/AST/DeclPrinter.cpp @@ -105,6 +105,8 @@ namespace { void VisitOMPDeclareReductionDecl(OMPDeclareReductionDecl *D); void VisitOMPDeclareMapperDecl(OMPDeclareMapperDecl *D); void VisitOMPCapturedExprDecl(OMPCapturedExprDecl *D); + void VisitTemplateTypeParmDecl(const TemplateTypeParmDecl *TTP); + void VisitNonTypeTemplateParmDecl(const NonTypeTemplateParmDecl *NTTP); void printTemplateParameters(const TemplateParameterList *Params, bool OmitTemplateKW = false); @@ -1051,37 +1053,10 @@ void DeclPrinter::printTemplateParameters(const TemplateParameterList *Params, else NeedComma = true; - if (auto TTP = dyn_cast(Param)) { - - if (const TypeConstraint *TC = TTP->getTypeConstraint()) - TC->print(Out, Policy); - else if (TTP->wasDeclaredWithTypename()) - Out << "typename"; - else - Out << "class"; - - if (TTP->isParameterPack()) - Out << " ..."; - else if (!TTP->getName().empty()) - Out << ' '; - - Out << *TTP; - - if (TTP->hasDefaultArgument()) { - Out << " = "; - Out << TTP->getDefaultArgument().getAsString(Policy); - }; + if (const auto *TTP = dyn_cast(Param)) { + VisitTemplateTypeParmDecl(TTP); } else if (auto NTTP = dyn_cast(Param)) { - StringRef Name; - if (IdentifierInfo *II = NTTP->getIdentifier()) - Name = II->getName(); - printDeclType(NTTP->getType(), Name, NTTP->isParameterPack()); - - if (NTTP->hasDefaultArgument()) { - Out << " = "; - NTTP->getDefaultArgument()->printPretty(Out, nullptr, Policy, - Indentation); - } + VisitNonTypeTemplateParmDecl(NTTP); } else if (auto TTPD = dyn_cast(Param)) { VisitTemplateDecl(TTPD); // FIXME: print the default argument, if present. @@ -1705,3 +1680,36 @@ void DeclPrinter::VisitOMPCapturedExprDecl(OMPCapturedExprDecl *D) { D->getInit()->printPretty(Out, nullptr, Policy, Indentation); } +void DeclPrinter::VisitTemplateTypeParmDecl(const TemplateTypeParmDecl *TTP) { + if (const TypeConstraint *TC = TTP->getTypeConstraint()) + TC->print(Out, Policy); + else if (TTP->wasDeclaredWithTypename()) + Out << "typename"; + else + Out << "class"; + + if (TTP->isParameterPack()) + Out << " ..."; + else if (!TTP->getName().empty()) + Out << ' '; + + Out << *TTP; + + if (TTP->hasDefaultArgument()) { + Out << " = "; + Out << TTP->getDefaultArgument().getAsString(Policy); + } +} + +void DeclPrinter::VisitNonTypeTemplateParmDecl( + const NonTypeTemplateParmDecl *NTTP) { + StringRef Name; + if (IdentifierInfo *II = NTTP->getIdentifier()) + Name = II->getName(); + printDeclType(NTTP->getType(), Name, NTTP->isParameterPack()); + + if (NTTP->hasDefaultArgument()) { + Out << " = "; + NTTP->getDefaultArgument()->printPretty(Out, nullptr, Policy, Indentation); + } +} diff --git a/clang/unittests/AST/DeclPrinterTest.cpp b/clang/unittests/AST/DeclPrinterTest.cpp index f85358b8f6c8e..e6732cc3f3152 100644 --- a/clang/unittests/AST/DeclPrinterTest.cpp +++ b/clang/unittests/AST/DeclPrinterTest.cpp @@ -22,6 +22,7 @@ #include "clang/ASTMatchers/ASTMatchFinder.h" #include "clang/Tooling/Tooling.h" #include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringRef.h" #include "gtest/gtest.h" using namespace clang; @@ -1273,6 +1274,15 @@ TEST(DeclPrinter, TestTemplateArgumentList15) { // Should be: with semicolon } +TEST(DeclPrinter, TestTemplateArgumentList16) { + llvm::StringLiteral Code = "template struct Z {};"; + ASSERT_TRUE(PrintedDeclCXX11Matches(Code, "T1", "typename T1")); + ASSERT_TRUE(PrintedDeclCXX11Matches(Code, "T2", "typename T2 = bool")); + ASSERT_TRUE(PrintedDeclCXX11Matches(Code, "NT1", "int NT1")); + ASSERT_TRUE(PrintedDeclCXX11Matches(Code, "NT2", "int NT2 = 5")); +} + TEST(DeclPrinter, TestStaticAssert1) { ASSERT_TRUE(PrintedDeclCXX1ZMatches( "static_assert(true);",