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[CUDA][LIBCLC] Implement RC11 seq_cst for PTX6.0 #12516

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merged 15 commits into from
Mar 18, 2024
Merged

[CUDA][LIBCLC] Implement RC11 seq_cst for PTX6.0 #12516

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b605993
ptx 6.0 seq_cst memory consistency model Impl.
JackAKirk Jan 26, 2024
a2321dc
Point to UR branch for testing.
JackAKirk Jan 29, 2024
e0aa6e1
Merge branch 'sycl' into cuda-atom-seq-cst
JackAKirk Jan 29, 2024
5d7bfab
Added missing arch check.
JackAKirk Jan 29, 2024
d8e0002
Added missing arch check.
JackAKirk Jan 29, 2024
b161136
Updated draft UR tag for CI testing.
JackAKirk Jan 29, 2024
164a0cc
Merge branch 'sycl' into cuda-atom-seq-cst
JackAKirk Jan 31, 2024
8e418e7
Fix syclcompat tests.
JackAKirk Jan 31, 2024
a231611
Merge branch 'sycl' into cuda-atom-seq-cst
JackAKirk Feb 1, 2024
f61f271
Point to testing branch.
JackAKirk Mar 15, 2024
1ed016f
Merge branch 'sycl' into cuda-atom-seq-cst
JackAKirk Mar 15, 2024
296ad12
Fix merge conflict.
JackAKirk Mar 15, 2024
859ff2f
Merge branch 'sycl' into cuda-atom-seq-cst
JackAKirk Mar 18, 2024
12b477c
Fix latest UR tag.
JackAKirk Mar 18, 2024
58689a9
Set UR repo.
JackAKirk Mar 18, 2024
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7 changes: 7 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_add.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,13 @@ Memory order is stored in the lowest 5 bits */
ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case SequentiallyConsistent: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_FENCE_SC_SM70() \
__CLC_NVVM_ATOMIC_IMPL_ORDER(double, double, d, add, ADDR_SPACE, \
ADDR_SPACE_NV, _acq_rel) \
break; \
} \
} \
__builtin_trap(); \
__builtin_unreachable(); \
Expand Down
8 changes: 8 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//

#include <atomic_helpers.h>
#include <spirv/spirv.h>
#include <spirv/spirv_types.h>

Expand Down Expand Up @@ -120,6 +121,13 @@ Memory order is stored in the lowest 5 bits */ \
TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case SequentiallyConsistent: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_FENCE_SC_SM70() \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
break; \
} \
} \
__builtin_trap(); \
__builtin_unreachable(); \
Expand Down
16 changes: 16 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_helpers.h
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Expand Up @@ -72,6 +72,15 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
} \
}

#define __CLC_NVVM_FENCE_SC_SM70() \
if (scope == CrossDevice) { \
__asm__ __volatile__("fence.sc.sys;"); \
} else if (scope == Device) { \
__asm__ __volatile__("fence.sc.gpu;"); \
} else { \
__asm__ __volatile__("fence.sc.cta;"); \
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}

#define __CLC_NVVM_ATOMIC_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, NAME_MANGLED, \
ADDR_SPACE, POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV, SUBSTITUTION) \
Expand Down Expand Up @@ -117,6 +126,13 @@ Memory order is stored in the lowest 5 bits */ \
OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case SequentiallyConsistent: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_FENCE_SC_SM70() \
__CLC_NVVM_ATOMIC_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
break; \
} \
} \
__builtin_trap(); \
__builtin_unreachable(); \
Expand Down
7 changes: 7 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_load.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//

#include <atomic_helpers.h>
#include <spirv/spirv.h>
#include <spirv/spirv_types.h>

Expand Down Expand Up @@ -53,6 +54,12 @@ Memory order is stored in the lowest 5 bits */ \
case Acquire: \
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
break; \
case SequentiallyConsistent: \
__CLC_NVVM_FENCE_SC_SM70() \
__CLC_NVVM_ATOMIC_LOAD_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
break; \
} \
} else { \
TYPE_NV res = __nvvm_volatile_ld##ADDR_SPACE_NV##TYPE_MANGLED_NV( \
Expand Down
8 changes: 8 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl
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Expand Up @@ -6,6 +6,7 @@
//
//===----------------------------------------------------------------------===//

#include <atomic_helpers.h>
#include <spirv/spirv.h>
#include <spirv/spirv_types.h>

Expand Down Expand Up @@ -54,6 +55,13 @@ Memory order is stored in the lowest 5 bits */ \
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
ADDR_SPACE, ADDR_SPACE_NV, \
_release) \
break; \
case SequentiallyConsistent: \
__CLC_NVVM_FENCE_SC_SM70() \
__CLC_NVVM_ATOMIC_STORE_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, \
ADDR_SPACE, ADDR_SPACE_NV, \
_release) \
break; \
} \
} else { \
switch (order) { \
Expand Down
29 changes: 21 additions & 8 deletions sycl/plugins/unified_runtime/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -56,14 +56,27 @@ endif()
if(SYCL_PI_UR_USE_FETCH_CONTENT)
include(FetchContent)

set(UNIFIED_RUNTIME_REPO "https://github.com/oneapi-src/unified-runtime.git")
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# commit ec634ff05b067d7922ec45059dda94665e5dcd9b
# Merge: 418ad535 8714b853
# Author: Piotr Balcer <piotr.balcer@intel.com>
# Date: Thu Mar 14 15:52:52 2024 +0100
# Merge pull request #1438 from PatKamin/disable-fuzztests
# Disable fuzz tests on ubuntu-22.04 runner
set(UNIFIED_RUNTIME_TAG ec634ff05b067d7922ec45059dda94665e5dcd9b)
#set(UNIFIED_RUNTIME_REPO "https://github.com/oneapi-src/unified-runtime")
set(UNIFIED_RUNTIME_REPO "https://github.com/JackAKirk/unified-runtime.git")

# commit 51d7180c344bbc2f942533e5fc51b0b04871f8d5
# Merge: b66cf9b1 0e37380e
# Author: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
# Date: Fri Jan 26 12:20:20 2024 +0000
# Merge pull request #1205 from ykhatav/ur_dependentload
# [UR] add dependent-load flag to exclude CWD from default search path …
set(UNIFIED_RUNTIME_TAG 35b6cd09dd92b04eae8195a706ef6c63541b3cf1)
#=======

# set(UNIFIED_RUNTIME_REPO "https://github.com/oneapi-src/unified-runtime")
# commit 3225b822b5d8cbfa85d7fc1bd5a5bf96e5bb8c1a
# Merge: edb281f3 5fc41099
# Author: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
# Date: Tue Jan 30 12:31:44 2024 +0000
# Merge pull request #1168 from Seanst98/sean/unique-addr-mode-per-dim-adapters
# [Bindless][CUDA] Unique addressing modes per dimension
# set(UNIFIED_RUNTIME_TAG 3225b822b5d8cbfa85d7fc1bd5a5bf96e5bb8c1a)

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if(SYCL_PI_UR_OVERRIDE_FETCH_CONTENT_REPO)
set(UNIFIED_RUNTIME_REPO "${SYCL_PI_UR_OVERRIDE_FETCH_CONTENT_REPO}")
Expand Down
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